1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Ingenic JZ47xx NAND driver
4  *
5  * Copyright (c) 2015 Imagination Technologies
6  * Author: Alex Smith <alex.smith@imgtec.com>
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/rawnand.h>
21 #include <linux/mtd/partitions.h>
22 
23 #include <linux/jz4780-nemc.h>
24 
25 #include "ingenic_ecc.h"
26 
27 #define DRV_NAME	"ingenic-nand"
28 
29 struct jz_soc_info {
30 	unsigned long data_offset;
31 	unsigned long addr_offset;
32 	unsigned long cmd_offset;
33 	const struct mtd_ooblayout_ops *oob_layout;
34 	bool oob_first;
35 };
36 
37 struct ingenic_nand_cs {
38 	unsigned int bank;
39 	void __iomem *base;
40 };
41 
42 struct ingenic_nfc {
43 	struct device *dev;
44 	struct ingenic_ecc *ecc;
45 	const struct jz_soc_info *soc_info;
46 	struct nand_controller controller;
47 	unsigned int num_banks;
48 	struct list_head chips;
49 	struct ingenic_nand_cs cs[];
50 };
51 
52 struct ingenic_nand {
53 	struct nand_chip chip;
54 	struct list_head chip_list;
55 
56 	struct gpio_desc *busy_gpio;
57 	struct gpio_desc *wp_gpio;
58 	unsigned int reading: 1;
59 };
60 
to_ingenic_nand(struct mtd_info * mtd)61 static inline struct ingenic_nand *to_ingenic_nand(struct mtd_info *mtd)
62 {
63 	return container_of(mtd_to_nand(mtd), struct ingenic_nand, chip);
64 }
65 
to_ingenic_nfc(struct nand_controller * ctrl)66 static inline struct ingenic_nfc *to_ingenic_nfc(struct nand_controller *ctrl)
67 {
68 	return container_of(ctrl, struct ingenic_nfc, controller);
69 }
70 
qi_lb60_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)71 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section,
72 				 struct mtd_oob_region *oobregion)
73 {
74 	struct nand_chip *chip = mtd_to_nand(mtd);
75 	struct nand_ecc_ctrl *ecc = &chip->ecc;
76 
77 	if (section || !ecc->total)
78 		return -ERANGE;
79 
80 	oobregion->length = ecc->total;
81 	oobregion->offset = 12;
82 
83 	return 0;
84 }
85 
qi_lb60_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)86 static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section,
87 				  struct mtd_oob_region *oobregion)
88 {
89 	struct nand_chip *chip = mtd_to_nand(mtd);
90 	struct nand_ecc_ctrl *ecc = &chip->ecc;
91 
92 	if (section)
93 		return -ERANGE;
94 
95 	oobregion->length = mtd->oobsize - ecc->total - 12;
96 	oobregion->offset = 12 + ecc->total;
97 
98 	return 0;
99 }
100 
101 static const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = {
102 	.ecc = qi_lb60_ooblayout_ecc,
103 	.free = qi_lb60_ooblayout_free,
104 };
105 
jz4725b_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)106 static int jz4725b_ooblayout_ecc(struct mtd_info *mtd, int section,
107 				 struct mtd_oob_region *oobregion)
108 {
109 	struct nand_chip *chip = mtd_to_nand(mtd);
110 	struct nand_ecc_ctrl *ecc = &chip->ecc;
111 
112 	if (section || !ecc->total)
113 		return -ERANGE;
114 
115 	oobregion->length = ecc->total;
116 	oobregion->offset = 3;
117 
118 	return 0;
119 }
120 
jz4725b_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)121 static int jz4725b_ooblayout_free(struct mtd_info *mtd, int section,
122 				  struct mtd_oob_region *oobregion)
123 {
124 	struct nand_chip *chip = mtd_to_nand(mtd);
125 	struct nand_ecc_ctrl *ecc = &chip->ecc;
126 
127 	if (section)
128 		return -ERANGE;
129 
130 	oobregion->length = mtd->oobsize - ecc->total - 3;
131 	oobregion->offset = 3 + ecc->total;
132 
133 	return 0;
134 }
135 
136 static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
137 	.ecc = jz4725b_ooblayout_ecc,
138 	.free = jz4725b_ooblayout_free,
139 };
140 
ingenic_nand_ecc_hwctl(struct nand_chip * chip,int mode)141 static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
142 {
143 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
144 
145 	nand->reading = (mode == NAND_ECC_READ);
146 }
147 
ingenic_nand_ecc_calculate(struct nand_chip * chip,const u8 * dat,u8 * ecc_code)148 static int ingenic_nand_ecc_calculate(struct nand_chip *chip, const u8 *dat,
149 				      u8 *ecc_code)
150 {
151 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
152 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
153 	struct ingenic_ecc_params params;
154 
155 	/*
156 	 * Don't need to generate the ECC when reading, the ECC engine does it
157 	 * for us as part of decoding/correction.
158 	 */
159 	if (nand->reading)
160 		return 0;
161 
162 	params.size = nand->chip.ecc.size;
163 	params.bytes = nand->chip.ecc.bytes;
164 	params.strength = nand->chip.ecc.strength;
165 
166 	return ingenic_ecc_calculate(nfc->ecc, &params, dat, ecc_code);
167 }
168 
ingenic_nand_ecc_correct(struct nand_chip * chip,u8 * dat,u8 * read_ecc,u8 * calc_ecc)169 static int ingenic_nand_ecc_correct(struct nand_chip *chip, u8 *dat,
170 				    u8 *read_ecc, u8 *calc_ecc)
171 {
172 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
173 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
174 	struct ingenic_ecc_params params;
175 
176 	params.size = nand->chip.ecc.size;
177 	params.bytes = nand->chip.ecc.bytes;
178 	params.strength = nand->chip.ecc.strength;
179 
180 	return ingenic_ecc_correct(nfc->ecc, &params, dat, read_ecc);
181 }
182 
ingenic_nand_attach_chip(struct nand_chip * chip)183 static int ingenic_nand_attach_chip(struct nand_chip *chip)
184 {
185 	struct mtd_info *mtd = nand_to_mtd(chip);
186 	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
187 	int eccbytes;
188 
189 	if (chip->ecc.strength == 4) {
190 		/* JZ4740 uses 9 bytes of ECC to correct maximum 4 errors */
191 		chip->ecc.bytes = 9;
192 	} else {
193 		chip->ecc.bytes = fls((1 + 8) * chip->ecc.size)	*
194 				  (chip->ecc.strength / 8);
195 	}
196 
197 	switch (chip->ecc.engine_type) {
198 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
199 		if (!nfc->ecc) {
200 			dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
201 			return -ENODEV;
202 		}
203 
204 		chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
205 		chip->ecc.calculate = ingenic_nand_ecc_calculate;
206 		chip->ecc.correct = ingenic_nand_ecc_correct;
207 		fallthrough;
208 	case NAND_ECC_ENGINE_TYPE_SOFT:
209 		dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
210 			 (nfc->ecc) ? "hardware ECC" : "software ECC",
211 			 chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
212 		break;
213 	case NAND_ECC_ENGINE_TYPE_NONE:
214 		dev_info(nfc->dev, "not using ECC\n");
215 		break;
216 	default:
217 		dev_err(nfc->dev, "ECC mode %d not supported\n",
218 			chip->ecc.engine_type);
219 		return -EINVAL;
220 	}
221 
222 	/* The NAND core will generate the ECC layout for SW ECC */
223 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
224 		return 0;
225 
226 	/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
227 	eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
228 
229 	if (eccbytes > mtd->oobsize - 2) {
230 		dev_err(nfc->dev,
231 			"invalid ECC config: required %d ECC bytes, but only %d are available",
232 			eccbytes, mtd->oobsize - 2);
233 		return -EINVAL;
234 	}
235 
236 	/*
237 	 * The generic layout for BBT markers will most likely overlap with our
238 	 * ECC bytes in the OOB, so move the BBT markers outside the OOB area.
239 	 */
240 	if (chip->bbt_options & NAND_BBT_USE_FLASH)
241 		chip->bbt_options |= NAND_BBT_NO_OOB;
242 
243 	if (nfc->soc_info->oob_first)
244 		chip->ecc.read_page = nand_read_page_hwecc_oob_first;
245 
246 	/* For legacy reasons we use a different layout on the qi,lb60 board. */
247 	if (of_machine_is_compatible("qi,lb60"))
248 		mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops);
249 	else if (nfc->soc_info->oob_layout)
250 		mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout);
251 	else
252 		mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
253 
254 	return 0;
255 }
256 
ingenic_nand_exec_instr(struct nand_chip * chip,struct ingenic_nand_cs * cs,const struct nand_op_instr * instr)257 static int ingenic_nand_exec_instr(struct nand_chip *chip,
258 				   struct ingenic_nand_cs *cs,
259 				   const struct nand_op_instr *instr)
260 {
261 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
262 	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
263 	unsigned int i;
264 
265 	switch (instr->type) {
266 	case NAND_OP_CMD_INSTR:
267 		writeb(instr->ctx.cmd.opcode,
268 		       cs->base + nfc->soc_info->cmd_offset);
269 		return 0;
270 	case NAND_OP_ADDR_INSTR:
271 		for (i = 0; i < instr->ctx.addr.naddrs; i++)
272 			writeb(instr->ctx.addr.addrs[i],
273 			       cs->base + nfc->soc_info->addr_offset);
274 		return 0;
275 	case NAND_OP_DATA_IN_INSTR:
276 		if (instr->ctx.data.force_8bit ||
277 		    !(chip->options & NAND_BUSWIDTH_16))
278 			ioread8_rep(cs->base + nfc->soc_info->data_offset,
279 				    instr->ctx.data.buf.in,
280 				    instr->ctx.data.len);
281 		else
282 			ioread16_rep(cs->base + nfc->soc_info->data_offset,
283 				     instr->ctx.data.buf.in,
284 				     instr->ctx.data.len);
285 		return 0;
286 	case NAND_OP_DATA_OUT_INSTR:
287 		if (instr->ctx.data.force_8bit ||
288 		    !(chip->options & NAND_BUSWIDTH_16))
289 			iowrite8_rep(cs->base + nfc->soc_info->data_offset,
290 				     instr->ctx.data.buf.out,
291 				     instr->ctx.data.len);
292 		else
293 			iowrite16_rep(cs->base + nfc->soc_info->data_offset,
294 				      instr->ctx.data.buf.out,
295 				      instr->ctx.data.len);
296 		return 0;
297 	case NAND_OP_WAITRDY_INSTR:
298 		if (!nand->busy_gpio)
299 			return nand_soft_waitrdy(chip,
300 						 instr->ctx.waitrdy.timeout_ms);
301 
302 		return nand_gpio_waitrdy(chip, nand->busy_gpio,
303 					 instr->ctx.waitrdy.timeout_ms);
304 	default:
305 		break;
306 	}
307 
308 	return -EINVAL;
309 }
310 
ingenic_nand_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)311 static int ingenic_nand_exec_op(struct nand_chip *chip,
312 				const struct nand_operation *op,
313 				bool check_only)
314 {
315 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
316 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
317 	struct ingenic_nand_cs *cs;
318 	unsigned int i;
319 	int ret = 0;
320 
321 	if (check_only)
322 		return 0;
323 
324 	cs = &nfc->cs[op->cs];
325 	jz4780_nemc_assert(nfc->dev, cs->bank, true);
326 	for (i = 0; i < op->ninstrs; i++) {
327 		ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
328 		if (ret)
329 			break;
330 
331 		if (op->instrs[i].delay_ns)
332 			ndelay(op->instrs[i].delay_ns);
333 	}
334 	jz4780_nemc_assert(nfc->dev, cs->bank, false);
335 
336 	return ret;
337 }
338 
339 static const struct nand_controller_ops ingenic_nand_controller_ops = {
340 	.attach_chip = ingenic_nand_attach_chip,
341 	.exec_op = ingenic_nand_exec_op,
342 };
343 
ingenic_nand_init_chip(struct platform_device * pdev,struct ingenic_nfc * nfc,struct device_node * np,unsigned int chipnr)344 static int ingenic_nand_init_chip(struct platform_device *pdev,
345 				  struct ingenic_nfc *nfc,
346 				  struct device_node *np,
347 				  unsigned int chipnr)
348 {
349 	struct device *dev = &pdev->dev;
350 	struct ingenic_nand *nand;
351 	struct ingenic_nand_cs *cs;
352 	struct nand_chip *chip;
353 	struct mtd_info *mtd;
354 	const __be32 *reg;
355 	int ret = 0;
356 
357 	cs = &nfc->cs[chipnr];
358 
359 	reg = of_get_property(np, "reg", NULL);
360 	if (!reg)
361 		return -EINVAL;
362 
363 	cs->bank = be32_to_cpu(*reg);
364 
365 	jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
366 
367 	cs->base = devm_platform_ioremap_resource(pdev, chipnr);
368 	if (IS_ERR(cs->base))
369 		return PTR_ERR(cs->base);
370 
371 	nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
372 	if (!nand)
373 		return -ENOMEM;
374 
375 	nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
376 
377 	if (IS_ERR(nand->busy_gpio)) {
378 		ret = PTR_ERR(nand->busy_gpio);
379 		dev_err(dev, "failed to request busy GPIO: %d\n", ret);
380 		return ret;
381 	}
382 
383 	/*
384 	 * The rb-gpios semantics was undocumented and qi,lb60 (along with
385 	 * the ingenic driver) got it wrong. The active state encodes the
386 	 * NAND ready state, which is high level. Since there's no signal
387 	 * inverter on this board, it should be active-high. Let's fix that
388 	 * here for older DTs so we can re-use the generic nand_gpio_waitrdy()
389 	 * helper, and be consistent with what other drivers do.
390 	 */
391 	if (of_machine_is_compatible("qi,lb60") &&
392 	    gpiod_is_active_low(nand->busy_gpio))
393 		gpiod_toggle_active_low(nand->busy_gpio);
394 
395 	nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
396 
397 	if (IS_ERR(nand->wp_gpio)) {
398 		ret = PTR_ERR(nand->wp_gpio);
399 		dev_err(dev, "failed to request WP GPIO: %d\n", ret);
400 		return ret;
401 	}
402 
403 	chip = &nand->chip;
404 	mtd = nand_to_mtd(chip);
405 	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
406 				   cs->bank);
407 	if (!mtd->name)
408 		return -ENOMEM;
409 	mtd->dev.parent = dev;
410 
411 	chip->options = NAND_NO_SUBPAGE_WRITE;
412 	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
413 	chip->controller = &nfc->controller;
414 	nand_set_flash_node(chip, np);
415 
416 	chip->controller->ops = &ingenic_nand_controller_ops;
417 	ret = nand_scan(chip, 1);
418 	if (ret)
419 		return ret;
420 
421 	ret = mtd_device_register(mtd, NULL, 0);
422 	if (ret) {
423 		nand_cleanup(chip);
424 		return ret;
425 	}
426 
427 	list_add_tail(&nand->chip_list, &nfc->chips);
428 
429 	return 0;
430 }
431 
ingenic_nand_cleanup_chips(struct ingenic_nfc * nfc)432 static void ingenic_nand_cleanup_chips(struct ingenic_nfc *nfc)
433 {
434 	struct ingenic_nand *ingenic_chip;
435 	struct nand_chip *chip;
436 	int ret;
437 
438 	while (!list_empty(&nfc->chips)) {
439 		ingenic_chip = list_first_entry(&nfc->chips,
440 						struct ingenic_nand, chip_list);
441 		chip = &ingenic_chip->chip;
442 		ret = mtd_device_unregister(nand_to_mtd(chip));
443 		WARN_ON(ret);
444 		nand_cleanup(chip);
445 		list_del(&ingenic_chip->chip_list);
446 	}
447 }
448 
ingenic_nand_init_chips(struct ingenic_nfc * nfc,struct platform_device * pdev)449 static int ingenic_nand_init_chips(struct ingenic_nfc *nfc,
450 				   struct platform_device *pdev)
451 {
452 	struct device *dev = &pdev->dev;
453 	struct device_node *np;
454 	int i = 0;
455 	int ret;
456 	int num_chips = of_get_child_count(dev->of_node);
457 
458 	if (num_chips > nfc->num_banks) {
459 		dev_err(dev, "found %d chips but only %d banks\n",
460 			num_chips, nfc->num_banks);
461 		return -EINVAL;
462 	}
463 
464 	for_each_child_of_node(dev->of_node, np) {
465 		ret = ingenic_nand_init_chip(pdev, nfc, np, i);
466 		if (ret) {
467 			ingenic_nand_cleanup_chips(nfc);
468 			of_node_put(np);
469 			return ret;
470 		}
471 
472 		i++;
473 	}
474 
475 	return 0;
476 }
477 
ingenic_nand_probe(struct platform_device * pdev)478 static int ingenic_nand_probe(struct platform_device *pdev)
479 {
480 	struct device *dev = &pdev->dev;
481 	unsigned int num_banks;
482 	struct ingenic_nfc *nfc;
483 	int ret;
484 
485 	num_banks = jz4780_nemc_num_banks(dev);
486 	if (num_banks == 0) {
487 		dev_err(dev, "no banks found\n");
488 		return -ENODEV;
489 	}
490 
491 	nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
492 	if (!nfc)
493 		return -ENOMEM;
494 
495 	nfc->soc_info = device_get_match_data(dev);
496 	if (!nfc->soc_info)
497 		return -EINVAL;
498 
499 	/*
500 	 * Check for ECC HW before we call nand_scan_ident, to prevent us from
501 	 * having to call it again if the ECC driver returns -EPROBE_DEFER.
502 	 */
503 	nfc->ecc = of_ingenic_ecc_get(dev->of_node);
504 	if (IS_ERR(nfc->ecc))
505 		return PTR_ERR(nfc->ecc);
506 
507 	nfc->dev = dev;
508 	nfc->num_banks = num_banks;
509 
510 	nand_controller_init(&nfc->controller);
511 	INIT_LIST_HEAD(&nfc->chips);
512 
513 	ret = ingenic_nand_init_chips(nfc, pdev);
514 	if (ret) {
515 		if (nfc->ecc)
516 			ingenic_ecc_release(nfc->ecc);
517 		return ret;
518 	}
519 
520 	platform_set_drvdata(pdev, nfc);
521 	return 0;
522 }
523 
ingenic_nand_remove(struct platform_device * pdev)524 static void ingenic_nand_remove(struct platform_device *pdev)
525 {
526 	struct ingenic_nfc *nfc = platform_get_drvdata(pdev);
527 
528 	if (nfc->ecc)
529 		ingenic_ecc_release(nfc->ecc);
530 
531 	ingenic_nand_cleanup_chips(nfc);
532 }
533 
534 static const struct jz_soc_info jz4740_soc_info = {
535 	.data_offset = 0x00000000,
536 	.cmd_offset = 0x00008000,
537 	.addr_offset = 0x00010000,
538 	.oob_first = true,
539 };
540 
541 static const struct jz_soc_info jz4725b_soc_info = {
542 	.data_offset = 0x00000000,
543 	.cmd_offset = 0x00008000,
544 	.addr_offset = 0x00010000,
545 	.oob_layout = &jz4725b_ooblayout_ops,
546 };
547 
548 static const struct jz_soc_info jz4780_soc_info = {
549 	.data_offset = 0x00000000,
550 	.cmd_offset = 0x00400000,
551 	.addr_offset = 0x00800000,
552 };
553 
554 static const struct of_device_id ingenic_nand_dt_match[] = {
555 	{ .compatible = "ingenic,jz4740-nand", .data = &jz4740_soc_info },
556 	{ .compatible = "ingenic,jz4725b-nand", .data = &jz4725b_soc_info },
557 	{ .compatible = "ingenic,jz4780-nand", .data = &jz4780_soc_info },
558 	{},
559 };
560 MODULE_DEVICE_TABLE(of, ingenic_nand_dt_match);
561 
562 static struct platform_driver ingenic_nand_driver = {
563 	.probe		= ingenic_nand_probe,
564 	.remove_new	= ingenic_nand_remove,
565 	.driver	= {
566 		.name	= DRV_NAME,
567 		.of_match_table = ingenic_nand_dt_match,
568 	},
569 };
570 module_platform_driver(ingenic_nand_driver);
571 
572 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
573 MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
574 MODULE_DESCRIPTION("Ingenic JZ47xx NAND driver");
575 MODULE_LICENSE("GPL v2");
576