1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
4 */
5
6 #include <common.h>
7 #include <mapmem.h>
8 #include <linux/io.h>
9 #include <linux/err.h>
10 #include <dm.h>
11 #include <dm/pinctrl.h>
12
13 #include "pinctrl-imx.h"
14
15 DECLARE_GLOBAL_DATA_PTR;
16
imx_pinctrl_set_state(struct udevice * dev,struct udevice * config)17 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
18 {
19 struct imx_pinctrl_priv *priv = dev_get_priv(dev);
20 struct imx_pinctrl_soc_info *info = priv->info;
21 int node = dev_of_offset(config);
22 const struct fdt_property *prop;
23 u32 *pin_data;
24 int npins, size, pin_size;
25 int mux_reg, conf_reg, input_reg;
26 u32 input_val, mux_mode, config_val;
27 u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
28 int i, j = 0;
29
30 dev_dbg(dev, "%s: %s\n", __func__, config->name);
31
32 if (info->flags & IMX8_USE_SCU)
33 pin_size = SHARE_IMX8_PIN_SIZE;
34 else if (info->flags & SHARE_MUX_CONF_REG)
35 pin_size = SHARE_FSL_PIN_SIZE;
36 else
37 pin_size = FSL_PIN_SIZE;
38
39 prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
40 if (!prop) {
41 dev_err(dev, "No fsl,pins property in node %s\n", config->name);
42 return -EINVAL;
43 }
44
45 if (!size || size % pin_size) {
46 dev_err(dev, "Invalid fsl,pins property in node %s\n",
47 config->name);
48 return -EINVAL;
49 }
50
51 pin_data = devm_kzalloc(dev, size, 0);
52 if (!pin_data)
53 return -ENOMEM;
54
55 if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
56 pin_data, size >> 2)) {
57 dev_err(dev, "Error reading pin data.\n");
58 devm_kfree(dev, pin_data);
59 return -EINVAL;
60 }
61
62 npins = size / pin_size;
63
64 if (info->flags & IMX8_USE_SCU) {
65 imx_pinctrl_scu_conf_pins(info, pin_data, npins);
66 } else {
67 /*
68 * Refer to linux documentation for details:
69 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
70 */
71 for (i = 0; i < npins; i++) {
72 mux_reg = pin_data[j++];
73
74 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
75 mux_reg = -1;
76
77 if (info->flags & SHARE_MUX_CONF_REG) {
78 conf_reg = mux_reg;
79 } else {
80 conf_reg = pin_data[j++];
81 if (!(info->flags & ZERO_OFFSET_VALID) &&
82 !conf_reg)
83 conf_reg = -1;
84 }
85
86 if ((mux_reg == -1) || (conf_reg == -1)) {
87 dev_err(dev, "Error mux_reg or conf_reg\n");
88 devm_kfree(dev, pin_data);
89 return -EINVAL;
90 }
91
92 input_reg = pin_data[j++];
93 mux_mode = pin_data[j++];
94 input_val = pin_data[j++];
95 config_val = pin_data[j++];
96
97 dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
98 "input_reg 0x%x, mux_mode 0x%x, "
99 "input_val 0x%x, config_val 0x%x\n",
100 mux_reg, conf_reg, input_reg, mux_mode,
101 input_val, config_val);
102
103 if (config_val & IMX_PAD_SION)
104 mux_mode |= IOMUXC_CONFIG_SION;
105
106 config_val &= ~IMX_PAD_SION;
107
108 /* Set Mux */
109 if (info->flags & SHARE_MUX_CONF_REG) {
110 clrsetbits_le32(info->base + mux_reg,
111 info->mux_mask,
112 mux_mode << mux_shift);
113 } else {
114 writel(mux_mode, info->base + mux_reg);
115 }
116
117 dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
118 mux_reg, mux_mode);
119
120 /*
121 * Set select input
122 *
123 * If the select input value begins with 0xff,
124 * it's a quirky select input and the value should
125 * be interpreted as below.
126 * 31 23 15 7 0
127 * | 0xff | shift | width | select |
128 * It's used to work around the problem that the
129 * select input for some pin is not implemented in
130 * the select input register but in some general
131 * purpose register. We encode the select input
132 * value, width and shift of the bit field into
133 * input_val cell of pin function ID in device tree,
134 * and then decode them here for setting up the select
135 * input bits in general purpose register.
136 */
137
138 if (input_val >> 24 == 0xff) {
139 u32 val = input_val;
140 u8 select = val & 0xff;
141 u8 width = (val >> 8) & 0xff;
142 u8 shift = (val >> 16) & 0xff;
143 u32 mask = ((1 << width) - 1) << shift;
144 /*
145 * The input_reg[i] here is actually some
146 * IOMUXC general purpose register, not
147 * regular select input register.
148 */
149 val = readl(info->base + input_reg);
150 val &= ~mask;
151 val |= select << shift;
152 writel(val, info->base + input_reg);
153 } else if (input_reg) {
154 /*
155 * Regular select input register can never be
156 * at offset 0, and we only print register
157 * value for regular case.
158 */
159 if (info->input_sel_base)
160 writel(input_val,
161 info->input_sel_base +
162 input_reg);
163 else
164 writel(input_val,
165 info->base + input_reg);
166
167 dev_dbg(dev, "select_input: offset 0x%x val "
168 "0x%x\n", input_reg, input_val);
169 }
170
171 /* Set config */
172 if (!(config_val & IMX_NO_PAD_CTL)) {
173 if (info->flags & SHARE_MUX_CONF_REG) {
174 clrsetbits_le32(info->base + conf_reg,
175 ~info->mux_mask,
176 config_val);
177 } else {
178 writel(config_val,
179 info->base + conf_reg);
180 }
181
182 dev_dbg(dev, "write config: offset 0x%x val "
183 "0x%x\n", conf_reg, config_val);
184 }
185 }
186 }
187
188 devm_kfree(dev, pin_data);
189
190 return 0;
191 }
192
193 const struct pinctrl_ops imx_pinctrl_ops = {
194 .set_state = imx_pinctrl_set_state,
195 };
196
imx_pinctrl_probe(struct udevice * dev,struct imx_pinctrl_soc_info * info)197 int imx_pinctrl_probe(struct udevice *dev,
198 struct imx_pinctrl_soc_info *info)
199 {
200 struct imx_pinctrl_priv *priv = dev_get_priv(dev);
201 int node = dev_of_offset(dev), ret;
202 struct fdtdec_phandle_args arg;
203 fdt_addr_t addr;
204 fdt_size_t size;
205
206 if (!info) {
207 dev_err(dev, "wrong pinctrl info\n");
208 return -EINVAL;
209 }
210
211 priv->dev = dev;
212 priv->info = info;
213
214 if (info->flags & IMX8_USE_SCU)
215 return 0;
216
217 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
218 &size);
219
220 if (addr == FDT_ADDR_T_NONE)
221 return -EINVAL;
222
223 info->base = map_sysmem(addr, size);
224 if (!info->base)
225 return -ENOMEM;
226 priv->info = info;
227
228 info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
229 /*
230 * Refer to linux documentation for details:
231 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
232 */
233 if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
234 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
235 node, "fsl,input-sel",
236 NULL, 0, 0, &arg);
237 if (ret) {
238 dev_err(dev, "iomuxc fsl,input-sel property not found\n");
239 return -EINVAL;
240 }
241
242 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
243 &size);
244 if (addr == FDT_ADDR_T_NONE)
245 return -EINVAL;
246
247 info->input_sel_base = map_sysmem(addr, size);
248 if (!info->input_sel_base)
249 return -ENOMEM;
250 }
251
252 dev_dbg(dev, "initialized IMX pinctrl driver\n");
253
254 return 0;
255 }
256
imx_pinctrl_remove(struct udevice * dev)257 int imx_pinctrl_remove(struct udevice *dev)
258 {
259 struct imx_pinctrl_priv *priv = dev_get_priv(dev);
260 struct imx_pinctrl_soc_info *info = priv->info;
261
262 if (info->flags & IMX8_USE_SCU)
263 return 0;
264
265 if (info->input_sel_base)
266 unmap_sysmem(info->input_sel_base);
267 if (info->base)
268 unmap_sysmem(info->base);
269
270 return 0;
271 }
272