xref: /openbmc/linux/drivers/gpu/drm/imx/lcdc/imx-lcdc.c (revision 9c010be0)
1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: 2020 Marian Cichy <M.Cichy@pengutronix.de>
3 
4 #include <drm/drm_bridge.h>
5 #include <drm/drm_bridge_connector.h>
6 #include <drm/drm_damage_helper.h>
7 #include <drm/drm_drv.h>
8 #include <drm/drm_fbdev_generic.h>
9 #include <drm/drm_fb_dma_helper.h>
10 #include <drm/drm_fourcc.h>
11 #include <drm/drm_framebuffer.h>
12 #include <drm/drm_gem_atomic_helper.h>
13 #include <drm/drm_gem_dma_helper.h>
14 #include <drm/drm_gem_framebuffer_helper.h>
15 #include <drm/drm_of.h>
16 #include <drm/drm_probe_helper.h>
17 #include <drm/drm_simple_kms_helper.h>
18 #include <drm/drm_vblank.h>
19 #include <linux/bitfield.h>
20 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 
26 #define IMX21LCDC_LSSAR         0x0000 /* LCDC Screen Start Address Register */
27 #define IMX21LCDC_LSR           0x0004 /* LCDC Size Register */
28 #define IMX21LCDC_LVPWR         0x0008 /* LCDC Virtual Page Width Register */
29 #define IMX21LCDC_LCPR          0x000C /* LCDC Cursor Position Register */
30 #define IMX21LCDC_LCWHB         0x0010 /* LCDC Cursor Width Height and Blink Register*/
31 #define IMX21LCDC_LCCMR         0x0014 /* LCDC Color Cursor Mapping Register */
32 #define IMX21LCDC_LPCR          0x0018 /* LCDC Panel Configuration Register */
33 #define IMX21LCDC_LHCR          0x001C /* LCDC Horizontal Configuration Register */
34 #define IMX21LCDC_LVCR          0x0020 /* LCDC Vertical Configuration Register */
35 #define IMX21LCDC_LPOR          0x0024 /* LCDC Panning Offset Register */
36 #define IMX21LCDC_LSCR          0x0028 /* LCDC Sharp Configuration Register */
37 #define IMX21LCDC_LPCCR         0x002C /* LCDC PWM Contrast Control Register */
38 #define IMX21LCDC_LDCR          0x0030 /* LCDC DMA Control Register */
39 #define IMX21LCDC_LRMCR         0x0034 /* LCDC Refresh Mode Control Register */
40 #define IMX21LCDC_LICR          0x0038 /* LCDC Interrupt Configuration Register */
41 #define IMX21LCDC_LIER          0x003C /* LCDC Interrupt Enable Register */
42 #define IMX21LCDC_LISR          0x0040 /* LCDC Interrupt Status Register */
43 #define IMX21LCDC_LGWSAR        0x0050 /* LCDC Graphic Window Start Address Register */
44 #define IMX21LCDC_LGWSR         0x0054 /* LCDC Graph Window Size Register */
45 #define IMX21LCDC_LGWVPWR       0x0058 /* LCDC Graphic Window Virtual Page Width Register */
46 #define IMX21LCDC_LGWPOR        0x005C /* LCDC Graphic Window Panning Offset Register */
47 #define IMX21LCDC_LGWPR         0x0060 /* LCDC Graphic Window Position Register */
48 #define IMX21LCDC_LGWCR         0x0064 /* LCDC Graphic Window Control Register */
49 #define IMX21LCDC_LGWDCR        0x0068 /* LCDC Graphic Window DMA Control Register */
50 #define IMX21LCDC_LAUSCR        0x0080 /* LCDC AUS Mode Control Register */
51 #define IMX21LCDC_LAUSCCR       0x0084 /* LCDC AUS Mode Cursor Control Register */
52 #define IMX21LCDC_BGLUT         0x0800 /* Background Lookup Table */
53 #define IMX21LCDC_GWLUT         0x0C00 /* Graphic Window Lookup Table */
54 
55 #define IMX21LCDC_LCPR_CC0 BIT(30) /* Cursor Control Bit 0 */
56 #define IMX21LCDC_LCPR_CC1 BIT(31) /* Cursor Control Bit 1 */
57 
58 /* Values HSYNC, VSYNC and Framesize Register */
59 #define IMX21LCDC_LHCR_HWIDTH		GENMASK(31, 26)
60 #define IMX21LCDC_LHCR_HFPORCH		GENMASK(15, 8)		/* H_WAIT_1 in the i.MX25 Reference manual */
61 #define IMX21LCDC_LHCR_HBPORCH		GENMASK(7, 0)		/* H_WAIT_2 in the i.MX25 Reference manual */
62 
63 #define IMX21LCDC_LVCR_VWIDTH		GENMASK(31, 26)
64 #define IMX21LCDC_LVCR_VFPORCH		GENMASK(15, 8)		/* V_WAIT_1 in the i.MX25 Reference manual */
65 #define IMX21LCDC_LVCR_VBPORCH		GENMASK(7, 0)		/* V_WAIT_2 in the i.MX25 Reference manual */
66 
67 #define IMX21LCDC_LSR_XMAX		GENMASK(25, 20)
68 #define IMX21LCDC_LSR_YMAX		GENMASK(9, 0)
69 
70 /* Values for LPCR Register */
71 #define IMX21LCDC_LPCR_PCD		GENMASK(5, 0)
72 #define IMX21LCDC_LPCR_SHARP		BIT(6)
73 #define IMX21LCDC_LPCR_SCLKSEL		BIT(7)
74 #define IMX21LCDC_LPCR_ACD		GENMASK(14, 8)
75 #define IMX21LCDC_LPCR_ACDSEL		BIT(15)
76 #define IMX21LCDC_LPCR_REV_VS		BIT(16)
77 #define IMX21LCDC_LPCR_SWAP_SEL		BIT(17)
78 #define IMX21LCDC_LPCR_END_SEL		BIT(18)
79 #define IMX21LCDC_LPCR_SCLKIDLE		BIT(19)
80 #define IMX21LCDC_LPCR_OEPOL		BIT(20)
81 #define IMX21LCDC_LPCR_CLKPOL		BIT(21)
82 #define IMX21LCDC_LPCR_LPPOL		BIT(22)
83 #define IMX21LCDC_LPCR_FLMPOL		BIT(23)
84 #define IMX21LCDC_LPCR_PIXPOL		BIT(24)
85 #define IMX21LCDC_LPCR_BPIX		GENMASK(27, 25)
86 #define IMX21LCDC_LPCR_PBSIZ		GENMASK(29, 28)
87 #define IMX21LCDC_LPCR_COLOR		BIT(30)
88 #define IMX21LCDC_LPCR_TFT		BIT(31)
89 
90 #define INTR_EOF BIT(1) /* VBLANK Interrupt Bit */
91 
92 #define BPP_RGB565	0x05
93 #define BPP_XRGB8888	0x07
94 
95 #define LCDC_MIN_XRES 64
96 #define LCDC_MIN_YRES 64
97 
98 #define LCDC_MAX_XRES 1024
99 #define LCDC_MAX_YRES 1024
100 
101 struct imx_lcdc {
102 	struct drm_device drm;
103 	struct drm_simple_display_pipe pipe;
104 	struct drm_connector *connector;
105 	void __iomem *base;
106 
107 	struct clk *clk_ipg;
108 	struct clk *clk_ahb;
109 	struct clk *clk_per;
110 };
111 
112 static const u32 imx_lcdc_formats[] = {
113 	DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
114 };
115 
imx_lcdc_from_drmdev(struct drm_device * drm)116 static inline struct imx_lcdc *imx_lcdc_from_drmdev(struct drm_device *drm)
117 {
118 	return container_of(drm, struct imx_lcdc, drm);
119 }
120 
imx_lcdc_get_format(unsigned int drm_format)121 static unsigned int imx_lcdc_get_format(unsigned int drm_format)
122 {
123 	switch (drm_format) {
124 	default:
125 		DRM_WARN("Format not supported - fallback to XRGB8888\n");
126 		fallthrough;
127 
128 	case DRM_FORMAT_XRGB8888:
129 		return BPP_XRGB8888;
130 
131 	case DRM_FORMAT_RGB565:
132 		return BPP_RGB565;
133 	}
134 }
135 
imx_lcdc_update_hw_registers(struct drm_simple_display_pipe * pipe,struct drm_plane_state * old_state,bool mode_set)136 static void imx_lcdc_update_hw_registers(struct drm_simple_display_pipe *pipe,
137 					 struct drm_plane_state *old_state,
138 					 bool mode_set)
139 {
140 	struct drm_crtc *crtc = &pipe->crtc;
141 	struct drm_plane_state *new_state = pipe->plane.state;
142 	struct drm_framebuffer *fb = new_state->fb;
143 	struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev);
144 	u32 lpcr, lvcr, lhcr;
145 	u32 framesize;
146 	dma_addr_t addr;
147 
148 	addr = drm_fb_dma_get_gem_addr(fb, new_state, 0);
149 	/* The LSSAR register specifies the LCD screen start address (SSA). */
150 	writel(addr, lcdc->base + IMX21LCDC_LSSAR);
151 
152 	if (!mode_set)
153 		return;
154 
155 	/* Disable PER clock to make register write possible */
156 	if (old_state && old_state->crtc && old_state->crtc->enabled)
157 		clk_disable_unprepare(lcdc->clk_per);
158 
159 	/* Framesize */
160 	framesize = FIELD_PREP(IMX21LCDC_LSR_XMAX, crtc->mode.hdisplay >> 4) |
161 		FIELD_PREP(IMX21LCDC_LSR_YMAX, crtc->mode.vdisplay);
162 	writel(framesize, lcdc->base + IMX21LCDC_LSR);
163 
164 	/* HSYNC */
165 	lhcr = FIELD_PREP(IMX21LCDC_LHCR_HFPORCH, crtc->mode.hsync_start - crtc->mode.hdisplay - 1) |
166 		FIELD_PREP(IMX21LCDC_LHCR_HWIDTH, crtc->mode.hsync_end - crtc->mode.hsync_start - 1) |
167 		FIELD_PREP(IMX21LCDC_LHCR_HBPORCH, crtc->mode.htotal - crtc->mode.hsync_end - 3);
168 	writel(lhcr, lcdc->base + IMX21LCDC_LHCR);
169 
170 	/* VSYNC */
171 	lvcr = FIELD_PREP(IMX21LCDC_LVCR_VFPORCH, crtc->mode.vsync_start - crtc->mode.vdisplay) |
172 		FIELD_PREP(IMX21LCDC_LVCR_VWIDTH, crtc->mode.vsync_end - crtc->mode.vsync_start) |
173 		FIELD_PREP(IMX21LCDC_LVCR_VBPORCH, crtc->mode.vtotal - crtc->mode.vsync_end);
174 	writel(lvcr, lcdc->base + IMX21LCDC_LVCR);
175 
176 	lpcr = readl(lcdc->base + IMX21LCDC_LPCR);
177 	lpcr &= ~IMX21LCDC_LPCR_BPIX;
178 	lpcr |= FIELD_PREP(IMX21LCDC_LPCR_BPIX, imx_lcdc_get_format(fb->format->format));
179 	writel(lpcr, lcdc->base + IMX21LCDC_LPCR);
180 
181 	/* Virtual Page Width */
182 	writel(new_state->fb->pitches[0] / 4, lcdc->base + IMX21LCDC_LVPWR);
183 
184 	/* Enable PER clock */
185 	if (new_state->crtc->enabled)
186 		clk_prepare_enable(lcdc->clk_per);
187 }
188 
imx_lcdc_pipe_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)189 static void imx_lcdc_pipe_enable(struct drm_simple_display_pipe *pipe,
190 				 struct drm_crtc_state *crtc_state,
191 				 struct drm_plane_state *plane_state)
192 {
193 	int ret;
194 	int clk_div;
195 	int bpp;
196 	struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev);
197 	struct drm_display_mode *mode = &pipe->crtc.mode;
198 	struct drm_display_info *disp_info = &lcdc->connector->display_info;
199 	const int hsync_pol = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : 1;
200 	const int vsync_pol = (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : 1;
201 	const int data_enable_pol =
202 		(disp_info->bus_flags & DRM_BUS_FLAG_DE_HIGH) ? 0 : 1;
203 	const int clk_pol =
204 		(disp_info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) ? 0 : 1;
205 
206 	clk_div = DIV_ROUND_CLOSEST_ULL(clk_get_rate(lcdc->clk_per),
207 					mode->clock * 1000);
208 	bpp = imx_lcdc_get_format(plane_state->fb->format->format);
209 
210 	writel(FIELD_PREP(IMX21LCDC_LPCR_PCD, clk_div - 1) |
211 	       FIELD_PREP(IMX21LCDC_LPCR_LPPOL, hsync_pol) |
212 	       FIELD_PREP(IMX21LCDC_LPCR_FLMPOL, vsync_pol) |
213 	       FIELD_PREP(IMX21LCDC_LPCR_OEPOL, data_enable_pol) |
214 	       FIELD_PREP(IMX21LCDC_LPCR_TFT, 1) |
215 	       FIELD_PREP(IMX21LCDC_LPCR_COLOR, 1) |
216 	       FIELD_PREP(IMX21LCDC_LPCR_PBSIZ, 3) |
217 	       FIELD_PREP(IMX21LCDC_LPCR_BPIX, bpp) |
218 	       FIELD_PREP(IMX21LCDC_LPCR_SCLKSEL, 1) |
219 	       FIELD_PREP(IMX21LCDC_LPCR_PIXPOL, 0) |
220 	       FIELD_PREP(IMX21LCDC_LPCR_CLKPOL, clk_pol),
221 	       lcdc->base + IMX21LCDC_LPCR);
222 
223 	/* 0px panning offset */
224 	writel(0x00000000, lcdc->base + IMX21LCDC_LPOR);
225 
226 	/* disable hardware cursor */
227 	writel(readl(lcdc->base + IMX21LCDC_LCPR) & ~(IMX21LCDC_LCPR_CC0 | IMX21LCDC_LCPR_CC1),
228 	       lcdc->base + IMX21LCDC_LCPR);
229 
230 	ret = clk_prepare_enable(lcdc->clk_ipg);
231 	if (ret) {
232 		dev_err(pipe->crtc.dev->dev, "Cannot enable ipg clock: %pe\n", ERR_PTR(ret));
233 		return;
234 	}
235 	ret = clk_prepare_enable(lcdc->clk_ahb);
236 	if (ret) {
237 		dev_err(pipe->crtc.dev->dev, "Cannot enable ahb clock: %pe\n", ERR_PTR(ret));
238 
239 		clk_disable_unprepare(lcdc->clk_ipg);
240 
241 		return;
242 	}
243 
244 	imx_lcdc_update_hw_registers(pipe, NULL, true);
245 
246 	/* Enable VBLANK Interrupt */
247 	writel(INTR_EOF, lcdc->base + IMX21LCDC_LIER);
248 }
249 
imx_lcdc_pipe_disable(struct drm_simple_display_pipe * pipe)250 static void imx_lcdc_pipe_disable(struct drm_simple_display_pipe *pipe)
251 {
252 	struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev);
253 	struct drm_crtc *crtc = &lcdc->pipe.crtc;
254 	struct drm_pending_vblank_event *event;
255 
256 	clk_disable_unprepare(lcdc->clk_ahb);
257 	clk_disable_unprepare(lcdc->clk_ipg);
258 
259 	if (pipe->crtc.enabled)
260 		clk_disable_unprepare(lcdc->clk_per);
261 
262 	spin_lock_irq(&lcdc->drm.event_lock);
263 	event = crtc->state->event;
264 	if (event) {
265 		crtc->state->event = NULL;
266 		drm_crtc_send_vblank_event(crtc, event);
267 	}
268 	spin_unlock_irq(&lcdc->drm.event_lock);
269 
270 	/* Disable VBLANK Interrupt */
271 	writel(0, lcdc->base + IMX21LCDC_LIER);
272 }
273 
imx_lcdc_pipe_check(struct drm_simple_display_pipe * pipe,struct drm_plane_state * plane_state,struct drm_crtc_state * crtc_state)274 static int imx_lcdc_pipe_check(struct drm_simple_display_pipe *pipe,
275 			       struct drm_plane_state *plane_state,
276 			       struct drm_crtc_state *crtc_state)
277 {
278 	const struct drm_display_mode *mode = &crtc_state->mode;
279 	const struct drm_display_mode *old_mode = &pipe->crtc.state->mode;
280 
281 	if (mode->hdisplay < LCDC_MIN_XRES || mode->hdisplay > LCDC_MAX_XRES ||
282 	    mode->vdisplay < LCDC_MIN_YRES || mode->vdisplay > LCDC_MAX_YRES ||
283 	    mode->hdisplay % 0x10) { /* must be multiple of 16 */
284 		drm_err(pipe->crtc.dev, "unsupported display mode (%u x %u)\n",
285 			mode->hdisplay, mode->vdisplay);
286 		return -EINVAL;
287 	}
288 
289 	crtc_state->mode_changed =
290 		old_mode->hdisplay != mode->hdisplay ||
291 		old_mode->vdisplay != mode->vdisplay;
292 
293 	return 0;
294 }
295 
imx_lcdc_pipe_update(struct drm_simple_display_pipe * pipe,struct drm_plane_state * old_state)296 static void imx_lcdc_pipe_update(struct drm_simple_display_pipe *pipe,
297 				 struct drm_plane_state *old_state)
298 {
299 	struct drm_crtc *crtc = &pipe->crtc;
300 	struct drm_pending_vblank_event *event = crtc->state->event;
301 	struct drm_plane_state *new_state = pipe->plane.state;
302 	struct drm_framebuffer *fb = new_state->fb;
303 	struct drm_framebuffer *old_fb = old_state->fb;
304 	struct drm_crtc *old_crtc = old_state->crtc;
305 	bool mode_changed = false;
306 
307 	if (old_fb && old_fb->format != fb->format)
308 		mode_changed = true;
309 	else if (old_crtc != crtc)
310 		mode_changed = true;
311 
312 	imx_lcdc_update_hw_registers(pipe, old_state, mode_changed);
313 
314 	if (event) {
315 		crtc->state->event = NULL;
316 
317 		spin_lock_irq(&crtc->dev->event_lock);
318 
319 		if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
320 			drm_crtc_arm_vblank_event(crtc, event);
321 		else
322 			drm_crtc_send_vblank_event(crtc, event);
323 
324 		spin_unlock_irq(&crtc->dev->event_lock);
325 	}
326 }
327 
328 static const struct drm_simple_display_pipe_funcs imx_lcdc_pipe_funcs = {
329 	.enable = imx_lcdc_pipe_enable,
330 	.disable = imx_lcdc_pipe_disable,
331 	.check = imx_lcdc_pipe_check,
332 	.update = imx_lcdc_pipe_update,
333 };
334 
335 static const struct drm_mode_config_funcs imx_lcdc_mode_config_funcs = {
336 	.fb_create = drm_gem_fb_create_with_dirty,
337 	.atomic_check = drm_atomic_helper_check,
338 	.atomic_commit = drm_atomic_helper_commit,
339 };
340 
341 static const struct drm_mode_config_helper_funcs imx_lcdc_mode_config_helpers = {
342 	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
343 };
344 
345 DEFINE_DRM_GEM_DMA_FOPS(imx_lcdc_drm_fops);
346 
347 static struct drm_driver imx_lcdc_drm_driver = {
348 	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
349 	.fops = &imx_lcdc_drm_fops,
350 	DRM_GEM_DMA_DRIVER_OPS_VMAP,
351 	.name = "imx-lcdc",
352 	.desc = "i.MX LCDC driver",
353 	.date = "20200716",
354 };
355 
356 static const struct of_device_id imx_lcdc_of_dev_id[] = {
357 	{
358 		.compatible = "fsl,imx21-lcdc",
359 	},
360 	{
361 		.compatible = "fsl,imx25-lcdc",
362 	},
363 	{ /* sentinel */ }
364 };
365 MODULE_DEVICE_TABLE(of, imx_lcdc_of_dev_id);
366 
imx_lcdc_irq_handler(int irq,void * arg)367 static irqreturn_t imx_lcdc_irq_handler(int irq, void *arg)
368 {
369 	struct imx_lcdc *lcdc = arg;
370 	struct drm_crtc *crtc = &lcdc->pipe.crtc;
371 	unsigned int status;
372 
373 	status = readl(lcdc->base + IMX21LCDC_LISR);
374 
375 	if (status & INTR_EOF) {
376 		drm_crtc_handle_vblank(crtc);
377 		return IRQ_HANDLED;
378 	}
379 
380 	return IRQ_NONE;
381 }
382 
imx_lcdc_probe(struct platform_device * pdev)383 static int imx_lcdc_probe(struct platform_device *pdev)
384 {
385 	struct imx_lcdc *lcdc;
386 	struct drm_device *drm;
387 	struct drm_bridge *bridge;
388 	int irq;
389 	int ret;
390 	struct device *dev = &pdev->dev;
391 
392 	lcdc = devm_drm_dev_alloc(dev, &imx_lcdc_drm_driver,
393 				  struct imx_lcdc, drm);
394 	if (IS_ERR(lcdc))
395 		return PTR_ERR(lcdc);
396 
397 	drm = &lcdc->drm;
398 
399 	lcdc->base = devm_platform_ioremap_resource(pdev, 0);
400 	if (IS_ERR(lcdc->base))
401 		return dev_err_probe(dev, PTR_ERR(lcdc->base), "Cannot get IO memory\n");
402 
403 	bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
404 	if (IS_ERR(bridge))
405 		return dev_err_probe(dev, PTR_ERR(bridge), "Failed to find bridge\n");
406 
407 	/* Get Clocks */
408 	lcdc->clk_ipg = devm_clk_get(dev, "ipg");
409 	if (IS_ERR(lcdc->clk_ipg))
410 		return dev_err_probe(dev, PTR_ERR(lcdc->clk_ipg), "Failed to get %s clk\n", "ipg");
411 
412 	lcdc->clk_ahb = devm_clk_get(dev, "ahb");
413 	if (IS_ERR(lcdc->clk_ahb))
414 		return dev_err_probe(dev, PTR_ERR(lcdc->clk_ahb), "Failed to get %s clk\n", "ahb");
415 
416 	lcdc->clk_per = devm_clk_get(dev, "per");
417 	if (IS_ERR(lcdc->clk_per))
418 		return dev_err_probe(dev, PTR_ERR(lcdc->clk_per), "Failed to get %s clk\n", "per");
419 
420 	ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
421 	if (ret)
422 		return dev_err_probe(dev, ret, "Cannot set DMA Mask\n");
423 
424 	/* Modeset init */
425 	ret = drmm_mode_config_init(drm);
426 	if (ret)
427 		return dev_err_probe(dev, ret, "Cannot initialize mode configuration structure\n");
428 
429 	/* CRTC, Plane, Encoder */
430 	ret = drm_simple_display_pipe_init(drm, &lcdc->pipe,
431 					   &imx_lcdc_pipe_funcs,
432 					   imx_lcdc_formats,
433 					   ARRAY_SIZE(imx_lcdc_formats), NULL, NULL);
434 	if (ret < 0)
435 		return dev_err_probe(drm->dev, ret, "Cannot setup simple display pipe\n");
436 
437 	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
438 	if (ret < 0)
439 		return dev_err_probe(drm->dev, ret, "Failed to initialize vblank\n");
440 
441 	ret = drm_bridge_attach(&lcdc->pipe.encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
442 	if (ret)
443 		return dev_err_probe(drm->dev, ret, "Cannot attach bridge\n");
444 
445 	lcdc->connector = drm_bridge_connector_init(drm, &lcdc->pipe.encoder);
446 	if (IS_ERR(lcdc->connector))
447 		return dev_err_probe(drm->dev, PTR_ERR(lcdc->connector), "Cannot init bridge connector\n");
448 
449 	drm_connector_attach_encoder(lcdc->connector, &lcdc->pipe.encoder);
450 
451 	/*
452 	 * The LCDC controller does not have an enable bit. The
453 	 * controller starts directly when the clocks are enabled.
454 	 * If the clocks are enabled when the controller is not yet
455 	 * programmed with proper register values (enabled at the
456 	 * bootloader, for example) then it just goes into some undefined
457 	 * state.
458 	 * To avoid this issue, let's enable and disable LCDC IPG,
459 	 * PER and AHB clock so that we force some kind of 'reset'
460 	 * to the LCDC block.
461 	 */
462 
463 	ret = clk_prepare_enable(lcdc->clk_ipg);
464 	if (ret)
465 		return dev_err_probe(dev, ret, "Cannot enable ipg clock\n");
466 	clk_disable_unprepare(lcdc->clk_ipg);
467 
468 	ret = clk_prepare_enable(lcdc->clk_per);
469 	if (ret)
470 		return dev_err_probe(dev, ret, "Cannot enable per clock\n");
471 	clk_disable_unprepare(lcdc->clk_per);
472 
473 	ret = clk_prepare_enable(lcdc->clk_ahb);
474 	if (ret)
475 		return dev_err_probe(dev, ret, "Cannot enable ahb clock\n");
476 	clk_disable_unprepare(lcdc->clk_ahb);
477 
478 	drm->mode_config.min_width = LCDC_MIN_XRES;
479 	drm->mode_config.max_width = LCDC_MAX_XRES;
480 	drm->mode_config.min_height = LCDC_MIN_YRES;
481 	drm->mode_config.max_height = LCDC_MAX_YRES;
482 	drm->mode_config.preferred_depth = 16;
483 	drm->mode_config.funcs = &imx_lcdc_mode_config_funcs;
484 	drm->mode_config.helper_private = &imx_lcdc_mode_config_helpers;
485 
486 	drm_mode_config_reset(drm);
487 
488 	irq = platform_get_irq(pdev, 0);
489 	if (irq < 0) {
490 		ret = irq;
491 		return ret;
492 	}
493 
494 	ret = devm_request_irq(dev, irq, imx_lcdc_irq_handler, 0, "imx-lcdc", lcdc);
495 	if (ret < 0)
496 		return dev_err_probe(drm->dev, ret, "Failed to install IRQ handler\n");
497 
498 	platform_set_drvdata(pdev, drm);
499 
500 	ret = drm_dev_register(&lcdc->drm, 0);
501 	if (ret)
502 		return dev_err_probe(dev, ret, "Cannot register device\n");
503 
504 	drm_fbdev_generic_setup(drm, 0);
505 
506 	return 0;
507 }
508 
imx_lcdc_remove(struct platform_device * pdev)509 static int imx_lcdc_remove(struct platform_device *pdev)
510 {
511 	struct drm_device *drm = platform_get_drvdata(pdev);
512 
513 	drm_dev_unregister(drm);
514 	drm_atomic_helper_shutdown(drm);
515 
516 	return 0;
517 }
518 
imx_lcdc_shutdown(struct platform_device * pdev)519 static void imx_lcdc_shutdown(struct platform_device *pdev)
520 {
521 	drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
522 }
523 
524 static struct platform_driver imx_lcdc_driver = {
525 	.driver = {
526 		.name = "imx-lcdc",
527 		.of_match_table = imx_lcdc_of_dev_id,
528 	},
529 	.probe = imx_lcdc_probe,
530 	.remove = imx_lcdc_remove,
531 	.shutdown = imx_lcdc_shutdown,
532 };
533 module_platform_driver(imx_lcdc_driver);
534 
535 MODULE_AUTHOR("Marian Cichy <M.Cichy@pengutronix.de>");
536 MODULE_DESCRIPTION("Freescale i.MX LCDC driver");
537 MODULE_LICENSE("GPL");
538