xref: /openbmc/u-boot/arch/arm/mach-imx/iomux-v3.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Based on the iomux-v3.c from Linux kernel:
4  * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
5  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
6  *                       <armlinux@phytec.de>
7  *
8  * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
9  */
10 #include <common.h>
11 #include <asm/io.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <asm/mach-imx/sys_proto.h>
15 
16 static void *base = (void *)IOMUXC_BASE_ADDR;
17 
18 /*
19  * configures a single pad in the iomuxer
20  */
imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)21 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
22 {
23 	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
24 	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
25 	u32 sel_input_ofs =
26 		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
27 	u32 sel_input =
28 		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
29 	u32 pad_ctrl_ofs =
30 		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
31 	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
32 
33 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
34 	/* Check whether LVE bit needs to be set */
35 	if (pad_ctrl & PAD_CTL_LVE) {
36 		pad_ctrl &= ~PAD_CTL_LVE;
37 		pad_ctrl |= PAD_CTL_LVE_BIT;
38 	}
39 #endif
40 
41 #ifdef CONFIG_IOMUX_LPSR
42 	u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
43 
44 #ifdef CONFIG_MX7
45 	if (lpsr == IOMUX_CONFIG_LPSR) {
46 		base = (void *)IOMUXC_LPSR_BASE_ADDR;
47 		mux_mode &= ~IOMUX_CONFIG_LPSR;
48 		/* set daisy chain sel_input */
49 		if (sel_input_ofs)
50 			sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
51 	}
52 #else
53 	if (is_mx6ull() || is_mx6sll()) {
54 		if (lpsr == IOMUX_CONFIG_LPSR) {
55 			base = (void *)IOMUXC_SNVS_BASE_ADDR;
56 			mux_mode &= ~IOMUX_CONFIG_LPSR;
57 		}
58 	}
59 #endif
60 #endif
61 
62 	if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
63 		__raw_writel(mux_mode, base + mux_ctrl_ofs);
64 
65 	if (sel_input_ofs)
66 		__raw_writel(sel_input, base + sel_input_ofs);
67 
68 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
69 	if (!(pad_ctrl & NO_PAD_CTRL))
70 		__raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
71 			base + pad_ctrl_ofs);
72 #else
73 	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
74 		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
75 #if defined(CONFIG_MX6SLL)
76 	else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
77 		clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
78 #endif
79 #endif
80 
81 #ifdef CONFIG_IOMUX_LPSR
82 	if (lpsr == IOMUX_CONFIG_LPSR)
83 		base = (void *)IOMUXC_BASE_ADDR;
84 #endif
85 
86 }
87 
88 /* configures a list of pads within declared with IOMUX_PADS macro */
imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const * pad_list,unsigned count)89 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
90 				      unsigned count)
91 {
92 	iomux_v3_cfg_t const *p = pad_list;
93 	int stride;
94 	int i;
95 
96 #if defined(CONFIG_MX6QDL)
97 	stride = 2;
98 	if (!is_mx6dq() && !is_mx6dqp())
99 		p += 1;
100 #else
101 	stride = 1;
102 #endif
103 	for (i = 0; i < count; i++) {
104 		imx_iomux_v3_setup_pad(*p);
105 		p += stride;
106 	}
107 }
108 
imx_iomux_set_gpr_register(int group,int start_bit,int num_bits,int value)109 void imx_iomux_set_gpr_register(int group, int start_bit,
110 					int num_bits, int value)
111 {
112 	int i = 0;
113 	u32 reg;
114 	reg = readl(base + group * 4);
115 	while (num_bits) {
116 		reg &= ~(1<<(start_bit + i));
117 		i++;
118 		num_bits--;
119 	}
120 	reg |= (value << start_bit);
121 	writel(reg, base + group * 4);
122 }
123 
124 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
imx_iomux_gpio_set_direction(unsigned int gpio,unsigned int direction)125 void imx_iomux_gpio_set_direction(unsigned int gpio,
126 				unsigned int direction)
127 {
128 	u32 reg;
129 	/*
130 	 * Only on Vybrid the input/output buffer enable flags
131 	 * are part of the shared mux/conf register.
132 	 */
133 	reg = readl(base + (gpio << 2));
134 
135 	if (direction)
136 		reg |= 0x2;
137 	else
138 		reg &= ~0x2;
139 
140 	writel(reg, base + (gpio << 2));
141 }
142 
imx_iomux_gpio_get_function(unsigned int gpio,u32 * gpio_state)143 void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
144 {
145 	*gpio_state = readl(base + (gpio << 2)) &
146 		((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
147 }
148 #endif
149