1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/i2c/busses/i2c-ibm_iic.c
4 *
5 * Support for the IIC peripheral on IBM PPC 4xx
6 *
7 * Copyright (c) 2003, 2004 Zultys Technologies.
8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
9 *
10 * Copyright (c) 2008 PIKA Technologies
11 * Sean MacLennan <smaclennan@pikatech.com>
12 *
13 * Based on original work by
14 * Ian DaSilva <idasilva@mvista.com>
15 * Armin Kuster <akuster@mvista.com>
16 * Matt Porter <mporter@mvista.com>
17 *
18 * Copyright 2000-2003 MontaVista Software Inc.
19 *
20 * Original driver version was highly leveraged from i2c-elektor.c
21 *
22 * Copyright 1995-97 Simon G. Vogl
23 * 1998-99 Hans Berglund
24 *
25 * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
26 * and even Frodo Looijaard <frodol@dds.nl>
27 */
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/ioport.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched/signal.h>
36
37 #include <asm/irq.h>
38 #include <linux/io.h>
39 #include <linux/i2c.h>
40 #include <linux/of.h>
41 #include <linux/of_address.h>
42 #include <linux/of_irq.h>
43 #include <linux/platform_device.h>
44
45 #include "i2c-ibm_iic.h"
46
47 #define DRIVER_VERSION "2.2"
48
49 MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
50 MODULE_LICENSE("GPL");
51
52 static bool iic_force_poll;
53 module_param(iic_force_poll, bool, 0);
54 MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
55
56 static bool iic_force_fast;
57 module_param(iic_force_fast, bool, 0);
58 MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
59
60 #define DBG_LEVEL 0
61
62 #ifdef DBG
63 #undef DBG
64 #endif
65
66 #ifdef DBG2
67 #undef DBG2
68 #endif
69
70 #if DBG_LEVEL > 0
71 # define DBG(f,x...) printk(KERN_DEBUG "ibm-iic" f, ##x)
72 #else
73 # define DBG(f,x...) ((void)0)
74 #endif
75 #if DBG_LEVEL > 1
76 # define DBG2(f,x...) DBG(f, ##x)
77 #else
78 # define DBG2(f,x...) ((void)0)
79 #endif
80 #if DBG_LEVEL > 2
dump_iic_regs(const char * header,struct ibm_iic_private * dev)81 static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
82 {
83 volatile struct iic_regs __iomem *iic = dev->vaddr;
84 printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
85 printk(KERN_DEBUG
86 " cntl = 0x%02x, mdcntl = 0x%02x\n"
87 " sts = 0x%02x, extsts = 0x%02x\n"
88 " clkdiv = 0x%02x, xfrcnt = 0x%02x\n"
89 " xtcntlss = 0x%02x, directcntl = 0x%02x\n",
90 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
91 in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
92 in_8(&iic->xtcntlss), in_8(&iic->directcntl));
93 }
94 # define DUMP_REGS(h,dev) dump_iic_regs((h),(dev))
95 #else
96 # define DUMP_REGS(h,dev) ((void)0)
97 #endif
98
99 /* Bus timings (in ns) for bit-banging */
100 static struct ibm_iic_timings {
101 unsigned int hd_sta;
102 unsigned int su_sto;
103 unsigned int low;
104 unsigned int high;
105 unsigned int buf;
106 } timings [] = {
107 /* Standard mode (100 KHz) */
108 {
109 .hd_sta = 4000,
110 .su_sto = 4000,
111 .low = 4700,
112 .high = 4000,
113 .buf = 4700,
114 },
115 /* Fast mode (400 KHz) */
116 {
117 .hd_sta = 600,
118 .su_sto = 600,
119 .low = 1300,
120 .high = 600,
121 .buf = 1300,
122 }};
123
124 /* Enable/disable interrupt generation */
iic_interrupt_mode(struct ibm_iic_private * dev,int enable)125 static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
126 {
127 out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
128 }
129
130 /*
131 * Initialize IIC interface.
132 */
iic_dev_init(struct ibm_iic_private * dev)133 static void iic_dev_init(struct ibm_iic_private* dev)
134 {
135 volatile struct iic_regs __iomem *iic = dev->vaddr;
136
137 DBG("%d: init\n", dev->idx);
138
139 /* Clear master address */
140 out_8(&iic->lmadr, 0);
141 out_8(&iic->hmadr, 0);
142
143 /* Clear slave address */
144 out_8(&iic->lsadr, 0);
145 out_8(&iic->hsadr, 0);
146
147 /* Clear status & extended status */
148 out_8(&iic->sts, STS_SCMP | STS_IRQA);
149 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
150 | EXTSTS_ICT | EXTSTS_XFRA);
151
152 /* Set clock divider */
153 out_8(&iic->clkdiv, dev->clckdiv);
154
155 /* Clear transfer count */
156 out_8(&iic->xfrcnt, 0);
157
158 /* Clear extended control and status */
159 out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
160 | XTCNTLSS_SWS);
161
162 /* Clear control register */
163 out_8(&iic->cntl, 0);
164
165 /* Enable interrupts if possible */
166 iic_interrupt_mode(dev, dev->irq >= 0);
167
168 /* Set mode control */
169 out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
170 | (dev->fast_mode ? MDCNTL_FSM : 0));
171
172 DUMP_REGS("iic_init", dev);
173 }
174
175 /*
176 * Reset IIC interface
177 */
iic_dev_reset(struct ibm_iic_private * dev)178 static void iic_dev_reset(struct ibm_iic_private* dev)
179 {
180 volatile struct iic_regs __iomem *iic = dev->vaddr;
181 int i;
182 u8 dc;
183
184 DBG("%d: soft reset\n", dev->idx);
185 DUMP_REGS("reset", dev);
186
187 /* Place chip in the reset state */
188 out_8(&iic->xtcntlss, XTCNTLSS_SRST);
189
190 /* Check if bus is free */
191 dc = in_8(&iic->directcntl);
192 if (!DIRCTNL_FREE(dc)){
193 DBG("%d: trying to regain bus control\n", dev->idx);
194
195 /* Try to set bus free state */
196 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
197
198 /* Wait until we regain bus control */
199 for (i = 0; i < 100; ++i){
200 dc = in_8(&iic->directcntl);
201 if (DIRCTNL_FREE(dc))
202 break;
203
204 /* Toggle SCL line */
205 dc ^= DIRCNTL_SCC;
206 out_8(&iic->directcntl, dc);
207 udelay(10);
208 dc ^= DIRCNTL_SCC;
209 out_8(&iic->directcntl, dc);
210
211 /* be nice */
212 cond_resched();
213 }
214 }
215
216 /* Remove reset */
217 out_8(&iic->xtcntlss, 0);
218
219 /* Reinitialize interface */
220 iic_dev_init(dev);
221 }
222
223 /*
224 * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
225 */
226
227 /* Wait for SCL and/or SDA to be high */
iic_dc_wait(volatile struct iic_regs __iomem * iic,u8 mask)228 static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
229 {
230 unsigned long x = jiffies + HZ / 28 + 2;
231 while ((in_8(&iic->directcntl) & mask) != mask){
232 if (unlikely(time_after(jiffies, x)))
233 return -1;
234 cond_resched();
235 }
236 return 0;
237 }
238
iic_smbus_quick(struct ibm_iic_private * dev,const struct i2c_msg * p)239 static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
240 {
241 volatile struct iic_regs __iomem *iic = dev->vaddr;
242 const struct ibm_iic_timings *t = &timings[dev->fast_mode ? 1 : 0];
243 u8 mask, v, sda;
244 int i, res;
245
246 /* Only 7-bit addresses are supported */
247 if (unlikely(p->flags & I2C_M_TEN)){
248 DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
249 dev->idx);
250 return -EINVAL;
251 }
252
253 DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
254
255 /* Reset IIC interface */
256 out_8(&iic->xtcntlss, XTCNTLSS_SRST);
257
258 /* Wait for bus to become free */
259 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
260 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
261 goto err;
262 ndelay(t->buf);
263
264 /* START */
265 out_8(&iic->directcntl, DIRCNTL_SCC);
266 sda = 0;
267 ndelay(t->hd_sta);
268
269 /* Send address */
270 v = i2c_8bit_addr_from_msg(p);
271 for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
272 out_8(&iic->directcntl, sda);
273 ndelay(t->low / 2);
274 sda = (v & mask) ? DIRCNTL_SDAC : 0;
275 out_8(&iic->directcntl, sda);
276 ndelay(t->low / 2);
277
278 out_8(&iic->directcntl, DIRCNTL_SCC | sda);
279 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
280 goto err;
281 ndelay(t->high);
282 }
283
284 /* ACK */
285 out_8(&iic->directcntl, sda);
286 ndelay(t->low / 2);
287 out_8(&iic->directcntl, DIRCNTL_SDAC);
288 ndelay(t->low / 2);
289 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
290 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
291 goto err;
292 res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
293 ndelay(t->high);
294
295 /* STOP */
296 out_8(&iic->directcntl, 0);
297 ndelay(t->low);
298 out_8(&iic->directcntl, DIRCNTL_SCC);
299 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
300 goto err;
301 ndelay(t->su_sto);
302 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
303
304 ndelay(t->buf);
305
306 DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
307 out:
308 /* Remove reset */
309 out_8(&iic->xtcntlss, 0);
310
311 /* Reinitialize interface */
312 iic_dev_init(dev);
313
314 return res;
315 err:
316 DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
317 res = -EREMOTEIO;
318 goto out;
319 }
320
321 /*
322 * IIC interrupt handler
323 */
iic_handler(int irq,void * dev_id)324 static irqreturn_t iic_handler(int irq, void *dev_id)
325 {
326 struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
327 volatile struct iic_regs __iomem *iic = dev->vaddr;
328
329 DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
330 dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
331
332 /* Acknowledge IRQ and wakeup iic_wait_for_tc */
333 out_8(&iic->sts, STS_IRQA | STS_SCMP);
334 wake_up_interruptible(&dev->wq);
335
336 return IRQ_HANDLED;
337 }
338
339 /*
340 * Get master transfer result and clear errors if any.
341 * Returns the number of actually transferred bytes or error (<0)
342 */
iic_xfer_result(struct ibm_iic_private * dev)343 static int iic_xfer_result(struct ibm_iic_private* dev)
344 {
345 volatile struct iic_regs __iomem *iic = dev->vaddr;
346
347 if (unlikely(in_8(&iic->sts) & STS_ERR)){
348 DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
349 in_8(&iic->extsts));
350
351 /* Clear errors and possible pending IRQs */
352 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
353 EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
354
355 /* Flush master data buffer */
356 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
357
358 /* Is bus free?
359 * If error happened during combined xfer
360 * IIC interface is usually stuck in some strange
361 * state, the only way out - soft reset.
362 */
363 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
364 DBG("%d: bus is stuck, resetting\n", dev->idx);
365 iic_dev_reset(dev);
366 }
367 return -EREMOTEIO;
368 }
369 else
370 return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
371 }
372
373 /*
374 * Try to abort active transfer.
375 */
iic_abort_xfer(struct ibm_iic_private * dev)376 static void iic_abort_xfer(struct ibm_iic_private* dev)
377 {
378 volatile struct iic_regs __iomem *iic = dev->vaddr;
379 unsigned long x;
380
381 DBG("%d: iic_abort_xfer\n", dev->idx);
382
383 out_8(&iic->cntl, CNTL_HMT);
384
385 /*
386 * Wait for the abort command to complete.
387 * It's not worth to be optimized, just poll (timeout >= 1 tick)
388 */
389 x = jiffies + 2;
390 while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
391 if (time_after(jiffies, x)){
392 DBG("%d: abort timeout, resetting...\n", dev->idx);
393 iic_dev_reset(dev);
394 return;
395 }
396 schedule();
397 }
398
399 /* Just to clear errors */
400 iic_xfer_result(dev);
401 }
402
403 /*
404 * Wait for master transfer to complete.
405 * It puts current process to sleep until we get interrupt or timeout expires.
406 * Returns the number of transferred bytes or error (<0)
407 */
iic_wait_for_tc(struct ibm_iic_private * dev)408 static int iic_wait_for_tc(struct ibm_iic_private* dev){
409
410 volatile struct iic_regs __iomem *iic = dev->vaddr;
411 int ret = 0;
412
413 if (dev->irq >= 0){
414 /* Interrupt mode */
415 ret = wait_event_interruptible_timeout(dev->wq,
416 !(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
417
418 if (unlikely(ret < 0))
419 DBG("%d: wait interrupted\n", dev->idx);
420 else if (unlikely(in_8(&iic->sts) & STS_PT)){
421 DBG("%d: wait timeout\n", dev->idx);
422 ret = -ETIMEDOUT;
423 }
424 }
425 else {
426 /* Polling mode */
427 unsigned long x = jiffies + dev->adap.timeout;
428
429 while (in_8(&iic->sts) & STS_PT){
430 if (unlikely(time_after(jiffies, x))){
431 DBG("%d: poll timeout\n", dev->idx);
432 ret = -ETIMEDOUT;
433 break;
434 }
435
436 if (signal_pending(current)){
437 DBG("%d: poll interrupted\n", dev->idx);
438 ret = -ERESTARTSYS;
439 break;
440 }
441 schedule();
442 }
443 }
444
445 if (unlikely(ret < 0))
446 iic_abort_xfer(dev);
447 else
448 ret = iic_xfer_result(dev);
449
450 DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
451
452 return ret;
453 }
454
455 /*
456 * Low level master transfer routine
457 */
iic_xfer_bytes(struct ibm_iic_private * dev,struct i2c_msg * pm,int combined_xfer)458 static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
459 int combined_xfer)
460 {
461 volatile struct iic_regs __iomem *iic = dev->vaddr;
462 char* buf = pm->buf;
463 int i, j, loops, ret = 0;
464 int len = pm->len;
465
466 u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
467 if (pm->flags & I2C_M_RD)
468 cntl |= CNTL_RW;
469
470 loops = (len + 3) / 4;
471 for (i = 0; i < loops; ++i, len -= 4){
472 int count = len > 4 ? 4 : len;
473 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
474
475 if (!(cntl & CNTL_RW))
476 for (j = 0; j < count; ++j)
477 out_8((void __iomem *)&iic->mdbuf, *buf++);
478
479 if (i < loops - 1)
480 cmd |= CNTL_CHT;
481 else if (combined_xfer)
482 cmd |= CNTL_RPST;
483
484 DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
485
486 /* Start transfer */
487 out_8(&iic->cntl, cmd);
488
489 /* Wait for completion */
490 ret = iic_wait_for_tc(dev);
491
492 if (unlikely(ret < 0))
493 break;
494 else if (unlikely(ret != count)){
495 DBG("%d: xfer_bytes, requested %d, transferred %d\n",
496 dev->idx, count, ret);
497
498 /* If it's not a last part of xfer, abort it */
499 if (combined_xfer || (i < loops - 1))
500 iic_abort_xfer(dev);
501
502 ret = -EREMOTEIO;
503 break;
504 }
505
506 if (cntl & CNTL_RW)
507 for (j = 0; j < count; ++j)
508 *buf++ = in_8((void __iomem *)&iic->mdbuf);
509 }
510
511 return ret > 0 ? 0 : ret;
512 }
513
514 /*
515 * Set target slave address for master transfer
516 */
iic_address(struct ibm_iic_private * dev,struct i2c_msg * msg)517 static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
518 {
519 volatile struct iic_regs __iomem *iic = dev->vaddr;
520 u16 addr = msg->addr;
521
522 DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
523 addr, msg->flags & I2C_M_TEN ? 10 : 7);
524
525 if (msg->flags & I2C_M_TEN){
526 out_8(&iic->cntl, CNTL_AMD);
527 out_8(&iic->lmadr, addr);
528 out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
529 }
530 else {
531 out_8(&iic->cntl, 0);
532 out_8(&iic->lmadr, addr << 1);
533 }
534 }
535
iic_invalid_address(const struct i2c_msg * p)536 static inline int iic_invalid_address(const struct i2c_msg* p)
537 {
538 return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
539 }
540
iic_address_neq(const struct i2c_msg * p1,const struct i2c_msg * p2)541 static inline int iic_address_neq(const struct i2c_msg* p1,
542 const struct i2c_msg* p2)
543 {
544 return (p1->addr != p2->addr)
545 || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
546 }
547
548 /*
549 * Generic master transfer entrypoint.
550 * Returns the number of processed messages or error (<0)
551 */
iic_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)552 static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
553 {
554 struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
555 volatile struct iic_regs __iomem *iic = dev->vaddr;
556 int i, ret = 0;
557
558 DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
559
560 /* Check the sanity of the passed messages.
561 * Uhh, generic i2c layer is more suitable place for such code...
562 */
563 if (unlikely(iic_invalid_address(&msgs[0]))){
564 DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
565 msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
566 return -EINVAL;
567 }
568 for (i = 0; i < num; ++i){
569 if (unlikely(msgs[i].len <= 0)){
570 if (num == 1 && !msgs[0].len){
571 /* Special case for I2C_SMBUS_QUICK emulation.
572 * IBM IIC doesn't support 0-length transactions
573 * so we have to emulate them using bit-banging.
574 */
575 return iic_smbus_quick(dev, &msgs[0]);
576 }
577 DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
578 msgs[i].len, i);
579 return -EINVAL;
580 }
581 if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
582 DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
583 return -EINVAL;
584 }
585 }
586
587 /* Check bus state */
588 if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
589 DBG("%d: iic_xfer, bus is not free\n", dev->idx);
590
591 /* Usually it means something serious has happened.
592 * We *cannot* have unfinished previous transfer
593 * so it doesn't make any sense to try to stop it.
594 * Probably we were not able to recover from the
595 * previous error.
596 * The only *reasonable* thing I can think of here
597 * is soft reset. --ebs
598 */
599 iic_dev_reset(dev);
600
601 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
602 DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
603 return -EREMOTEIO;
604 }
605 }
606 else {
607 /* Flush master data buffer (just in case) */
608 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
609 }
610
611 /* Load slave address */
612 iic_address(dev, &msgs[0]);
613
614 /* Do real transfer */
615 for (i = 0; i < num && !ret; ++i)
616 ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
617
618 return ret < 0 ? ret : num;
619 }
620
iic_func(struct i2c_adapter * adap)621 static u32 iic_func(struct i2c_adapter *adap)
622 {
623 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
624 }
625
626 static const struct i2c_algorithm iic_algo = {
627 .master_xfer = iic_xfer,
628 .functionality = iic_func
629 };
630
631 /*
632 * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
633 */
iic_clckdiv(unsigned int opb)634 static inline u8 iic_clckdiv(unsigned int opb)
635 {
636 /* Compatibility kludge, should go away after all cards
637 * are fixed to fill correct value for opbfreq.
638 * Previous driver version used hardcoded divider value 4,
639 * it corresponds to OPB frequency from the range (40, 50] MHz
640 */
641 if (!opb){
642 printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
643 " fix your board specific setup\n");
644 opb = 50000000;
645 }
646
647 /* Convert to MHz */
648 opb /= 1000000;
649
650 if (opb < 20 || opb > 150){
651 printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
652 opb);
653 opb = opb < 20 ? 20 : 150;
654 }
655 return (u8)((opb + 9) / 10 - 1);
656 }
657
iic_request_irq(struct platform_device * ofdev,struct ibm_iic_private * dev)658 static int iic_request_irq(struct platform_device *ofdev,
659 struct ibm_iic_private *dev)
660 {
661 struct device_node *np = ofdev->dev.of_node;
662 int irq;
663
664 if (iic_force_poll)
665 return 0;
666
667 irq = irq_of_parse_and_map(np, 0);
668 if (!irq) {
669 dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
670 return 0;
671 }
672
673 /* Disable interrupts until we finish initialization, assumes
674 * level-sensitive IRQ setup...
675 */
676 iic_interrupt_mode(dev, 0);
677 if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
678 dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
679 /* Fallback to the polling mode */
680 return 0;
681 }
682
683 return irq;
684 }
685
686 /*
687 * Register single IIC interface
688 */
iic_probe(struct platform_device * ofdev)689 static int iic_probe(struct platform_device *ofdev)
690 {
691 struct device_node *np = ofdev->dev.of_node;
692 struct ibm_iic_private *dev;
693 struct i2c_adapter *adap;
694 const u32 *freq;
695 int ret;
696
697 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
698 if (!dev)
699 return -ENOMEM;
700
701 platform_set_drvdata(ofdev, dev);
702
703 dev->vaddr = of_iomap(np, 0);
704 if (dev->vaddr == NULL) {
705 dev_err(&ofdev->dev, "failed to iomap device\n");
706 ret = -ENXIO;
707 goto error_cleanup;
708 }
709
710 init_waitqueue_head(&dev->wq);
711
712 dev->irq = iic_request_irq(ofdev, dev);
713 if (!dev->irq)
714 dev_warn(&ofdev->dev, "using polling mode\n");
715
716 /* Board specific settings */
717 if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
718 dev->fast_mode = 1;
719
720 freq = of_get_property(np, "clock-frequency", NULL);
721 if (freq == NULL) {
722 freq = of_get_property(np->parent, "clock-frequency", NULL);
723 if (freq == NULL) {
724 dev_err(&ofdev->dev, "Unable to get bus frequency\n");
725 ret = -EINVAL;
726 goto error_cleanup;
727 }
728 }
729
730 dev->clckdiv = iic_clckdiv(*freq);
731 dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
732
733 /* Initialize IIC interface */
734 iic_dev_init(dev);
735
736 /* Register it with i2c layer */
737 adap = &dev->adap;
738 adap->dev.parent = &ofdev->dev;
739 adap->dev.of_node = of_node_get(np);
740 strscpy(adap->name, "IBM IIC", sizeof(adap->name));
741 i2c_set_adapdata(adap, dev);
742 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
743 adap->algo = &iic_algo;
744 adap->timeout = HZ;
745
746 ret = i2c_add_adapter(adap);
747 if (ret < 0)
748 goto error_cleanup;
749
750 dev_info(&ofdev->dev, "using %s mode\n",
751 dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
752
753 return 0;
754
755 error_cleanup:
756 if (dev->irq) {
757 iic_interrupt_mode(dev, 0);
758 free_irq(dev->irq, dev);
759 }
760
761 if (dev->vaddr)
762 iounmap(dev->vaddr);
763
764 kfree(dev);
765 return ret;
766 }
767
768 /*
769 * Cleanup initialized IIC interface
770 */
iic_remove(struct platform_device * ofdev)771 static void iic_remove(struct platform_device *ofdev)
772 {
773 struct ibm_iic_private *dev = platform_get_drvdata(ofdev);
774
775 i2c_del_adapter(&dev->adap);
776
777 if (dev->irq) {
778 iic_interrupt_mode(dev, 0);
779 free_irq(dev->irq, dev);
780 }
781
782 iounmap(dev->vaddr);
783 kfree(dev);
784 }
785
786 static const struct of_device_id ibm_iic_match[] = {
787 { .compatible = "ibm,iic", },
788 {}
789 };
790 MODULE_DEVICE_TABLE(of, ibm_iic_match);
791
792 static struct platform_driver ibm_iic_driver = {
793 .driver = {
794 .name = "ibm-iic",
795 .of_match_table = ibm_iic_match,
796 },
797 .probe = iic_probe,
798 .remove_new = iic_remove,
799 };
800
801 module_platform_driver(ibm_iic_driver);
802