1 /*
2 * QEMU IDE Emulation: MacIO support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/irq.h"
28 #include "hw/ppc/mac_dbdma.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "qemu/module.h"
32 #include "hw/misc/macio/macio.h"
33 #include "sysemu/block-backend.h"
34 #include "sysemu/dma.h"
35
36 #include "ide-internal.h"
37
38 /* debug MACIO */
39 // #define DEBUG_MACIO
40
41 #ifdef DEBUG_MACIO
42 static const int debug_macio = 1;
43 #else
44 static const int debug_macio = 0;
45 #endif
46
47 #define MACIO_DPRINTF(fmt, ...) do { \
48 if (debug_macio) { \
49 printf(fmt , ## __VA_ARGS__); \
50 } \
51 } while (0)
52
53
54 /***********************************************************/
55 /* MacIO based PowerPC IDE */
56
57 #define MACIO_PAGE_SIZE 4096
58
pmac_ide_atapi_transfer_cb(void * opaque,int ret)59 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
60 {
61 DBDMA_io *io = opaque;
62 MACIOIDEState *m = io->opaque;
63 IDEState *s = ide_bus_active_if(&m->bus);
64 int64_t offset;
65
66 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
67
68 if (ret < 0) {
69 MACIO_DPRINTF("DMA error: %d\n", ret);
70 qemu_sglist_destroy(&s->sg);
71 ide_atapi_io_error(s, ret);
72 goto done;
73 }
74
75 if (!m->dma_active) {
76 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
77 s->nsector, io->len, s->status);
78 /* data not ready yet, wait for the channel to get restarted */
79 io->processing = false;
80 return;
81 }
82
83 if (s->io_buffer_size <= 0) {
84 MACIO_DPRINTF("End of IDE transfer\n");
85 qemu_sglist_destroy(&s->sg);
86 ide_atapi_cmd_ok(s);
87 m->dma_active = false;
88 goto done;
89 }
90
91 if (io->len == 0) {
92 MACIO_DPRINTF("End of DMA transfer\n");
93 goto done;
94 }
95
96 if (s->lba == -1) {
97 /* Non-block ATAPI transfer - just copy to RAM */
98 s->io_buffer_size = MIN(s->io_buffer_size, io->len);
99 dma_memory_write(&address_space_memory, io->addr, s->io_buffer,
100 s->io_buffer_size, MEMTXATTRS_UNSPECIFIED);
101 io->len = 0;
102 ide_atapi_cmd_ok(s);
103 m->dma_active = false;
104 goto done;
105 }
106
107 /* Calculate current offset */
108 offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
109
110 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
111 &address_space_memory);
112 qemu_sglist_add(&s->sg, io->addr, io->len);
113 s->io_buffer_size -= io->len;
114 s->io_buffer_index += io->len;
115 io->len = 0;
116
117 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
118 pmac_ide_atapi_transfer_cb, io);
119 return;
120
121 done:
122 if (ret < 0) {
123 block_acct_failed(blk_get_stats(s->blk), &s->acct);
124 } else {
125 block_acct_done(blk_get_stats(s->blk), &s->acct);
126 }
127
128 ide_set_inactive(s, false);
129 io->dma_end(opaque);
130 }
131
pmac_ide_transfer_cb(void * opaque,int ret)132 static void pmac_ide_transfer_cb(void *opaque, int ret)
133 {
134 DBDMA_io *io = opaque;
135 MACIOIDEState *m = io->opaque;
136 IDEState *s = ide_bus_active_if(&m->bus);
137 int64_t offset;
138
139 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
140
141 if (ret < 0) {
142 MACIO_DPRINTF("DMA error: %d\n", ret);
143 qemu_sglist_destroy(&s->sg);
144 ide_dma_error(s);
145 goto done;
146 }
147
148 if (!m->dma_active) {
149 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
150 s->nsector, io->len, s->status);
151 /* data not ready yet, wait for the channel to get restarted */
152 io->processing = false;
153 return;
154 }
155
156 if (s->io_buffer_size <= 0) {
157 MACIO_DPRINTF("End of IDE transfer\n");
158 qemu_sglist_destroy(&s->sg);
159 s->status = READY_STAT | SEEK_STAT;
160 ide_bus_set_irq(s->bus);
161 m->dma_active = false;
162 goto done;
163 }
164
165 if (io->len == 0) {
166 MACIO_DPRINTF("End of DMA transfer\n");
167 goto done;
168 }
169
170 /* Calculate number of sectors */
171 offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
172
173 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
174 &address_space_memory);
175 qemu_sglist_add(&s->sg, io->addr, io->len);
176 s->io_buffer_size -= io->len;
177 s->io_buffer_index += io->len;
178 io->len = 0;
179
180 switch (s->dma_cmd) {
181 case IDE_DMA_READ:
182 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
183 pmac_ide_atapi_transfer_cb, io);
184 break;
185 case IDE_DMA_WRITE:
186 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1,
187 pmac_ide_transfer_cb, io);
188 break;
189 case IDE_DMA_TRIM:
190 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg,
191 offset, 0x1, ide_issue_trim, s,
192 pmac_ide_transfer_cb, io,
193 DMA_DIRECTION_TO_DEVICE);
194 break;
195 default:
196 abort();
197 }
198
199 return;
200
201 done:
202 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
203 if (ret < 0) {
204 block_acct_failed(blk_get_stats(s->blk), &s->acct);
205 } else {
206 block_acct_done(blk_get_stats(s->blk), &s->acct);
207 }
208 }
209
210 ide_set_inactive(s, false);
211 io->dma_end(opaque);
212 }
213
pmac_ide_transfer(DBDMA_io * io)214 static void pmac_ide_transfer(DBDMA_io *io)
215 {
216 MACIOIDEState *m = io->opaque;
217 IDEState *s = ide_bus_active_if(&m->bus);
218
219 MACIO_DPRINTF("\n");
220
221 if (s->drive_kind == IDE_CD) {
222 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
223 BLOCK_ACCT_READ);
224
225 pmac_ide_atapi_transfer_cb(io, 0);
226 return;
227 }
228
229 switch (s->dma_cmd) {
230 case IDE_DMA_READ:
231 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
232 BLOCK_ACCT_READ);
233 break;
234 case IDE_DMA_WRITE:
235 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
236 BLOCK_ACCT_WRITE);
237 break;
238 default:
239 break;
240 }
241
242 pmac_ide_transfer_cb(io, 0);
243 }
244
pmac_ide_flush(DBDMA_io * io)245 static void pmac_ide_flush(DBDMA_io *io)
246 {
247 MACIOIDEState *m = io->opaque;
248 IDEState *s = ide_bus_active_if(&m->bus);
249
250 if (s->bus->dma->aiocb) {
251 blk_drain(s->blk);
252 }
253 }
254
255 /* PowerMac IDE memory IO */
pmac_ide_read(void * opaque,hwaddr addr,unsigned size)256 static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
257 {
258 MACIOIDEState *d = opaque;
259 uint64_t retval = 0xffffffff;
260 int reg = addr >> 4;
261
262 switch (reg) {
263 case 0x0:
264 if (size == 1) {
265 retval = ide_data_readw(&d->bus, 0) & 0xFF;
266 } else if (size == 2) {
267 retval = ide_data_readw(&d->bus, 0);
268 } else if (size == 4) {
269 retval = ide_data_readl(&d->bus, 0);
270 }
271 break;
272 case 0x1 ... 0x7:
273 if (size == 1) {
274 retval = ide_ioport_read(&d->bus, reg);
275 }
276 break;
277 case 0x8:
278 case 0x16:
279 if (size == 1) {
280 retval = ide_status_read(&d->bus, 0);
281 }
282 break;
283 case 0x20:
284 if (size == 4) {
285 retval = d->timing_reg;
286 }
287 break;
288 case 0x30:
289 /* This is an interrupt state register that only exists
290 * in the KeyLargo and later variants. Bit 0x8000_0000
291 * latches the DMA interrupt and has to be written to
292 * clear. Bit 0x4000_0000 is an image of the disk
293 * interrupt. MacOS X relies on this and will hang if
294 * we don't provide at least the disk interrupt
295 */
296 if (size == 4) {
297 retval = d->irq_reg;
298 }
299 break;
300 }
301
302 return retval;
303 }
304
305
pmac_ide_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)306 static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
307 unsigned size)
308 {
309 MACIOIDEState *d = opaque;
310 int reg = addr >> 4;
311
312 switch (reg) {
313 case 0x0:
314 if (size == 2) {
315 ide_data_writew(&d->bus, 0, val);
316 } else if (size == 4) {
317 ide_data_writel(&d->bus, 0, val);
318 }
319 break;
320 case 0x1 ... 0x7:
321 if (size == 1) {
322 ide_ioport_write(&d->bus, reg, val);
323 }
324 break;
325 case 0x8:
326 case 0x16:
327 if (size == 1) {
328 ide_ctrl_write(&d->bus, 0, val);
329 }
330 break;
331 case 0x20:
332 if (size == 4) {
333 d->timing_reg = val;
334 }
335 break;
336 case 0x30:
337 if (size == 4) {
338 if (val & 0x80000000u) {
339 d->irq_reg &= 0x7fffffff;
340 }
341 }
342 break;
343 }
344 }
345
346 static const MemoryRegionOps pmac_ide_ops = {
347 .read = pmac_ide_read,
348 .write = pmac_ide_write,
349 .valid.min_access_size = 1,
350 .valid.max_access_size = 4,
351 .endianness = DEVICE_LITTLE_ENDIAN,
352 };
353
354 static const VMStateDescription vmstate_pmac = {
355 .name = "ide",
356 .version_id = 5,
357 .minimum_version_id = 0,
358 .fields = (const VMStateField[]) {
359 VMSTATE_IDE_BUS(bus, MACIOIDEState),
360 VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
361 VMSTATE_BOOL(dma_active, MACIOIDEState),
362 VMSTATE_UINT32(timing_reg, MACIOIDEState),
363 VMSTATE_UINT32(irq_reg, MACIOIDEState),
364 VMSTATE_END_OF_LIST()
365 }
366 };
367
macio_ide_reset(DeviceState * dev)368 static void macio_ide_reset(DeviceState *dev)
369 {
370 MACIOIDEState *d = MACIO_IDE(dev);
371
372 ide_bus_reset(&d->bus);
373 }
374
ide_nop_int(const IDEDMA * dma,bool is_write)375 static int ide_nop_int(const IDEDMA *dma, bool is_write)
376 {
377 return 0;
378 }
379
ide_nop_int32(const IDEDMA * dma,int32_t l)380 static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
381 {
382 return 0;
383 }
384
ide_dbdma_start(const IDEDMA * dma,IDEState * s,BlockCompletionFunc * cb)385 static void ide_dbdma_start(const IDEDMA *dma, IDEState *s,
386 BlockCompletionFunc *cb)
387 {
388 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
389
390 s->io_buffer_index = 0;
391 if (s->drive_kind == IDE_CD) {
392 s->io_buffer_size = s->packet_transfer_size;
393 } else {
394 s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
395 }
396
397 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
398 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
399 s->io_buffer_size, s->io_buffer_index);
400 MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
401 MACIO_DPRINTF("-------------------------\n");
402
403 m->dma_active = true;
404 DBDMA_kick(m->dbdma);
405 }
406
407 static const IDEDMAOps dbdma_ops = {
408 .start_dma = ide_dbdma_start,
409 .prepare_buf = ide_nop_int32,
410 .rw_buf = ide_nop_int,
411 };
412
macio_ide_realizefn(DeviceState * dev,Error ** errp)413 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
414 {
415 MACIOIDEState *s = MACIO_IDE(dev);
416
417 ide_bus_init_output_irq(&s->bus,
418 qdev_get_gpio_in(dev, MACIO_IDE_PMAC_IDE_IRQ));
419
420 /* Register DMA callbacks */
421 s->dma.ops = &dbdma_ops;
422 s->bus.dma = &s->dma;
423 }
424
pmac_ide_irq(void * opaque,int n,int level)425 static void pmac_ide_irq(void *opaque, int n, int level)
426 {
427 MACIOIDEState *s = opaque;
428 uint32_t mask = 0x80000000u >> n;
429
430 /* We need to reflect the IRQ state in the irq register */
431 if (level) {
432 s->irq_reg |= mask;
433 } else {
434 s->irq_reg &= ~mask;
435 }
436
437 if (n) {
438 qemu_set_irq(s->real_ide_irq, level);
439 } else {
440 qemu_set_irq(s->real_dma_irq, level);
441 }
442 }
443
macio_ide_initfn(Object * obj)444 static void macio_ide_initfn(Object *obj)
445 {
446 SysBusDevice *d = SYS_BUS_DEVICE(obj);
447 MACIOIDEState *s = MACIO_IDE(obj);
448
449 ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
450 memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
451 sysbus_init_mmio(d, &s->mem);
452 sysbus_init_irq(d, &s->real_ide_irq);
453 sysbus_init_irq(d, &s->real_dma_irq);
454
455 qdev_init_gpio_in(DEVICE(obj), pmac_ide_irq, MACIO_IDE_PMAC_NIRQS);
456
457 object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA,
458 (Object **) &s->dbdma,
459 qdev_prop_allow_set_link_before_realize, 0);
460 }
461
462 static Property macio_ide_properties[] = {
463 DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0),
464 DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1),
465 DEFINE_PROP_END_OF_LIST(),
466 };
467
macio_ide_class_init(ObjectClass * oc,void * data)468 static void macio_ide_class_init(ObjectClass *oc, void *data)
469 {
470 DeviceClass *dc = DEVICE_CLASS(oc);
471
472 dc->realize = macio_ide_realizefn;
473 dc->reset = macio_ide_reset;
474 device_class_set_props(dc, macio_ide_properties);
475 dc->vmsd = &vmstate_pmac;
476 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
477 }
478
479 static const TypeInfo macio_ide_type_info = {
480 .name = TYPE_MACIO_IDE,
481 .parent = TYPE_SYS_BUS_DEVICE,
482 .instance_size = sizeof(MACIOIDEState),
483 .instance_init = macio_ide_initfn,
484 .class_init = macio_ide_class_init,
485 };
486
macio_ide_register_types(void)487 static void macio_ide_register_types(void)
488 {
489 type_register_static(&macio_ide_type_info);
490 }
491
492 /* hd_table must contain 2 block drivers */
macio_ide_init_drives(MACIOIDEState * s,DriveInfo ** hd_table)493 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
494 {
495 int i;
496
497 for (i = 0; i < 2; i++) {
498 if (hd_table[i]) {
499 ide_bus_create_drive(&s->bus, i, hd_table[i]);
500 }
501 }
502 }
503
macio_ide_register_dma(MACIOIDEState * s)504 void macio_ide_register_dma(MACIOIDEState *s)
505 {
506 DBDMA_register_channel(s->dbdma, s->channel,
507 qdev_get_gpio_in(DEVICE(s), MACIO_IDE_PMAC_DMA_IRQ),
508 pmac_ide_transfer, pmac_ide_flush, s);
509 }
510
511 type_init(macio_ide_register_types)
512