1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8
9 #include "ics307_clk.h"
10
11 #if defined(CONFIG_FSL_NGPIXIS)
12 #include "ngpixis.h"
13 #define fpga_reg pixis
14 #elif defined(CONFIG_FSL_QIXIS)
15 #include "qixis.h"
16 #define fpga_reg ((struct qixis *)QIXIS_BASE)
17 #else
18 #include "pixis.h"
19 #define fpga_reg pixis
20 #endif
21
22 /* define for SYS CLK or CLK1Frequency */
23 #define TTL 1
24 #define CLK2 0
25 #define CRYSTAL 0
26 #define MAX_VDW (511 + 8)
27 #define MAX_RDW (127 + 2)
28 #define MIN_VDW (4 + 8)
29 #define MIN_RDW (1 + 2)
30 #define NUM_OD_SETTING 8
31 /*
32 * These defines cover the industrial temperature range part,
33 * for commercial, change below to 400000 and 55000, respectively
34 */
35 #define MAX_VCO 360000
36 #define MIN_VCO 60000
37
38 /* decode S[0-2] to Output Divider (OD) */
39 static u8 ics307_s_to_od[] = {
40 10, 2, 8, 4, 5, 7, 3, 6
41 };
42
43 /*
44 * Find one solution to generate required frequency for SYSCLK
45 * out_freq: KHz, required frequency to the SYSCLK
46 * the result will be retuned with component RDW, VDW, OD, TTL,
47 * CLK2 and crystal
48 */
ics307_sysclk_calculator(unsigned long out_freq)49 unsigned long ics307_sysclk_calculator(unsigned long out_freq)
50 {
51 const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
52 unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
53 unsigned long tmp_out, diff, result = 0;
54 int found = 0;
55
56 for (odp = 0; odp < NUM_OD_SETTING; odp++) {
57 od = ics307_s_to_od[odp];
58 if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
59 continue;
60 for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
61 /* Calculate the VDW */
62 vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
63 if (vdw > MAX_VDW)
64 vdw = MAX_VDW;
65 if (vdw < MIN_VDW)
66 continue;
67 /* Calculate the temp out frequency */
68 tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
69 diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
70 /*
71 * calculate the percent, the precision is 1/1000
72 * If greater than 1/1000, continue
73 * otherwise, we think the solution is we required
74 */
75 if (diff * 1000 / out_freq > 1)
76 continue;
77 else {
78 s_vdw = vdw;
79 s_rdw = rdw;
80 s_odp = odp;
81 found = 1;
82 break;
83 }
84 }
85 }
86
87 if (found)
88 result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
89 CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
90
91 debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
92 ics307_s_to_od[s_odp]);
93 return result;
94 }
95
96 /*
97 * Calculate frequency being generated by ICS307-02 clock chip based upon
98 * the control bytes being programmed into it.
99 */
ics307_clk_freq(u8 cw0,u8 cw1,u8 cw2)100 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
101 {
102 const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
103 unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
104 unsigned long rdw = cw2 & 0x7F;
105 unsigned long od = ics307_s_to_od[cw0 & 0x7];
106 unsigned long freq;
107
108 /*
109 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
110 *
111 * cw0: C1 C0 TTL F1 F0 S2 S1 S0
112 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
113 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
114 *
115 * R6:R0 = Reference Divider Word (RDW)
116 * V8:V0 = VCO Divider Word (VDW)
117 * S2:S0 = Output Divider Select (OD)
118 * F1:F0 = Function of CLK2 Output
119 * TTL = duty cycle
120 * C1:C0 = internal load capacitance for cyrstal
121 *
122 */
123
124 freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
125
126 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
127 freq);
128 return freq;
129 }
130
get_board_sys_clk(void)131 unsigned long get_board_sys_clk(void)
132 {
133 return ics307_clk_freq(
134 in_8(&fpga_reg->sclk[0]),
135 in_8(&fpga_reg->sclk[1]),
136 in_8(&fpga_reg->sclk[2]));
137 }
138
get_board_ddr_clk(void)139 unsigned long get_board_ddr_clk(void)
140 {
141 return ics307_clk_freq(
142 in_8(&fpga_reg->dclk[0]),
143 in_8(&fpga_reg->dclk[1]),
144 in_8(&fpga_reg->dclk[2]));
145 }
146