1 /*
2 * ACPI implementation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
8 *
9 * This is based on acpi.c.
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License version 2.1 as published by the Free Software Foundation.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
22 *
23 * Contributions after 2012-01-13 are licensed under the terms of the
24 * GNU GPL, version 2 or (at your option) any later version.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "hw/pci/pci.h"
31 #include "migration/vmstate.h"
32 #include "qemu/timer.h"
33 #include "hw/core/cpu.h"
34 #include "system/reset.h"
35 #include "system/runstate.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/ich9_tco.h"
38 #include "hw/acpi/ich9_timer.h"
39
40 #include "hw/southbridge/ich9.h"
41 #include "hw/mem/pc-dimm.h"
42 #include "hw/mem/nvdimm.h"
43
ich9_pm_update_sci_fn(ACPIREGS * regs)44 static void ich9_pm_update_sci_fn(ACPIREGS *regs)
45 {
46 ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
47 acpi_update_sci(&pm->acpi_regs, pm->irq);
48 }
49
ich9_gpe_readb(void * opaque,hwaddr addr,unsigned width)50 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
51 {
52 ICH9LPCPMRegs *pm = opaque;
53 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
54 }
55
ich9_gpe_writeb(void * opaque,hwaddr addr,uint64_t val,unsigned width)56 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
57 unsigned width)
58 {
59 ICH9LPCPMRegs *pm = opaque;
60 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
61 acpi_update_sci(&pm->acpi_regs, pm->irq);
62 }
63
64 static const MemoryRegionOps ich9_gpe_ops = {
65 .read = ich9_gpe_readb,
66 .write = ich9_gpe_writeb,
67 .valid.min_access_size = 1,
68 .valid.max_access_size = 4,
69 .impl.min_access_size = 1,
70 .impl.max_access_size = 1,
71 .endianness = DEVICE_LITTLE_ENDIAN,
72 };
73
ich9_smi_readl(void * opaque,hwaddr addr,unsigned width)74 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
75 {
76 ICH9LPCPMRegs *pm = opaque;
77 switch (addr) {
78 case 0:
79 return pm->smi_en;
80 case 4:
81 return pm->smi_sts;
82 default:
83 return 0;
84 }
85 }
86
ich9_smi_writel(void * opaque,hwaddr addr,uint64_t val,unsigned width)87 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
88 unsigned width)
89 {
90 ICH9LPCPMRegs *pm = opaque;
91 TCOIORegs *tr = &pm->tco_regs;
92 uint64_t tco_en;
93
94 switch (addr) {
95 case 0:
96 tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;
97 /* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */
98 if (tr->tco.cnt1 & TCO_LOCK) {
99 val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en;
100 }
101 pm->smi_en &= ~pm->smi_en_wmask;
102 pm->smi_en |= (val & pm->smi_en_wmask);
103 if (pm->swsmi_timer_enabled) {
104 ich9_pm_update_swsmi_timer(pm, pm->smi_en &
105 ICH9_PMIO_SMI_EN_SWSMI_EN);
106 }
107 if (pm->periodic_timer_enabled) {
108 ich9_pm_update_periodic_timer(pm, pm->smi_en &
109 ICH9_PMIO_SMI_EN_PERIODIC_EN);
110 }
111 break;
112 case 4:
113 pm->smi_sts &= ~pm->smi_sts_wmask;
114 pm->smi_sts |= (val & pm->smi_sts_wmask);
115 break;
116 }
117 }
118
119 static const MemoryRegionOps ich9_smi_ops = {
120 .read = ich9_smi_readl,
121 .write = ich9_smi_writel,
122 .valid.min_access_size = 4,
123 .valid.max_access_size = 4,
124 .endianness = DEVICE_LITTLE_ENDIAN,
125 };
126
ich9_pm_iospace_update(ICH9LPCPMRegs * pm,uint32_t pm_io_base)127 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
128 {
129 assert((pm_io_base & ICH9_PMIO_MASK) == 0);
130
131 pm->pm_io_base = pm_io_base;
132 memory_region_transaction_begin();
133 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
134 memory_region_set_address(&pm->io, pm->pm_io_base);
135 memory_region_transaction_commit();
136 }
137
ich9_pm_post_load(void * opaque,int version_id)138 static int ich9_pm_post_load(void *opaque, int version_id)
139 {
140 ICH9LPCPMRegs *pm = opaque;
141 uint32_t pm_io_base = pm->pm_io_base;
142 pm->pm_io_base = 0;
143 ich9_pm_iospace_update(pm, pm_io_base);
144 return 0;
145 }
146
147 #define VMSTATE_GPE_ARRAY(_field, _state) \
148 { \
149 .name = (stringify(_field)), \
150 .version_id = 0, \
151 .num = ICH9_PMIO_GPE0_LEN, \
152 .info = &vmstate_info_uint8, \
153 .size = sizeof(uint8_t), \
154 .flags = VMS_ARRAY | VMS_POINTER, \
155 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
156 }
157
158 static const VMStateDescription vmstate_memhp_state = {
159 .name = "ich9_pm/memhp",
160 .version_id = 1,
161 .minimum_version_id = 1,
162 .fields = (const VMStateField[]) {
163 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
164 VMSTATE_END_OF_LIST()
165 }
166 };
167
vmstate_test_use_tco(void * opaque)168 static bool vmstate_test_use_tco(void *opaque)
169 {
170 ICH9LPCPMRegs *s = opaque;
171 return s->enable_tco;
172 }
173
174 static const VMStateDescription vmstate_tco_io_state = {
175 .name = "ich9_pm/tco",
176 .version_id = 1,
177 .minimum_version_id = 1,
178 .needed = vmstate_test_use_tco,
179 .fields = (const VMStateField[]) {
180 VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,
181 TCOIORegs),
182 VMSTATE_END_OF_LIST()
183 }
184 };
185
vmstate_test_use_cpuhp(void * opaque)186 static bool vmstate_test_use_cpuhp(void *opaque)
187 {
188 ICH9LPCPMRegs *s = opaque;
189 return !s->cpu_hotplug_legacy;
190 }
191
vmstate_cpuhp_pre_load(void * opaque)192 static int vmstate_cpuhp_pre_load(void *opaque)
193 {
194 ICH9LPCPMRegs *s = opaque;
195 Object *obj = OBJECT(s->gpe_cpu.device);
196 object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort);
197 return 0;
198 }
199
200 static const VMStateDescription vmstate_cpuhp_state = {
201 .name = "ich9_pm/cpuhp",
202 .version_id = 1,
203 .minimum_version_id = 1,
204 .needed = vmstate_test_use_cpuhp,
205 .pre_load = vmstate_cpuhp_pre_load,
206 .fields = (const VMStateField[]) {
207 VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs),
208 VMSTATE_END_OF_LIST()
209 }
210 };
211
vmstate_test_use_pcihp(void * opaque)212 static bool vmstate_test_use_pcihp(void *opaque)
213 {
214 ICH9LPCPMRegs *s = opaque;
215
216 return s->acpi_pci_hotplug.use_acpi_hotplug_bridge;
217 }
218
219 static const VMStateDescription vmstate_pcihp_state = {
220 .name = "ich9_pm/pcihp",
221 .version_id = 1,
222 .minimum_version_id = 1,
223 .needed = vmstate_test_use_pcihp,
224 .fields = (const VMStateField[]) {
225 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug,
226 ICH9LPCPMRegs,
227 NULL, NULL),
228 VMSTATE_END_OF_LIST()
229 }
230 };
231
232 const VMStateDescription vmstate_ich9_pm = {
233 .name = "ich9_pm",
234 .version_id = 1,
235 .minimum_version_id = 1,
236 .post_load = ich9_pm_post_load,
237 .fields = (const VMStateField[]) {
238 VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
239 VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
240 VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
241 VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
242 VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
243 VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
244 VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
245 VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
246 VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
247 VMSTATE_END_OF_LIST()
248 },
249 .subsections = (const VMStateDescription * const []) {
250 &vmstate_memhp_state,
251 &vmstate_tco_io_state,
252 &vmstate_cpuhp_state,
253 &vmstate_pcihp_state,
254 NULL
255 }
256 };
257
pm_reset(void * opaque)258 static void pm_reset(void *opaque)
259 {
260 ICH9LPCPMRegs *pm = opaque;
261 ich9_pm_iospace_update(pm, 0);
262
263 acpi_pm1_evt_reset(&pm->acpi_regs);
264 acpi_pm1_cnt_reset(&pm->acpi_regs);
265 acpi_pm_tmr_reset(&pm->acpi_regs);
266 acpi_gpe_reset(&pm->acpi_regs);
267
268 pm->smi_en = 0;
269 if (!pm->smm_enabled) {
270 /* Mark SMM as already inited to prevent SMM from running. */
271 pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
272 }
273 pm->smi_en_wmask = ~0;
274
275 if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) {
276 acpi_pcihp_reset(&pm->acpi_pci_hotplug);
277 }
278
279 acpi_update_sci(&pm->acpi_regs, pm->irq);
280 }
281
pm_powerdown_req(Notifier * n,void * opaque)282 static void pm_powerdown_req(Notifier *n, void *opaque)
283 {
284 ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
285
286 acpi_pm1_evt_power_down(&pm->acpi_regs);
287 }
288
ich9_pm_init(PCIDevice * lpc_pci,ICH9LPCPMRegs * pm,qemu_irq sci_irq)289 void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq)
290 {
291 pm->smi_sts_wmask = 0;
292
293 memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
294 memory_region_set_enabled(&pm->io, false);
295 memory_region_add_subregion(pci_address_space_io(lpc_pci),
296 0, &pm->io);
297
298 acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
299 acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
300 acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
301 pm->s4_val, !pm->smm_compat && !pm->smm_enabled);
302
303 acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
304 memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
305 "acpi-gpe0", ICH9_PMIO_GPE0_LEN);
306 memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
307
308 memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
309 "acpi-smi", 8);
310 memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
311
312 if (pm->swsmi_timer_enabled) {
313 ich9_pm_swsmi_timer_init(pm);
314 }
315
316 if (pm->periodic_timer_enabled) {
317 ich9_pm_periodic_timer_init(pm);
318 }
319
320 if (pm->enable_tco) {
321 acpi_pm_tco_init(&pm->tco_regs, &pm->io);
322 }
323
324 if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) {
325 object_property_set_link(OBJECT(lpc_pci), "bus",
326 OBJECT(pci_get_bus(lpc_pci)), &error_abort);
327 acpi_pcihp_init(OBJECT(lpc_pci),
328 &pm->acpi_pci_hotplug,
329 pci_address_space_io(lpc_pci),
330 ACPI_PCIHP_ADDR_ICH9);
331
332 qbus_set_hotplug_handler(BUS(pci_get_bus(lpc_pci)),
333 OBJECT(lpc_pci));
334 }
335
336 pm->irq = sci_irq;
337 qemu_register_reset(pm_reset, pm);
338 pm->powerdown_notifier.notify = pm_powerdown_req;
339 qemu_register_powerdown_notifier(&pm->powerdown_notifier);
340
341 legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci),
342 OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
343
344 acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
345 &pm->acpi_memory_hotplug,
346 ACPI_MEMORY_HOTPLUG_BASE);
347 }
348
ich9_pm_get_gpe0_blk(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)349 static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name,
350 void *opaque, Error **errp)
351 {
352 ICH9LPCPMRegs *pm = opaque;
353 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
354
355 visit_type_uint32(v, name, &value, errp);
356 }
357
ich9_pm_get_cpu_hotplug_legacy(Object * obj,Error ** errp)358 static bool ich9_pm_get_cpu_hotplug_legacy(Object *obj, Error **errp)
359 {
360 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
361
362 return s->pm.cpu_hotplug_legacy;
363 }
364
ich9_pm_set_cpu_hotplug_legacy(Object * obj,bool value,Error ** errp)365 static void ich9_pm_set_cpu_hotplug_legacy(Object *obj, bool value,
366 Error **errp)
367 {
368 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
369
370 assert(!value);
371 if (s->pm.cpu_hotplug_legacy && value == false) {
372 acpi_switch_to_modern_cphp(&s->pm.gpe_cpu, &s->pm.cpuhp_state,
373 ICH9_CPU_HOTPLUG_IO_BASE);
374 }
375 s->pm.cpu_hotplug_legacy = value;
376 }
377
ich9_pm_get_enable_tco(Object * obj,Error ** errp)378 static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)
379 {
380 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
381 return s->pm.enable_tco;
382 }
383
ich9_pm_set_enable_tco(Object * obj,bool value,Error ** errp)384 static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp)
385 {
386 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
387 s->pm.enable_tco = value;
388 }
389
ich9_pm_get_acpi_pci_hotplug(Object * obj,Error ** errp)390 static bool ich9_pm_get_acpi_pci_hotplug(Object *obj, Error **errp)
391 {
392 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
393
394 return s->pm.acpi_pci_hotplug.use_acpi_hotplug_bridge;
395 }
396
ich9_pm_set_acpi_pci_hotplug(Object * obj,bool value,Error ** errp)397 static void ich9_pm_set_acpi_pci_hotplug(Object *obj, bool value, Error **errp)
398 {
399 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
400
401 s->pm.acpi_pci_hotplug.use_acpi_hotplug_bridge = value;
402 }
403
ich9_pm_get_keep_pci_slot_hpc(Object * obj,Error ** errp)404 static bool ich9_pm_get_keep_pci_slot_hpc(Object *obj, Error **errp)
405 {
406 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
407
408 return s->pm.keep_pci_slot_hpc;
409 }
410
ich9_pm_set_keep_pci_slot_hpc(Object * obj,bool value,Error ** errp)411 static void ich9_pm_set_keep_pci_slot_hpc(Object *obj, bool value, Error **errp)
412 {
413 ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
414
415 s->pm.keep_pci_slot_hpc = value;
416 }
417
ich9_pm_add_properties(Object * obj,ICH9LPCPMRegs * pm)418 void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
419 {
420 static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
421 pm->acpi_memory_hotplug.is_enabled = true;
422 pm->cpu_hotplug_legacy = true;
423 pm->disable_s3 = 0;
424 pm->disable_s4 = 0;
425 pm->s4_val = 2;
426 pm->acpi_pci_hotplug.use_acpi_hotplug_bridge = true;
427 pm->keep_pci_slot_hpc = true;
428 pm->enable_tco = true;
429
430 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
431 &pm->pm_io_base, OBJ_PROP_FLAG_READ);
432 object_property_add_link(obj, "bus", TYPE_PCI_BUS,
433 (Object **)&pm->acpi_pci_hotplug.root,
434 object_property_allow_set_link,
435 OBJ_PROP_LINK_STRONG);
436 object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
437 ich9_pm_get_gpe0_blk,
438 NULL, NULL, pm);
439 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
440 &gpe0_len, OBJ_PROP_FLAG_READ);
441 object_property_add_bool(obj, "cpu-hotplug-legacy",
442 ich9_pm_get_cpu_hotplug_legacy,
443 ich9_pm_set_cpu_hotplug_legacy);
444 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S3_DISABLED,
445 &pm->disable_s3, OBJ_PROP_FLAG_READWRITE);
446 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_DISABLED,
447 &pm->disable_s4, OBJ_PROP_FLAG_READWRITE);
448 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_VAL,
449 &pm->s4_val, OBJ_PROP_FLAG_READWRITE);
450 object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
451 ich9_pm_get_enable_tco,
452 ich9_pm_set_enable_tco);
453 object_property_add_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
454 ich9_pm_get_acpi_pci_hotplug,
455 ich9_pm_set_acpi_pci_hotplug);
456 object_property_add_bool(obj, "x-keep-pci-slot-hpc",
457 ich9_pm_get_keep_pci_slot_hpc,
458 ich9_pm_set_keep_pci_slot_hpc);
459 }
460
ich9_pm_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)461 void ich9_pm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
462 Error **errp)
463 {
464 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
465
466 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
467 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
468 return;
469 }
470
471 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
472 uint64_t negotiated = lpc->smi_negotiated_features;
473
474 if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) &&
475 !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) {
476 error_setg(errp, "cpu hotplug with SMI wasn't enabled by firmware");
477 error_append_hint(errp, "update machine type to newer than 5.1 "
478 "and firmware that suppors CPU hotplug with SMM");
479 }
480 }
481 }
482
ich9_pm_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)483 void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
484 Error **errp)
485 {
486 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
487
488 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
489 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
490 nvdimm_acpi_plug_cb(hotplug_dev, dev);
491 } else {
492 acpi_memory_plug_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug,
493 dev, errp);
494 }
495 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
496 if (lpc->pm.cpu_hotplug_legacy) {
497 legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp);
498 } else {
499 acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp);
500 }
501 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
502 acpi_pcihp_device_plug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug,
503 dev, errp);
504 } else {
505 error_setg(errp, "acpi: device plug request for not supported device"
506 " type: %s", object_get_typename(OBJECT(dev)));
507 }
508 }
509
ich9_pm_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)510 void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
511 DeviceState *dev, Error **errp)
512 {
513 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
514
515 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
516 acpi_memory_unplug_request_cb(hotplug_dev,
517 &lpc->pm.acpi_memory_hotplug, dev,
518 errp);
519 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
520 !lpc->pm.cpu_hotplug_legacy) {
521 uint64_t negotiated = lpc->smi_negotiated_features;
522
523 if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) &&
524 !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) {
525 error_setg(errp, "cpu hot-unplug with SMI wasn't enabled "
526 "by firmware");
527 error_append_hint(errp, "update machine type to a version having "
528 "x-smi-cpu-hotunplug=on and firmware that "
529 "supports CPU hot-unplug with SMM");
530 return;
531 }
532
533 acpi_cpu_unplug_request_cb(hotplug_dev, &lpc->pm.cpuhp_state,
534 dev, errp);
535 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
536 acpi_pcihp_device_unplug_request_cb(hotplug_dev,
537 &lpc->pm.acpi_pci_hotplug,
538 dev, errp);
539 } else {
540 error_setg(errp, "acpi: device unplug request for not supported device"
541 " type: %s", object_get_typename(OBJECT(dev)));
542 }
543 }
544
ich9_pm_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)545 void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
546 Error **errp)
547 {
548 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
549
550 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
551 acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp);
552 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
553 !lpc->pm.cpu_hotplug_legacy) {
554 acpi_cpu_unplug_cb(&lpc->pm.cpuhp_state, dev, errp);
555 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
556 acpi_pcihp_device_unplug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug,
557 dev, errp);
558 } else {
559 error_setg(errp, "acpi: device unplug for not supported device"
560 " type: %s", object_get_typename(OBJECT(dev)));
561 }
562 }
563
ich9_pm_is_hotpluggable_bus(HotplugHandler * hotplug_dev,BusState * bus)564 bool ich9_pm_is_hotpluggable_bus(HotplugHandler *hotplug_dev, BusState *bus)
565 {
566 ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
567 return acpi_pcihp_is_hotpluggable_bus(&lpc->pm.acpi_pci_hotplug, bus);
568 }
569
ich9_pm_ospm_status(AcpiDeviceIf * adev,ACPIOSTInfoList *** list)570 void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
571 {
572 ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
573
574 acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list);
575 if (!s->pm.cpu_hotplug_legacy) {
576 acpi_cpu_ospm_status(&s->pm.cpuhp_state, list);
577 }
578 }
579