xref: /openbmc/linux/drivers/video/fbdev/i740fb.c (revision 7f075499)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * i740fb - framebuffer driver for Intel740
4  * Copyright (c) 2011 Ondrej Zary
5  *
6  * Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <drey@rt.mipt.ru>
7  * which was partially based on:
8  *  VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <pfaffben@debian.org>
9  *	and Petr Vandrovec <VANDROVE@vc.cvut.cz>
10  *  i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park,
11  *	Texas.
12  *  i740fb by Patrick LERDA, v0.9
13  */
14 
15 #include <linux/aperture.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/mm.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/fb.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c-algo-bit.h>
29 #include <linux/console.h>
30 #include <video/vga.h>
31 
32 #include "i740_reg.h"
33 
34 static char *mode_option;
35 static int mtrr = 1;
36 
37 struct i740fb_par {
38 	unsigned char __iomem *regs;
39 	bool has_sgram;
40 	int wc_cookie;
41 	bool ddc_registered;
42 	struct i2c_adapter ddc_adapter;
43 	struct i2c_algo_bit_data ddc_algo;
44 	u32 pseudo_palette[16];
45 	struct mutex open_lock;
46 	unsigned int ref_count;
47 
48 	u8 crtc[VGA_CRT_C];
49 	u8 atc[VGA_ATT_C];
50 	u8 gdc[VGA_GFX_C];
51 	u8 seq[VGA_SEQ_C];
52 	u8 misc;
53 	u8 vss;
54 
55 	/* i740 specific registers */
56 	u8 display_cntl;
57 	u8 pixelpipe_cfg0;
58 	u8 pixelpipe_cfg1;
59 	u8 pixelpipe_cfg2;
60 	u8 video_clk2_m;
61 	u8 video_clk2_n;
62 	u8 video_clk2_mn_msbs;
63 	u8 video_clk2_div_sel;
64 	u8 pll_cntl;
65 	u8 address_mapping;
66 	u8 io_cntl;
67 	u8 bitblt_cntl;
68 	u8 ext_vert_total;
69 	u8 ext_vert_disp_end;
70 	u8 ext_vert_sync_start;
71 	u8 ext_vert_blank_start;
72 	u8 ext_horiz_total;
73 	u8 ext_horiz_blank;
74 	u8 ext_offset;
75 	u8 interlace_cntl;
76 	u32 lmi_fifo_watermark;
77 	u8 ext_start_addr;
78 	u8 ext_start_addr_hi;
79 };
80 
81 #define DACSPEED8	203
82 #define DACSPEED16	163
83 #define DACSPEED24_SG	136
84 #define DACSPEED24_SD	128
85 #define DACSPEED32	86
86 
87 static const struct fb_fix_screeninfo i740fb_fix = {
88 	.id =		"i740fb",
89 	.type =		FB_TYPE_PACKED_PIXELS,
90 	.visual =	FB_VISUAL_TRUECOLOR,
91 	.xpanstep =	8,
92 	.ypanstep =	1,
93 	.accel =	FB_ACCEL_NONE,
94 };
95 
i740outb(struct i740fb_par * par,u16 port,u8 val)96 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
97 {
98 	vga_mm_w(par->regs, port, val);
99 }
i740inb(struct i740fb_par * par,u16 port)100 static inline u8 i740inb(struct i740fb_par *par, u16 port)
101 {
102 	return vga_mm_r(par->regs, port);
103 }
i740outreg(struct i740fb_par * par,u16 port,u8 reg,u8 val)104 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
105 {
106 	vga_mm_w_fast(par->regs, port, reg, val);
107 }
i740inreg(struct i740fb_par * par,u16 port,u8 reg)108 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
109 {
110 	vga_mm_w(par->regs, port, reg);
111 	return vga_mm_r(par->regs, port+1);
112 }
i740outreg_mask(struct i740fb_par * par,u16 port,u8 reg,u8 val,u8 mask)113 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,
114 				   u8 val, u8 mask)
115 {
116 	vga_mm_w_fast(par->regs, port, reg, (val & mask)
117 		| (i740inreg(par, port, reg) & ~mask));
118 }
119 
120 #define REG_DDC_DRIVE	0x62
121 #define REG_DDC_STATE	0x63
122 #define DDC_SCL		(1 << 3)
123 #define DDC_SDA		(1 << 2)
124 
i740fb_ddc_setscl(void * data,int val)125 static void i740fb_ddc_setscl(void *data, int val)
126 {
127 	struct i740fb_par *par = data;
128 
129 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
130 	i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
131 }
132 
i740fb_ddc_setsda(void * data,int val)133 static void i740fb_ddc_setsda(void *data, int val)
134 {
135 	struct i740fb_par *par = data;
136 
137 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
138 	i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
139 }
140 
i740fb_ddc_getscl(void * data)141 static int i740fb_ddc_getscl(void *data)
142 {
143 	struct i740fb_par *par = data;
144 
145 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
146 
147 	return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
148 }
149 
i740fb_ddc_getsda(void * data)150 static int i740fb_ddc_getsda(void *data)
151 {
152 	struct i740fb_par *par = data;
153 
154 	i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
155 
156 	return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
157 }
158 
i740fb_setup_ddc_bus(struct fb_info * info)159 static int i740fb_setup_ddc_bus(struct fb_info *info)
160 {
161 	struct i740fb_par *par = info->par;
162 
163 	strscpy(par->ddc_adapter.name, info->fix.id,
164 		sizeof(par->ddc_adapter.name));
165 	par->ddc_adapter.owner		= THIS_MODULE;
166 	par->ddc_adapter.class		= I2C_CLASS_DDC;
167 	par->ddc_adapter.algo_data	= &par->ddc_algo;
168 	par->ddc_adapter.dev.parent	= info->device;
169 	par->ddc_algo.setsda		= i740fb_ddc_setsda;
170 	par->ddc_algo.setscl		= i740fb_ddc_setscl;
171 	par->ddc_algo.getsda		= i740fb_ddc_getsda;
172 	par->ddc_algo.getscl		= i740fb_ddc_getscl;
173 	par->ddc_algo.udelay		= 10;
174 	par->ddc_algo.timeout		= 20;
175 	par->ddc_algo.data		= par;
176 
177 	i2c_set_adapdata(&par->ddc_adapter, par);
178 
179 	return i2c_bit_add_bus(&par->ddc_adapter);
180 }
181 
i740fb_open(struct fb_info * info,int user)182 static int i740fb_open(struct fb_info *info, int user)
183 {
184 	struct i740fb_par *par = info->par;
185 
186 	mutex_lock(&(par->open_lock));
187 	par->ref_count++;
188 	mutex_unlock(&(par->open_lock));
189 
190 	return 0;
191 }
192 
i740fb_release(struct fb_info * info,int user)193 static int i740fb_release(struct fb_info *info, int user)
194 {
195 	struct i740fb_par *par = info->par;
196 
197 	mutex_lock(&(par->open_lock));
198 	if (par->ref_count == 0) {
199 		fb_err(info, "release called with zero refcount\n");
200 		mutex_unlock(&(par->open_lock));
201 		return -EINVAL;
202 	}
203 
204 	par->ref_count--;
205 	mutex_unlock(&(par->open_lock));
206 
207 	return 0;
208 }
209 
i740_calc_fifo(struct i740fb_par * par,u32 freq,int bpp)210 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
211 {
212 	/*
213 	 * Would like to calculate these values automatically, but a generic
214 	 * algorithm does not seem possible.  Note: These FIFO water mark
215 	 * values were tested on several cards and seem to eliminate the
216 	 * all of the snow and vertical banding, but fine adjustments will
217 	 * probably be required for other cards.
218 	 */
219 
220 	u32 wm;
221 
222 	switch (bpp) {
223 	case 8:
224 		if	(freq > 200)
225 			wm = 0x18120000;
226 		else if (freq > 175)
227 			wm = 0x16110000;
228 		else if (freq > 135)
229 			wm = 0x120E0000;
230 		else
231 			wm = 0x100D0000;
232 		break;
233 	case 15:
234 	case 16:
235 		if (par->has_sgram) {
236 			if	(freq > 140)
237 				wm = 0x2C1D0000;
238 			else if (freq > 120)
239 				wm = 0x2C180000;
240 			else if (freq > 100)
241 				wm = 0x24160000;
242 			else if (freq >  90)
243 				wm = 0x18120000;
244 			else if (freq >  50)
245 				wm = 0x16110000;
246 			else if (freq >  32)
247 				wm = 0x13100000;
248 			else
249 				wm = 0x120E0000;
250 		} else {
251 			if	(freq > 160)
252 				wm = 0x28200000;
253 			else if (freq > 140)
254 				wm = 0x2A1E0000;
255 			else if (freq > 130)
256 				wm = 0x2B1A0000;
257 			else if (freq > 120)
258 				wm = 0x2C180000;
259 			else if (freq > 100)
260 				wm = 0x24180000;
261 			else if (freq >  90)
262 				wm = 0x18120000;
263 			else if (freq >  50)
264 				wm = 0x16110000;
265 			else if (freq >  32)
266 				wm = 0x13100000;
267 			else
268 				wm = 0x120E0000;
269 		}
270 		break;
271 	case 24:
272 		if (par->has_sgram) {
273 			if	(freq > 130)
274 				wm = 0x31200000;
275 			else if (freq > 120)
276 				wm = 0x2E200000;
277 			else if (freq > 100)
278 				wm = 0x2C1D0000;
279 			else if (freq >  80)
280 				wm = 0x25180000;
281 			else if (freq >  64)
282 				wm = 0x24160000;
283 			else if (freq >  49)
284 				wm = 0x18120000;
285 			else if (freq >  32)
286 				wm = 0x16110000;
287 			else
288 				wm = 0x13100000;
289 		} else {
290 			if	(freq > 120)
291 				wm = 0x311F0000;
292 			else if (freq > 100)
293 				wm = 0x2C1D0000;
294 			else if (freq >  80)
295 				wm = 0x25180000;
296 			else if (freq >  64)
297 				wm = 0x24160000;
298 			else if (freq >  49)
299 				wm = 0x18120000;
300 			else if (freq >  32)
301 				wm = 0x16110000;
302 			else
303 				wm = 0x13100000;
304 		}
305 		break;
306 	case 32:
307 		if (par->has_sgram) {
308 			if	(freq >  80)
309 				wm = 0x2A200000;
310 			else if (freq >  60)
311 				wm = 0x281A0000;
312 			else if (freq >  49)
313 				wm = 0x25180000;
314 			else if (freq >  32)
315 				wm = 0x18120000;
316 			else
317 				wm = 0x16110000;
318 		} else {
319 			if	(freq >  80)
320 				wm = 0x29200000;
321 			else if (freq >  60)
322 				wm = 0x281A0000;
323 			else if (freq >  49)
324 				wm = 0x25180000;
325 			else if (freq >  32)
326 				wm = 0x18120000;
327 			else
328 				wm = 0x16110000;
329 		}
330 		break;
331 	}
332 
333 	return wm;
334 }
335 
336 /* clock calculation from i740fb by Patrick LERDA */
337 
338 #define I740_RFREQ		1000000
339 #define TARGET_MAX_N		30
340 #define I740_FFIX		(1 << 8)
341 #define I740_RFREQ_FIX		(I740_RFREQ / I740_FFIX)
342 #define I740_REF_FREQ		(6667 * I740_FFIX / 100)	/* 66.67 MHz */
343 #define I740_MAX_VCO_FREQ	(450 * I740_FFIX)		/* 450 MHz */
344 
i740_calc_vclk(u32 freq,struct i740fb_par * par)345 static void i740_calc_vclk(u32 freq, struct i740fb_par *par)
346 {
347 	const u32 err_max    = freq / (200  * I740_RFREQ / I740_FFIX);
348 	const u32 err_target = freq / (1000 * I740_RFREQ / I740_FFIX);
349 	u32 err_best = 512 * I740_FFIX;
350 	u32 f_err, f_vco;
351 	int m_best = 0, n_best = 0, p_best = 0;
352 	int m, n;
353 
354 	p_best = min(15, ilog2(I740_MAX_VCO_FREQ / (freq / I740_RFREQ_FIX)));
355 	f_vco = (freq * (1 << p_best)) / I740_RFREQ_FIX;
356 	freq = freq / I740_RFREQ_FIX;
357 
358 	n = 2;
359 	do {
360 		n++;
361 		m = ((f_vco * n) / I740_REF_FREQ + 2) / 4;
362 
363 		if (m < 3)
364 			m = 3;
365 
366 		{
367 			u32 f_out = (((m * I740_REF_FREQ * 4)
368 				 / n) + ((1 << p_best) / 2)) / (1 << p_best);
369 
370 			f_err = (freq - f_out);
371 
372 			if (abs(f_err) < err_max) {
373 				m_best = m;
374 				n_best = n;
375 				err_best = f_err;
376 			}
377 		}
378 	} while ((abs(f_err) >= err_target) &&
379 		 ((n <= TARGET_MAX_N) || (abs(err_best) > err_max)));
380 
381 	if (abs(f_err) < err_target) {
382 		m_best = m;
383 		n_best = n;
384 	}
385 
386 	par->video_clk2_m = (m_best - 2) & 0xFF;
387 	par->video_clk2_n = (n_best - 2) & 0xFF;
388 	par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS)
389 				 | (((m_best - 2) >> 8) & VCO_M_MSBS));
390 	par->video_clk2_div_sel = ((p_best << 4) | REF_DIV_1);
391 }
392 
i740fb_decode_var(const struct fb_var_screeninfo * var,struct i740fb_par * par,struct fb_info * info)393 static int i740fb_decode_var(const struct fb_var_screeninfo *var,
394 			     struct i740fb_par *par, struct fb_info *info)
395 {
396 	/*
397 	 * Get the video params out of 'var'.
398 	 * If a value doesn't fit, round it up, if it's too big, return -EINVAL.
399 	 */
400 
401 	u32 xres, right, hslen, left, xtotal;
402 	u32 yres, lower, vslen, upper, ytotal;
403 	u32 vxres, xoffset, vyres, yoffset;
404 	u32 bpp, base, dacspeed24, mem, freq;
405 	u8 r7;
406 	int i;
407 
408 	dev_dbg(info->device, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
409 		  var->xres, var->yres, var->xres_virtual, var->xres_virtual);
410 	dev_dbg(info->device, "	xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
411 		  var->xoffset, var->yoffset, var->bits_per_pixel,
412 		  var->grayscale);
413 	dev_dbg(info->device, "	activate: %i, nonstd: %i, vmode: %i\n",
414 		  var->activate, var->nonstd, var->vmode);
415 	dev_dbg(info->device, "	pixclock: %i, hsynclen:%i, vsynclen:%i\n",
416 		  var->pixclock, var->hsync_len, var->vsync_len);
417 	dev_dbg(info->device, "	left: %i, right: %i, up:%i, lower:%i\n",
418 		  var->left_margin, var->right_margin, var->upper_margin,
419 		  var->lower_margin);
420 
421 
422 	bpp = var->bits_per_pixel;
423 	switch (bpp) {
424 	case 1 ... 8:
425 		bpp = 8;
426 		if ((1000000 / var->pixclock) > DACSPEED8) {
427 			dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n",
428 				1000000 / var->pixclock, DACSPEED8);
429 			return -EINVAL;
430 		}
431 		break;
432 	case 9 ... 15:
433 		bpp = 15;
434 		fallthrough;
435 	case 16:
436 		if ((1000000 / var->pixclock) > DACSPEED16) {
437 			dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n",
438 				1000000 / var->pixclock, DACSPEED16);
439 			return -EINVAL;
440 		}
441 		break;
442 	case 17 ... 24:
443 		bpp = 24;
444 		dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
445 		if ((1000000 / var->pixclock) > dacspeed24) {
446 			dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n",
447 				1000000 / var->pixclock, dacspeed24);
448 			return -EINVAL;
449 		}
450 		break;
451 	case 25 ... 32:
452 		bpp = 32;
453 		if ((1000000 / var->pixclock) > DACSPEED32) {
454 			dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n",
455 				1000000 / var->pixclock, DACSPEED32);
456 			return -EINVAL;
457 		}
458 		break;
459 	default:
460 		return -EINVAL;
461 	}
462 
463 	xres = ALIGN(var->xres, 8);
464 	vxres = ALIGN(var->xres_virtual, 16);
465 	if (vxres < xres)
466 		vxres = xres;
467 
468 	xoffset = ALIGN(var->xoffset, 8);
469 	if (xres + xoffset > vxres)
470 		xoffset = vxres - xres;
471 
472 	left = ALIGN(var->left_margin, 8);
473 	right = ALIGN(var->right_margin, 8);
474 	hslen = ALIGN(var->hsync_len, 8);
475 
476 	yres = var->yres;
477 	vyres = var->yres_virtual;
478 	if (yres > vyres)
479 		vyres = yres;
480 
481 	yoffset = var->yoffset;
482 	if (yres + yoffset > vyres)
483 		yoffset = vyres - yres;
484 
485 	lower = var->lower_margin;
486 	vslen = var->vsync_len;
487 	upper = var->upper_margin;
488 
489 	mem = vxres * vyres * ((bpp + 1) / 8);
490 	if (mem > info->screen_size) {
491 		dev_err(info->device, "not enough video memory (%d KB requested, %ld KB available)\n",
492 			mem >> 10, info->screen_size >> 10);
493 		return -ENOMEM;
494 	}
495 
496 	if (yoffset + yres > vyres)
497 		yoffset = vyres - yres;
498 
499 	xtotal = xres + right + hslen + left;
500 	ytotal = yres + lower + vslen + upper;
501 
502 	par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
503 	par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
504 	par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
505 	par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
506 	par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
507 		| ((((xres + right + hslen) >> 3) & 0x20) << 2);
508 	par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F)
509 		| 0x80;
510 
511 	par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
512 
513 	r7 = 0x10;	/* disable linecompare */
514 	if (ytotal & 0x100)
515 		r7 |= 0x01;
516 	if (ytotal & 0x200)
517 		r7 |= 0x20;
518 
519 	par->crtc[VGA_CRTC_PRESET_ROW] = 0;
520 	par->crtc[VGA_CRTC_MAX_SCAN] = 0x40;	/* 1 scanline, no linecmp */
521 	if (var->vmode & FB_VMODE_DOUBLE)
522 		par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
523 	par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
524 	par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
525 	par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
526 	par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
527 	par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
528 	if ((yres-1) & 0x100)
529 		r7 |= 0x02;
530 	if ((yres-1) & 0x200)
531 		r7 |= 0x40;
532 
533 	par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
534 	par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
535 	if ((yres + lower - 1) & 0x100)
536 		r7 |= 0x0C;
537 	if ((yres + lower - 1) & 0x200) {
538 		par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
539 		r7 |= 0x80;
540 	}
541 
542 	/* disabled IRQ */
543 	par->crtc[VGA_CRTC_V_SYNC_END] =
544 		((yres + lower - 1 + vslen) & 0x0F) & ~0x10;
545 	/* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */
546 	par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF;
547 
548 	par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
549 	par->crtc[VGA_CRTC_MODE] = 0xC3 ;
550 	par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
551 	par->crtc[VGA_CRTC_OVERFLOW] = r7;
552 
553 	par->vss = 0x00;	/* 3DA */
554 
555 	for (i = 0x00; i < 0x10; i++)
556 		par->atc[i] = i;
557 	par->atc[VGA_ATC_MODE] = 0x81;
558 	par->atc[VGA_ATC_OVERSCAN] = 0x00;	/* 0 for EGA, 0xFF for VGA */
559 	par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
560 	par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
561 
562 	par->misc = 0xC3;
563 	if (var->sync & FB_SYNC_HOR_HIGH_ACT)
564 		par->misc &= ~0x40;
565 	if (var->sync & FB_SYNC_VERT_HIGH_ACT)
566 		par->misc &= ~0x80;
567 
568 	par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
569 	par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
570 	par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
571 	par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
572 
573 	par->gdc[VGA_GFX_SR_VALUE] = 0x00;
574 	par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
575 	par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
576 	par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
577 	par->gdc[VGA_GFX_PLANE_READ] = 0;
578 	par->gdc[VGA_GFX_MODE] = 0x02;
579 	par->gdc[VGA_GFX_MISC] = 0x05;
580 	par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
581 	par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
582 
583 	base = (yoffset * vxres + (xoffset & ~7)) >> 2;
584 	switch (bpp) {
585 	case 8:
586 		par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
587 		par->ext_offset = vxres >> 11;
588 		par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
589 		par->bitblt_cntl = COLEXP_8BPP;
590 		break;
591 	case 15: /* 0rrrrrgg gggbbbbb */
592 	case 16: /* rrrrrggg gggbbbbb */
593 		par->pixelpipe_cfg1 = (var->green.length == 6) ?
594 			DISPLAY_16BPP_MODE : DISPLAY_15BPP_MODE;
595 		par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
596 		par->ext_offset = vxres >> 10;
597 		par->bitblt_cntl = COLEXP_16BPP;
598 		base *= 2;
599 		break;
600 	case 24:
601 		par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
602 		par->ext_offset = (vxres * 3) >> 11;
603 		par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
604 		par->bitblt_cntl = COLEXP_24BPP;
605 		base &= 0xFFFFFFFE; /* ...ignore the last bit. */
606 		base *= 3;
607 		break;
608 	case 32:
609 		par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
610 		par->ext_offset = vxres >> 9;
611 		par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
612 		par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */
613 		base *= 4;
614 		break;
615 	}
616 
617 	par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
618 	par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
619 	par->ext_start_addr =
620 		((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
621 	par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
622 
623 	par->pixelpipe_cfg0 = DAC_8_BIT;
624 
625 	par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
626 	par->io_cntl = EXTENDED_CRTC_CNTL;
627 	par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
628 	par->display_cntl = HIRES_MODE;
629 
630 	/* Set the MCLK freq */
631 	par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
632 
633 	/* Calculate the extended CRTC regs */
634 	par->ext_vert_total = (ytotal - 2) >> 8;
635 	par->ext_vert_disp_end = (yres - 1) >> 8;
636 	par->ext_vert_sync_start = (yres + lower) >> 8;
637 	par->ext_vert_blank_start = (yres + lower) >> 8;
638 	par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
639 	par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
640 
641 	par->interlace_cntl = INTERLACE_DISABLE;
642 
643 	/* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */
644 	par->atc[VGA_ATC_OVERSCAN] = 0;
645 
646 	/* Calculate VCLK that most closely matches the requested dot clock */
647 	freq = (((u32)1e9) / var->pixclock) * (u32)(1e3);
648 	if (freq < I740_RFREQ_FIX) {
649 		fb_dbg(info, "invalid pixclock\n");
650 		freq = I740_RFREQ_FIX;
651 	}
652 	i740_calc_vclk(freq, par);
653 
654 	/* Since we program the clocks ourselves, always use VCLK2. */
655 	par->misc |= 0x0C;
656 
657 	/* Calculate the FIFO Watermark and Burst Length. */
658 	par->lmi_fifo_watermark =
659 		i740_calc_fifo(par, 1000000 / var->pixclock, bpp);
660 
661 	return 0;
662 }
663 
i740fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)664 static int i740fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
665 {
666 	if (!var->pixclock)
667 		return -EINVAL;
668 
669 	switch (var->bits_per_pixel) {
670 	case 8:
671 		var->red.offset	= var->green.offset = var->blue.offset = 0;
672 		var->red.length	= var->green.length = var->blue.length = 8;
673 		break;
674 	case 16:
675 		switch (var->green.length) {
676 		default:
677 		case 5:
678 			var->red.offset = 10;
679 			var->green.offset = 5;
680 			var->blue.offset = 0;
681 			var->red.length	= 5;
682 			var->green.length = 5;
683 			var->blue.length = 5;
684 			break;
685 		case 6:
686 			var->red.offset = 11;
687 			var->green.offset = 5;
688 			var->blue.offset = 0;
689 			var->red.length = var->blue.length = 5;
690 			break;
691 		}
692 		break;
693 	case 24:
694 		var->red.offset = 16;
695 		var->green.offset = 8;
696 		var->blue.offset = 0;
697 		var->red.length	= var->green.length = var->blue.length = 8;
698 		break;
699 	case 32:
700 		var->transp.offset = 24;
701 		var->red.offset = 16;
702 		var->green.offset = 8;
703 		var->blue.offset = 0;
704 		var->transp.length = 8;
705 		var->red.length = var->green.length = var->blue.length = 8;
706 		break;
707 	default:
708 		return -EINVAL;
709 	}
710 
711 	if (var->xres > var->xres_virtual)
712 		var->xres_virtual = var->xres;
713 
714 	if (var->yres > var->yres_virtual)
715 		var->yres_virtual = var->yres;
716 
717 	if (info->monspecs.hfmax && info->monspecs.vfmax &&
718 	    info->monspecs.dclkmax && fb_validate_mode(var, info) < 0)
719 		return -EINVAL;
720 
721 	return 0;
722 }
723 
vga_protect(struct i740fb_par * par)724 static void vga_protect(struct i740fb_par *par)
725 {
726 	/* disable the display */
727 	i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);
728 
729 	i740inb(par, 0x3DA);
730 	i740outb(par, VGA_ATT_W, 0x00);	/* enable palette access */
731 }
732 
vga_unprotect(struct i740fb_par * par)733 static void vga_unprotect(struct i740fb_par *par)
734 {
735 	/* reenable display */
736 	i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);
737 
738 	i740inb(par, 0x3DA);
739 	i740outb(par, VGA_ATT_W, 0x20);	/* disable palette access */
740 }
741 
i740fb_set_par(struct fb_info * info)742 static int i740fb_set_par(struct fb_info *info)
743 {
744 	struct i740fb_par *par = info->par;
745 	u32 itemp;
746 	int i;
747 
748 	i = i740fb_decode_var(&info->var, par, info);
749 	if (i)
750 		return i;
751 
752 	memset_io(info->screen_base, 0, info->screen_size);
753 
754 	vga_protect(par);
755 
756 	i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
757 
758 	mdelay(1);
759 
760 	i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
761 	i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
762 	i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
763 	i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
764 
765 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
766 			par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
767 
768 	i740inb(par, 0x3DA);
769 	i740outb(par, 0x3C0, 0x00);
770 
771 	/* update misc output register */
772 	i740outb(par, VGA_MIS_W, par->misc | 0x01);
773 
774 	/* synchronous reset on */
775 	i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
776 	/* write sequencer registers */
777 	i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE,
778 			par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
779 	for (i = 2; i < VGA_SEQ_C; i++)
780 		i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
781 
782 	/* synchronous reset off */
783 	i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
784 
785 	/* deprotect CRT registers 0-7 */
786 	i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END,
787 			par->crtc[VGA_CRTC_V_SYNC_END]);
788 
789 	/* write CRT registers */
790 	for (i = 0; i < VGA_CRT_C; i++)
791 		i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
792 
793 	/* write graphics controller registers */
794 	for (i = 0; i < VGA_GFX_C; i++)
795 		i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
796 
797 	/* write attribute controller registers */
798 	for (i = 0; i < VGA_ATT_C; i++) {
799 		i740inb(par, VGA_IS1_RC);		/* reset flip-flop */
800 		i740outb(par, VGA_ATT_IW, i);
801 		i740outb(par, VGA_ATT_IW, par->atc[i]);
802 	}
803 
804 	i740inb(par, VGA_IS1_RC);
805 	i740outb(par, VGA_ATT_IW, 0x20);
806 
807 	i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
808 	i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
809 	i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START,
810 			par->ext_vert_sync_start);
811 	i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START,
812 			par->ext_vert_blank_start);
813 	i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
814 	i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
815 	i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
816 	i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
817 	i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
818 
819 	i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,
820 			par->interlace_cntl, INTERLACE_ENABLE);
821 	i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
822 	i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
823 	i740outreg_mask(par, XRX, DISPLAY_CNTL,
824 			par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
825 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
826 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
827 
828 	i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
829 
830 	i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
831 			par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
832 
833 	itemp = readl(par->regs + FWATER_BLC);
834 	itemp &= ~(LMI_BURST_LENGTH | LMI_FIFO_WATERMARK);
835 	itemp |= par->lmi_fifo_watermark;
836 	writel(itemp, par->regs + FWATER_BLC);
837 
838 	i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
839 
840 	i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
841 	i740outreg_mask(par, XRX, IO_CTNL,
842 			par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
843 
844 	if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
845 		i740outb(par, VGA_PEL_MSK, 0xFF);
846 		i740outb(par, VGA_PEL_IW, 0x00);
847 		for (i = 0; i < 256; i++) {
848 			itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2;
849 			i740outb(par, VGA_PEL_D, itemp);
850 			i740outb(par, VGA_PEL_D, itemp);
851 			i740outb(par, VGA_PEL_D, itemp);
852 		}
853 	}
854 
855 	/* Wait for screen to stabilize. */
856 	mdelay(50);
857 	vga_unprotect(par);
858 
859 	info->fix.line_length =
860 			info->var.xres_virtual * info->var.bits_per_pixel / 8;
861 	if (info->var.bits_per_pixel == 8)
862 		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
863 	else
864 		info->fix.visual = FB_VISUAL_TRUECOLOR;
865 
866 	return 0;
867 }
868 
i740fb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)869 static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green,
870 			   unsigned blue, unsigned transp,
871 			   struct fb_info *info)
872 {
873 	u32 r, g, b;
874 
875 	dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
876 		regno, red, green, blue, transp, info->var.bits_per_pixel);
877 
878 	switch (info->fix.visual) {
879 	case FB_VISUAL_PSEUDOCOLOR:
880 		if (regno >= 256)
881 			return -EINVAL;
882 		i740outb(info->par, VGA_PEL_IW, regno);
883 		i740outb(info->par, VGA_PEL_D, red >> 8);
884 		i740outb(info->par, VGA_PEL_D, green >> 8);
885 		i740outb(info->par, VGA_PEL_D, blue >> 8);
886 		break;
887 	case FB_VISUAL_TRUECOLOR:
888 		if (regno >= 16)
889 			return -EINVAL;
890 		r = (red >> (16 - info->var.red.length))
891 			<< info->var.red.offset;
892 		b = (blue >> (16 - info->var.blue.length))
893 			<< info->var.blue.offset;
894 		g = (green >> (16 - info->var.green.length))
895 			<< info->var.green.offset;
896 		((u32 *) info->pseudo_palette)[regno] = r | g | b;
897 		break;
898 	default:
899 		return -EINVAL;
900 	}
901 
902 	return 0;
903 }
904 
i740fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)905 static int i740fb_pan_display(struct fb_var_screeninfo *var,
906 				 struct fb_info *info)
907 {
908 	struct i740fb_par *par = info->par;
909 	u32 base = (var->yoffset * info->var.xres_virtual
910 		 + (var->xoffset & ~7)) >> 2;
911 
912 	dev_dbg(info->device, "pan_display: xoffset: %i yoffset: %i base: %i\n",
913 		var->xoffset, var->yoffset, base);
914 
915 	switch (info->var.bits_per_pixel) {
916 	case 8:
917 		break;
918 	case 15:
919 	case 16:
920 		base *= 2;
921 		break;
922 	case 24:
923 		/*
924 		 * The last bit does not seem to have any effect on the start
925 		 * address register in 24bpp mode, so...
926 		 */
927 		base &= 0xFFFFFFFE; /* ...ignore the last bit. */
928 		base *= 3;
929 		break;
930 	case 32:
931 		base *= 4;
932 		break;
933 	}
934 
935 	par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
936 	par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
937 	par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
938 	par->ext_start_addr =
939 			((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
940 
941 	i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO,  base & 0x000000FF);
942 	i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI,
943 			(base & 0x0000FF00) >> 8);
944 	i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI,
945 			(base & 0x3FC00000) >> 22);
946 	i740outreg(par, VGA_CRT_IC, EXT_START_ADDR,
947 			((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE);
948 
949 	return 0;
950 }
951 
i740fb_blank(int blank_mode,struct fb_info * info)952 static int i740fb_blank(int blank_mode, struct fb_info *info)
953 {
954 	struct i740fb_par *par = info->par;
955 
956 	unsigned char SEQ01;
957 	int DPMSSyncSelect;
958 
959 	switch (blank_mode) {
960 	case FB_BLANK_UNBLANK:
961 	case FB_BLANK_NORMAL:
962 		SEQ01 = 0x00;
963 		DPMSSyncSelect = HSYNC_ON | VSYNC_ON;
964 		break;
965 	case FB_BLANK_VSYNC_SUSPEND:
966 		SEQ01 = 0x20;
967 		DPMSSyncSelect = HSYNC_ON | VSYNC_OFF;
968 		break;
969 	case FB_BLANK_HSYNC_SUSPEND:
970 		SEQ01 = 0x20;
971 		DPMSSyncSelect = HSYNC_OFF | VSYNC_ON;
972 		break;
973 	case FB_BLANK_POWERDOWN:
974 		SEQ01 = 0x20;
975 		DPMSSyncSelect = HSYNC_OFF | VSYNC_OFF;
976 		break;
977 	default:
978 		return -EINVAL;
979 	}
980 	/* Turn the screen on/off */
981 	i740outb(par, SRX, 0x01);
982 	SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
983 	i740outb(par, SRX, 0x01);
984 	i740outb(par, SRX + 1, SEQ01);
985 
986 	/* Set the DPMS mode */
987 	i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
988 
989 	/* Let fbcon do a soft blank for us */
990 	return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
991 }
992 
993 static const struct fb_ops i740fb_ops = {
994 	.owner		= THIS_MODULE,
995 	.fb_open	= i740fb_open,
996 	.fb_release	= i740fb_release,
997 	FB_DEFAULT_IOMEM_OPS,
998 	.fb_check_var	= i740fb_check_var,
999 	.fb_set_par	= i740fb_set_par,
1000 	.fb_setcolreg	= i740fb_setcolreg,
1001 	.fb_blank	= i740fb_blank,
1002 	.fb_pan_display	= i740fb_pan_display,
1003 };
1004 
1005 /* ------------------------------------------------------------------------- */
1006 
i740fb_probe(struct pci_dev * dev,const struct pci_device_id * ent)1007 static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1008 {
1009 	struct fb_info *info;
1010 	struct i740fb_par *par;
1011 	int ret, tmp;
1012 	bool found = false;
1013 	u8 *edid;
1014 
1015 	ret = aperture_remove_conflicting_pci_devices(dev, "i740fb");
1016 	if (ret)
1017 		return ret;
1018 
1019 	info = framebuffer_alloc(sizeof(struct i740fb_par), &(dev->dev));
1020 	if (!info)
1021 		return -ENOMEM;
1022 
1023 	par = info->par;
1024 	mutex_init(&par->open_lock);
1025 
1026 	info->var.activate = FB_ACTIVATE_NOW;
1027 	info->var.bits_per_pixel = 8;
1028 	info->fbops = &i740fb_ops;
1029 	info->pseudo_palette = par->pseudo_palette;
1030 
1031 	ret = pci_enable_device(dev);
1032 	if (ret) {
1033 		dev_err(info->device, "cannot enable PCI device\n");
1034 		goto err_enable_device;
1035 	}
1036 
1037 	ret = pci_request_regions(dev, info->fix.id);
1038 	if (ret) {
1039 		dev_err(info->device, "error requesting regions\n");
1040 		goto err_request_regions;
1041 	}
1042 
1043 	info->screen_base = pci_ioremap_wc_bar(dev, 0);
1044 	if (!info->screen_base) {
1045 		dev_err(info->device, "error remapping base\n");
1046 		ret = -ENOMEM;
1047 		goto err_ioremap_1;
1048 	}
1049 
1050 	par->regs = pci_ioremap_bar(dev, 1);
1051 	if (!par->regs) {
1052 		dev_err(info->device, "error remapping MMIO\n");
1053 		ret = -ENOMEM;
1054 		goto err_ioremap_2;
1055 	}
1056 
1057 	/* detect memory size */
1058 	if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1059 							== DRAM_ROW_1_SDRAM)
1060 		i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1061 	else
1062 		i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1063 	info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1064 	/* detect memory type */
1065 	tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
1066 	par->has_sgram = !((tmp & DRAM_RAS_TIMING) ||
1067 			   (tmp & DRAM_RAS_PRECHARGE));
1068 
1069 	fb_info(info, "Intel740 on %s, %ld KB %s\n",
1070 		pci_name(dev), info->screen_size >> 10,
1071 		par->has_sgram ? "SGRAM" : "SDRAM");
1072 
1073 	info->fix = i740fb_fix;
1074 	info->fix.mmio_start = pci_resource_start(dev, 1);
1075 	info->fix.mmio_len = pci_resource_len(dev, 1);
1076 	info->fix.smem_start = pci_resource_start(dev, 0);
1077 	info->fix.smem_len = info->screen_size;
1078 	info->flags = FBINFO_HWACCEL_YPAN;
1079 
1080 	if (i740fb_setup_ddc_bus(info) == 0) {
1081 		par->ddc_registered = true;
1082 		edid = fb_ddc_read(&par->ddc_adapter);
1083 		if (edid) {
1084 			fb_edid_to_monspecs(edid, &info->monspecs);
1085 			kfree(edid);
1086 			if (!info->monspecs.modedb)
1087 				dev_err(info->device,
1088 					"error getting mode database\n");
1089 			else {
1090 				const struct fb_videomode *m;
1091 
1092 				fb_videomode_to_modelist(
1093 					info->monspecs.modedb,
1094 					info->monspecs.modedb_len,
1095 					&info->modelist);
1096 				m = fb_find_best_display(&info->monspecs,
1097 							 &info->modelist);
1098 				if (m) {
1099 					fb_videomode_to_var(&info->var, m);
1100 					/* fill all other info->var's fields */
1101 					if (!i740fb_check_var(&info->var, info))
1102 						found = true;
1103 				}
1104 			}
1105 		}
1106 	}
1107 
1108 	if (!mode_option && !found)
1109 		mode_option = "640x480-8@60";
1110 
1111 	if (mode_option) {
1112 		ret = fb_find_mode(&info->var, info, mode_option,
1113 				   info->monspecs.modedb,
1114 				   info->monspecs.modedb_len,
1115 				   NULL, info->var.bits_per_pixel);
1116 		if (!ret || ret == 4) {
1117 			dev_err(info->device, "mode %s not found\n",
1118 				mode_option);
1119 			ret = -EINVAL;
1120 		}
1121 	}
1122 
1123 	fb_destroy_modedb(info->monspecs.modedb);
1124 	info->monspecs.modedb = NULL;
1125 
1126 	/* maximize virtual vertical size for fast scrolling */
1127 	info->var.yres_virtual = info->fix.smem_len * 8 /
1128 			(info->var.bits_per_pixel * info->var.xres_virtual);
1129 
1130 	if (ret == -EINVAL)
1131 		goto err_find_mode;
1132 
1133 	ret = fb_alloc_cmap(&info->cmap, 256, 0);
1134 	if (ret) {
1135 		dev_err(info->device, "cannot allocate colormap\n");
1136 		goto err_alloc_cmap;
1137 	}
1138 
1139 	ret = register_framebuffer(info);
1140 	if (ret) {
1141 		dev_err(info->device, "error registering framebuffer\n");
1142 		goto err_reg_framebuffer;
1143 	}
1144 
1145 	fb_info(info, "%s frame buffer device\n", info->fix.id);
1146 	pci_set_drvdata(dev, info);
1147 	if (mtrr)
1148 		par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1149 						  info->fix.smem_len);
1150 	return 0;
1151 
1152 err_reg_framebuffer:
1153 	fb_dealloc_cmap(&info->cmap);
1154 err_alloc_cmap:
1155 err_find_mode:
1156 	if (par->ddc_registered)
1157 		i2c_del_adapter(&par->ddc_adapter);
1158 	pci_iounmap(dev, par->regs);
1159 err_ioremap_2:
1160 	pci_iounmap(dev, info->screen_base);
1161 err_ioremap_1:
1162 	pci_release_regions(dev);
1163 err_request_regions:
1164 /*	pci_disable_device(dev); */
1165 err_enable_device:
1166 	framebuffer_release(info);
1167 	return ret;
1168 }
1169 
i740fb_remove(struct pci_dev * dev)1170 static void i740fb_remove(struct pci_dev *dev)
1171 {
1172 	struct fb_info *info = pci_get_drvdata(dev);
1173 
1174 	if (info) {
1175 		struct i740fb_par *par = info->par;
1176 		arch_phys_wc_del(par->wc_cookie);
1177 		unregister_framebuffer(info);
1178 		fb_dealloc_cmap(&info->cmap);
1179 		if (par->ddc_registered)
1180 			i2c_del_adapter(&par->ddc_adapter);
1181 		pci_iounmap(dev, par->regs);
1182 		pci_iounmap(dev, info->screen_base);
1183 		pci_release_regions(dev);
1184 /*		pci_disable_device(dev); */
1185 		framebuffer_release(info);
1186 	}
1187 }
1188 
i740fb_suspend(struct device * dev)1189 static int __maybe_unused i740fb_suspend(struct device *dev)
1190 {
1191 	struct fb_info *info = dev_get_drvdata(dev);
1192 	struct i740fb_par *par = info->par;
1193 
1194 	console_lock();
1195 	mutex_lock(&(par->open_lock));
1196 
1197 	/* do nothing if framebuffer is not active */
1198 	if (par->ref_count == 0) {
1199 		mutex_unlock(&(par->open_lock));
1200 		console_unlock();
1201 		return 0;
1202 	}
1203 
1204 	fb_set_suspend(info, 1);
1205 
1206 	mutex_unlock(&(par->open_lock));
1207 	console_unlock();
1208 
1209 	return 0;
1210 }
1211 
i740fb_resume(struct device * dev)1212 static int __maybe_unused i740fb_resume(struct device *dev)
1213 {
1214 	struct fb_info *info = dev_get_drvdata(dev);
1215 	struct i740fb_par *par = info->par;
1216 
1217 	console_lock();
1218 	mutex_lock(&(par->open_lock));
1219 
1220 	if (par->ref_count == 0)
1221 		goto fail;
1222 
1223 	i740fb_set_par(info);
1224 	fb_set_suspend(info, 0);
1225 
1226 fail:
1227 	mutex_unlock(&(par->open_lock));
1228 	console_unlock();
1229 	return 0;
1230 }
1231 
1232 static const struct dev_pm_ops i740fb_pm_ops = {
1233 #ifdef CONFIG_PM_SLEEP
1234 	.suspend	= i740fb_suspend,
1235 	.resume		= i740fb_resume,
1236 	.freeze		= NULL,
1237 	.thaw		= i740fb_resume,
1238 	.poweroff	= i740fb_suspend,
1239 	.restore	= i740fb_resume,
1240 #endif /* CONFIG_PM_SLEEP */
1241 };
1242 
1243 #define I740_ID_PCI 0x00d1
1244 #define I740_ID_AGP 0x7800
1245 
1246 static const struct pci_device_id i740fb_id_table[] = {
1247 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) },
1248 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) },
1249 	{ 0 }
1250 };
1251 MODULE_DEVICE_TABLE(pci, i740fb_id_table);
1252 
1253 static struct pci_driver i740fb_driver = {
1254 	.name		= "i740fb",
1255 	.id_table	= i740fb_id_table,
1256 	.probe		= i740fb_probe,
1257 	.remove		= i740fb_remove,
1258 	.driver.pm	= &i740fb_pm_ops,
1259 };
1260 
1261 #ifndef MODULE
i740fb_setup(char * options)1262 static int  __init i740fb_setup(char *options)
1263 {
1264 	char *opt;
1265 
1266 	if (!options || !*options)
1267 		return 0;
1268 
1269 	while ((opt = strsep(&options, ",")) != NULL) {
1270 		if (!*opt)
1271 			continue;
1272 		else if (!strncmp(opt, "mtrr:", 5))
1273 			mtrr = simple_strtoul(opt + 5, NULL, 0);
1274 		else
1275 			mode_option = opt;
1276 	}
1277 
1278 	return 0;
1279 }
1280 #endif
1281 
i740fb_init(void)1282 static int __init i740fb_init(void)
1283 {
1284 #ifndef MODULE
1285 	char *option = NULL;
1286 #endif
1287 
1288 	if (fb_modesetting_disabled("i740fb"))
1289 		return -ENODEV;
1290 
1291 #ifndef MODULE
1292 	if (fb_get_options("i740fb", &option))
1293 		return -ENODEV;
1294 	i740fb_setup(option);
1295 #endif
1296 
1297 	return pci_register_driver(&i740fb_driver);
1298 }
1299 
i740fb_exit(void)1300 static void __exit i740fb_exit(void)
1301 {
1302 	pci_unregister_driver(&i740fb_driver);
1303 }
1304 
1305 module_init(i740fb_init);
1306 module_exit(i740fb_exit);
1307 
1308 MODULE_AUTHOR("(c) 2011 Ondrej Zary <linux@rainbow-software.org>");
1309 MODULE_LICENSE("GPL");
1310 MODULE_DESCRIPTION("fbdev driver for Intel740");
1311 
1312 module_param(mode_option, charp, 0444);
1313 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
1314 
1315 module_param(mtrr, int, 0444);
1316 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
1317