1 /*
2 * QEMU i440FX PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/range.h"
28 #include "hw/i386/pc.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_host.h"
31 #include "hw/pci-host/i440fx.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "qapi/error.h"
35 #include "migration/vmstate.h"
36 #include "qapi/visitor.h"
37 #include "qemu/error-report.h"
38 #include "qom/object.h"
39
40 /*
41 * I440FX chipset data sheet.
42 * https://wiki.qemu.org/File:29054901.pdf
43 */
44
45 OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE)
46
47 struct I440FXState {
48 PCIHostState parent_obj;
49
50 MemoryRegion *system_memory;
51 MemoryRegion *io_memory;
52 MemoryRegion *pci_address_space;
53 MemoryRegion *ram_memory;
54 Range pci_hole;
55 uint64_t below_4g_mem_size;
56 uint64_t above_4g_mem_size;
57 uint64_t pci_hole64_size;
58 bool pci_hole64_fix;
59
60 char *pci_type;
61 };
62
63 #define I440FX_PAM 0x59
64 #define I440FX_PAM_SIZE 7
65 #define I440FX_SMRAM 0x72
66
67 /* Keep it 2G to comply with older win32 guests */
68 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
69
70 /* Older coreboot versions (4.0 and older) read a config register that doesn't
71 * exist in real hardware, to get the RAM size from QEMU.
72 */
73 #define I440FX_COREBOOT_RAM_SIZE 0x57
74
i440fx_realize(PCIDevice * dev,Error ** errp)75 static void i440fx_realize(PCIDevice *dev, Error **errp)
76 {
77 dev->config[I440FX_SMRAM] = 0x02;
78
79 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
80 warn_report("i440fx doesn't support emulated iommu");
81 }
82 }
83
i440fx_update_memory_mappings(PCII440FXState * d)84 static void i440fx_update_memory_mappings(PCII440FXState *d)
85 {
86 int i;
87 PCIDevice *pd = PCI_DEVICE(d);
88
89 memory_region_transaction_begin();
90 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
91 pam_update(&d->pam_regions[i], i,
92 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
93 }
94 memory_region_set_enabled(&d->smram_region,
95 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
96 memory_region_set_enabled(&d->smram,
97 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
98 memory_region_transaction_commit();
99 }
100
101
i440fx_write_config(PCIDevice * dev,uint32_t address,uint32_t val,int len)102 static void i440fx_write_config(PCIDevice *dev,
103 uint32_t address, uint32_t val, int len)
104 {
105 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
106
107 /* XXX: implement SMRAM.D_LOCK */
108 pci_default_write_config(dev, address, val, len);
109 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
110 range_covers_byte(address, len, I440FX_SMRAM)) {
111 i440fx_update_memory_mappings(d);
112 }
113 }
114
i440fx_post_load(void * opaque,int version_id)115 static int i440fx_post_load(void *opaque, int version_id)
116 {
117 PCII440FXState *d = opaque;
118
119 i440fx_update_memory_mappings(d);
120 return 0;
121 }
122
123 static const VMStateDescription vmstate_i440fx = {
124 .name = "I440FX",
125 .version_id = 3,
126 .minimum_version_id = 3,
127 .post_load = i440fx_post_load,
128 .fields = (const VMStateField[]) {
129 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
130 /* Used to be smm_enabled, which was basically always zero because
131 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
132 */
133 VMSTATE_UNUSED(1),
134 VMSTATE_END_OF_LIST()
135 }
136 };
137
i440fx_pcihost_get_pci_hole_start(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)138 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
139 const char *name, void *opaque,
140 Error **errp)
141 {
142 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
143 uint64_t val64;
144 uint32_t value;
145
146 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
147 value = val64;
148 assert(value == val64);
149 visit_type_uint32(v, name, &value, errp);
150 }
151
i440fx_pcihost_get_pci_hole_end(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)152 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
153 const char *name, void *opaque,
154 Error **errp)
155 {
156 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
157 uint64_t val64;
158 uint32_t value;
159
160 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
161 value = val64;
162 assert(value == val64);
163 visit_type_uint32(v, name, &value, errp);
164 }
165
166 /*
167 * The 64bit PCI hole start is set by the Guest firmware
168 * as the address of the first 64bit PCI MEM resource.
169 * If no PCI device has resources on the 64bit area,
170 * the 64bit PCI hole will start after "over 4G RAM" and the
171 * reserved space for memory hotplug if any.
172 */
i440fx_pcihost_get_pci_hole64_start_value(Object * obj)173 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
174 {
175 PCIHostState *h = PCI_HOST_BRIDGE(obj);
176 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
177 Range w64;
178 uint64_t value;
179
180 pci_bus_get_w64_range(h->bus, &w64);
181 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
182 if (!value && s->pci_hole64_fix) {
183 value = pc_pci_hole64_start();
184 }
185 return value;
186 }
187
i440fx_pcihost_get_pci_hole64_start(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)188 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
189 const char *name,
190 void *opaque, Error **errp)
191 {
192 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
193
194 visit_type_uint64(v, name, &hole64_start, errp);
195 }
196
197 /*
198 * The 64bit PCI hole end is set by the Guest firmware
199 * as the address of the last 64bit PCI MEM resource.
200 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
201 * that can be configured by the user.
202 */
i440fx_pcihost_get_pci_hole64_end(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)203 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
204 const char *name, void *opaque,
205 Error **errp)
206 {
207 PCIHostState *h = PCI_HOST_BRIDGE(obj);
208 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
209 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
210 Range w64;
211 uint64_t value, hole64_end;
212
213 pci_bus_get_w64_range(h->bus, &w64);
214 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
215 hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
216 if (s->pci_hole64_fix && value < hole64_end) {
217 value = hole64_end;
218 }
219 visit_type_uint64(v, name, &value, errp);
220 }
221
i440fx_pcihost_initfn(Object * obj)222 static void i440fx_pcihost_initfn(Object *obj)
223 {
224 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
225 PCIHostState *phb = PCI_HOST_BRIDGE(obj);
226
227 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
228 "pci-conf-idx", 4);
229 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
230 "pci-conf-data", 4);
231
232 object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
233 (Object **) &s->ram_memory,
234 qdev_prop_allow_set_link_before_realize, 0);
235
236 object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
237 (Object **) &s->pci_address_space,
238 qdev_prop_allow_set_link_before_realize, 0);
239
240 object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
241 (Object **) &s->system_memory,
242 qdev_prop_allow_set_link_before_realize, 0);
243
244 object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
245 (Object **) &s->io_memory,
246 qdev_prop_allow_set_link_before_realize, 0);
247 }
248
i440fx_pcihost_realize(DeviceState * dev,Error ** errp)249 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
250 {
251 ERRP_GUARD();
252 I440FXState *s = I440FX_PCI_HOST_BRIDGE(dev);
253 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
254 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
255 PCIBus *b;
256 PCIDevice *d;
257 PCII440FXState *f;
258 unsigned i;
259
260 memory_region_add_subregion(s->io_memory, 0xcf8, &phb->conf_mem);
261 sysbus_init_ioports(sbd, 0xcf8, 4);
262
263 memory_region_add_subregion(s->io_memory, 0xcfc, &phb->data_mem);
264 sysbus_init_ioports(sbd, 0xcfc, 4);
265
266 /* register i440fx 0xcf8 port as coalesced pio */
267 memory_region_set_flush_coalesced(&phb->data_mem);
268 memory_region_add_coalescing(&phb->conf_mem, 0, 4);
269
270 b = pci_root_bus_new(dev, NULL, s->pci_address_space,
271 s->io_memory, 0, TYPE_PCI_BUS);
272 phb->bus = b;
273
274 d = pci_create_simple(b, 0, s->pci_type);
275 f = I440FX_PCI_DEVICE(d);
276
277 range_set_bounds(&s->pci_hole, s->below_4g_mem_size,
278 IO_APIC_DEFAULT_ADDRESS - 1);
279
280 /* setup pci memory mapping */
281 pc_pci_as_mapping_init(s->system_memory, s->pci_address_space);
282
283 /* if *disabled* show SMRAM to all CPUs */
284 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
285 s->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE);
286 memory_region_add_subregion_overlap(s->system_memory, SMRAM_C_BASE,
287 &f->smram_region, 1);
288 memory_region_set_enabled(&f->smram_region, true);
289
290 /* smram, as seen by SMM CPUs */
291 memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB);
292 memory_region_set_enabled(&f->smram, true);
293 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
294 s->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE);
295 memory_region_set_enabled(&f->low_smram, true);
296 memory_region_add_subregion(&f->smram, SMRAM_C_BASE, &f->low_smram);
297 object_property_add_const_link(qdev_get_machine(), "smram",
298 OBJECT(&f->smram));
299
300 init_pam(&f->pam_regions[0], OBJECT(d), s->ram_memory, s->system_memory,
301 s->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE);
302 for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
303 init_pam(&f->pam_regions[i + 1], OBJECT(d), s->ram_memory,
304 s->system_memory, s->pci_address_space,
305 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
306 }
307
308 ram_addr_t ram_size = s->below_4g_mem_size + s->above_4g_mem_size;
309 ram_size = ram_size / 8 / 1024 / 1024;
310 if (ram_size > 255) {
311 ram_size = 255;
312 }
313 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
314
315 i440fx_update_memory_mappings(f);
316 }
317
i440fx_class_init(ObjectClass * klass,void * data)318 static void i440fx_class_init(ObjectClass *klass, void *data)
319 {
320 DeviceClass *dc = DEVICE_CLASS(klass);
321 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
322
323 k->realize = i440fx_realize;
324 k->config_write = i440fx_write_config;
325 k->vendor_id = PCI_VENDOR_ID_INTEL;
326 k->device_id = PCI_DEVICE_ID_INTEL_82441;
327 k->revision = 0x02;
328 k->class_id = PCI_CLASS_BRIDGE_HOST;
329 dc->desc = "Host bridge";
330 dc->vmsd = &vmstate_i440fx;
331 /*
332 * PCI-facing part of the host bridge, not usable without the
333 * host-facing part, which can't be device_add'ed, yet.
334 */
335 dc->user_creatable = false;
336 dc->hotpluggable = false;
337 }
338
339 static const TypeInfo i440fx_info = {
340 .name = TYPE_I440FX_PCI_DEVICE,
341 .parent = TYPE_PCI_DEVICE,
342 .instance_size = sizeof(PCII440FXState),
343 .class_init = i440fx_class_init,
344 .interfaces = (InterfaceInfo[]) {
345 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
346 { },
347 },
348 };
349
i440fx_pcihost_root_bus_path(PCIHostState * host_bridge,PCIBus * rootbus)350 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
351 PCIBus *rootbus)
352 {
353 return "0000:00";
354 }
355
356 static Property i440fx_props[] = {
357 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
358 pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
359 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, I440FXState,
360 below_4g_mem_size, 0),
361 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, I440FXState,
362 above_4g_mem_size, 0),
363 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
364 DEFINE_PROP_STRING(I440FX_HOST_PROP_PCI_TYPE, I440FXState, pci_type),
365 DEFINE_PROP_END_OF_LIST(),
366 };
367
i440fx_pcihost_class_init(ObjectClass * klass,void * data)368 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
369 {
370 DeviceClass *dc = DEVICE_CLASS(klass);
371 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
372
373 hc->root_bus_path = i440fx_pcihost_root_bus_path;
374 dc->realize = i440fx_pcihost_realize;
375 dc->fw_name = "pci";
376 device_class_set_props(dc, i440fx_props);
377 /* Reason: needs to be wired up by pc_init1 */
378 dc->user_creatable = false;
379
380 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
381 i440fx_pcihost_get_pci_hole_start,
382 NULL, NULL, NULL);
383
384 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
385 i440fx_pcihost_get_pci_hole_end,
386 NULL, NULL, NULL);
387
388 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
389 i440fx_pcihost_get_pci_hole64_start,
390 NULL, NULL, NULL);
391
392 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
393 i440fx_pcihost_get_pci_hole64_end,
394 NULL, NULL, NULL);
395 }
396
397 static const TypeInfo i440fx_pcihost_info = {
398 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
399 .parent = TYPE_PCI_HOST_BRIDGE,
400 .instance_size = sizeof(I440FXState),
401 .instance_init = i440fx_pcihost_initfn,
402 .class_init = i440fx_pcihost_class_init,
403 };
404
i440fx_register_types(void)405 static void i440fx_register_types(void)
406 {
407 type_register_static(&i440fx_info);
408 type_register_static(&i440fx_pcihost_info);
409 }
410
411 type_init(i440fx_register_types)
412