1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26
27 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
28 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
29
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
32
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
35
36 static struct class timecard_class = {
37 .name = "timecard",
38 };
39
40 struct ocp_reg {
41 u32 ctrl;
42 u32 status;
43 u32 select;
44 u32 version;
45 u32 time_ns;
46 u32 time_sec;
47 u32 __pad0[2];
48 u32 adjust_ns;
49 u32 adjust_sec;
50 u32 __pad1[2];
51 u32 offset_ns;
52 u32 offset_window_ns;
53 u32 __pad2[2];
54 u32 drift_ns;
55 u32 drift_window_ns;
56 u32 __pad3[6];
57 u32 servo_offset_p;
58 u32 servo_offset_i;
59 u32 servo_drift_p;
60 u32 servo_drift_i;
61 u32 status_offset;
62 u32 status_drift;
63 };
64
65 #define OCP_CTRL_ENABLE BIT(0)
66 #define OCP_CTRL_ADJUST_TIME BIT(1)
67 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
68 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
69 #define OCP_CTRL_ADJUST_SERVO BIT(8)
70 #define OCP_CTRL_READ_TIME_REQ BIT(30)
71 #define OCP_CTRL_READ_TIME_DONE BIT(31)
72
73 #define OCP_STATUS_IN_SYNC BIT(0)
74 #define OCP_STATUS_IN_HOLDOVER BIT(1)
75
76 #define OCP_SELECT_CLK_NONE 0
77 #define OCP_SELECT_CLK_REG 0xfe
78
79 struct tod_reg {
80 u32 ctrl;
81 u32 status;
82 u32 uart_polarity;
83 u32 version;
84 u32 adj_sec;
85 u32 __pad0[3];
86 u32 uart_baud;
87 u32 __pad1[3];
88 u32 utc_status;
89 u32 leap;
90 };
91
92 #define TOD_CTRL_PROTOCOL BIT(28)
93 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
94 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
95 #define TOD_CTRL_ENABLE BIT(0)
96 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
97 #define TOD_CTRL_GNSS_SHIFT 24
98
99 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
100 #define TOD_STATUS_UTC_VALID BIT(8)
101 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
102 #define TOD_STATUS_LEAP_VALID BIT(16)
103
104 struct ts_reg {
105 u32 enable;
106 u32 error;
107 u32 polarity;
108 u32 version;
109 u32 __pad0[4];
110 u32 cable_delay;
111 u32 __pad1[3];
112 u32 intr;
113 u32 intr_mask;
114 u32 event_count;
115 u32 __pad2[1];
116 u32 ts_count;
117 u32 time_ns;
118 u32 time_sec;
119 u32 data_width;
120 u32 data;
121 };
122
123 struct pps_reg {
124 u32 ctrl;
125 u32 status;
126 u32 __pad0[6];
127 u32 cable_delay;
128 };
129
130 #define PPS_STATUS_FILTER_ERR BIT(0)
131 #define PPS_STATUS_SUPERV_ERR BIT(1)
132
133 struct img_reg {
134 u32 version;
135 };
136
137 struct gpio_reg {
138 u32 gpio1;
139 u32 __pad0;
140 u32 gpio2;
141 u32 __pad1;
142 };
143
144 struct irig_master_reg {
145 u32 ctrl;
146 u32 status;
147 u32 __pad0;
148 u32 version;
149 u32 adj_sec;
150 u32 mode_ctrl;
151 };
152
153 #define IRIG_M_CTRL_ENABLE BIT(0)
154
155 struct irig_slave_reg {
156 u32 ctrl;
157 u32 status;
158 u32 __pad0;
159 u32 version;
160 u32 adj_sec;
161 u32 mode_ctrl;
162 };
163
164 #define IRIG_S_CTRL_ENABLE BIT(0)
165
166 struct dcf_master_reg {
167 u32 ctrl;
168 u32 status;
169 u32 __pad0;
170 u32 version;
171 u32 adj_sec;
172 };
173
174 #define DCF_M_CTRL_ENABLE BIT(0)
175
176 struct dcf_slave_reg {
177 u32 ctrl;
178 u32 status;
179 u32 __pad0;
180 u32 version;
181 u32 adj_sec;
182 };
183
184 #define DCF_S_CTRL_ENABLE BIT(0)
185
186 struct signal_reg {
187 u32 enable;
188 u32 status;
189 u32 polarity;
190 u32 version;
191 u32 __pad0[4];
192 u32 cable_delay;
193 u32 __pad1[3];
194 u32 intr;
195 u32 intr_mask;
196 u32 __pad2[2];
197 u32 start_ns;
198 u32 start_sec;
199 u32 pulse_ns;
200 u32 pulse_sec;
201 u32 period_ns;
202 u32 period_sec;
203 u32 repeat_count;
204 };
205
206 struct frequency_reg {
207 u32 ctrl;
208 u32 status;
209 };
210
211 struct board_config_reg {
212 u32 mro50_serial_activate;
213 };
214
215 #define FREQ_STATUS_VALID BIT(31)
216 #define FREQ_STATUS_ERROR BIT(30)
217 #define FREQ_STATUS_OVERRUN BIT(29)
218 #define FREQ_STATUS_MASK GENMASK(23, 0)
219
220 struct ptp_ocp_flash_info {
221 const char *name;
222 int pci_offset;
223 int data_size;
224 void *data;
225 };
226
227 struct ptp_ocp_firmware_header {
228 char magic[4];
229 __be16 pci_vendor_id;
230 __be16 pci_device_id;
231 __be32 image_size;
232 __be16 hw_revision;
233 __be16 crc;
234 };
235
236 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
237
238 struct ptp_ocp_i2c_info {
239 const char *name;
240 unsigned long fixed_rate;
241 size_t data_size;
242 void *data;
243 };
244
245 struct ptp_ocp_ext_info {
246 int index;
247 irqreturn_t (*irq_fcn)(int irq, void *priv);
248 int (*enable)(void *priv, u32 req, bool enable);
249 };
250
251 struct ptp_ocp_ext_src {
252 void __iomem *mem;
253 struct ptp_ocp *bp;
254 struct ptp_ocp_ext_info *info;
255 int irq_vec;
256 };
257
258 enum ptp_ocp_sma_mode {
259 SMA_MODE_IN,
260 SMA_MODE_OUT,
261 };
262
263 struct ptp_ocp_sma_connector {
264 enum ptp_ocp_sma_mode mode;
265 bool fixed_fcn;
266 bool fixed_dir;
267 bool disabled;
268 u8 default_fcn;
269 };
270
271 struct ocp_attr_group {
272 u64 cap;
273 const struct attribute_group *group;
274 };
275
276 #define OCP_CAP_BASIC BIT(0)
277 #define OCP_CAP_SIGNAL BIT(1)
278 #define OCP_CAP_FREQ BIT(2)
279
280 struct ptp_ocp_signal {
281 ktime_t period;
282 ktime_t pulse;
283 ktime_t phase;
284 ktime_t start;
285 int duty;
286 bool polarity;
287 bool running;
288 };
289
290 struct ptp_ocp_serial_port {
291 int line;
292 int baud;
293 };
294
295 #define OCP_BOARD_ID_LEN 13
296 #define OCP_SERIAL_LEN 6
297
298 struct ptp_ocp {
299 struct pci_dev *pdev;
300 struct device dev;
301 spinlock_t lock;
302 struct ocp_reg __iomem *reg;
303 struct tod_reg __iomem *tod;
304 struct pps_reg __iomem *pps_to_ext;
305 struct pps_reg __iomem *pps_to_clk;
306 struct board_config_reg __iomem *board_config;
307 struct gpio_reg __iomem *pps_select;
308 struct gpio_reg __iomem *sma_map1;
309 struct gpio_reg __iomem *sma_map2;
310 struct irig_master_reg __iomem *irig_out;
311 struct irig_slave_reg __iomem *irig_in;
312 struct dcf_master_reg __iomem *dcf_out;
313 struct dcf_slave_reg __iomem *dcf_in;
314 struct tod_reg __iomem *nmea_out;
315 struct frequency_reg __iomem *freq_in[4];
316 struct ptp_ocp_ext_src *signal_out[4];
317 struct ptp_ocp_ext_src *pps;
318 struct ptp_ocp_ext_src *ts0;
319 struct ptp_ocp_ext_src *ts1;
320 struct ptp_ocp_ext_src *ts2;
321 struct ptp_ocp_ext_src *ts3;
322 struct ptp_ocp_ext_src *ts4;
323 struct ocp_art_gpio_reg __iomem *art_sma;
324 struct img_reg __iomem *image;
325 struct ptp_clock *ptp;
326 struct ptp_clock_info ptp_info;
327 struct platform_device *i2c_ctrl;
328 struct platform_device *spi_flash;
329 struct clk_hw *i2c_clk;
330 struct timer_list watchdog;
331 const struct attribute_group **attr_group;
332 const struct ptp_ocp_eeprom_map *eeprom_map;
333 struct dentry *debug_root;
334 time64_t gnss_lost;
335 int id;
336 int n_irqs;
337 struct ptp_ocp_serial_port gnss_port;
338 struct ptp_ocp_serial_port gnss2_port;
339 struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */
340 struct ptp_ocp_serial_port nmea_port;
341 bool fw_loader;
342 u8 fw_tag;
343 u16 fw_version;
344 u8 board_id[OCP_BOARD_ID_LEN];
345 u8 serial[OCP_SERIAL_LEN];
346 bool has_eeprom_data;
347 u32 pps_req_map;
348 int flash_start;
349 u32 utc_tai_offset;
350 u32 ts_window_adjust;
351 u64 fw_cap;
352 struct ptp_ocp_signal signal[4];
353 struct ptp_ocp_sma_connector sma[4];
354 const struct ocp_sma_op *sma_op;
355 };
356
357 #define OCP_REQ_TIMESTAMP BIT(0)
358 #define OCP_REQ_PPS BIT(1)
359
360 struct ocp_resource {
361 unsigned long offset;
362 int size;
363 int irq_vec;
364 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
365 void *extra;
366 unsigned long bp_offset;
367 const char * const name;
368 };
369
370 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
371 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
372 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
373 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
374 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
375 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
376 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
377 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
378 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
379 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
380 struct ptp_perout_request *req);
381 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
382 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
383
384 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
385
386 static const struct ocp_attr_group fb_timecard_groups[];
387
388 static const struct ocp_attr_group art_timecard_groups[];
389
390 struct ptp_ocp_eeprom_map {
391 u16 off;
392 u16 len;
393 u32 bp_offset;
394 const void * const tag;
395 };
396
397 #define EEPROM_ENTRY(addr, member) \
398 .off = addr, \
399 .len = sizeof_field(struct ptp_ocp, member), \
400 .bp_offset = offsetof(struct ptp_ocp, member)
401
402 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
403 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
404 })
405
406 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
407 { EEPROM_ENTRY(0x43, board_id) },
408 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
409 { }
410 };
411
412 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
413 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
414 { EEPROM_ENTRY(0x200 + 0x63, serial) },
415 { }
416 };
417
418 #define bp_assign_entry(bp, res, val) ({ \
419 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
420 *(typeof(val) *)addr = val; \
421 })
422
423 #define OCP_RES_LOCATION(member) \
424 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
425
426 #define OCP_MEM_RESOURCE(member) \
427 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
428
429 #define OCP_SERIAL_RESOURCE(member) \
430 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
431
432 #define OCP_I2C_RESOURCE(member) \
433 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
434
435 #define OCP_SPI_RESOURCE(member) \
436 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
437
438 #define OCP_EXT_RESOURCE(member) \
439 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
440
441 /* This is the MSI vector mapping used.
442 * 0: PPS (TS5)
443 * 1: TS0
444 * 2: TS1
445 * 3: GNSS1
446 * 4: GNSS2
447 * 5: MAC
448 * 6: TS2
449 * 7: I2C controller
450 * 8: HWICAP (notused)
451 * 9: SPI Flash
452 * 10: NMEA
453 * 11: Signal Generator 1
454 * 12: Signal Generator 2
455 * 13: Signal Generator 3
456 * 14: Signal Generator 4
457 * 15: TS3
458 * 16: TS4
459 --
460 * 8: Orolia TS1
461 * 10: Orolia TS2
462 * 11: Orolia TS0 (GNSS)
463 * 12: Orolia PPS
464 * 14: Orolia TS3
465 * 15: Orolia TS4
466 */
467
468 static struct ocp_resource ocp_fb_resource[] = {
469 {
470 OCP_MEM_RESOURCE(reg),
471 .offset = 0x01000000, .size = 0x10000,
472 },
473 {
474 OCP_EXT_RESOURCE(ts0),
475 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
476 .extra = &(struct ptp_ocp_ext_info) {
477 .index = 0,
478 .irq_fcn = ptp_ocp_ts_irq,
479 .enable = ptp_ocp_ts_enable,
480 },
481 },
482 {
483 OCP_EXT_RESOURCE(ts1),
484 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
485 .extra = &(struct ptp_ocp_ext_info) {
486 .index = 1,
487 .irq_fcn = ptp_ocp_ts_irq,
488 .enable = ptp_ocp_ts_enable,
489 },
490 },
491 {
492 OCP_EXT_RESOURCE(ts2),
493 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
494 .extra = &(struct ptp_ocp_ext_info) {
495 .index = 2,
496 .irq_fcn = ptp_ocp_ts_irq,
497 .enable = ptp_ocp_ts_enable,
498 },
499 },
500 {
501 OCP_EXT_RESOURCE(ts3),
502 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
503 .extra = &(struct ptp_ocp_ext_info) {
504 .index = 3,
505 .irq_fcn = ptp_ocp_ts_irq,
506 .enable = ptp_ocp_ts_enable,
507 },
508 },
509 {
510 OCP_EXT_RESOURCE(ts4),
511 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
512 .extra = &(struct ptp_ocp_ext_info) {
513 .index = 4,
514 .irq_fcn = ptp_ocp_ts_irq,
515 .enable = ptp_ocp_ts_enable,
516 },
517 },
518 /* Timestamp for PHC and/or PPS generator */
519 {
520 OCP_EXT_RESOURCE(pps),
521 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
522 .extra = &(struct ptp_ocp_ext_info) {
523 .index = 5,
524 .irq_fcn = ptp_ocp_ts_irq,
525 .enable = ptp_ocp_ts_enable,
526 },
527 },
528 {
529 OCP_EXT_RESOURCE(signal_out[0]),
530 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
531 .extra = &(struct ptp_ocp_ext_info) {
532 .index = 1,
533 .irq_fcn = ptp_ocp_signal_irq,
534 .enable = ptp_ocp_signal_enable,
535 },
536 },
537 {
538 OCP_EXT_RESOURCE(signal_out[1]),
539 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
540 .extra = &(struct ptp_ocp_ext_info) {
541 .index = 2,
542 .irq_fcn = ptp_ocp_signal_irq,
543 .enable = ptp_ocp_signal_enable,
544 },
545 },
546 {
547 OCP_EXT_RESOURCE(signal_out[2]),
548 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
549 .extra = &(struct ptp_ocp_ext_info) {
550 .index = 3,
551 .irq_fcn = ptp_ocp_signal_irq,
552 .enable = ptp_ocp_signal_enable,
553 },
554 },
555 {
556 OCP_EXT_RESOURCE(signal_out[3]),
557 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
558 .extra = &(struct ptp_ocp_ext_info) {
559 .index = 4,
560 .irq_fcn = ptp_ocp_signal_irq,
561 .enable = ptp_ocp_signal_enable,
562 },
563 },
564 {
565 OCP_MEM_RESOURCE(pps_to_ext),
566 .offset = 0x01030000, .size = 0x10000,
567 },
568 {
569 OCP_MEM_RESOURCE(pps_to_clk),
570 .offset = 0x01040000, .size = 0x10000,
571 },
572 {
573 OCP_MEM_RESOURCE(tod),
574 .offset = 0x01050000, .size = 0x10000,
575 },
576 {
577 OCP_MEM_RESOURCE(irig_in),
578 .offset = 0x01070000, .size = 0x10000,
579 },
580 {
581 OCP_MEM_RESOURCE(irig_out),
582 .offset = 0x01080000, .size = 0x10000,
583 },
584 {
585 OCP_MEM_RESOURCE(dcf_in),
586 .offset = 0x01090000, .size = 0x10000,
587 },
588 {
589 OCP_MEM_RESOURCE(dcf_out),
590 .offset = 0x010A0000, .size = 0x10000,
591 },
592 {
593 OCP_MEM_RESOURCE(nmea_out),
594 .offset = 0x010B0000, .size = 0x10000,
595 },
596 {
597 OCP_MEM_RESOURCE(image),
598 .offset = 0x00020000, .size = 0x1000,
599 },
600 {
601 OCP_MEM_RESOURCE(pps_select),
602 .offset = 0x00130000, .size = 0x1000,
603 },
604 {
605 OCP_MEM_RESOURCE(sma_map1),
606 .offset = 0x00140000, .size = 0x1000,
607 },
608 {
609 OCP_MEM_RESOURCE(sma_map2),
610 .offset = 0x00220000, .size = 0x1000,
611 },
612 {
613 OCP_I2C_RESOURCE(i2c_ctrl),
614 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
615 .extra = &(struct ptp_ocp_i2c_info) {
616 .name = "xiic-i2c",
617 .fixed_rate = 50000000,
618 .data_size = sizeof(struct xiic_i2c_platform_data),
619 .data = &(struct xiic_i2c_platform_data) {
620 .num_devices = 2,
621 .devices = (struct i2c_board_info[]) {
622 { I2C_BOARD_INFO("24c02", 0x50) },
623 { I2C_BOARD_INFO("24mac402", 0x58),
624 .platform_data = "mac" },
625 },
626 },
627 },
628 },
629 {
630 OCP_SERIAL_RESOURCE(gnss_port),
631 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
632 .extra = &(struct ptp_ocp_serial_port) {
633 .baud = 115200,
634 },
635 },
636 {
637 OCP_SERIAL_RESOURCE(gnss2_port),
638 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
639 .extra = &(struct ptp_ocp_serial_port) {
640 .baud = 115200,
641 },
642 },
643 {
644 OCP_SERIAL_RESOURCE(mac_port),
645 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
646 .extra = &(struct ptp_ocp_serial_port) {
647 .baud = 57600,
648 },
649 },
650 {
651 OCP_SERIAL_RESOURCE(nmea_port),
652 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
653 },
654 {
655 OCP_SPI_RESOURCE(spi_flash),
656 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
657 .extra = &(struct ptp_ocp_flash_info) {
658 .name = "xilinx_spi", .pci_offset = 0,
659 .data_size = sizeof(struct xspi_platform_data),
660 .data = &(struct xspi_platform_data) {
661 .num_chipselect = 1,
662 .bits_per_word = 8,
663 .num_devices = 1,
664 .force_irq = true,
665 .devices = &(struct spi_board_info) {
666 .modalias = "spi-nor",
667 },
668 },
669 },
670 },
671 {
672 OCP_MEM_RESOURCE(freq_in[0]),
673 .offset = 0x01200000, .size = 0x10000,
674 },
675 {
676 OCP_MEM_RESOURCE(freq_in[1]),
677 .offset = 0x01210000, .size = 0x10000,
678 },
679 {
680 OCP_MEM_RESOURCE(freq_in[2]),
681 .offset = 0x01220000, .size = 0x10000,
682 },
683 {
684 OCP_MEM_RESOURCE(freq_in[3]),
685 .offset = 0x01230000, .size = 0x10000,
686 },
687 {
688 .setup = ptp_ocp_fb_board_init,
689 },
690 { }
691 };
692
693 #define OCP_ART_CONFIG_SIZE 144
694 #define OCP_ART_TEMP_TABLE_SIZE 368
695
696 struct ocp_art_gpio_reg {
697 struct {
698 u32 gpio;
699 u32 __pad[3];
700 } map[4];
701 };
702
703 static struct ocp_resource ocp_art_resource[] = {
704 {
705 OCP_MEM_RESOURCE(reg),
706 .offset = 0x01000000, .size = 0x10000,
707 },
708 {
709 OCP_SERIAL_RESOURCE(gnss_port),
710 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
711 .extra = &(struct ptp_ocp_serial_port) {
712 .baud = 115200,
713 },
714 },
715 {
716 OCP_MEM_RESOURCE(art_sma),
717 .offset = 0x003C0000, .size = 0x1000,
718 },
719 /* Timestamp associated with GNSS1 receiver PPS */
720 {
721 OCP_EXT_RESOURCE(ts0),
722 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
723 .extra = &(struct ptp_ocp_ext_info) {
724 .index = 0,
725 .irq_fcn = ptp_ocp_ts_irq,
726 .enable = ptp_ocp_ts_enable,
727 },
728 },
729 {
730 OCP_EXT_RESOURCE(ts1),
731 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
732 .extra = &(struct ptp_ocp_ext_info) {
733 .index = 1,
734 .irq_fcn = ptp_ocp_ts_irq,
735 .enable = ptp_ocp_ts_enable,
736 },
737 },
738 {
739 OCP_EXT_RESOURCE(ts2),
740 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
741 .extra = &(struct ptp_ocp_ext_info) {
742 .index = 2,
743 .irq_fcn = ptp_ocp_ts_irq,
744 .enable = ptp_ocp_ts_enable,
745 },
746 },
747 {
748 OCP_EXT_RESOURCE(ts3),
749 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
750 .extra = &(struct ptp_ocp_ext_info) {
751 .index = 3,
752 .irq_fcn = ptp_ocp_ts_irq,
753 .enable = ptp_ocp_ts_enable,
754 },
755 },
756 {
757 OCP_EXT_RESOURCE(ts4),
758 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
759 .extra = &(struct ptp_ocp_ext_info) {
760 .index = 4,
761 .irq_fcn = ptp_ocp_ts_irq,
762 .enable = ptp_ocp_ts_enable,
763 },
764 },
765 /* Timestamp associated with Internal PPS of the card */
766 {
767 OCP_EXT_RESOURCE(pps),
768 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
769 .extra = &(struct ptp_ocp_ext_info) {
770 .index = 5,
771 .irq_fcn = ptp_ocp_ts_irq,
772 .enable = ptp_ocp_ts_enable,
773 },
774 },
775 {
776 OCP_SPI_RESOURCE(spi_flash),
777 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
778 .extra = &(struct ptp_ocp_flash_info) {
779 .name = "spi_altera", .pci_offset = 0,
780 .data_size = sizeof(struct altera_spi_platform_data),
781 .data = &(struct altera_spi_platform_data) {
782 .num_chipselect = 1,
783 .num_devices = 1,
784 .devices = &(struct spi_board_info) {
785 .modalias = "spi-nor",
786 },
787 },
788 },
789 },
790 {
791 OCP_I2C_RESOURCE(i2c_ctrl),
792 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
793 .extra = &(struct ptp_ocp_i2c_info) {
794 .name = "ocores-i2c",
795 .fixed_rate = 400000,
796 .data_size = sizeof(struct ocores_i2c_platform_data),
797 .data = &(struct ocores_i2c_platform_data) {
798 .clock_khz = 125000,
799 .bus_khz = 400,
800 .num_devices = 1,
801 .devices = &(struct i2c_board_info) {
802 I2C_BOARD_INFO("24c08", 0x50),
803 },
804 },
805 },
806 },
807 {
808 OCP_SERIAL_RESOURCE(mac_port),
809 .offset = 0x00190000, .irq_vec = 7,
810 .extra = &(struct ptp_ocp_serial_port) {
811 .baud = 9600,
812 },
813 },
814 {
815 OCP_MEM_RESOURCE(board_config),
816 .offset = 0x210000, .size = 0x1000,
817 },
818 {
819 .setup = ptp_ocp_art_board_init,
820 },
821 { }
822 };
823
824 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
825 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
826 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
827 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
828 { }
829 };
830 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
831
832 static DEFINE_MUTEX(ptp_ocp_lock);
833 static DEFINE_IDR(ptp_ocp_idr);
834
835 struct ocp_selector {
836 const char *name;
837 int value;
838 };
839
840 static const struct ocp_selector ptp_ocp_clock[] = {
841 { .name = "NONE", .value = 0 },
842 { .name = "TOD", .value = 1 },
843 { .name = "IRIG", .value = 2 },
844 { .name = "PPS", .value = 3 },
845 { .name = "PTP", .value = 4 },
846 { .name = "RTC", .value = 5 },
847 { .name = "DCF", .value = 6 },
848 { .name = "REGS", .value = 0xfe },
849 { .name = "EXT", .value = 0xff },
850 { }
851 };
852
853 #define SMA_DISABLE BIT(16)
854 #define SMA_ENABLE BIT(15)
855 #define SMA_SELECT_MASK GENMASK(14, 0)
856
857 static const struct ocp_selector ptp_ocp_sma_in[] = {
858 { .name = "10Mhz", .value = 0x0000 },
859 { .name = "PPS1", .value = 0x0001 },
860 { .name = "PPS2", .value = 0x0002 },
861 { .name = "TS1", .value = 0x0004 },
862 { .name = "TS2", .value = 0x0008 },
863 { .name = "IRIG", .value = 0x0010 },
864 { .name = "DCF", .value = 0x0020 },
865 { .name = "TS3", .value = 0x0040 },
866 { .name = "TS4", .value = 0x0080 },
867 { .name = "FREQ1", .value = 0x0100 },
868 { .name = "FREQ2", .value = 0x0200 },
869 { .name = "FREQ3", .value = 0x0400 },
870 { .name = "FREQ4", .value = 0x0800 },
871 { .name = "None", .value = SMA_DISABLE },
872 { }
873 };
874
875 static const struct ocp_selector ptp_ocp_sma_out[] = {
876 { .name = "10Mhz", .value = 0x0000 },
877 { .name = "PHC", .value = 0x0001 },
878 { .name = "MAC", .value = 0x0002 },
879 { .name = "GNSS1", .value = 0x0004 },
880 { .name = "GNSS2", .value = 0x0008 },
881 { .name = "IRIG", .value = 0x0010 },
882 { .name = "DCF", .value = 0x0020 },
883 { .name = "GEN1", .value = 0x0040 },
884 { .name = "GEN2", .value = 0x0080 },
885 { .name = "GEN3", .value = 0x0100 },
886 { .name = "GEN4", .value = 0x0200 },
887 { .name = "GND", .value = 0x2000 },
888 { .name = "VCC", .value = 0x4000 },
889 { }
890 };
891
892 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
893 { .name = "PPS1", .value = 0x0001 },
894 { .name = "10Mhz", .value = 0x0008 },
895 { }
896 };
897
898 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
899 { .name = "PHC", .value = 0x0002 },
900 { .name = "GNSS", .value = 0x0004 },
901 { .name = "10Mhz", .value = 0x0010 },
902 { }
903 };
904
905 struct ocp_sma_op {
906 const struct ocp_selector *tbl[2];
907 void (*init)(struct ptp_ocp *bp);
908 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
909 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
910 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
911 };
912
913 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)914 ptp_ocp_sma_init(struct ptp_ocp *bp)
915 {
916 return bp->sma_op->init(bp);
917 }
918
919 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)920 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
921 {
922 return bp->sma_op->get(bp, sma_nr);
923 }
924
925 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)926 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
927 {
928 return bp->sma_op->set_inputs(bp, sma_nr, val);
929 }
930
931 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)932 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
933 {
934 return bp->sma_op->set_output(bp, sma_nr, val);
935 }
936
937 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)938 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
939 {
940 int i;
941
942 for (i = 0; tbl[i].name; i++)
943 if (tbl[i].value == val)
944 return tbl[i].name;
945 return NULL;
946 }
947
948 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)949 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
950 {
951 const char *select;
952 int i;
953
954 for (i = 0; tbl[i].name; i++) {
955 select = tbl[i].name;
956 if (!strncasecmp(name, select, strlen(select)))
957 return tbl[i].value;
958 }
959 return -EINVAL;
960 }
961
962 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)963 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
964 {
965 ssize_t count;
966 int i;
967
968 count = 0;
969 for (i = 0; tbl[i].name; i++)
970 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
971 if (count)
972 count--;
973 count += sysfs_emit_at(buf, count, "\n");
974 return count;
975 }
976
977 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)978 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
979 struct ptp_system_timestamp *sts)
980 {
981 u32 ctrl, time_sec, time_ns;
982 int i;
983
984 ptp_read_system_prets(sts);
985
986 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
987 iowrite32(ctrl, &bp->reg->ctrl);
988
989 for (i = 0; i < 100; i++) {
990 ctrl = ioread32(&bp->reg->ctrl);
991 if (ctrl & OCP_CTRL_READ_TIME_DONE)
992 break;
993 }
994 ptp_read_system_postts(sts);
995
996 if (sts && bp->ts_window_adjust) {
997 s64 ns = timespec64_to_ns(&sts->post_ts);
998
999 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1000 }
1001
1002 time_ns = ioread32(&bp->reg->time_ns);
1003 time_sec = ioread32(&bp->reg->time_sec);
1004
1005 ts->tv_sec = time_sec;
1006 ts->tv_nsec = time_ns;
1007
1008 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1009 }
1010
1011 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)1012 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1013 struct ptp_system_timestamp *sts)
1014 {
1015 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1016 unsigned long flags;
1017 int err;
1018
1019 spin_lock_irqsave(&bp->lock, flags);
1020 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1021 spin_unlock_irqrestore(&bp->lock, flags);
1022
1023 return err;
1024 }
1025
1026 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)1027 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1028 {
1029 u32 ctrl, time_sec, time_ns;
1030 u32 select;
1031
1032 time_ns = ts->tv_nsec;
1033 time_sec = ts->tv_sec;
1034
1035 select = ioread32(&bp->reg->select);
1036 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1037
1038 iowrite32(time_ns, &bp->reg->adjust_ns);
1039 iowrite32(time_sec, &bp->reg->adjust_sec);
1040
1041 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1042 iowrite32(ctrl, &bp->reg->ctrl);
1043
1044 /* restore clock selection */
1045 iowrite32(select >> 16, &bp->reg->select);
1046 }
1047
1048 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)1049 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1050 {
1051 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1052 unsigned long flags;
1053
1054 spin_lock_irqsave(&bp->lock, flags);
1055 __ptp_ocp_settime_locked(bp, ts);
1056 spin_unlock_irqrestore(&bp->lock, flags);
1057
1058 return 0;
1059 }
1060
1061 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)1062 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1063 {
1064 u32 select, ctrl;
1065
1066 select = ioread32(&bp->reg->select);
1067 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1068
1069 iowrite32(adj_val, &bp->reg->offset_ns);
1070 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1071
1072 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1073 iowrite32(ctrl, &bp->reg->ctrl);
1074
1075 /* restore clock selection */
1076 iowrite32(select >> 16, &bp->reg->select);
1077 }
1078
1079 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)1080 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1081 {
1082 struct timespec64 ts;
1083 unsigned long flags;
1084 int err;
1085
1086 spin_lock_irqsave(&bp->lock, flags);
1087 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1088 if (likely(!err)) {
1089 set_normalized_timespec64(&ts, ts.tv_sec,
1090 ts.tv_nsec + delta_ns);
1091 __ptp_ocp_settime_locked(bp, &ts);
1092 }
1093 spin_unlock_irqrestore(&bp->lock, flags);
1094 }
1095
1096 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)1097 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1098 {
1099 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1100 unsigned long flags;
1101 u32 adj_ns, sign;
1102
1103 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1104 ptp_ocp_adjtime_coarse(bp, delta_ns);
1105 return 0;
1106 }
1107
1108 sign = delta_ns < 0 ? BIT(31) : 0;
1109 adj_ns = sign ? -delta_ns : delta_ns;
1110
1111 spin_lock_irqsave(&bp->lock, flags);
1112 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1113 spin_unlock_irqrestore(&bp->lock, flags);
1114
1115 return 0;
1116 }
1117
1118 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)1119 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1120 {
1121 if (scaled_ppm == 0)
1122 return 0;
1123
1124 return -EOPNOTSUPP;
1125 }
1126
1127 static s32
ptp_ocp_null_getmaxphase(struct ptp_clock_info * ptp_info)1128 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1129 {
1130 return 0;
1131 }
1132
1133 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)1134 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1135 {
1136 return -EOPNOTSUPP;
1137 }
1138
1139 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)1140 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1141 int on)
1142 {
1143 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1144 struct ptp_ocp_ext_src *ext = NULL;
1145 u32 req;
1146 int err;
1147
1148 switch (rq->type) {
1149 case PTP_CLK_REQ_EXTTS:
1150 req = OCP_REQ_TIMESTAMP;
1151 switch (rq->extts.index) {
1152 case 0:
1153 ext = bp->ts0;
1154 break;
1155 case 1:
1156 ext = bp->ts1;
1157 break;
1158 case 2:
1159 ext = bp->ts2;
1160 break;
1161 case 3:
1162 ext = bp->ts3;
1163 break;
1164 case 4:
1165 ext = bp->ts4;
1166 break;
1167 case 5:
1168 ext = bp->pps;
1169 break;
1170 }
1171 break;
1172 case PTP_CLK_REQ_PPS:
1173 req = OCP_REQ_PPS;
1174 ext = bp->pps;
1175 break;
1176 case PTP_CLK_REQ_PEROUT:
1177 switch (rq->perout.index) {
1178 case 0:
1179 /* This is a request for 1PPS on an output SMA.
1180 * Allow, but assume manual configuration.
1181 */
1182 if (on && (rq->perout.period.sec != 1 ||
1183 rq->perout.period.nsec != 0))
1184 return -EINVAL;
1185 return 0;
1186 case 1:
1187 case 2:
1188 case 3:
1189 case 4:
1190 req = rq->perout.index - 1;
1191 ext = bp->signal_out[req];
1192 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1193 if (err)
1194 return err;
1195 break;
1196 }
1197 break;
1198 default:
1199 return -EOPNOTSUPP;
1200 }
1201
1202 err = -ENXIO;
1203 if (ext)
1204 err = ext->info->enable(ext, req, on);
1205
1206 return err;
1207 }
1208
1209 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1210 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1211 enum ptp_pin_function func, unsigned chan)
1212 {
1213 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1214 char buf[16];
1215
1216 switch (func) {
1217 case PTP_PF_NONE:
1218 snprintf(buf, sizeof(buf), "IN: None");
1219 break;
1220 case PTP_PF_EXTTS:
1221 /* Allow timestamps, but require sysfs configuration. */
1222 return 0;
1223 case PTP_PF_PEROUT:
1224 /* channel 0 is 1PPS from PHC.
1225 * channels 1..4 are the frequency generators.
1226 */
1227 if (chan)
1228 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1229 else
1230 snprintf(buf, sizeof(buf), "OUT: PHC");
1231 break;
1232 default:
1233 return -EOPNOTSUPP;
1234 }
1235
1236 return ptp_ocp_sma_store(bp, buf, pin + 1);
1237 }
1238
1239 static const struct ptp_clock_info ptp_ocp_clock_info = {
1240 .owner = THIS_MODULE,
1241 .name = KBUILD_MODNAME,
1242 .max_adj = 100000000,
1243 .gettimex64 = ptp_ocp_gettimex,
1244 .settime64 = ptp_ocp_settime,
1245 .adjtime = ptp_ocp_adjtime,
1246 .adjfine = ptp_ocp_null_adjfine,
1247 .adjphase = ptp_ocp_null_adjphase,
1248 .getmaxphase = ptp_ocp_null_getmaxphase,
1249 .enable = ptp_ocp_enable,
1250 .verify = ptp_ocp_verify,
1251 .pps = true,
1252 .n_ext_ts = 6,
1253 .n_per_out = 5,
1254 };
1255
1256 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1257 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1258 {
1259 u32 ctrl, select;
1260
1261 select = ioread32(&bp->reg->select);
1262 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1263
1264 iowrite32(0, &bp->reg->drift_ns);
1265
1266 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1267 iowrite32(ctrl, &bp->reg->ctrl);
1268
1269 /* restore clock selection */
1270 iowrite32(select >> 16, &bp->reg->select);
1271 }
1272
1273 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1274 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1275 {
1276 unsigned long flags;
1277
1278 spin_lock_irqsave(&bp->lock, flags);
1279
1280 bp->utc_tai_offset = val;
1281
1282 if (bp->irig_out)
1283 iowrite32(val, &bp->irig_out->adj_sec);
1284 if (bp->dcf_out)
1285 iowrite32(val, &bp->dcf_out->adj_sec);
1286 if (bp->nmea_out)
1287 iowrite32(val, &bp->nmea_out->adj_sec);
1288
1289 spin_unlock_irqrestore(&bp->lock, flags);
1290 }
1291
1292 static void
ptp_ocp_watchdog(struct timer_list * t)1293 ptp_ocp_watchdog(struct timer_list *t)
1294 {
1295 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1296 unsigned long flags;
1297 u32 status, utc_offset;
1298
1299 status = ioread32(&bp->pps_to_clk->status);
1300
1301 if (status & PPS_STATUS_SUPERV_ERR) {
1302 iowrite32(status, &bp->pps_to_clk->status);
1303 if (!bp->gnss_lost) {
1304 spin_lock_irqsave(&bp->lock, flags);
1305 __ptp_ocp_clear_drift_locked(bp);
1306 spin_unlock_irqrestore(&bp->lock, flags);
1307 bp->gnss_lost = ktime_get_real_seconds();
1308 }
1309
1310 } else if (bp->gnss_lost) {
1311 bp->gnss_lost = 0;
1312 }
1313
1314 /* if GNSS provides correct data we can rely on
1315 * it to get leap second information
1316 */
1317 if (bp->tod) {
1318 status = ioread32(&bp->tod->utc_status);
1319 utc_offset = status & TOD_STATUS_UTC_MASK;
1320 if (status & TOD_STATUS_UTC_VALID &&
1321 utc_offset != bp->utc_tai_offset)
1322 ptp_ocp_utc_distribute(bp, utc_offset);
1323 }
1324
1325 mod_timer(&bp->watchdog, jiffies + HZ);
1326 }
1327
1328 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1329 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1330 {
1331 ktime_t start, end;
1332 ktime_t delay;
1333 u32 ctrl;
1334
1335 ctrl = ioread32(&bp->reg->ctrl);
1336 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1337
1338 iowrite32(ctrl, &bp->reg->ctrl);
1339
1340 start = ktime_get_ns();
1341
1342 ctrl = ioread32(&bp->reg->ctrl);
1343
1344 end = ktime_get_ns();
1345
1346 delay = end - start;
1347 bp->ts_window_adjust = (delay >> 5) * 3;
1348 }
1349
1350 static int
ptp_ocp_init_clock(struct ptp_ocp * bp)1351 ptp_ocp_init_clock(struct ptp_ocp *bp)
1352 {
1353 struct timespec64 ts;
1354 bool sync;
1355 u32 ctrl;
1356
1357 ctrl = OCP_CTRL_ENABLE;
1358 iowrite32(ctrl, &bp->reg->ctrl);
1359
1360 /* NO DRIFT Correction */
1361 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
1362 iowrite32(0x2000, &bp->reg->servo_offset_p);
1363 iowrite32(0x1000, &bp->reg->servo_offset_i);
1364 iowrite32(0, &bp->reg->servo_drift_p);
1365 iowrite32(0, &bp->reg->servo_drift_i);
1366
1367 /* latch servo values */
1368 ctrl |= OCP_CTRL_ADJUST_SERVO;
1369 iowrite32(ctrl, &bp->reg->ctrl);
1370
1371 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1372 dev_err(&bp->pdev->dev, "clock not enabled\n");
1373 return -ENODEV;
1374 }
1375
1376 ptp_ocp_estimate_pci_timing(bp);
1377
1378 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1379 if (!sync) {
1380 ktime_get_clocktai_ts64(&ts);
1381 ptp_ocp_settime(&bp->ptp_info, &ts);
1382 }
1383
1384 /* If there is a clock supervisor, then enable the watchdog */
1385 if (bp->pps_to_clk) {
1386 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1387 mod_timer(&bp->watchdog, jiffies + HZ);
1388 }
1389
1390 return 0;
1391 }
1392
1393 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1394 ptp_ocp_tod_init(struct ptp_ocp *bp)
1395 {
1396 u32 ctrl, reg;
1397
1398 ctrl = ioread32(&bp->tod->ctrl);
1399 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1400 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1401 iowrite32(ctrl, &bp->tod->ctrl);
1402
1403 reg = ioread32(&bp->tod->utc_status);
1404 if (reg & TOD_STATUS_UTC_VALID)
1405 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1406 }
1407
1408 static const char *
ptp_ocp_tod_proto_name(const int idx)1409 ptp_ocp_tod_proto_name(const int idx)
1410 {
1411 static const char * const proto_name[] = {
1412 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1413 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1414 };
1415 return proto_name[idx];
1416 }
1417
1418 static const char *
ptp_ocp_tod_gnss_name(int idx)1419 ptp_ocp_tod_gnss_name(int idx)
1420 {
1421 static const char * const gnss_name[] = {
1422 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1423 "Unknown"
1424 };
1425 if (idx >= ARRAY_SIZE(gnss_name))
1426 idx = ARRAY_SIZE(gnss_name) - 1;
1427 return gnss_name[idx];
1428 }
1429
1430 struct ptp_ocp_nvmem_match_info {
1431 struct ptp_ocp *bp;
1432 const void * const tag;
1433 };
1434
1435 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1436 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1437 {
1438 const struct ptp_ocp_nvmem_match_info *info = data;
1439
1440 dev = dev->parent;
1441 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1442 return 0;
1443
1444 while ((dev = dev->parent))
1445 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1446 return info->bp == dev_get_drvdata(dev);
1447 return 0;
1448 }
1449
1450 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1451 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1452 {
1453 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1454
1455 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1456 }
1457
1458 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1459 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1460 {
1461 if (!IS_ERR_OR_NULL(*nvmemp))
1462 nvmem_device_put(*nvmemp);
1463 *nvmemp = NULL;
1464 }
1465
1466 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1467 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1468 {
1469 const struct ptp_ocp_eeprom_map *map;
1470 struct nvmem_device *nvmem;
1471 const void *tag;
1472 int ret;
1473
1474 if (!bp->i2c_ctrl)
1475 return;
1476
1477 tag = NULL;
1478 nvmem = NULL;
1479
1480 for (map = bp->eeprom_map; map->len; map++) {
1481 if (map->tag != tag) {
1482 tag = map->tag;
1483 ptp_ocp_nvmem_device_put(&nvmem);
1484 }
1485 if (!nvmem) {
1486 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1487 if (IS_ERR(nvmem)) {
1488 ret = PTR_ERR(nvmem);
1489 goto fail;
1490 }
1491 }
1492 ret = nvmem_device_read(nvmem, map->off, map->len,
1493 BP_MAP_ENTRY_ADDR(bp, map));
1494 if (ret != map->len)
1495 goto fail;
1496 }
1497
1498 bp->has_eeprom_data = true;
1499
1500 out:
1501 ptp_ocp_nvmem_device_put(&nvmem);
1502 return;
1503
1504 fail:
1505 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1506 goto out;
1507 }
1508
1509 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)1510 ptp_ocp_find_flash(struct ptp_ocp *bp)
1511 {
1512 struct device *dev, *last;
1513
1514 last = NULL;
1515 dev = &bp->spi_flash->dev;
1516
1517 while ((dev = device_find_any_child(dev))) {
1518 if (!strcmp("mtd", dev_bus_name(dev)))
1519 break;
1520 put_device(last);
1521 last = dev;
1522 }
1523 put_device(last);
1524
1525 return dev;
1526 }
1527
1528 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)1529 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1530 const u8 **data, size_t *size)
1531 {
1532 struct ptp_ocp *bp = devlink_priv(devlink);
1533 const struct ptp_ocp_firmware_header *hdr;
1534 size_t offset, length;
1535 u16 crc;
1536
1537 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1538 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1539 devlink_flash_update_status_notify(devlink,
1540 "No firmware header found, cancel firmware upgrade",
1541 NULL, 0, 0);
1542 return -EINVAL;
1543 }
1544
1545 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1546 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1547 devlink_flash_update_status_notify(devlink,
1548 "Firmware image compatibility check failed",
1549 NULL, 0, 0);
1550 return -EINVAL;
1551 }
1552
1553 offset = sizeof(*hdr);
1554 length = be32_to_cpu(hdr->image_size);
1555 if (length != (fw->size - offset)) {
1556 devlink_flash_update_status_notify(devlink,
1557 "Firmware image size check failed",
1558 NULL, 0, 0);
1559 return -EINVAL;
1560 }
1561
1562 crc = crc16(0xffff, &fw->data[offset], length);
1563 if (be16_to_cpu(hdr->crc) != crc) {
1564 devlink_flash_update_status_notify(devlink,
1565 "Firmware image CRC check failed",
1566 NULL, 0, 0);
1567 return -EINVAL;
1568 }
1569
1570 *data = &fw->data[offset];
1571 *size = length;
1572
1573 return 0;
1574 }
1575
1576 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)1577 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1578 const struct firmware *fw)
1579 {
1580 struct mtd_info *mtd = dev_get_drvdata(dev);
1581 struct ptp_ocp *bp = devlink_priv(devlink);
1582 size_t off, len, size, resid, wrote;
1583 struct erase_info erase;
1584 size_t base, blksz;
1585 const u8 *data;
1586 int err;
1587
1588 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1589 if (err)
1590 goto out;
1591
1592 off = 0;
1593 base = bp->flash_start;
1594 blksz = 4096;
1595 resid = size;
1596
1597 while (resid) {
1598 devlink_flash_update_status_notify(devlink, "Flashing",
1599 NULL, off, size);
1600
1601 len = min_t(size_t, resid, blksz);
1602 erase.addr = base + off;
1603 erase.len = blksz;
1604
1605 err = mtd_erase(mtd, &erase);
1606 if (err)
1607 goto out;
1608
1609 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1610 if (err)
1611 goto out;
1612
1613 off += blksz;
1614 resid -= len;
1615 }
1616 out:
1617 return err;
1618 }
1619
1620 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)1621 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1622 struct devlink_flash_update_params *params,
1623 struct netlink_ext_ack *extack)
1624 {
1625 struct ptp_ocp *bp = devlink_priv(devlink);
1626 struct device *dev;
1627 const char *msg;
1628 int err;
1629
1630 dev = ptp_ocp_find_flash(bp);
1631 if (!dev) {
1632 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1633 return -ENODEV;
1634 }
1635
1636 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1637 NULL, 0, 0);
1638
1639 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1640
1641 msg = err ? "Flash error" : "Flash complete";
1642 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1643
1644 put_device(dev);
1645 return err;
1646 }
1647
1648 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)1649 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1650 struct netlink_ext_ack *extack)
1651 {
1652 struct ptp_ocp *bp = devlink_priv(devlink);
1653 const char *fw_image;
1654 char buf[32];
1655 int err;
1656
1657 fw_image = bp->fw_loader ? "loader" : "fw";
1658 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1659 err = devlink_info_version_running_put(req, fw_image, buf);
1660 if (err)
1661 return err;
1662
1663 if (!bp->has_eeprom_data) {
1664 ptp_ocp_read_eeprom(bp);
1665 if (!bp->has_eeprom_data)
1666 return 0;
1667 }
1668
1669 sprintf(buf, "%pM", bp->serial);
1670 err = devlink_info_serial_number_put(req, buf);
1671 if (err)
1672 return err;
1673
1674 err = devlink_info_version_fixed_put(req,
1675 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1676 bp->board_id);
1677 if (err)
1678 return err;
1679
1680 return 0;
1681 }
1682
1683 static const struct devlink_ops ptp_ocp_devlink_ops = {
1684 .flash_update = ptp_ocp_devlink_flash_update,
1685 .info_get = ptp_ocp_devlink_info_get,
1686 };
1687
1688 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)1689 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1690 {
1691 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1692
1693 return devm_ioremap_resource(&bp->pdev->dev, &res);
1694 }
1695
1696 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)1697 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1698 {
1699 resource_size_t start;
1700
1701 start = pci_resource_start(bp->pdev, 0) + r->offset;
1702 return __ptp_ocp_get_mem(bp, start, r->size);
1703 }
1704
1705 static void
ptp_ocp_set_irq_resource(struct resource * res,int irq)1706 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1707 {
1708 struct resource r = DEFINE_RES_IRQ(irq);
1709 *res = r;
1710 }
1711
1712 static void
ptp_ocp_set_mem_resource(struct resource * res,resource_size_t start,int size)1713 ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size)
1714 {
1715 struct resource r = DEFINE_RES_MEM(start, size);
1716 *res = r;
1717 }
1718
1719 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)1720 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1721 {
1722 struct ptp_ocp_flash_info *info;
1723 struct pci_dev *pdev = bp->pdev;
1724 struct platform_device *p;
1725 struct resource res[2];
1726 resource_size_t start;
1727 int id;
1728
1729 start = pci_resource_start(pdev, 0) + r->offset;
1730 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1731 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1732
1733 info = r->extra;
1734 id = pci_dev_id(pdev) << 1;
1735 id += info->pci_offset;
1736
1737 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1738 res, 2, info->data,
1739 info->data_size);
1740 if (IS_ERR(p))
1741 return PTR_ERR(p);
1742
1743 bp_assign_entry(bp, r, p);
1744
1745 return 0;
1746 }
1747
1748 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)1749 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1750 {
1751 struct ptp_ocp_i2c_info *info;
1752 struct resource res[2];
1753 resource_size_t start;
1754
1755 info = r->extra;
1756 start = pci_resource_start(pdev, 0) + r->offset;
1757 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1758 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1759
1760 return platform_device_register_resndata(&pdev->dev, info->name,
1761 id, res, 2,
1762 info->data, info->data_size);
1763 }
1764
1765 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)1766 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1767 {
1768 struct pci_dev *pdev = bp->pdev;
1769 struct ptp_ocp_i2c_info *info;
1770 struct platform_device *p;
1771 struct clk_hw *clk;
1772 char buf[32];
1773 int id;
1774
1775 info = r->extra;
1776 id = pci_dev_id(bp->pdev);
1777
1778 sprintf(buf, "AXI.%d", id);
1779 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1780 info->fixed_rate);
1781 if (IS_ERR(clk))
1782 return PTR_ERR(clk);
1783 bp->i2c_clk = clk;
1784
1785 sprintf(buf, "%s.%d", info->name, id);
1786 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1787 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1788 if (IS_ERR(p))
1789 return PTR_ERR(p);
1790
1791 bp_assign_entry(bp, r, p);
1792
1793 return 0;
1794 }
1795
1796 /* The expectation is that this is triggered only on error. */
1797 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)1798 ptp_ocp_signal_irq(int irq, void *priv)
1799 {
1800 struct ptp_ocp_ext_src *ext = priv;
1801 struct signal_reg __iomem *reg = ext->mem;
1802 struct ptp_ocp *bp = ext->bp;
1803 u32 enable, status;
1804 int gen;
1805
1806 gen = ext->info->index - 1;
1807
1808 enable = ioread32(®->enable);
1809 status = ioread32(®->status);
1810
1811 /* disable generator on error */
1812 if (status || !enable) {
1813 iowrite32(0, ®->intr_mask);
1814 iowrite32(0, ®->enable);
1815 bp->signal[gen].running = false;
1816 }
1817
1818 iowrite32(0, ®->intr); /* ack interrupt */
1819
1820 return IRQ_HANDLED;
1821 }
1822
1823 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)1824 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
1825 {
1826 struct ptp_system_timestamp sts;
1827 struct timespec64 ts;
1828 ktime_t start_ns;
1829 int err;
1830
1831 if (!s->period)
1832 return 0;
1833
1834 if (!s->pulse)
1835 s->pulse = ktime_divns(s->period * s->duty, 100);
1836
1837 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
1838 if (err)
1839 return err;
1840
1841 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1842 if (!s->start) {
1843 /* roundup() does not work on 32-bit systems */
1844 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1845 s->start *= s->period;
1846 s->start = ktime_add(s->start, s->phase);
1847 }
1848
1849 if (s->duty < 1 || s->duty > 99)
1850 return -EINVAL;
1851
1852 if (s->pulse < 1 || s->pulse > s->period)
1853 return -EINVAL;
1854
1855 if (s->start < start_ns)
1856 return -EINVAL;
1857
1858 bp->signal[gen] = *s;
1859
1860 return 0;
1861 }
1862
1863 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)1864 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
1865 struct ptp_perout_request *req)
1866 {
1867 struct ptp_ocp_signal s = { };
1868
1869 s.polarity = bp->signal[gen].polarity;
1870 s.period = ktime_set(req->period.sec, req->period.nsec);
1871 if (!s.period)
1872 return 0;
1873
1874 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
1875 s.pulse = ktime_set(req->on.sec, req->on.nsec);
1876 s.duty = ktime_divns(s.pulse * 100, s.period);
1877 }
1878
1879 if (req->flags & PTP_PEROUT_PHASE)
1880 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
1881 else
1882 s.start = ktime_set(req->start.sec, req->start.nsec);
1883
1884 return ptp_ocp_signal_set(bp, gen, &s);
1885 }
1886
1887 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)1888 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
1889 {
1890 struct ptp_ocp_ext_src *ext = priv;
1891 struct signal_reg __iomem *reg = ext->mem;
1892 struct ptp_ocp *bp = ext->bp;
1893 struct timespec64 ts;
1894 int gen;
1895
1896 gen = ext->info->index - 1;
1897
1898 iowrite32(0, ®->intr_mask);
1899 iowrite32(0, ®->enable);
1900 bp->signal[gen].running = false;
1901 if (!enable)
1902 return 0;
1903
1904 ts = ktime_to_timespec64(bp->signal[gen].start);
1905 iowrite32(ts.tv_sec, ®->start_sec);
1906 iowrite32(ts.tv_nsec, ®->start_ns);
1907
1908 ts = ktime_to_timespec64(bp->signal[gen].period);
1909 iowrite32(ts.tv_sec, ®->period_sec);
1910 iowrite32(ts.tv_nsec, ®->period_ns);
1911
1912 ts = ktime_to_timespec64(bp->signal[gen].pulse);
1913 iowrite32(ts.tv_sec, ®->pulse_sec);
1914 iowrite32(ts.tv_nsec, ®->pulse_ns);
1915
1916 iowrite32(bp->signal[gen].polarity, ®->polarity);
1917 iowrite32(0, ®->repeat_count);
1918
1919 iowrite32(0, ®->intr); /* clear interrupt state */
1920 iowrite32(1, ®->intr_mask); /* enable interrupt */
1921 iowrite32(3, ®->enable); /* valid & enable */
1922
1923 bp->signal[gen].running = true;
1924
1925 return 0;
1926 }
1927
1928 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)1929 ptp_ocp_ts_irq(int irq, void *priv)
1930 {
1931 struct ptp_ocp_ext_src *ext = priv;
1932 struct ts_reg __iomem *reg = ext->mem;
1933 struct ptp_clock_event ev;
1934 u32 sec, nsec;
1935
1936 if (ext == ext->bp->pps) {
1937 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1938 ev.type = PTP_CLOCK_PPS;
1939 ptp_clock_event(ext->bp->ptp, &ev);
1940 }
1941
1942 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1943 goto out;
1944 }
1945
1946 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
1947 sec = ioread32(®->time_sec);
1948 nsec = ioread32(®->time_ns);
1949
1950 ev.type = PTP_CLOCK_EXTTS;
1951 ev.index = ext->info->index;
1952 ev.timestamp = sec * NSEC_PER_SEC + nsec;
1953
1954 ptp_clock_event(ext->bp->ptp, &ev);
1955
1956 out:
1957 iowrite32(1, ®->intr); /* write 1 to ack */
1958
1959 return IRQ_HANDLED;
1960 }
1961
1962 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)1963 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1964 {
1965 struct ptp_ocp_ext_src *ext = priv;
1966 struct ts_reg __iomem *reg = ext->mem;
1967 struct ptp_ocp *bp = ext->bp;
1968
1969 if (ext == bp->pps) {
1970 u32 old_map = bp->pps_req_map;
1971
1972 if (enable)
1973 bp->pps_req_map |= req;
1974 else
1975 bp->pps_req_map &= ~req;
1976
1977 /* if no state change, just return */
1978 if ((!!old_map ^ !!bp->pps_req_map) == 0)
1979 return 0;
1980 }
1981
1982 if (enable) {
1983 iowrite32(1, ®->enable);
1984 iowrite32(1, ®->intr_mask);
1985 iowrite32(1, ®->intr);
1986 } else {
1987 iowrite32(0, ®->intr_mask);
1988 iowrite32(0, ®->enable);
1989 }
1990
1991 return 0;
1992 }
1993
1994 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)1995 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1996 {
1997 ext->info->enable(ext, ~0, false);
1998 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1999 kfree(ext);
2000 }
2001
2002 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)2003 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2004 {
2005 struct pci_dev *pdev = bp->pdev;
2006 struct ptp_ocp_ext_src *ext;
2007 int err;
2008
2009 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2010 if (!ext)
2011 return -ENOMEM;
2012
2013 ext->mem = ptp_ocp_get_mem(bp, r);
2014 if (IS_ERR(ext->mem)) {
2015 err = PTR_ERR(ext->mem);
2016 goto out;
2017 }
2018
2019 ext->bp = bp;
2020 ext->info = r->extra;
2021 ext->irq_vec = r->irq_vec;
2022
2023 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2024 ext, "ocp%d.%s", bp->id, r->name);
2025 if (err) {
2026 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2027 goto out;
2028 }
2029
2030 bp_assign_entry(bp, r, ext);
2031
2032 return 0;
2033
2034 out:
2035 kfree(ext);
2036 return err;
2037 }
2038
2039 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)2040 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2041 {
2042 struct pci_dev *pdev = bp->pdev;
2043 struct uart_8250_port uart;
2044
2045 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2046 * the serial port device claim and release the pci resource.
2047 */
2048 memset(&uart, 0, sizeof(uart));
2049 uart.port.dev = &pdev->dev;
2050 uart.port.iotype = UPIO_MEM;
2051 uart.port.regshift = 2;
2052 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2053 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2054 uart.port.uartclk = 50000000;
2055 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2056 uart.port.type = PORT_16550A;
2057
2058 return serial8250_register_8250_port(&uart);
2059 }
2060
2061 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)2062 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2063 {
2064 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2065 struct ptp_ocp_serial_port port = {};
2066
2067 port.line = ptp_ocp_serial_line(bp, r);
2068 if (port.line < 0)
2069 return port.line;
2070
2071 if (p)
2072 port.baud = p->baud;
2073
2074 bp_assign_entry(bp, r, port);
2075
2076 return 0;
2077 }
2078
2079 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)2080 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2081 {
2082 void __iomem *mem;
2083
2084 mem = ptp_ocp_get_mem(bp, r);
2085 if (IS_ERR(mem))
2086 return PTR_ERR(mem);
2087
2088 bp_assign_entry(bp, r, mem);
2089
2090 return 0;
2091 }
2092
2093 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)2094 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2095 {
2096 if (!bp->nmea_out)
2097 return;
2098
2099 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2100 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2101 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2102 }
2103
2104 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)2105 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2106 {
2107 u32 val;
2108
2109 iowrite32(0, ®->enable); /* disable */
2110
2111 val = ioread32(®->polarity);
2112 s->polarity = val ? true : false;
2113 s->duty = 50;
2114 }
2115
2116 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)2117 ptp_ocp_signal_init(struct ptp_ocp *bp)
2118 {
2119 int i;
2120
2121 for (i = 0; i < 4; i++)
2122 if (bp->signal_out[i])
2123 _ptp_ocp_signal_init(&bp->signal[i],
2124 bp->signal_out[i]->mem);
2125 }
2126
2127 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)2128 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2129 {
2130 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2131 kfree(bp->attr_group);
2132 }
2133
2134 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)2135 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2136 const struct ocp_attr_group *attr_tbl)
2137 {
2138 int count, i;
2139 int err;
2140
2141 count = 0;
2142 for (i = 0; attr_tbl[i].cap; i++)
2143 if (attr_tbl[i].cap & bp->fw_cap)
2144 count++;
2145
2146 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2147 GFP_KERNEL);
2148 if (!bp->attr_group)
2149 return -ENOMEM;
2150
2151 count = 0;
2152 for (i = 0; attr_tbl[i].cap; i++)
2153 if (attr_tbl[i].cap & bp->fw_cap)
2154 bp->attr_group[count++] = attr_tbl[i].group;
2155
2156 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2157 if (err)
2158 bp->attr_group[0] = NULL;
2159
2160 return err;
2161 }
2162
2163 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)2164 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2165 {
2166 u32 ctrl;
2167 bool on;
2168
2169 ctrl = ioread32(reg);
2170 on = ctrl & bit;
2171 if (on ^ enable) {
2172 ctrl &= ~bit;
2173 ctrl |= enable ? bit : 0;
2174 iowrite32(ctrl, reg);
2175 }
2176 }
2177
2178 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)2179 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2180 {
2181 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2182 IRIG_M_CTRL_ENABLE, enable);
2183 }
2184
2185 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)2186 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2187 {
2188 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2189 IRIG_S_CTRL_ENABLE, enable);
2190 }
2191
2192 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2193 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2194 {
2195 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2196 DCF_M_CTRL_ENABLE, enable);
2197 }
2198
2199 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2200 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2201 {
2202 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2203 DCF_S_CTRL_ENABLE, enable);
2204 }
2205
2206 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2207 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2208 {
2209 ptp_ocp_irig_out(bp, val & 0x00100010);
2210 ptp_ocp_dcf_out(bp, val & 0x00200020);
2211 }
2212
2213 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2214 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2215 {
2216 ptp_ocp_irig_in(bp, val & 0x00100010);
2217 ptp_ocp_dcf_in(bp, val & 0x00200020);
2218 }
2219
2220 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2221 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2222 {
2223 u32 __iomem *gpio;
2224 u32 shift;
2225
2226 if (bp->sma[sma_nr - 1].fixed_fcn)
2227 return (sma_nr - 1) & 1;
2228
2229 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2230 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2231 else
2232 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2233 shift = sma_nr & 1 ? 0 : 16;
2234
2235 return (ioread32(gpio) >> shift) & 0xffff;
2236 }
2237
2238 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2239 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2240 {
2241 u32 reg, mask, shift;
2242 unsigned long flags;
2243 u32 __iomem *gpio;
2244
2245 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2246 shift = sma_nr & 1 ? 0 : 16;
2247
2248 mask = 0xffff << (16 - shift);
2249
2250 spin_lock_irqsave(&bp->lock, flags);
2251
2252 reg = ioread32(gpio);
2253 reg = (reg & mask) | (val << shift);
2254
2255 __handle_signal_outputs(bp, reg);
2256
2257 iowrite32(reg, gpio);
2258
2259 spin_unlock_irqrestore(&bp->lock, flags);
2260
2261 return 0;
2262 }
2263
2264 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2265 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2266 {
2267 u32 reg, mask, shift;
2268 unsigned long flags;
2269 u32 __iomem *gpio;
2270
2271 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2272 shift = sma_nr & 1 ? 0 : 16;
2273
2274 mask = 0xffff << (16 - shift);
2275
2276 spin_lock_irqsave(&bp->lock, flags);
2277
2278 reg = ioread32(gpio);
2279 reg = (reg & mask) | (val << shift);
2280
2281 __handle_signal_inputs(bp, reg);
2282
2283 iowrite32(reg, gpio);
2284
2285 spin_unlock_irqrestore(&bp->lock, flags);
2286
2287 return 0;
2288 }
2289
2290 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2291 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2292 {
2293 u32 reg;
2294 int i;
2295
2296 /* defaults */
2297 bp->sma[0].mode = SMA_MODE_IN;
2298 bp->sma[1].mode = SMA_MODE_IN;
2299 bp->sma[2].mode = SMA_MODE_OUT;
2300 bp->sma[3].mode = SMA_MODE_OUT;
2301 for (i = 0; i < 4; i++)
2302 bp->sma[i].default_fcn = i & 1;
2303
2304 /* If no SMA1 map, the pin functions and directions are fixed. */
2305 if (!bp->sma_map1) {
2306 for (i = 0; i < 4; i++) {
2307 bp->sma[i].fixed_fcn = true;
2308 bp->sma[i].fixed_dir = true;
2309 }
2310 return;
2311 }
2312
2313 /* If SMA2 GPIO output map is all 1, it is not present.
2314 * This indicates the firmware has fixed direction SMA pins.
2315 */
2316 reg = ioread32(&bp->sma_map2->gpio2);
2317 if (reg == 0xffffffff) {
2318 for (i = 0; i < 4; i++)
2319 bp->sma[i].fixed_dir = true;
2320 } else {
2321 reg = ioread32(&bp->sma_map1->gpio1);
2322 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2323 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2324
2325 reg = ioread32(&bp->sma_map1->gpio2);
2326 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2327 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2328 }
2329 }
2330
2331 static const struct ocp_sma_op ocp_fb_sma_op = {
2332 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2333 .init = ptp_ocp_sma_fb_init,
2334 .get = ptp_ocp_sma_fb_get,
2335 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2336 .set_output = ptp_ocp_sma_fb_set_output,
2337 };
2338
2339 static int
ptp_ocp_fb_set_pins(struct ptp_ocp * bp)2340 ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
2341 {
2342 struct ptp_pin_desc *config;
2343 int i;
2344
2345 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2346 if (!config)
2347 return -ENOMEM;
2348
2349 for (i = 0; i < 4; i++) {
2350 sprintf(config[i].name, "sma%d", i + 1);
2351 config[i].index = i;
2352 }
2353
2354 bp->ptp_info.n_pins = 4;
2355 bp->ptp_info.pin_config = config;
2356
2357 return 0;
2358 }
2359
2360 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2361 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2362 {
2363 u64 cap = OCP_CAP_BASIC;
2364 u32 version;
2365
2366 version = ioread32(&bp->image->version);
2367
2368 /* if lower 16 bits are empty, this is the fw loader. */
2369 if ((version & 0xffff) == 0) {
2370 version = version >> 16;
2371 bp->fw_loader = true;
2372 }
2373
2374 bp->fw_tag = version >> 15;
2375 bp->fw_version = version & 0x7fff;
2376
2377 if (bp->fw_tag) {
2378 /* FPGA firmware */
2379 if (version >= 5)
2380 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2381 } else {
2382 /* SOM firmware */
2383 if (version >= 19)
2384 cap |= OCP_CAP_SIGNAL;
2385 if (version >= 20)
2386 cap |= OCP_CAP_FREQ;
2387 }
2388
2389 bp->fw_cap = cap;
2390 }
2391
2392 /* FB specific board initializers; last "resource" registered. */
2393 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2394 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2395 {
2396 int err;
2397
2398 bp->flash_start = 1024 * 4096;
2399 bp->eeprom_map = fb_eeprom_map;
2400 bp->fw_version = ioread32(&bp->image->version);
2401 bp->sma_op = &ocp_fb_sma_op;
2402
2403 ptp_ocp_fb_set_version(bp);
2404
2405 ptp_ocp_tod_init(bp);
2406 ptp_ocp_nmea_out_init(bp);
2407 ptp_ocp_sma_init(bp);
2408 ptp_ocp_signal_init(bp);
2409
2410 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2411 if (err)
2412 return err;
2413
2414 err = ptp_ocp_fb_set_pins(bp);
2415 if (err)
2416 return err;
2417
2418 return ptp_ocp_init_clock(bp);
2419 }
2420
2421 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)2422 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2423 {
2424 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2425
2426 if (!allow)
2427 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2428 r->irq_vec, r->name);
2429 return allow;
2430 }
2431
2432 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)2433 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2434 {
2435 struct ocp_resource *r, *table;
2436 int err = 0;
2437
2438 table = (struct ocp_resource *)driver_data;
2439 for (r = table; r->setup; r++) {
2440 if (!ptp_ocp_allow_irq(bp, r))
2441 continue;
2442 err = r->setup(bp, r);
2443 if (err) {
2444 dev_err(&bp->pdev->dev,
2445 "Could not register %s: err %d\n",
2446 r->name, err);
2447 break;
2448 }
2449 }
2450 return err;
2451 }
2452
2453 static void
ptp_ocp_art_sma_init(struct ptp_ocp * bp)2454 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2455 {
2456 u32 reg;
2457 int i;
2458
2459 /* defaults */
2460 bp->sma[0].mode = SMA_MODE_IN;
2461 bp->sma[1].mode = SMA_MODE_IN;
2462 bp->sma[2].mode = SMA_MODE_OUT;
2463 bp->sma[3].mode = SMA_MODE_OUT;
2464
2465 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2466 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2467 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2468 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2469
2470 /* If no SMA map, the pin functions and directions are fixed. */
2471 if (!bp->art_sma) {
2472 for (i = 0; i < 4; i++) {
2473 bp->sma[i].fixed_fcn = true;
2474 bp->sma[i].fixed_dir = true;
2475 }
2476 return;
2477 }
2478
2479 for (i = 0; i < 4; i++) {
2480 reg = ioread32(&bp->art_sma->map[i].gpio);
2481
2482 switch (reg & 0xff) {
2483 case 0:
2484 bp->sma[i].fixed_fcn = true;
2485 bp->sma[i].fixed_dir = true;
2486 break;
2487 case 1:
2488 case 8:
2489 bp->sma[i].mode = SMA_MODE_IN;
2490 break;
2491 default:
2492 bp->sma[i].mode = SMA_MODE_OUT;
2493 break;
2494 }
2495 }
2496 }
2497
2498 static u32
ptp_ocp_art_sma_get(struct ptp_ocp * bp,int sma_nr)2499 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2500 {
2501 if (bp->sma[sma_nr - 1].fixed_fcn)
2502 return bp->sma[sma_nr - 1].default_fcn;
2503
2504 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2505 }
2506
2507 /* note: store 0 is considered invalid. */
2508 static int
ptp_ocp_art_sma_set(struct ptp_ocp * bp,int sma_nr,u32 val)2509 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2510 {
2511 unsigned long flags;
2512 u32 __iomem *gpio;
2513 int err = 0;
2514 u32 reg;
2515
2516 val &= SMA_SELECT_MASK;
2517 if (hweight32(val) > 1)
2518 return -EINVAL;
2519
2520 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2521
2522 spin_lock_irqsave(&bp->lock, flags);
2523 reg = ioread32(gpio);
2524 if (((reg >> 16) & val) == 0) {
2525 err = -EOPNOTSUPP;
2526 } else {
2527 reg = (reg & 0xff00) | (val & 0xff);
2528 iowrite32(reg, gpio);
2529 }
2530 spin_unlock_irqrestore(&bp->lock, flags);
2531
2532 return err;
2533 }
2534
2535 static const struct ocp_sma_op ocp_art_sma_op = {
2536 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2537 .init = ptp_ocp_art_sma_init,
2538 .get = ptp_ocp_art_sma_get,
2539 .set_inputs = ptp_ocp_art_sma_set,
2540 .set_output = ptp_ocp_art_sma_set,
2541 };
2542
2543 /* ART specific board initializers; last "resource" registered. */
2544 static int
ptp_ocp_art_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2545 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2546 {
2547 int err;
2548
2549 bp->flash_start = 0x1000000;
2550 bp->eeprom_map = art_eeprom_map;
2551 bp->fw_cap = OCP_CAP_BASIC;
2552 bp->fw_version = ioread32(&bp->reg->version);
2553 bp->fw_tag = 2;
2554 bp->sma_op = &ocp_art_sma_op;
2555
2556 /* Enable MAC serial port during initialisation */
2557 iowrite32(1, &bp->board_config->mro50_serial_activate);
2558
2559 ptp_ocp_sma_init(bp);
2560
2561 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2562 if (err)
2563 return err;
2564
2565 return ptp_ocp_init_clock(bp);
2566 }
2567
2568 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2569 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2570 int def_val)
2571 {
2572 const char *name;
2573 ssize_t count;
2574
2575 count = sysfs_emit(buf, "OUT: ");
2576 name = ptp_ocp_select_name_from_val(tbl, val);
2577 if (!name)
2578 name = ptp_ocp_select_name_from_val(tbl, def_val);
2579 count += sysfs_emit_at(buf, count, "%s\n", name);
2580 return count;
2581 }
2582
2583 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2584 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2585 int def_val)
2586 {
2587 const char *name;
2588 ssize_t count;
2589 int i;
2590
2591 count = sysfs_emit(buf, "IN: ");
2592 for (i = 0; tbl[i].name; i++) {
2593 if (val & tbl[i].value) {
2594 name = tbl[i].name;
2595 count += sysfs_emit_at(buf, count, "%s ", name);
2596 }
2597 }
2598 if (!val && def_val >= 0) {
2599 name = ptp_ocp_select_name_from_val(tbl, def_val);
2600 count += sysfs_emit_at(buf, count, "%s ", name);
2601 }
2602 if (count)
2603 count--;
2604 count += sysfs_emit_at(buf, count, "\n");
2605 return count;
2606 }
2607
2608 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)2609 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2610 enum ptp_ocp_sma_mode *mode)
2611 {
2612 int idx, count, dir;
2613 char **argv;
2614 int ret;
2615
2616 argv = argv_split(GFP_KERNEL, buf, &count);
2617 if (!argv)
2618 return -ENOMEM;
2619
2620 ret = -EINVAL;
2621 if (!count)
2622 goto out;
2623
2624 idx = 0;
2625 dir = *mode == SMA_MODE_IN ? 0 : 1;
2626 if (!strcasecmp("IN:", argv[0])) {
2627 dir = 0;
2628 idx++;
2629 }
2630 if (!strcasecmp("OUT:", argv[0])) {
2631 dir = 1;
2632 idx++;
2633 }
2634 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2635
2636 ret = 0;
2637 for (; idx < count; idx++)
2638 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2639 if (ret < 0)
2640 ret = -EINVAL;
2641
2642 out:
2643 argv_free(argv);
2644 return ret;
2645 }
2646
2647 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)2648 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2649 int default_in_val, int default_out_val)
2650 {
2651 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2652 const struct ocp_selector * const *tbl;
2653 u32 val;
2654
2655 tbl = bp->sma_op->tbl;
2656 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2657
2658 if (sma->mode == SMA_MODE_IN) {
2659 if (sma->disabled)
2660 val = SMA_DISABLE;
2661 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2662 }
2663
2664 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2665 }
2666
2667 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)2668 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2669 {
2670 struct ptp_ocp *bp = dev_get_drvdata(dev);
2671
2672 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2673 }
2674
2675 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)2676 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2677 {
2678 struct ptp_ocp *bp = dev_get_drvdata(dev);
2679
2680 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2681 }
2682
2683 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)2684 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2685 {
2686 struct ptp_ocp *bp = dev_get_drvdata(dev);
2687
2688 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2689 }
2690
2691 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)2692 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2693 {
2694 struct ptp_ocp *bp = dev_get_drvdata(dev);
2695
2696 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2697 }
2698
2699 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)2700 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
2701 {
2702 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2703 enum ptp_ocp_sma_mode mode;
2704 int val;
2705
2706 mode = sma->mode;
2707 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
2708 if (val < 0)
2709 return val;
2710
2711 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2712 return -EOPNOTSUPP;
2713
2714 if (sma->fixed_fcn) {
2715 if (val != sma->default_fcn)
2716 return -EOPNOTSUPP;
2717 return 0;
2718 }
2719
2720 sma->disabled = !!(val & SMA_DISABLE);
2721
2722 if (mode != sma->mode) {
2723 if (mode == SMA_MODE_IN)
2724 ptp_ocp_sma_set_output(bp, sma_nr, 0);
2725 else
2726 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
2727 sma->mode = mode;
2728 }
2729
2730 if (!sma->fixed_dir)
2731 val |= SMA_ENABLE; /* add enable bit */
2732
2733 if (sma->disabled)
2734 val = 0;
2735
2736 if (mode == SMA_MODE_IN)
2737 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
2738 else
2739 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
2740
2741 return val;
2742 }
2743
2744 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2745 sma1_store(struct device *dev, struct device_attribute *attr,
2746 const char *buf, size_t count)
2747 {
2748 struct ptp_ocp *bp = dev_get_drvdata(dev);
2749 int err;
2750
2751 err = ptp_ocp_sma_store(bp, buf, 1);
2752 return err ? err : count;
2753 }
2754
2755 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2756 sma2_store(struct device *dev, struct device_attribute *attr,
2757 const char *buf, size_t count)
2758 {
2759 struct ptp_ocp *bp = dev_get_drvdata(dev);
2760 int err;
2761
2762 err = ptp_ocp_sma_store(bp, buf, 2);
2763 return err ? err : count;
2764 }
2765
2766 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2767 sma3_store(struct device *dev, struct device_attribute *attr,
2768 const char *buf, size_t count)
2769 {
2770 struct ptp_ocp *bp = dev_get_drvdata(dev);
2771 int err;
2772
2773 err = ptp_ocp_sma_store(bp, buf, 3);
2774 return err ? err : count;
2775 }
2776
2777 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2778 sma4_store(struct device *dev, struct device_attribute *attr,
2779 const char *buf, size_t count)
2780 {
2781 struct ptp_ocp *bp = dev_get_drvdata(dev);
2782 int err;
2783
2784 err = ptp_ocp_sma_store(bp, buf, 4);
2785 return err ? err : count;
2786 }
2787 static DEVICE_ATTR_RW(sma1);
2788 static DEVICE_ATTR_RW(sma2);
2789 static DEVICE_ATTR_RW(sma3);
2790 static DEVICE_ATTR_RW(sma4);
2791
2792 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)2793 available_sma_inputs_show(struct device *dev,
2794 struct device_attribute *attr, char *buf)
2795 {
2796 struct ptp_ocp *bp = dev_get_drvdata(dev);
2797
2798 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
2799 }
2800 static DEVICE_ATTR_RO(available_sma_inputs);
2801
2802 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)2803 available_sma_outputs_show(struct device *dev,
2804 struct device_attribute *attr, char *buf)
2805 {
2806 struct ptp_ocp *bp = dev_get_drvdata(dev);
2807
2808 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
2809 }
2810 static DEVICE_ATTR_RO(available_sma_outputs);
2811
2812 #define EXT_ATTR_RO(_group, _name, _val) \
2813 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2814 { __ATTR_RO(_name), (void *)_val }
2815 #define EXT_ATTR_RW(_group, _name, _val) \
2816 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2817 { __ATTR_RW(_name), (void *)_val }
2818 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
2819
2820 /* period [duty [phase [polarity]]] */
2821 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2822 signal_store(struct device *dev, struct device_attribute *attr,
2823 const char *buf, size_t count)
2824 {
2825 struct dev_ext_attribute *ea = to_ext_attr(attr);
2826 struct ptp_ocp *bp = dev_get_drvdata(dev);
2827 struct ptp_ocp_signal s = { };
2828 int gen = (uintptr_t)ea->var;
2829 int argc, err;
2830 char **argv;
2831
2832 argv = argv_split(GFP_KERNEL, buf, &argc);
2833 if (!argv)
2834 return -ENOMEM;
2835
2836 err = -EINVAL;
2837 s.duty = bp->signal[gen].duty;
2838 s.phase = bp->signal[gen].phase;
2839 s.period = bp->signal[gen].period;
2840 s.polarity = bp->signal[gen].polarity;
2841
2842 switch (argc) {
2843 case 4:
2844 argc--;
2845 err = kstrtobool(argv[argc], &s.polarity);
2846 if (err)
2847 goto out;
2848 fallthrough;
2849 case 3:
2850 argc--;
2851 err = kstrtou64(argv[argc], 0, &s.phase);
2852 if (err)
2853 goto out;
2854 fallthrough;
2855 case 2:
2856 argc--;
2857 err = kstrtoint(argv[argc], 0, &s.duty);
2858 if (err)
2859 goto out;
2860 fallthrough;
2861 case 1:
2862 argc--;
2863 err = kstrtou64(argv[argc], 0, &s.period);
2864 if (err)
2865 goto out;
2866 break;
2867 default:
2868 goto out;
2869 }
2870
2871 err = ptp_ocp_signal_set(bp, gen, &s);
2872 if (err)
2873 goto out;
2874
2875 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
2876
2877 out:
2878 argv_free(argv);
2879 return err ? err : count;
2880 }
2881
2882 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)2883 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
2884 {
2885 struct dev_ext_attribute *ea = to_ext_attr(attr);
2886 struct ptp_ocp *bp = dev_get_drvdata(dev);
2887 struct ptp_ocp_signal *signal;
2888 struct timespec64 ts;
2889 ssize_t count;
2890 int i;
2891
2892 i = (uintptr_t)ea->var;
2893 signal = &bp->signal[i];
2894
2895 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
2896 signal->duty, signal->phase, signal->polarity);
2897
2898 ts = ktime_to_timespec64(signal->start);
2899 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
2900
2901 return count;
2902 }
2903 static EXT_ATTR_RW(signal, signal, 0);
2904 static EXT_ATTR_RW(signal, signal, 1);
2905 static EXT_ATTR_RW(signal, signal, 2);
2906 static EXT_ATTR_RW(signal, signal, 3);
2907
2908 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)2909 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
2910 {
2911 struct dev_ext_attribute *ea = to_ext_attr(attr);
2912 struct ptp_ocp *bp = dev_get_drvdata(dev);
2913 int i = (uintptr_t)ea->var;
2914
2915 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
2916 }
2917 static EXT_ATTR_RO(signal, duty, 0);
2918 static EXT_ATTR_RO(signal, duty, 1);
2919 static EXT_ATTR_RO(signal, duty, 2);
2920 static EXT_ATTR_RO(signal, duty, 3);
2921
2922 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)2923 period_show(struct device *dev, struct device_attribute *attr, char *buf)
2924 {
2925 struct dev_ext_attribute *ea = to_ext_attr(attr);
2926 struct ptp_ocp *bp = dev_get_drvdata(dev);
2927 int i = (uintptr_t)ea->var;
2928
2929 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
2930 }
2931 static EXT_ATTR_RO(signal, period, 0);
2932 static EXT_ATTR_RO(signal, period, 1);
2933 static EXT_ATTR_RO(signal, period, 2);
2934 static EXT_ATTR_RO(signal, period, 3);
2935
2936 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)2937 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
2938 {
2939 struct dev_ext_attribute *ea = to_ext_attr(attr);
2940 struct ptp_ocp *bp = dev_get_drvdata(dev);
2941 int i = (uintptr_t)ea->var;
2942
2943 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
2944 }
2945 static EXT_ATTR_RO(signal, phase, 0);
2946 static EXT_ATTR_RO(signal, phase, 1);
2947 static EXT_ATTR_RO(signal, phase, 2);
2948 static EXT_ATTR_RO(signal, phase, 3);
2949
2950 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)2951 polarity_show(struct device *dev, struct device_attribute *attr,
2952 char *buf)
2953 {
2954 struct dev_ext_attribute *ea = to_ext_attr(attr);
2955 struct ptp_ocp *bp = dev_get_drvdata(dev);
2956 int i = (uintptr_t)ea->var;
2957
2958 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
2959 }
2960 static EXT_ATTR_RO(signal, polarity, 0);
2961 static EXT_ATTR_RO(signal, polarity, 1);
2962 static EXT_ATTR_RO(signal, polarity, 2);
2963 static EXT_ATTR_RO(signal, polarity, 3);
2964
2965 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)2966 running_show(struct device *dev, struct device_attribute *attr, char *buf)
2967 {
2968 struct dev_ext_attribute *ea = to_ext_attr(attr);
2969 struct ptp_ocp *bp = dev_get_drvdata(dev);
2970 int i = (uintptr_t)ea->var;
2971
2972 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
2973 }
2974 static EXT_ATTR_RO(signal, running, 0);
2975 static EXT_ATTR_RO(signal, running, 1);
2976 static EXT_ATTR_RO(signal, running, 2);
2977 static EXT_ATTR_RO(signal, running, 3);
2978
2979 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)2980 start_show(struct device *dev, struct device_attribute *attr, char *buf)
2981 {
2982 struct dev_ext_attribute *ea = to_ext_attr(attr);
2983 struct ptp_ocp *bp = dev_get_drvdata(dev);
2984 int i = (uintptr_t)ea->var;
2985 struct timespec64 ts;
2986
2987 ts = ktime_to_timespec64(bp->signal[i].start);
2988 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
2989 }
2990 static EXT_ATTR_RO(signal, start, 0);
2991 static EXT_ATTR_RO(signal, start, 1);
2992 static EXT_ATTR_RO(signal, start, 2);
2993 static EXT_ATTR_RO(signal, start, 3);
2994
2995 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2996 seconds_store(struct device *dev, struct device_attribute *attr,
2997 const char *buf, size_t count)
2998 {
2999 struct dev_ext_attribute *ea = to_ext_attr(attr);
3000 struct ptp_ocp *bp = dev_get_drvdata(dev);
3001 int idx = (uintptr_t)ea->var;
3002 u32 val;
3003 int err;
3004
3005 err = kstrtou32(buf, 0, &val);
3006 if (err)
3007 return err;
3008 if (val > 0xff)
3009 return -EINVAL;
3010
3011 if (val)
3012 val = (val << 8) | 0x1;
3013
3014 iowrite32(val, &bp->freq_in[idx]->ctrl);
3015
3016 return count;
3017 }
3018
3019 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)3020 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3021 {
3022 struct dev_ext_attribute *ea = to_ext_attr(attr);
3023 struct ptp_ocp *bp = dev_get_drvdata(dev);
3024 int idx = (uintptr_t)ea->var;
3025 u32 val;
3026
3027 val = ioread32(&bp->freq_in[idx]->ctrl);
3028 if (val & 1)
3029 val = (val >> 8) & 0xff;
3030 else
3031 val = 0;
3032
3033 return sysfs_emit(buf, "%u\n", val);
3034 }
3035 static EXT_ATTR_RW(freq, seconds, 0);
3036 static EXT_ATTR_RW(freq, seconds, 1);
3037 static EXT_ATTR_RW(freq, seconds, 2);
3038 static EXT_ATTR_RW(freq, seconds, 3);
3039
3040 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)3041 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3042 {
3043 struct dev_ext_attribute *ea = to_ext_attr(attr);
3044 struct ptp_ocp *bp = dev_get_drvdata(dev);
3045 int idx = (uintptr_t)ea->var;
3046 u32 val;
3047
3048 val = ioread32(&bp->freq_in[idx]->status);
3049 if (val & FREQ_STATUS_ERROR)
3050 return sysfs_emit(buf, "error\n");
3051 if (val & FREQ_STATUS_OVERRUN)
3052 return sysfs_emit(buf, "overrun\n");
3053 if (val & FREQ_STATUS_VALID)
3054 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3055 return 0;
3056 }
3057 static EXT_ATTR_RO(freq, frequency, 0);
3058 static EXT_ATTR_RO(freq, frequency, 1);
3059 static EXT_ATTR_RO(freq, frequency, 2);
3060 static EXT_ATTR_RO(freq, frequency, 3);
3061
3062 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)3063 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3064 {
3065 struct ptp_ocp *bp = dev_get_drvdata(dev);
3066
3067 if (!bp->has_eeprom_data)
3068 ptp_ocp_read_eeprom(bp);
3069
3070 return sysfs_emit(buf, "%pM\n", bp->serial);
3071 }
3072 static DEVICE_ATTR_RO(serialnum);
3073
3074 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)3075 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3076 {
3077 struct ptp_ocp *bp = dev_get_drvdata(dev);
3078 ssize_t ret;
3079
3080 if (bp->gnss_lost)
3081 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3082 else
3083 ret = sysfs_emit(buf, "SYNC\n");
3084
3085 return ret;
3086 }
3087 static DEVICE_ATTR_RO(gnss_sync);
3088
3089 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3090 utc_tai_offset_show(struct device *dev,
3091 struct device_attribute *attr, char *buf)
3092 {
3093 struct ptp_ocp *bp = dev_get_drvdata(dev);
3094
3095 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3096 }
3097
3098 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3099 utc_tai_offset_store(struct device *dev,
3100 struct device_attribute *attr,
3101 const char *buf, size_t count)
3102 {
3103 struct ptp_ocp *bp = dev_get_drvdata(dev);
3104 int err;
3105 u32 val;
3106
3107 err = kstrtou32(buf, 0, &val);
3108 if (err)
3109 return err;
3110
3111 ptp_ocp_utc_distribute(bp, val);
3112
3113 return count;
3114 }
3115 static DEVICE_ATTR_RW(utc_tai_offset);
3116
3117 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)3118 ts_window_adjust_show(struct device *dev,
3119 struct device_attribute *attr, char *buf)
3120 {
3121 struct ptp_ocp *bp = dev_get_drvdata(dev);
3122
3123 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3124 }
3125
3126 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3127 ts_window_adjust_store(struct device *dev,
3128 struct device_attribute *attr,
3129 const char *buf, size_t count)
3130 {
3131 struct ptp_ocp *bp = dev_get_drvdata(dev);
3132 int err;
3133 u32 val;
3134
3135 err = kstrtou32(buf, 0, &val);
3136 if (err)
3137 return err;
3138
3139 bp->ts_window_adjust = val;
3140
3141 return count;
3142 }
3143 static DEVICE_ATTR_RW(ts_window_adjust);
3144
3145 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)3146 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3147 {
3148 struct ptp_ocp *bp = dev_get_drvdata(dev);
3149 u32 val;
3150
3151 val = ioread32(&bp->irig_out->ctrl);
3152 val = (val >> 16) & 0x07;
3153 return sysfs_emit(buf, "%d\n", val);
3154 }
3155
3156 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3157 irig_b_mode_store(struct device *dev,
3158 struct device_attribute *attr,
3159 const char *buf, size_t count)
3160 {
3161 struct ptp_ocp *bp = dev_get_drvdata(dev);
3162 unsigned long flags;
3163 int err;
3164 u32 reg;
3165 u8 val;
3166
3167 err = kstrtou8(buf, 0, &val);
3168 if (err)
3169 return err;
3170 if (val > 7)
3171 return -EINVAL;
3172
3173 reg = ((val & 0x7) << 16);
3174
3175 spin_lock_irqsave(&bp->lock, flags);
3176 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3177 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3178 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3179 spin_unlock_irqrestore(&bp->lock, flags);
3180
3181 return count;
3182 }
3183 static DEVICE_ATTR_RW(irig_b_mode);
3184
3185 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)3186 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3187 {
3188 struct ptp_ocp *bp = dev_get_drvdata(dev);
3189 const char *p;
3190 u32 select;
3191
3192 select = ioread32(&bp->reg->select);
3193 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3194
3195 return sysfs_emit(buf, "%s\n", p);
3196 }
3197
3198 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3199 clock_source_store(struct device *dev, struct device_attribute *attr,
3200 const char *buf, size_t count)
3201 {
3202 struct ptp_ocp *bp = dev_get_drvdata(dev);
3203 unsigned long flags;
3204 int val;
3205
3206 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3207 if (val < 0)
3208 return val;
3209
3210 spin_lock_irqsave(&bp->lock, flags);
3211 iowrite32(val, &bp->reg->select);
3212 spin_unlock_irqrestore(&bp->lock, flags);
3213
3214 return count;
3215 }
3216 static DEVICE_ATTR_RW(clock_source);
3217
3218 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)3219 available_clock_sources_show(struct device *dev,
3220 struct device_attribute *attr, char *buf)
3221 {
3222 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3223 }
3224 static DEVICE_ATTR_RO(available_clock_sources);
3225
3226 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)3227 clock_status_drift_show(struct device *dev,
3228 struct device_attribute *attr, char *buf)
3229 {
3230 struct ptp_ocp *bp = dev_get_drvdata(dev);
3231 u32 val;
3232 int res;
3233
3234 val = ioread32(&bp->reg->status_drift);
3235 res = (val & ~INT_MAX) ? -1 : 1;
3236 res *= (val & INT_MAX);
3237 return sysfs_emit(buf, "%d\n", res);
3238 }
3239 static DEVICE_ATTR_RO(clock_status_drift);
3240
3241 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3242 clock_status_offset_show(struct device *dev,
3243 struct device_attribute *attr, char *buf)
3244 {
3245 struct ptp_ocp *bp = dev_get_drvdata(dev);
3246 u32 val;
3247 int res;
3248
3249 val = ioread32(&bp->reg->status_offset);
3250 res = (val & ~INT_MAX) ? -1 : 1;
3251 res *= (val & INT_MAX);
3252 return sysfs_emit(buf, "%d\n", res);
3253 }
3254 static DEVICE_ATTR_RO(clock_status_offset);
3255
3256 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)3257 tod_correction_show(struct device *dev,
3258 struct device_attribute *attr, char *buf)
3259 {
3260 struct ptp_ocp *bp = dev_get_drvdata(dev);
3261 u32 val;
3262 int res;
3263
3264 val = ioread32(&bp->tod->adj_sec);
3265 res = (val & ~INT_MAX) ? -1 : 1;
3266 res *= (val & INT_MAX);
3267 return sysfs_emit(buf, "%d\n", res);
3268 }
3269
3270 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3271 tod_correction_store(struct device *dev, struct device_attribute *attr,
3272 const char *buf, size_t count)
3273 {
3274 struct ptp_ocp *bp = dev_get_drvdata(dev);
3275 unsigned long flags;
3276 int err, res;
3277 u32 val = 0;
3278
3279 err = kstrtos32(buf, 0, &res);
3280 if (err)
3281 return err;
3282 if (res < 0) {
3283 res *= -1;
3284 val |= BIT(31);
3285 }
3286 val |= res;
3287
3288 spin_lock_irqsave(&bp->lock, flags);
3289 iowrite32(val, &bp->tod->adj_sec);
3290 spin_unlock_irqrestore(&bp->lock, flags);
3291
3292 return count;
3293 }
3294 static DEVICE_ATTR_RW(tod_correction);
3295
3296 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3297 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3298 &dev_attr_signal##_nr##_signal.attr.attr, \
3299 &dev_attr_signal##_nr##_duty.attr.attr, \
3300 &dev_attr_signal##_nr##_phase.attr.attr, \
3301 &dev_attr_signal##_nr##_period.attr.attr, \
3302 &dev_attr_signal##_nr##_polarity.attr.attr, \
3303 &dev_attr_signal##_nr##_running.attr.attr, \
3304 &dev_attr_signal##_nr##_start.attr.attr, \
3305 NULL, \
3306 }
3307
3308 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3309 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3310 static const struct attribute_group \
3311 fb_timecard_signal##_nr##_group = { \
3312 .name = #_name, \
3313 .attrs = fb_timecard_signal##_nr##_attrs, \
3314 }
3315
3316 DEVICE_SIGNAL_GROUP(gen1, 0);
3317 DEVICE_SIGNAL_GROUP(gen2, 1);
3318 DEVICE_SIGNAL_GROUP(gen3, 2);
3319 DEVICE_SIGNAL_GROUP(gen4, 3);
3320
3321 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3322 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3323 &dev_attr_freq##_nr##_seconds.attr.attr, \
3324 &dev_attr_freq##_nr##_frequency.attr.attr, \
3325 NULL, \
3326 }
3327
3328 #define DEVICE_FREQ_GROUP(_name, _nr) \
3329 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3330 static const struct attribute_group \
3331 fb_timecard_freq##_nr##_group = { \
3332 .name = #_name, \
3333 .attrs = fb_timecard_freq##_nr##_attrs, \
3334 }
3335
3336 DEVICE_FREQ_GROUP(freq1, 0);
3337 DEVICE_FREQ_GROUP(freq2, 1);
3338 DEVICE_FREQ_GROUP(freq3, 2);
3339 DEVICE_FREQ_GROUP(freq4, 3);
3340
3341 static ssize_t
disciplining_config_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3342 disciplining_config_read(struct file *filp, struct kobject *kobj,
3343 struct bin_attribute *bin_attr, char *buf,
3344 loff_t off, size_t count)
3345 {
3346 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3347 size_t size = OCP_ART_CONFIG_SIZE;
3348 struct nvmem_device *nvmem;
3349 ssize_t err;
3350
3351 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3352 if (IS_ERR(nvmem))
3353 return PTR_ERR(nvmem);
3354
3355 if (off > size) {
3356 err = 0;
3357 goto out;
3358 }
3359
3360 if (off + count > size)
3361 count = size - off;
3362
3363 // the configuration is in the very beginning of the EEPROM
3364 err = nvmem_device_read(nvmem, off, count, buf);
3365 if (err != count) {
3366 err = -EFAULT;
3367 goto out;
3368 }
3369
3370 out:
3371 ptp_ocp_nvmem_device_put(&nvmem);
3372
3373 return err;
3374 }
3375
3376 static ssize_t
disciplining_config_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3377 disciplining_config_write(struct file *filp, struct kobject *kobj,
3378 struct bin_attribute *bin_attr, char *buf,
3379 loff_t off, size_t count)
3380 {
3381 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3382 struct nvmem_device *nvmem;
3383 ssize_t err;
3384
3385 /* Allow write of the whole area only */
3386 if (off || count != OCP_ART_CONFIG_SIZE)
3387 return -EFAULT;
3388
3389 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3390 if (IS_ERR(nvmem))
3391 return PTR_ERR(nvmem);
3392
3393 err = nvmem_device_write(nvmem, 0x00, count, buf);
3394 if (err != count)
3395 err = -EFAULT;
3396
3397 ptp_ocp_nvmem_device_put(&nvmem);
3398
3399 return err;
3400 }
3401 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3402
3403 static ssize_t
temperature_table_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3404 temperature_table_read(struct file *filp, struct kobject *kobj,
3405 struct bin_attribute *bin_attr, char *buf,
3406 loff_t off, size_t count)
3407 {
3408 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3409 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3410 struct nvmem_device *nvmem;
3411 ssize_t err;
3412
3413 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3414 if (IS_ERR(nvmem))
3415 return PTR_ERR(nvmem);
3416
3417 if (off > size) {
3418 err = 0;
3419 goto out;
3420 }
3421
3422 if (off + count > size)
3423 count = size - off;
3424
3425 // the configuration is in the very beginning of the EEPROM
3426 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3427 if (err != count) {
3428 err = -EFAULT;
3429 goto out;
3430 }
3431
3432 out:
3433 ptp_ocp_nvmem_device_put(&nvmem);
3434
3435 return err;
3436 }
3437
3438 static ssize_t
temperature_table_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3439 temperature_table_write(struct file *filp, struct kobject *kobj,
3440 struct bin_attribute *bin_attr, char *buf,
3441 loff_t off, size_t count)
3442 {
3443 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3444 struct nvmem_device *nvmem;
3445 ssize_t err;
3446
3447 /* Allow write of the whole area only */
3448 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3449 return -EFAULT;
3450
3451 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3452 if (IS_ERR(nvmem))
3453 return PTR_ERR(nvmem);
3454
3455 err = nvmem_device_write(nvmem, 0x90, count, buf);
3456 if (err != count)
3457 err = -EFAULT;
3458
3459 ptp_ocp_nvmem_device_put(&nvmem);
3460
3461 return err;
3462 }
3463 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3464
3465 static struct attribute *fb_timecard_attrs[] = {
3466 &dev_attr_serialnum.attr,
3467 &dev_attr_gnss_sync.attr,
3468 &dev_attr_clock_source.attr,
3469 &dev_attr_available_clock_sources.attr,
3470 &dev_attr_sma1.attr,
3471 &dev_attr_sma2.attr,
3472 &dev_attr_sma3.attr,
3473 &dev_attr_sma4.attr,
3474 &dev_attr_available_sma_inputs.attr,
3475 &dev_attr_available_sma_outputs.attr,
3476 &dev_attr_clock_status_drift.attr,
3477 &dev_attr_clock_status_offset.attr,
3478 &dev_attr_irig_b_mode.attr,
3479 &dev_attr_utc_tai_offset.attr,
3480 &dev_attr_ts_window_adjust.attr,
3481 &dev_attr_tod_correction.attr,
3482 NULL,
3483 };
3484
3485 static const struct attribute_group fb_timecard_group = {
3486 .attrs = fb_timecard_attrs,
3487 };
3488
3489 static const struct ocp_attr_group fb_timecard_groups[] = {
3490 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3491 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3492 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3493 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3494 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3495 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3496 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3497 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3498 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3499 { },
3500 };
3501
3502 static struct attribute *art_timecard_attrs[] = {
3503 &dev_attr_serialnum.attr,
3504 &dev_attr_clock_source.attr,
3505 &dev_attr_available_clock_sources.attr,
3506 &dev_attr_utc_tai_offset.attr,
3507 &dev_attr_ts_window_adjust.attr,
3508 &dev_attr_sma1.attr,
3509 &dev_attr_sma2.attr,
3510 &dev_attr_sma3.attr,
3511 &dev_attr_sma4.attr,
3512 &dev_attr_available_sma_inputs.attr,
3513 &dev_attr_available_sma_outputs.attr,
3514 NULL,
3515 };
3516
3517 static struct bin_attribute *bin_art_timecard_attrs[] = {
3518 &bin_attr_disciplining_config,
3519 &bin_attr_temperature_table,
3520 NULL,
3521 };
3522
3523 static const struct attribute_group art_timecard_group = {
3524 .attrs = art_timecard_attrs,
3525 .bin_attrs = bin_art_timecard_attrs,
3526 };
3527
3528 static const struct ocp_attr_group art_timecard_groups[] = {
3529 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3530 { },
3531 };
3532
3533 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)3534 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3535 const char *def)
3536 {
3537 int i;
3538
3539 for (i = 0; i < 4; i++) {
3540 if (bp->sma[i].mode != SMA_MODE_IN)
3541 continue;
3542 if (map[i][0] & (1 << bit)) {
3543 sprintf(buf, "sma%d", i + 1);
3544 return;
3545 }
3546 }
3547 if (!def)
3548 def = "----";
3549 strcpy(buf, def);
3550 }
3551
3552 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)3553 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3554 {
3555 char *ans = buf;
3556 int i;
3557
3558 strcpy(ans, "----");
3559 for (i = 0; i < 4; i++) {
3560 if (bp->sma[i].mode != SMA_MODE_OUT)
3561 continue;
3562 if (map[i][1] & (1 << bit))
3563 ans += sprintf(ans, "sma%d ", i + 1);
3564 }
3565 }
3566
3567 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)3568 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3569 {
3570 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3571 struct ptp_ocp_signal *signal = &bp->signal[nr];
3572 char label[8];
3573 bool on;
3574 u32 val;
3575
3576 if (!signal)
3577 return;
3578
3579 on = signal->running;
3580 sprintf(label, "GEN%d", nr + 1);
3581 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3582 label, on ? " ON" : "OFF",
3583 signal->period, signal->duty, signal->phase,
3584 signal->polarity);
3585
3586 val = ioread32(®->enable);
3587 seq_printf(s, " [%x", val);
3588 val = ioread32(®->status);
3589 seq_printf(s, " %x]", val);
3590
3591 seq_printf(s, " start:%llu\n", signal->start);
3592 }
3593
3594 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)3595 _frequency_summary_show(struct seq_file *s, int nr,
3596 struct frequency_reg __iomem *reg)
3597 {
3598 char label[8];
3599 bool on;
3600 u32 val;
3601
3602 if (!reg)
3603 return;
3604
3605 sprintf(label, "FREQ%d", nr + 1);
3606 val = ioread32(®->ctrl);
3607 on = val & 1;
3608 val = (val >> 8) & 0xff;
3609 seq_printf(s, "%7s: %s, sec:%u",
3610 label,
3611 on ? " ON" : "OFF",
3612 val);
3613
3614 val = ioread32(®->status);
3615 if (val & FREQ_STATUS_ERROR)
3616 seq_printf(s, ", error");
3617 if (val & FREQ_STATUS_OVERRUN)
3618 seq_printf(s, ", overrun");
3619 if (val & FREQ_STATUS_VALID)
3620 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3621 seq_printf(s, " reg:%x\n", val);
3622 }
3623
3624 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)3625 ptp_ocp_summary_show(struct seq_file *s, void *data)
3626 {
3627 struct device *dev = s->private;
3628 struct ptp_system_timestamp sts;
3629 struct ts_reg __iomem *ts_reg;
3630 char *buf, *src, *mac_src;
3631 struct timespec64 ts;
3632 struct ptp_ocp *bp;
3633 u16 sma_val[4][2];
3634 u32 ctrl, val;
3635 bool on, map;
3636 int i;
3637
3638 buf = (char *)__get_free_page(GFP_KERNEL);
3639 if (!buf)
3640 return -ENOMEM;
3641
3642 bp = dev_get_drvdata(dev);
3643
3644 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3645 if (bp->gnss_port.line != -1)
3646 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1",
3647 bp->gnss_port.line);
3648 if (bp->gnss2_port.line != -1)
3649 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2",
3650 bp->gnss2_port.line);
3651 if (bp->mac_port.line != -1)
3652 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line);
3653 if (bp->nmea_port.line != -1)
3654 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line);
3655
3656 memset(sma_val, 0xff, sizeof(sma_val));
3657 if (bp->sma_map1) {
3658 u32 reg;
3659
3660 reg = ioread32(&bp->sma_map1->gpio1);
3661 sma_val[0][0] = reg & 0xffff;
3662 sma_val[1][0] = reg >> 16;
3663
3664 reg = ioread32(&bp->sma_map1->gpio2);
3665 sma_val[2][1] = reg & 0xffff;
3666 sma_val[3][1] = reg >> 16;
3667
3668 reg = ioread32(&bp->sma_map2->gpio1);
3669 sma_val[2][0] = reg & 0xffff;
3670 sma_val[3][0] = reg >> 16;
3671
3672 reg = ioread32(&bp->sma_map2->gpio2);
3673 sma_val[0][1] = reg & 0xffff;
3674 sma_val[1][1] = reg >> 16;
3675 }
3676
3677 sma1_show(dev, NULL, buf);
3678 seq_printf(s, " sma1: %04x,%04x %s",
3679 sma_val[0][0], sma_val[0][1], buf);
3680
3681 sma2_show(dev, NULL, buf);
3682 seq_printf(s, " sma2: %04x,%04x %s",
3683 sma_val[1][0], sma_val[1][1], buf);
3684
3685 sma3_show(dev, NULL, buf);
3686 seq_printf(s, " sma3: %04x,%04x %s",
3687 sma_val[2][0], sma_val[2][1], buf);
3688
3689 sma4_show(dev, NULL, buf);
3690 seq_printf(s, " sma4: %04x,%04x %s",
3691 sma_val[3][0], sma_val[3][1], buf);
3692
3693 if (bp->ts0) {
3694 ts_reg = bp->ts0->mem;
3695 on = ioread32(&ts_reg->enable);
3696 src = "GNSS1";
3697 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
3698 on ? " ON" : "OFF", src);
3699 }
3700
3701 if (bp->ts1) {
3702 ts_reg = bp->ts1->mem;
3703 on = ioread32(&ts_reg->enable);
3704 gpio_input_map(buf, bp, sma_val, 2, NULL);
3705 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
3706 on ? " ON" : "OFF", buf);
3707 }
3708
3709 if (bp->ts2) {
3710 ts_reg = bp->ts2->mem;
3711 on = ioread32(&ts_reg->enable);
3712 gpio_input_map(buf, bp, sma_val, 3, NULL);
3713 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
3714 on ? " ON" : "OFF", buf);
3715 }
3716
3717 if (bp->ts3) {
3718 ts_reg = bp->ts3->mem;
3719 on = ioread32(&ts_reg->enable);
3720 gpio_input_map(buf, bp, sma_val, 6, NULL);
3721 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
3722 on ? " ON" : "OFF", buf);
3723 }
3724
3725 if (bp->ts4) {
3726 ts_reg = bp->ts4->mem;
3727 on = ioread32(&ts_reg->enable);
3728 gpio_input_map(buf, bp, sma_val, 7, NULL);
3729 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
3730 on ? " ON" : "OFF", buf);
3731 }
3732
3733 if (bp->pps) {
3734 ts_reg = bp->pps->mem;
3735 src = "PHC";
3736 on = ioread32(&ts_reg->enable);
3737 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
3738 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
3739 on && map ? " ON" : "OFF", src);
3740
3741 map = !!(bp->pps_req_map & OCP_REQ_PPS);
3742 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
3743 on && map ? " ON" : "OFF", src);
3744 }
3745
3746 if (bp->fw_cap & OCP_CAP_SIGNAL)
3747 for (i = 0; i < 4; i++)
3748 _signal_summary_show(s, bp, i);
3749
3750 if (bp->fw_cap & OCP_CAP_FREQ)
3751 for (i = 0; i < 4; i++)
3752 _frequency_summary_show(s, i, bp->freq_in[i]);
3753
3754 if (bp->irig_out) {
3755 ctrl = ioread32(&bp->irig_out->ctrl);
3756 on = ctrl & IRIG_M_CTRL_ENABLE;
3757 val = ioread32(&bp->irig_out->status);
3758 gpio_output_map(buf, bp, sma_val, 4);
3759 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
3760 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
3761 }
3762
3763 if (bp->irig_in) {
3764 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
3765 val = ioread32(&bp->irig_in->status);
3766 gpio_input_map(buf, bp, sma_val, 4, NULL);
3767 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
3768 on ? " ON" : "OFF", val, buf);
3769 }
3770
3771 if (bp->dcf_out) {
3772 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
3773 val = ioread32(&bp->dcf_out->status);
3774 gpio_output_map(buf, bp, sma_val, 5);
3775 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
3776 on ? " ON" : "OFF", val, buf);
3777 }
3778
3779 if (bp->dcf_in) {
3780 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
3781 val = ioread32(&bp->dcf_in->status);
3782 gpio_input_map(buf, bp, sma_val, 5, NULL);
3783 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
3784 on ? " ON" : "OFF", val, buf);
3785 }
3786
3787 if (bp->nmea_out) {
3788 on = ioread32(&bp->nmea_out->ctrl) & 1;
3789 val = ioread32(&bp->nmea_out->status);
3790 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
3791 on ? " ON" : "OFF", val);
3792 }
3793
3794 /* compute src for PPS1, used below. */
3795 if (bp->pps_select) {
3796 val = ioread32(&bp->pps_select->gpio1);
3797 src = &buf[80];
3798 mac_src = "GNSS1";
3799 if (val & 0x01) {
3800 gpio_input_map(src, bp, sma_val, 0, NULL);
3801 mac_src = src;
3802 } else if (val & 0x02) {
3803 src = "MAC";
3804 } else if (val & 0x04) {
3805 src = "GNSS1";
3806 } else {
3807 src = "----";
3808 mac_src = src;
3809 }
3810 } else {
3811 src = "?";
3812 mac_src = src;
3813 }
3814 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
3815
3816 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
3817 seq_printf(s, "MAC PPS2 src: %s\n", buf);
3818
3819 /* assumes automatic switchover/selection */
3820 val = ioread32(&bp->reg->select);
3821 switch (val >> 16) {
3822 case 0:
3823 sprintf(buf, "----");
3824 break;
3825 case 2:
3826 sprintf(buf, "IRIG");
3827 break;
3828 case 3:
3829 sprintf(buf, "%s via PPS1", src);
3830 break;
3831 case 6:
3832 sprintf(buf, "DCF");
3833 break;
3834 default:
3835 strcpy(buf, "unknown");
3836 break;
3837 }
3838 val = ioread32(&bp->reg->status);
3839 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
3840 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
3841
3842 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
3843 struct timespec64 sys_ts;
3844 s64 pre_ns, post_ns, ns;
3845
3846 pre_ns = timespec64_to_ns(&sts.pre_ts);
3847 post_ns = timespec64_to_ns(&sts.post_ts);
3848 ns = (pre_ns + post_ns) / 2;
3849 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
3850 sys_ts = ns_to_timespec64(ns);
3851
3852 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
3853 ts.tv_sec, ts.tv_nsec, &ts);
3854 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
3855 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
3856 bp->utc_tai_offset);
3857 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
3858 timespec64_to_ns(&ts) - ns,
3859 post_ns - pre_ns);
3860 }
3861
3862 free_page((unsigned long)buf);
3863 return 0;
3864 }
3865 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
3866
3867 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)3868 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
3869 {
3870 struct device *dev = s->private;
3871 struct ptp_ocp *bp;
3872 u32 val;
3873 int idx;
3874
3875 bp = dev_get_drvdata(dev);
3876
3877 val = ioread32(&bp->tod->ctrl);
3878 if (!(val & TOD_CTRL_ENABLE)) {
3879 seq_printf(s, "TOD Slave disabled\n");
3880 return 0;
3881 }
3882 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
3883
3884 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
3885 idx += (val >> 16) & 3;
3886 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
3887
3888 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
3889 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
3890
3891 val = ioread32(&bp->tod->version);
3892 seq_printf(s, "TOD Version %d.%d.%d\n",
3893 val >> 24, (val >> 16) & 0xff, val & 0xffff);
3894
3895 val = ioread32(&bp->tod->status);
3896 seq_printf(s, "Status register: 0x%08X\n", val);
3897
3898 val = ioread32(&bp->tod->adj_sec);
3899 idx = (val & ~INT_MAX) ? -1 : 1;
3900 idx *= (val & INT_MAX);
3901 seq_printf(s, "Correction seconds: %d\n", idx);
3902
3903 val = ioread32(&bp->tod->utc_status);
3904 seq_printf(s, "UTC status register: 0x%08X\n", val);
3905 seq_printf(s, "UTC offset: %ld valid:%d\n",
3906 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
3907 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
3908 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
3909 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
3910
3911 val = ioread32(&bp->tod->leap);
3912 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
3913
3914 return 0;
3915 }
3916 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
3917
3918 static struct dentry *ptp_ocp_debugfs_root;
3919
3920 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)3921 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
3922 {
3923 struct dentry *d;
3924
3925 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
3926 bp->debug_root = d;
3927 debugfs_create_file("summary", 0444, bp->debug_root,
3928 &bp->dev, &ptp_ocp_summary_fops);
3929 if (bp->tod)
3930 debugfs_create_file("tod_status", 0444, bp->debug_root,
3931 &bp->dev, &ptp_ocp_tod_status_fops);
3932 }
3933
3934 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)3935 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
3936 {
3937 debugfs_remove_recursive(bp->debug_root);
3938 }
3939
3940 static void
ptp_ocp_debugfs_init(void)3941 ptp_ocp_debugfs_init(void)
3942 {
3943 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
3944 }
3945
3946 static void
ptp_ocp_debugfs_fini(void)3947 ptp_ocp_debugfs_fini(void)
3948 {
3949 debugfs_remove_recursive(ptp_ocp_debugfs_root);
3950 }
3951
3952 static void
ptp_ocp_dev_release(struct device * dev)3953 ptp_ocp_dev_release(struct device *dev)
3954 {
3955 struct ptp_ocp *bp = dev_get_drvdata(dev);
3956
3957 mutex_lock(&ptp_ocp_lock);
3958 idr_remove(&ptp_ocp_idr, bp->id);
3959 mutex_unlock(&ptp_ocp_lock);
3960 }
3961
3962 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)3963 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
3964 {
3965 int err;
3966
3967 mutex_lock(&ptp_ocp_lock);
3968 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
3969 mutex_unlock(&ptp_ocp_lock);
3970 if (err < 0) {
3971 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
3972 return err;
3973 }
3974 bp->id = err;
3975
3976 bp->ptp_info = ptp_ocp_clock_info;
3977 spin_lock_init(&bp->lock);
3978 bp->gnss_port.line = -1;
3979 bp->gnss2_port.line = -1;
3980 bp->mac_port.line = -1;
3981 bp->nmea_port.line = -1;
3982 bp->pdev = pdev;
3983
3984 device_initialize(&bp->dev);
3985 dev_set_name(&bp->dev, "ocp%d", bp->id);
3986 bp->dev.class = &timecard_class;
3987 bp->dev.parent = &pdev->dev;
3988 bp->dev.release = ptp_ocp_dev_release;
3989 dev_set_drvdata(&bp->dev, bp);
3990
3991 err = device_add(&bp->dev);
3992 if (err) {
3993 dev_err(&bp->dev, "device add failed: %d\n", err);
3994 goto out;
3995 }
3996
3997 pci_set_drvdata(pdev, bp);
3998
3999 return 0;
4000
4001 out:
4002 put_device(&bp->dev);
4003 return err;
4004 }
4005
4006 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)4007 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4008 {
4009 struct device *dev = &bp->dev;
4010
4011 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4012 dev_err(dev, "%s symlink failed\n", link);
4013 }
4014
4015 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)4016 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4017 {
4018 struct device *dev, *child;
4019
4020 dev = &bp->pdev->dev;
4021
4022 child = device_find_child_by_name(dev, name);
4023 if (!child) {
4024 dev_err(dev, "Could not find device %s\n", name);
4025 return;
4026 }
4027
4028 ptp_ocp_symlink(bp, child, link);
4029 put_device(child);
4030 }
4031
4032 static int
ptp_ocp_complete(struct ptp_ocp * bp)4033 ptp_ocp_complete(struct ptp_ocp *bp)
4034 {
4035 struct pps_device *pps;
4036 char buf[32];
4037
4038 if (bp->gnss_port.line != -1) {
4039 sprintf(buf, "ttyS%d", bp->gnss_port.line);
4040 ptp_ocp_link_child(bp, buf, "ttyGNSS");
4041 }
4042 if (bp->gnss2_port.line != -1) {
4043 sprintf(buf, "ttyS%d", bp->gnss2_port.line);
4044 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
4045 }
4046 if (bp->mac_port.line != -1) {
4047 sprintf(buf, "ttyS%d", bp->mac_port.line);
4048 ptp_ocp_link_child(bp, buf, "ttyMAC");
4049 }
4050 if (bp->nmea_port.line != -1) {
4051 sprintf(buf, "ttyS%d", bp->nmea_port.line);
4052 ptp_ocp_link_child(bp, buf, "ttyNMEA");
4053 }
4054 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4055 ptp_ocp_link_child(bp, buf, "ptp");
4056
4057 pps = pps_lookup_dev(bp->ptp);
4058 if (pps)
4059 ptp_ocp_symlink(bp, &pps->dev, "pps");
4060
4061 ptp_ocp_debugfs_add_device(bp);
4062
4063 return 0;
4064 }
4065
4066 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)4067 ptp_ocp_phc_info(struct ptp_ocp *bp)
4068 {
4069 struct timespec64 ts;
4070 u32 version, select;
4071 bool sync;
4072
4073 version = ioread32(&bp->reg->version);
4074 select = ioread32(&bp->reg->select);
4075 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4076 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4077 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4078 ptp_clock_index(bp->ptp));
4079
4080 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
4081 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4082 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4083 ts.tv_sec, ts.tv_nsec,
4084 sync ? "in-sync" : "UNSYNCED");
4085 }
4086
4087 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)4088 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4089 {
4090 if (port != -1)
4091 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4092 }
4093
4094 static void
ptp_ocp_info(struct ptp_ocp * bp)4095 ptp_ocp_info(struct ptp_ocp *bp)
4096 {
4097 static int nmea_baud[] = {
4098 1200, 2400, 4800, 9600, 19200, 38400,
4099 57600, 115200, 230400, 460800, 921600,
4100 1000000, 2000000
4101 };
4102 struct device *dev = &bp->pdev->dev;
4103 u32 reg;
4104
4105 ptp_ocp_phc_info(bp);
4106
4107 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line,
4108 bp->gnss_port.baud);
4109 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line,
4110 bp->gnss2_port.baud);
4111 ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud);
4112 if (bp->nmea_out && bp->nmea_port.line != -1) {
4113 bp->nmea_port.baud = -1;
4114
4115 reg = ioread32(&bp->nmea_out->uart_baud);
4116 if (reg < ARRAY_SIZE(nmea_baud))
4117 bp->nmea_port.baud = nmea_baud[reg];
4118
4119 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line,
4120 bp->nmea_port.baud);
4121 }
4122 }
4123
4124 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)4125 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4126 {
4127 struct device *dev = &bp->dev;
4128
4129 sysfs_remove_link(&dev->kobj, "ttyGNSS");
4130 sysfs_remove_link(&dev->kobj, "ttyGNSS2");
4131 sysfs_remove_link(&dev->kobj, "ttyMAC");
4132 sysfs_remove_link(&dev->kobj, "ptp");
4133 sysfs_remove_link(&dev->kobj, "pps");
4134 }
4135
4136 static void
ptp_ocp_detach(struct ptp_ocp * bp)4137 ptp_ocp_detach(struct ptp_ocp *bp)
4138 {
4139 int i;
4140
4141 ptp_ocp_debugfs_remove_device(bp);
4142 ptp_ocp_detach_sysfs(bp);
4143 ptp_ocp_attr_group_del(bp);
4144 if (timer_pending(&bp->watchdog))
4145 del_timer_sync(&bp->watchdog);
4146 if (bp->ts0)
4147 ptp_ocp_unregister_ext(bp->ts0);
4148 if (bp->ts1)
4149 ptp_ocp_unregister_ext(bp->ts1);
4150 if (bp->ts2)
4151 ptp_ocp_unregister_ext(bp->ts2);
4152 if (bp->ts3)
4153 ptp_ocp_unregister_ext(bp->ts3);
4154 if (bp->ts4)
4155 ptp_ocp_unregister_ext(bp->ts4);
4156 if (bp->pps)
4157 ptp_ocp_unregister_ext(bp->pps);
4158 for (i = 0; i < 4; i++)
4159 if (bp->signal_out[i])
4160 ptp_ocp_unregister_ext(bp->signal_out[i]);
4161 if (bp->gnss_port.line != -1)
4162 serial8250_unregister_port(bp->gnss_port.line);
4163 if (bp->gnss2_port.line != -1)
4164 serial8250_unregister_port(bp->gnss2_port.line);
4165 if (bp->mac_port.line != -1)
4166 serial8250_unregister_port(bp->mac_port.line);
4167 if (bp->nmea_port.line != -1)
4168 serial8250_unregister_port(bp->nmea_port.line);
4169 platform_device_unregister(bp->spi_flash);
4170 platform_device_unregister(bp->i2c_ctrl);
4171 if (bp->i2c_clk)
4172 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4173 if (bp->n_irqs)
4174 pci_free_irq_vectors(bp->pdev);
4175 if (bp->ptp)
4176 ptp_clock_unregister(bp->ptp);
4177 kfree(bp->ptp_info.pin_config);
4178 device_unregister(&bp->dev);
4179 }
4180
4181 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)4182 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4183 {
4184 struct devlink *devlink;
4185 struct ptp_ocp *bp;
4186 int err;
4187
4188 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4189 if (!devlink) {
4190 dev_err(&pdev->dev, "devlink_alloc failed\n");
4191 return -ENOMEM;
4192 }
4193
4194 err = pci_enable_device(pdev);
4195 if (err) {
4196 dev_err(&pdev->dev, "pci_enable_device\n");
4197 goto out_free;
4198 }
4199
4200 bp = devlink_priv(devlink);
4201 err = ptp_ocp_device_init(bp, pdev);
4202 if (err)
4203 goto out_disable;
4204
4205 /* compat mode.
4206 * Older FPGA firmware only returns 2 irq's.
4207 * allow this - if not all of the IRQ's are returned, skip the
4208 * extra devices and just register the clock.
4209 */
4210 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4211 if (err < 0) {
4212 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4213 goto out;
4214 }
4215 bp->n_irqs = err;
4216 pci_set_master(pdev);
4217
4218 err = ptp_ocp_register_resources(bp, id->driver_data);
4219 if (err)
4220 goto out;
4221
4222 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4223 if (IS_ERR(bp->ptp)) {
4224 err = PTR_ERR(bp->ptp);
4225 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4226 bp->ptp = NULL;
4227 goto out;
4228 }
4229
4230 err = ptp_ocp_complete(bp);
4231 if (err)
4232 goto out;
4233
4234 ptp_ocp_info(bp);
4235 devlink_register(devlink);
4236 return 0;
4237
4238 out:
4239 ptp_ocp_detach(bp);
4240 out_disable:
4241 pci_disable_device(pdev);
4242 out_free:
4243 devlink_free(devlink);
4244 return err;
4245 }
4246
4247 static void
ptp_ocp_remove(struct pci_dev * pdev)4248 ptp_ocp_remove(struct pci_dev *pdev)
4249 {
4250 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4251 struct devlink *devlink = priv_to_devlink(bp);
4252
4253 devlink_unregister(devlink);
4254 ptp_ocp_detach(bp);
4255 pci_disable_device(pdev);
4256
4257 devlink_free(devlink);
4258 }
4259
4260 static struct pci_driver ptp_ocp_driver = {
4261 .name = KBUILD_MODNAME,
4262 .id_table = ptp_ocp_pcidev_id,
4263 .probe = ptp_ocp_probe,
4264 .remove = ptp_ocp_remove,
4265 };
4266
4267 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)4268 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4269 unsigned long action, void *data)
4270 {
4271 struct device *dev, *child = data;
4272 struct ptp_ocp *bp;
4273 bool add;
4274
4275 switch (action) {
4276 case BUS_NOTIFY_ADD_DEVICE:
4277 case BUS_NOTIFY_DEL_DEVICE:
4278 add = action == BUS_NOTIFY_ADD_DEVICE;
4279 break;
4280 default:
4281 return 0;
4282 }
4283
4284 if (!i2c_verify_adapter(child))
4285 return 0;
4286
4287 dev = child;
4288 while ((dev = dev->parent))
4289 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4290 goto found;
4291 return 0;
4292
4293 found:
4294 bp = dev_get_drvdata(dev);
4295 if (add)
4296 ptp_ocp_symlink(bp, child, "i2c");
4297 else
4298 sysfs_remove_link(&bp->dev.kobj, "i2c");
4299
4300 return 0;
4301 }
4302
4303 static struct notifier_block ptp_ocp_i2c_notifier = {
4304 .notifier_call = ptp_ocp_i2c_notifier_call,
4305 };
4306
4307 static int __init
ptp_ocp_init(void)4308 ptp_ocp_init(void)
4309 {
4310 const char *what;
4311 int err;
4312
4313 ptp_ocp_debugfs_init();
4314
4315 what = "timecard class";
4316 err = class_register(&timecard_class);
4317 if (err)
4318 goto out;
4319
4320 what = "i2c notifier";
4321 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4322 if (err)
4323 goto out_notifier;
4324
4325 what = "ptp_ocp driver";
4326 err = pci_register_driver(&ptp_ocp_driver);
4327 if (err)
4328 goto out_register;
4329
4330 return 0;
4331
4332 out_register:
4333 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4334 out_notifier:
4335 class_unregister(&timecard_class);
4336 out:
4337 ptp_ocp_debugfs_fini();
4338 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4339 return err;
4340 }
4341
4342 static void __exit
ptp_ocp_fini(void)4343 ptp_ocp_fini(void)
4344 {
4345 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4346 pci_unregister_driver(&ptp_ocp_driver);
4347 class_unregister(&timecard_class);
4348 ptp_ocp_debugfs_fini();
4349 }
4350
4351 module_init(ptp_ocp_init);
4352 module_exit(ptp_ocp_fini);
4353
4354 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4355 MODULE_LICENSE("GPL v2");
4356