| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1108.c | 31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
200 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_saradc_set_clk()
225 static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio1_set_clk()
251 static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio0_set_clk()
286 static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_dclk_vop_set_clk()
315 static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_bus_set_clk()
367 static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_peri_set_clk()
383 static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_hclk_peri_set_clk()
398 static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_pclk_peri_set_clk()
446 static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz) in rv1108_i2c_set_clk()
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| H A D | clk_rk3128.c | 29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
367 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_peri_set_pclk()
402 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz) in rk3128_saradc_set_clk()
416 static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_vop_set_clk()
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| H A D | clk_rk3188.c | 73 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
120 unsigned int hz, bool has_bwadj) in rkclk_configure_ddr()
166 unsigned int hz, bool has_bwadj) in rkclk_configure_cpu()
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| H A D | clk_rk3368.c | 43 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
400 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) in rk3368_spi_set_clk()
438 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) in rk3368_saradc_set_clk()
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| H A D | clk_rk3328.c | 32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
358 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) in rk3328_i2c_set_clk()
515 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_pwm_set_clk()
538 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_saradc_set_clk()
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| H A D | clk_rk3399.c | 44 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
552 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_i2c_set_clk()
651 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_spi_set_clk()
678 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) in rk3399_vop_set_clk()
876 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) in rk3399_saradc_set_clk()
1274 uint hz) in rk3399_i2c_set_pmuclk()
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| H A D | clk_rk3288.c | 133 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
176 unsigned int hz) in rkclk_configure_ddr()
729 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) in rockchip_saradc_set_clk()
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| H A D | clk_rk3036.c | 31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
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| H A D | clk_rk322x.c | 28 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
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| /openbmc/u-boot/drivers/spi/ |
| H A D | cadence_qspi.c | 22 static int cadence_spi_write_speed(struct udevice *bus, uint hz) in cadence_spi_write_speed()
39 static int spi_calibration(struct udevice *bus, uint hz) in spi_calibration()
118 static int cadence_spi_set_speed(struct udevice *bus, uint hz) in cadence_spi_set_speed()
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| H A D | mvebu_a3700_spi.c | 175 static int mvebu_spi_set_speed(struct udevice *bus, uint hz) in mvebu_spi_set_speed()
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| H A D | kirkwood_spi.c | 258 static int mvebu_spi_set_speed(struct udevice *bus, uint hz) in mvebu_spi_set_speed()
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| H A D | ti_qspi.c | 116 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) in ti_spi_set_speed()
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| /openbmc/u-boot/lib/ |
| H A D | strmhz.c | 8 char *strmhz (char *buf, unsigned long hz) in strmhz()
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| /openbmc/qemu/include/hw/ |
| H A D | clock.h | 54 #define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_PERIOD_1SEC / (hz) : 0u) argument
182 static inline bool clock_set_hz(Clock *clk, unsigned hz) in clock_set_hz()
220 static inline void clock_update_hz(Clock *clk, unsigned hz) in clock_update_hz()
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| /openbmc/qemu/tests/qtest/ |
| H A D | stm32l4x5.h | 16 #define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_PERIOD_1SEC / (hz) : 0u) argument
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | clock_sun4i.c | 118 void clock_set_pll1(unsigned int hz) in clock_set_pll1()
227 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) in clock_set_de_mod_clock()
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| H A D | clock_sun6i.c | 335 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) in clock_set_de_mod_clock()
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| /openbmc/u-boot/lib/bzip2/ |
| H A D | bzlib_blocksort.c | 120 #define fpush(lz,hz) { stackLo[sp] = lz; \ argument
124 #define fpop(lz,hz) { sp--; \ argument
636 #define mpush(lz,hz,dz) { stackLo[sp] = lz; \ argument
641 #define mpop(lz,hz,dz) { sp--; \ argument
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| /openbmc/u-boot/board/Arcturus/ucp1020/ |
| H A D | ucp1020.c | 41 void spi_set_speed(struct spi_slave *slave, uint hz) in spi_set_speed()
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| /openbmc/u-boot/cmd/ |
| H A D | bdinfo.c | 64 static void print_mhz(const char *name, unsigned long hz) in print_mhz()
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | gen_atmel_mci.c | 90 static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
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| H A D | sunxi_mmc.c | 109 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) in mmc_set_mod_clk()
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| H A D | mtk-sd.c | 714 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz) in msdc_set_mclk()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_pic32.c | 117 ulong hz; in pic32_get_sysclk() local
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