1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2018 Broadcom */
3
4 /**
5 * DOC: Broadcom V3D scheduling
6 *
7 * The shared DRM GPU scheduler is used to coordinate submitting jobs
8 * to the hardware. Each DRM fd (roughly a client process) gets its
9 * own scheduler entity, which will process jobs in order. The GPU
10 * scheduler will round-robin between clients to submit the next job.
11 *
12 * For simplicity, and in order to keep latency low for interactive
13 * jobs when bulk background jobs are queued up, we submit a new job
14 * to the HW only when it has completed the last one, instead of
15 * filling up the CT[01]Q FIFOs with jobs. Similarly, we use
16 * drm_sched_job_add_dependency() to manage the dependency between bin and
17 * render, instead of having the clients submit jobs using the HW's
18 * semaphores to interlock between them.
19 */
20
21 #include <linux/kthread.h>
22
23 #include "v3d_drv.h"
24 #include "v3d_regs.h"
25 #include "v3d_trace.h"
26
27 static struct v3d_job *
to_v3d_job(struct drm_sched_job * sched_job)28 to_v3d_job(struct drm_sched_job *sched_job)
29 {
30 return container_of(sched_job, struct v3d_job, base);
31 }
32
33 static struct v3d_bin_job *
to_bin_job(struct drm_sched_job * sched_job)34 to_bin_job(struct drm_sched_job *sched_job)
35 {
36 return container_of(sched_job, struct v3d_bin_job, base.base);
37 }
38
39 static struct v3d_render_job *
to_render_job(struct drm_sched_job * sched_job)40 to_render_job(struct drm_sched_job *sched_job)
41 {
42 return container_of(sched_job, struct v3d_render_job, base.base);
43 }
44
45 static struct v3d_tfu_job *
to_tfu_job(struct drm_sched_job * sched_job)46 to_tfu_job(struct drm_sched_job *sched_job)
47 {
48 return container_of(sched_job, struct v3d_tfu_job, base.base);
49 }
50
51 static struct v3d_csd_job *
to_csd_job(struct drm_sched_job * sched_job)52 to_csd_job(struct drm_sched_job *sched_job)
53 {
54 return container_of(sched_job, struct v3d_csd_job, base.base);
55 }
56
57 static void
v3d_sched_job_free(struct drm_sched_job * sched_job)58 v3d_sched_job_free(struct drm_sched_job *sched_job)
59 {
60 struct v3d_job *job = to_v3d_job(sched_job);
61
62 v3d_job_cleanup(job);
63 }
64
65 static void
v3d_switch_perfmon(struct v3d_dev * v3d,struct v3d_job * job)66 v3d_switch_perfmon(struct v3d_dev *v3d, struct v3d_job *job)
67 {
68 if (job->perfmon != v3d->active_perfmon)
69 v3d_perfmon_stop(v3d, v3d->active_perfmon, true);
70
71 if (job->perfmon && v3d->active_perfmon != job->perfmon)
72 v3d_perfmon_start(v3d, job->perfmon);
73 }
74
v3d_bin_job_run(struct drm_sched_job * sched_job)75 static struct dma_fence *v3d_bin_job_run(struct drm_sched_job *sched_job)
76 {
77 struct v3d_bin_job *job = to_bin_job(sched_job);
78 struct v3d_dev *v3d = job->base.v3d;
79 struct drm_device *dev = &v3d->drm;
80 struct dma_fence *fence;
81 unsigned long irqflags;
82
83 if (unlikely(job->base.base.s_fence->finished.error))
84 return NULL;
85
86 /* Lock required around bin_job update vs
87 * v3d_overflow_mem_work().
88 */
89 spin_lock_irqsave(&v3d->job_lock, irqflags);
90 v3d->bin_job = job;
91 /* Clear out the overflow allocation, so we don't
92 * reuse the overflow attached to a previous job.
93 */
94 V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0);
95 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
96
97 v3d_invalidate_caches(v3d);
98
99 fence = v3d_fence_create(v3d, V3D_BIN);
100 if (IS_ERR(fence))
101 return NULL;
102
103 if (job->base.irq_fence)
104 dma_fence_put(job->base.irq_fence);
105 job->base.irq_fence = dma_fence_get(fence);
106
107 trace_v3d_submit_cl(dev, false, to_v3d_fence(fence)->seqno,
108 job->start, job->end);
109
110 v3d_switch_perfmon(v3d, &job->base);
111
112 /* Set the current and end address of the control list.
113 * Writing the end register is what starts the job.
114 */
115 if (job->qma) {
116 V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, job->qma);
117 V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, job->qms);
118 }
119 if (job->qts) {
120 V3D_CORE_WRITE(0, V3D_CLE_CT0QTS,
121 V3D_CLE_CT0QTS_ENABLE |
122 job->qts);
123 }
124 V3D_CORE_WRITE(0, V3D_CLE_CT0QBA, job->start);
125 V3D_CORE_WRITE(0, V3D_CLE_CT0QEA, job->end);
126
127 return fence;
128 }
129
v3d_render_job_run(struct drm_sched_job * sched_job)130 static struct dma_fence *v3d_render_job_run(struct drm_sched_job *sched_job)
131 {
132 struct v3d_render_job *job = to_render_job(sched_job);
133 struct v3d_dev *v3d = job->base.v3d;
134 struct drm_device *dev = &v3d->drm;
135 struct dma_fence *fence;
136
137 if (unlikely(job->base.base.s_fence->finished.error))
138 return NULL;
139
140 v3d->render_job = job;
141
142 /* Can we avoid this flush? We need to be careful of
143 * scheduling, though -- imagine job0 rendering to texture and
144 * job1 reading, and them being executed as bin0, bin1,
145 * render0, render1, so that render1's flush at bin time
146 * wasn't enough.
147 */
148 v3d_invalidate_caches(v3d);
149
150 fence = v3d_fence_create(v3d, V3D_RENDER);
151 if (IS_ERR(fence))
152 return NULL;
153
154 if (job->base.irq_fence)
155 dma_fence_put(job->base.irq_fence);
156 job->base.irq_fence = dma_fence_get(fence);
157
158 trace_v3d_submit_cl(dev, true, to_v3d_fence(fence)->seqno,
159 job->start, job->end);
160
161 v3d_switch_perfmon(v3d, &job->base);
162
163 /* XXX: Set the QCFG */
164
165 /* Set the current and end address of the control list.
166 * Writing the end register is what starts the job.
167 */
168 V3D_CORE_WRITE(0, V3D_CLE_CT1QBA, job->start);
169 V3D_CORE_WRITE(0, V3D_CLE_CT1QEA, job->end);
170
171 return fence;
172 }
173
174 static struct dma_fence *
v3d_tfu_job_run(struct drm_sched_job * sched_job)175 v3d_tfu_job_run(struct drm_sched_job *sched_job)
176 {
177 struct v3d_tfu_job *job = to_tfu_job(sched_job);
178 struct v3d_dev *v3d = job->base.v3d;
179 struct drm_device *dev = &v3d->drm;
180 struct dma_fence *fence;
181
182 if (unlikely(job->base.base.s_fence->finished.error))
183 return NULL;
184
185 v3d->tfu_job = job;
186
187 fence = v3d_fence_create(v3d, V3D_TFU);
188 if (IS_ERR(fence))
189 return NULL;
190
191 if (job->base.irq_fence)
192 dma_fence_put(job->base.irq_fence);
193 job->base.irq_fence = dma_fence_get(fence);
194
195 trace_v3d_submit_tfu(dev, to_v3d_fence(fence)->seqno);
196
197 V3D_WRITE(V3D_TFU_IIA, job->args.iia);
198 V3D_WRITE(V3D_TFU_IIS, job->args.iis);
199 V3D_WRITE(V3D_TFU_ICA, job->args.ica);
200 V3D_WRITE(V3D_TFU_IUA, job->args.iua);
201 V3D_WRITE(V3D_TFU_IOA, job->args.ioa);
202 V3D_WRITE(V3D_TFU_IOS, job->args.ios);
203 V3D_WRITE(V3D_TFU_COEF0, job->args.coef[0]);
204 if (job->args.coef[0] & V3D_TFU_COEF0_USECOEF) {
205 V3D_WRITE(V3D_TFU_COEF1, job->args.coef[1]);
206 V3D_WRITE(V3D_TFU_COEF2, job->args.coef[2]);
207 V3D_WRITE(V3D_TFU_COEF3, job->args.coef[3]);
208 }
209 /* ICFG kicks off the job. */
210 V3D_WRITE(V3D_TFU_ICFG, job->args.icfg | V3D_TFU_ICFG_IOC);
211
212 return fence;
213 }
214
215 static struct dma_fence *
v3d_csd_job_run(struct drm_sched_job * sched_job)216 v3d_csd_job_run(struct drm_sched_job *sched_job)
217 {
218 struct v3d_csd_job *job = to_csd_job(sched_job);
219 struct v3d_dev *v3d = job->base.v3d;
220 struct drm_device *dev = &v3d->drm;
221 struct dma_fence *fence;
222 int i;
223
224 if (unlikely(job->base.base.s_fence->finished.error))
225 return NULL;
226
227 v3d->csd_job = job;
228
229 v3d_invalidate_caches(v3d);
230
231 fence = v3d_fence_create(v3d, V3D_CSD);
232 if (IS_ERR(fence))
233 return NULL;
234
235 if (job->base.irq_fence)
236 dma_fence_put(job->base.irq_fence);
237 job->base.irq_fence = dma_fence_get(fence);
238
239 trace_v3d_submit_csd(dev, to_v3d_fence(fence)->seqno);
240
241 v3d_switch_perfmon(v3d, &job->base);
242
243 for (i = 1; i <= 6; i++)
244 V3D_CORE_WRITE(0, V3D_CSD_QUEUED_CFG0 + 4 * i, job->args.cfg[i]);
245 /* CFG0 write kicks off the job. */
246 V3D_CORE_WRITE(0, V3D_CSD_QUEUED_CFG0, job->args.cfg[0]);
247
248 return fence;
249 }
250
251 static struct dma_fence *
v3d_cache_clean_job_run(struct drm_sched_job * sched_job)252 v3d_cache_clean_job_run(struct drm_sched_job *sched_job)
253 {
254 struct v3d_job *job = to_v3d_job(sched_job);
255 struct v3d_dev *v3d = job->v3d;
256
257 v3d_clean_caches(v3d);
258
259 return NULL;
260 }
261
262 static enum drm_gpu_sched_stat
v3d_gpu_reset_for_timeout(struct v3d_dev * v3d,struct drm_sched_job * sched_job)263 v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
264 {
265 enum v3d_queue q;
266
267 mutex_lock(&v3d->reset_lock);
268
269 /* block scheduler */
270 for (q = 0; q < V3D_MAX_QUEUES; q++)
271 drm_sched_stop(&v3d->queue[q].sched, sched_job);
272
273 if (sched_job)
274 drm_sched_increase_karma(sched_job);
275
276 /* get the GPU back into the init state */
277 v3d_reset(v3d);
278
279 for (q = 0; q < V3D_MAX_QUEUES; q++)
280 drm_sched_resubmit_jobs(&v3d->queue[q].sched);
281
282 /* Unblock schedulers and restart their jobs. */
283 for (q = 0; q < V3D_MAX_QUEUES; q++) {
284 drm_sched_start(&v3d->queue[q].sched, true);
285 }
286
287 mutex_unlock(&v3d->reset_lock);
288
289 return DRM_GPU_SCHED_STAT_NOMINAL;
290 }
291
292 /* If the current address or return address have changed, then the GPU
293 * has probably made progress and we should delay the reset. This
294 * could fail if the GPU got in an infinite loop in the CL, but that
295 * is pretty unlikely outside of an i-g-t testcase.
296 */
297 static enum drm_gpu_sched_stat
v3d_cl_job_timedout(struct drm_sched_job * sched_job,enum v3d_queue q,u32 * timedout_ctca,u32 * timedout_ctra)298 v3d_cl_job_timedout(struct drm_sched_job *sched_job, enum v3d_queue q,
299 u32 *timedout_ctca, u32 *timedout_ctra)
300 {
301 struct v3d_job *job = to_v3d_job(sched_job);
302 struct v3d_dev *v3d = job->v3d;
303 u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(q));
304 u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(q));
305
306 if (*timedout_ctca != ctca || *timedout_ctra != ctra) {
307 *timedout_ctca = ctca;
308 *timedout_ctra = ctra;
309 return DRM_GPU_SCHED_STAT_NOMINAL;
310 }
311
312 return v3d_gpu_reset_for_timeout(v3d, sched_job);
313 }
314
315 static enum drm_gpu_sched_stat
v3d_bin_job_timedout(struct drm_sched_job * sched_job)316 v3d_bin_job_timedout(struct drm_sched_job *sched_job)
317 {
318 struct v3d_bin_job *job = to_bin_job(sched_job);
319
320 return v3d_cl_job_timedout(sched_job, V3D_BIN,
321 &job->timedout_ctca, &job->timedout_ctra);
322 }
323
324 static enum drm_gpu_sched_stat
v3d_render_job_timedout(struct drm_sched_job * sched_job)325 v3d_render_job_timedout(struct drm_sched_job *sched_job)
326 {
327 struct v3d_render_job *job = to_render_job(sched_job);
328
329 return v3d_cl_job_timedout(sched_job, V3D_RENDER,
330 &job->timedout_ctca, &job->timedout_ctra);
331 }
332
333 static enum drm_gpu_sched_stat
v3d_generic_job_timedout(struct drm_sched_job * sched_job)334 v3d_generic_job_timedout(struct drm_sched_job *sched_job)
335 {
336 struct v3d_job *job = to_v3d_job(sched_job);
337
338 return v3d_gpu_reset_for_timeout(job->v3d, sched_job);
339 }
340
341 static enum drm_gpu_sched_stat
v3d_csd_job_timedout(struct drm_sched_job * sched_job)342 v3d_csd_job_timedout(struct drm_sched_job *sched_job)
343 {
344 struct v3d_csd_job *job = to_csd_job(sched_job);
345 struct v3d_dev *v3d = job->base.v3d;
346 u32 batches = V3D_CORE_READ(0, V3D_CSD_CURRENT_CFG4);
347
348 /* If we've made progress, skip reset and let the timer get
349 * rearmed.
350 */
351 if (job->timedout_batches != batches) {
352 job->timedout_batches = batches;
353 return DRM_GPU_SCHED_STAT_NOMINAL;
354 }
355
356 return v3d_gpu_reset_for_timeout(v3d, sched_job);
357 }
358
359 static const struct drm_sched_backend_ops v3d_bin_sched_ops = {
360 .run_job = v3d_bin_job_run,
361 .timedout_job = v3d_bin_job_timedout,
362 .free_job = v3d_sched_job_free,
363 };
364
365 static const struct drm_sched_backend_ops v3d_render_sched_ops = {
366 .run_job = v3d_render_job_run,
367 .timedout_job = v3d_render_job_timedout,
368 .free_job = v3d_sched_job_free,
369 };
370
371 static const struct drm_sched_backend_ops v3d_tfu_sched_ops = {
372 .run_job = v3d_tfu_job_run,
373 .timedout_job = v3d_generic_job_timedout,
374 .free_job = v3d_sched_job_free,
375 };
376
377 static const struct drm_sched_backend_ops v3d_csd_sched_ops = {
378 .run_job = v3d_csd_job_run,
379 .timedout_job = v3d_csd_job_timedout,
380 .free_job = v3d_sched_job_free
381 };
382
383 static const struct drm_sched_backend_ops v3d_cache_clean_sched_ops = {
384 .run_job = v3d_cache_clean_job_run,
385 .timedout_job = v3d_generic_job_timedout,
386 .free_job = v3d_sched_job_free
387 };
388
389 int
v3d_sched_init(struct v3d_dev * v3d)390 v3d_sched_init(struct v3d_dev *v3d)
391 {
392 int hw_jobs_limit = 1;
393 int job_hang_limit = 0;
394 int hang_limit_ms = 500;
395 int ret;
396
397 ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
398 &v3d_bin_sched_ops,
399 hw_jobs_limit, job_hang_limit,
400 msecs_to_jiffies(hang_limit_ms), NULL,
401 NULL, "v3d_bin", v3d->drm.dev);
402 if (ret)
403 return ret;
404
405 ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
406 &v3d_render_sched_ops,
407 hw_jobs_limit, job_hang_limit,
408 msecs_to_jiffies(hang_limit_ms), NULL,
409 NULL, "v3d_render", v3d->drm.dev);
410 if (ret)
411 goto fail;
412
413 ret = drm_sched_init(&v3d->queue[V3D_TFU].sched,
414 &v3d_tfu_sched_ops,
415 hw_jobs_limit, job_hang_limit,
416 msecs_to_jiffies(hang_limit_ms), NULL,
417 NULL, "v3d_tfu", v3d->drm.dev);
418 if (ret)
419 goto fail;
420
421 if (v3d_has_csd(v3d)) {
422 ret = drm_sched_init(&v3d->queue[V3D_CSD].sched,
423 &v3d_csd_sched_ops,
424 hw_jobs_limit, job_hang_limit,
425 msecs_to_jiffies(hang_limit_ms), NULL,
426 NULL, "v3d_csd", v3d->drm.dev);
427 if (ret)
428 goto fail;
429
430 ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched,
431 &v3d_cache_clean_sched_ops,
432 hw_jobs_limit, job_hang_limit,
433 msecs_to_jiffies(hang_limit_ms), NULL,
434 NULL, "v3d_cache_clean", v3d->drm.dev);
435 if (ret)
436 goto fail;
437 }
438
439 return 0;
440
441 fail:
442 v3d_sched_fini(v3d);
443 return ret;
444 }
445
446 void
v3d_sched_fini(struct v3d_dev * v3d)447 v3d_sched_fini(struct v3d_dev *v3d)
448 {
449 enum v3d_queue q;
450
451 for (q = 0; q < V3D_MAX_QUEUES; q++) {
452 if (v3d->queue[q].sched.ready)
453 drm_sched_fini(&v3d->queue[q].sched);
454 }
455 }
456