1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Freescale i.MX28 DIGCTL Register Definitions 4 * 5 * Copyright (C) 2012 Robert Delien <robert@delien.nl> 6 */ 7 8 #ifndef __MX28_REGS_DIGCTL_H__ 9 #define __MX28_REGS_DIGCTL_H__ 10 11 #include <asm/mach-imx/regs-common.h> 12 13 #ifndef __ASSEMBLY__ 14 struct mxs_digctl_regs { 15 mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ 16 mxs_reg_32(hw_digctl_status) /* 0x010 */ 17 mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ 18 mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ 19 mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ 20 mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ 21 uint32_t hw_digctl_writeonce; /* 0x060 */ 22 uint32_t reserved_writeonce[3]; 23 mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ 24 mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ 25 uint32_t hw_digctl_entropy; /* 0x090 */ 26 uint32_t reserved_entropy[3]; 27 uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ 28 uint32_t reserved_entropy_latched[3]; 29 30 uint32_t reserved1[4]; 31 32 mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ 33 uint32_t hw_digctl_dbgrd; /* 0x0d0 */ 34 uint32_t reserved_hw_digctl_dbgrd[3]; 35 uint32_t hw_digctl_dbg; /* 0x0e0 */ 36 uint32_t reserved_hw_digctl_dbg[3]; 37 38 uint32_t reserved2[4]; 39 40 mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ 41 mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ 42 mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ 43 mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ 44 mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ 45 mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ 46 mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ 47 mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ 48 mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ 49 mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ 50 mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ 51 mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ 52 mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ 53 mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ 54 mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ 55 56 uint32_t reserved3[36]; 57 58 uint32_t hw_digctl_scratch0; /* 0x280 */ 59 uint32_t reserved_hw_digctl_scratch0[3]; 60 uint32_t hw_digctl_scratch1; /* 0x290 */ 61 uint32_t reserved_hw_digctl_scratch1[3]; 62 uint32_t hw_digctl_armcache; /* 0x2a0 */ 63 uint32_t reserved_hw_digctl_armcache[3]; 64 mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ 65 uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ 66 uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; 67 uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ 68 uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; 69 uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ 70 uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; 71 uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ 72 uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; 73 uint32_t hw_digctl_fsl; /* 0x300 */ 74 uint32_t reserved_hw_digctl_fsl[3]; 75 uint32_t hw_digctl_chipid; /* 0x310 */ 76 uint32_t reserved_hw_digctl_chipid[3]; 77 78 uint32_t reserved4[4]; 79 80 uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ 81 uint32_t reserved_hw_digctl_ahb_stats_select[3]; 82 83 uint32_t reserved5[12]; 84 85 uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ 86 uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; 87 uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ 88 uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; 89 uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ 90 uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; 91 uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ 92 uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; 93 uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ 94 uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; 95 uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ 96 uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; 97 uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ 98 uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; 99 uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ 100 uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; 101 uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ 102 uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; 103 104 uint32_t reserved6[64]; 105 106 uint32_t hw_digctl_mpte0_loc; /* 0x500 */ 107 uint32_t reserved_hw_digctl_mpte0_loc[3]; 108 uint32_t hw_digctl_mpte1_loc; /* 0x510 */ 109 uint32_t reserved_hw_digctl_mpte1_loc[3]; 110 uint32_t hw_digctl_mpte2_loc; /* 0x520 */ 111 uint32_t reserved_hw_digctl_mpte2_loc[3]; 112 uint32_t hw_digctl_mpte3_loc; /* 0x530 */ 113 uint32_t reserved_hw_digctl_mpte3_loc[3]; 114 uint32_t hw_digctl_mpte4_loc; /* 0x540 */ 115 uint32_t reserved_hw_digctl_mpte4_loc[3]; 116 uint32_t hw_digctl_mpte5_loc; /* 0x550 */ 117 uint32_t reserved_hw_digctl_mpte5_loc[3]; 118 uint32_t hw_digctl_mpte6_loc; /* 0x560 */ 119 uint32_t reserved_hw_digctl_mpte6_loc[3]; 120 uint32_t hw_digctl_mpte7_loc; /* 0x570 */ 121 uint32_t reserved_hw_digctl_mpte7_loc[3]; 122 uint32_t hw_digctl_mpte8_loc; /* 0x580 */ 123 uint32_t reserved_hw_digctl_mpte8_loc[3]; 124 uint32_t hw_digctl_mpte9_loc; /* 0x590 */ 125 uint32_t reserved_hw_digctl_mpte9_loc[3]; 126 uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ 127 uint32_t reserved_hw_digctl_mpte10_loc[3]; 128 uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ 129 uint32_t reserved_hw_digctl_mpte11_loc[3]; 130 uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ 131 uint32_t reserved_hw_digctl_mpte12_loc[3]; 132 uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ 133 uint32_t reserved_hw_digctl_mpte13_loc[3]; 134 uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ 135 uint32_t reserved_hw_digctl_mpte14_loc[3]; 136 uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ 137 uint32_t reserved_hw_digctl_mpte15_loc[3]; 138 }; 139 #endif 140 141 /* Product code identification */ 142 #define HW_DIGCTL_CHIPID_MASK (0xffff << 16) 143 #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) 144 #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) 145 146 #endif /* __MX28_REGS_DIGCTL_H__ */ 147