1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HyperV Detection code.
4 *
5 * Copyright (C) 2010, Novell, Inc.
6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com>
7 */
8
9 #include <linux/types.h>
10 #include <linux/time.h>
11 #include <linux/clocksource.h>
12 #include <linux/init.h>
13 #include <linux/export.h>
14 #include <linux/hardirq.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kexec.h>
19 #include <linux/i8253.h>
20 #include <linux/random.h>
21 #include <asm/processor.h>
22 #include <asm/hypervisor.h>
23 #include <asm/hyperv-tlfs.h>
24 #include <asm/mshyperv.h>
25 #include <asm/desc.h>
26 #include <asm/idtentry.h>
27 #include <asm/irq_regs.h>
28 #include <asm/i8259.h>
29 #include <asm/apic.h>
30 #include <asm/timer.h>
31 #include <asm/reboot.h>
32 #include <asm/nmi.h>
33 #include <clocksource/hyperv_timer.h>
34 #include <asm/numa.h>
35 #include <asm/svm.h>
36
37 /* Is Linux running as the root partition? */
38 bool hv_root_partition;
39 /* Is Linux running on nested Microsoft Hypervisor */
40 bool hv_nested;
41 struct ms_hyperv_info ms_hyperv;
42
43 /* Used in modules via hv_do_hypercall(): see arch/x86/include/asm/mshyperv.h */
44 bool hyperv_paravisor_present __ro_after_init;
45 EXPORT_SYMBOL_GPL(hyperv_paravisor_present);
46
47 #if IS_ENABLED(CONFIG_HYPERV)
hv_get_nested_reg(unsigned int reg)48 static inline unsigned int hv_get_nested_reg(unsigned int reg)
49 {
50 if (hv_is_sint_reg(reg))
51 return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0;
52
53 switch (reg) {
54 case HV_REGISTER_SIMP:
55 return HV_REGISTER_NESTED_SIMP;
56 case HV_REGISTER_SIEFP:
57 return HV_REGISTER_NESTED_SIEFP;
58 case HV_REGISTER_SVERSION:
59 return HV_REGISTER_NESTED_SVERSION;
60 case HV_REGISTER_SCONTROL:
61 return HV_REGISTER_NESTED_SCONTROL;
62 case HV_REGISTER_EOM:
63 return HV_REGISTER_NESTED_EOM;
64 default:
65 return reg;
66 }
67 }
68
hv_get_non_nested_register(unsigned int reg)69 u64 hv_get_non_nested_register(unsigned int reg)
70 {
71 u64 value;
72
73 if (hv_is_synic_reg(reg) && ms_hyperv.paravisor_present)
74 hv_ivm_msr_read(reg, &value);
75 else
76 rdmsrl(reg, value);
77 return value;
78 }
79 EXPORT_SYMBOL_GPL(hv_get_non_nested_register);
80
hv_set_non_nested_register(unsigned int reg,u64 value)81 void hv_set_non_nested_register(unsigned int reg, u64 value)
82 {
83 if (hv_is_synic_reg(reg) && ms_hyperv.paravisor_present) {
84 hv_ivm_msr_write(reg, value);
85
86 /* Write proxy bit via wrmsl instruction */
87 if (hv_is_sint_reg(reg))
88 wrmsrl(reg, value | 1 << 20);
89 } else {
90 wrmsrl(reg, value);
91 }
92 }
93 EXPORT_SYMBOL_GPL(hv_set_non_nested_register);
94
hv_get_register(unsigned int reg)95 u64 hv_get_register(unsigned int reg)
96 {
97 if (hv_nested)
98 reg = hv_get_nested_reg(reg);
99
100 return hv_get_non_nested_register(reg);
101 }
102 EXPORT_SYMBOL_GPL(hv_get_register);
103
hv_set_register(unsigned int reg,u64 value)104 void hv_set_register(unsigned int reg, u64 value)
105 {
106 if (hv_nested)
107 reg = hv_get_nested_reg(reg);
108
109 hv_set_non_nested_register(reg, value);
110 }
111 EXPORT_SYMBOL_GPL(hv_set_register);
112
113 static void (*vmbus_handler)(void);
114 static void (*hv_stimer0_handler)(void);
115 static void (*hv_kexec_handler)(void);
116 static void (*hv_crash_handler)(struct pt_regs *regs);
117
DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)118 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)
119 {
120 struct pt_regs *old_regs = set_irq_regs(regs);
121
122 inc_irq_stat(irq_hv_callback_count);
123 if (vmbus_handler)
124 vmbus_handler();
125
126 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED)
127 apic_eoi();
128
129 set_irq_regs(old_regs);
130 }
131
hv_setup_vmbus_handler(void (* handler)(void))132 void hv_setup_vmbus_handler(void (*handler)(void))
133 {
134 vmbus_handler = handler;
135 }
136
hv_remove_vmbus_handler(void)137 void hv_remove_vmbus_handler(void)
138 {
139 /* We have no way to deallocate the interrupt gate */
140 vmbus_handler = NULL;
141 }
142
143 /*
144 * Routines to do per-architecture handling of stimer0
145 * interrupts when in Direct Mode
146 */
DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)147 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)
148 {
149 struct pt_regs *old_regs = set_irq_regs(regs);
150
151 inc_irq_stat(hyperv_stimer0_count);
152 if (hv_stimer0_handler)
153 hv_stimer0_handler();
154 add_interrupt_randomness(HYPERV_STIMER0_VECTOR);
155 apic_eoi();
156
157 set_irq_regs(old_regs);
158 }
159
160 /* For x86/x64, override weak placeholders in hyperv_timer.c */
hv_setup_stimer0_handler(void (* handler)(void))161 void hv_setup_stimer0_handler(void (*handler)(void))
162 {
163 hv_stimer0_handler = handler;
164 }
165
hv_remove_stimer0_handler(void)166 void hv_remove_stimer0_handler(void)
167 {
168 /* We have no way to deallocate the interrupt gate */
169 hv_stimer0_handler = NULL;
170 }
171
hv_setup_kexec_handler(void (* handler)(void))172 void hv_setup_kexec_handler(void (*handler)(void))
173 {
174 hv_kexec_handler = handler;
175 }
176
hv_remove_kexec_handler(void)177 void hv_remove_kexec_handler(void)
178 {
179 hv_kexec_handler = NULL;
180 }
181
hv_setup_crash_handler(void (* handler)(struct pt_regs * regs))182 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs))
183 {
184 hv_crash_handler = handler;
185 }
186
hv_remove_crash_handler(void)187 void hv_remove_crash_handler(void)
188 {
189 hv_crash_handler = NULL;
190 }
191
192 #ifdef CONFIG_KEXEC_CORE
hv_machine_shutdown(void)193 static void hv_machine_shutdown(void)
194 {
195 if (kexec_in_progress && hv_kexec_handler)
196 hv_kexec_handler();
197
198 /*
199 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
200 * corrupts the old VP Assist Pages and can crash the kexec kernel.
201 */
202 if (kexec_in_progress)
203 cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE);
204
205 /* The function calls stop_other_cpus(). */
206 native_machine_shutdown();
207
208 /* Disable the hypercall page when there is only 1 active CPU. */
209 if (kexec_in_progress)
210 hyperv_cleanup();
211 }
212
hv_machine_crash_shutdown(struct pt_regs * regs)213 static void hv_machine_crash_shutdown(struct pt_regs *regs)
214 {
215 if (hv_crash_handler)
216 hv_crash_handler(regs);
217
218 /* The function calls crash_smp_send_stop(). */
219 native_machine_crash_shutdown(regs);
220
221 /* Disable the hypercall page when there is only 1 active CPU. */
222 hyperv_cleanup();
223 }
224 #endif /* CONFIG_KEXEC_CORE */
225 #endif /* CONFIG_HYPERV */
226
ms_hyperv_platform(void)227 static uint32_t __init ms_hyperv_platform(void)
228 {
229 u32 eax;
230 u32 hyp_signature[3];
231
232 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
233 return 0;
234
235 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS,
236 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]);
237
238 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX ||
239 memcmp("Microsoft Hv", hyp_signature, 12))
240 return 0;
241
242 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */
243 eax = cpuid_eax(HYPERV_CPUID_FEATURES);
244 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) {
245 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n");
246 return 0;
247 }
248 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) {
249 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n");
250 return 0;
251 }
252
253 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
254 }
255
256 #ifdef CONFIG_X86_LOCAL_APIC
257 /*
258 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes
259 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle
260 * unknown NMI on the first CPU which gets it.
261 */
hv_nmi_unknown(unsigned int val,struct pt_regs * regs)262 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
263 {
264 static atomic_t nmi_cpu = ATOMIC_INIT(-1);
265
266 if (!unknown_nmi_panic)
267 return NMI_DONE;
268
269 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1)
270 return NMI_HANDLED;
271
272 return NMI_DONE;
273 }
274 #endif
275
hv_get_tsc_khz(void)276 static unsigned long hv_get_tsc_khz(void)
277 {
278 unsigned long freq;
279
280 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
281
282 return freq / 1000;
283 }
284
285 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV)
hv_smp_prepare_boot_cpu(void)286 static void __init hv_smp_prepare_boot_cpu(void)
287 {
288 native_smp_prepare_boot_cpu();
289 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS)
290 hv_init_spinlocks();
291 #endif
292 }
293
hv_smp_prepare_cpus(unsigned int max_cpus)294 static void __init hv_smp_prepare_cpus(unsigned int max_cpus)
295 {
296 #ifdef CONFIG_X86_64
297 int i;
298 int ret;
299 #endif
300
301 native_smp_prepare_cpus(max_cpus);
302
303 /*
304 * Override wakeup_secondary_cpu_64 callback for SEV-SNP
305 * enlightened guest.
306 */
307 if (!ms_hyperv.paravisor_present && hv_isolation_type_snp()) {
308 apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap;
309 return;
310 }
311
312 #ifdef CONFIG_X86_64
313 for_each_present_cpu(i) {
314 if (i == 0)
315 continue;
316 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i));
317 BUG_ON(ret);
318 }
319
320 for_each_present_cpu(i) {
321 if (i == 0)
322 continue;
323 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i);
324 BUG_ON(ret);
325 }
326 #endif
327 }
328 #endif
329
330 /*
331 * When a fully enlightened TDX VM runs on Hyper-V, the firmware sets the
332 * HW_REDUCED flag: refer to acpi_tb_create_local_fadt(). Consequently ttyS0
333 * interrupts can't work because request_irq() -> ... -> irq_to_desc() returns
334 * NULL for ttyS0. This happens because mp_config_acpi_legacy_irqs() sees a
335 * nr_legacy_irqs() of 0, so it doesn't initialize the array 'mp_irqs[]', and
336 * later setup_IO_APIC_irqs() -> find_irq_entry() fails to find the legacy irqs
337 * from the array and hence doesn't create the necessary irq description info.
338 *
339 * Clone arch/x86/kernel/acpi/boot.c: acpi_generic_reduced_hw_init() here,
340 * except don't change 'legacy_pic', which keeps its default value
341 * 'default_legacy_pic'. This way, mp_config_acpi_legacy_irqs() sees a non-zero
342 * nr_legacy_irqs() and eventually serial console interrupts works properly.
343 */
reduced_hw_init(void)344 static void __init reduced_hw_init(void)
345 {
346 x86_init.timers.timer_init = x86_init_noop;
347 x86_init.irqs.pre_vector_init = x86_init_noop;
348 }
349
ms_hyperv_init_platform(void)350 static void __init ms_hyperv_init_platform(void)
351 {
352 int hv_max_functions_eax;
353 int hv_host_info_eax;
354 int hv_host_info_ebx;
355 int hv_host_info_ecx;
356 int hv_host_info_edx;
357
358 #ifdef CONFIG_PARAVIRT
359 pv_info.name = "Hyper-V";
360 #endif
361
362 /*
363 * Extract the features and hints
364 */
365 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES);
366 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES);
367 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES);
368 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO);
369
370 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS);
371
372 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n",
373 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints,
374 ms_hyperv.misc_features);
375
376 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS);
377 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS);
378
379 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n",
380 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index);
381
382 /*
383 * Check CPU management privilege.
384 *
385 * To mirror what Windows does we should extract CPU management
386 * features and use the ReservedIdentityBit to detect if Linux is the
387 * root partition. But that requires negotiating CPU management
388 * interface (a process to be finalized). For now, use the privilege
389 * flag as the indicator for running as root.
390 *
391 * Hyper-V should never specify running as root and as a Confidential
392 * VM. But to protect against a compromised/malicious Hyper-V trying
393 * to exploit root behavior to expose Confidential VM memory, ignore
394 * the root partition setting if also a Confidential VM.
395 */
396 if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) &&
397 !(ms_hyperv.priv_high & HV_ISOLATION)) {
398 hv_root_partition = true;
399 pr_info("Hyper-V: running as root partition\n");
400 }
401
402 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) {
403 hv_nested = true;
404 pr_info("Hyper-V: running on a nested hypervisor\n");
405 }
406
407 /*
408 * Extract host information.
409 */
410 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) {
411 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION);
412 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION);
413 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION);
414 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION);
415
416 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n",
417 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF,
418 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF,
419 hv_host_info_ecx, hv_host_info_edx >> 24);
420 }
421
422 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
423 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
424 x86_platform.calibrate_tsc = hv_get_tsc_khz;
425 x86_platform.calibrate_cpu = hv_get_tsc_khz;
426 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
427 }
428
429 if (ms_hyperv.priv_high & HV_ISOLATION) {
430 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG);
431 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG);
432
433 if (ms_hyperv.shared_gpa_boundary_active)
434 ms_hyperv.shared_gpa_boundary =
435 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits);
436
437 hyperv_paravisor_present = !!ms_hyperv.paravisor_present;
438
439 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n",
440 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b);
441
442
443 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) {
444 static_branch_enable(&isolation_type_snp);
445 } else if (hv_get_isolation_type() == HV_ISOLATION_TYPE_TDX) {
446 static_branch_enable(&isolation_type_tdx);
447
448 /* A TDX VM must use x2APIC and doesn't use lazy EOI. */
449 ms_hyperv.hints &= ~HV_X64_APIC_ACCESS_RECOMMENDED;
450
451 if (!ms_hyperv.paravisor_present) {
452 /* To be supported: more work is required. */
453 ms_hyperv.features &= ~HV_MSR_REFERENCE_TSC_AVAILABLE;
454
455 /* HV_REGISTER_CRASH_CTL is unsupported. */
456 ms_hyperv.misc_features &= ~HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE;
457
458 /* Don't trust Hyper-V's TLB-flushing hypercalls. */
459 ms_hyperv.hints &= ~HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED;
460
461 x86_init.acpi.reduced_hw_early_init = reduced_hw_init;
462 }
463 }
464 }
465
466 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) {
467 ms_hyperv.nested_features =
468 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES);
469 pr_info("Hyper-V: Nested features: 0x%x\n",
470 ms_hyperv.nested_features);
471 }
472
473 #ifdef CONFIG_X86_LOCAL_APIC
474 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
475 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
476 /*
477 * Get the APIC frequency.
478 */
479 u64 hv_lapic_frequency;
480
481 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
482 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
483 lapic_timer_period = hv_lapic_frequency;
484 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
485 lapic_timer_period);
486 }
487
488 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST,
489 "hv_nmi_unknown");
490 #endif
491
492 #ifdef CONFIG_X86_IO_APIC
493 no_timer_check = 1;
494 #endif
495
496 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE)
497 machine_ops.shutdown = hv_machine_shutdown;
498 machine_ops.crash_shutdown = hv_machine_crash_shutdown;
499 #endif
500 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
501 /*
502 * Writing to synthetic MSR 0x40000118 updates/changes the
503 * guest visible CPUIDs. Setting bit 0 of this MSR enables
504 * guests to report invariant TSC feature through CPUID
505 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
506 * early_init_intel() where this bit is examined. The
507 * setting of this MSR bit should happen before init_intel()
508 * is called.
509 */
510 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC);
511 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
512 }
513
514 /*
515 * Generation 2 instances don't support reading the NMI status from
516 * 0x61 port.
517 */
518 if (efi_enabled(EFI_BOOT))
519 x86_platform.get_nmi_reason = hv_get_nmi_reason;
520
521 /*
522 * Hyper-V VMs have a PIT emulation quirk such that zeroing the
523 * counter register during PIT shutdown restarts the PIT. So it
524 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter
525 * to false tells pit_shutdown() not to zero the counter so that
526 * the PIT really is shutdown. Generation 2 VMs don't have a PIT,
527 * and setting this value has no effect.
528 */
529 i8253_clear_counter_on_shutdown = false;
530
531 #if IS_ENABLED(CONFIG_HYPERV)
532 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) ||
533 ms_hyperv.paravisor_present)
534 hv_vtom_init();
535 /*
536 * Setup the hook to get control post apic initialization.
537 */
538 x86_platform.apic_post_init = hyperv_init;
539 hyperv_setup_mmu_ops();
540 /* Setup the IDT for hypervisor callback */
541 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback);
542
543 /* Setup the IDT for reenlightenment notifications */
544 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) {
545 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR,
546 asm_sysvec_hyperv_reenlightenment);
547 }
548
549 /* Setup the IDT for stimer0 */
550 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) {
551 alloc_intr_gate(HYPERV_STIMER0_VECTOR,
552 asm_sysvec_hyperv_stimer0);
553 }
554
555 # ifdef CONFIG_SMP
556 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu;
557 if (hv_root_partition ||
558 (!ms_hyperv.paravisor_present && hv_isolation_type_snp()))
559 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus;
560 # endif
561
562 /*
563 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
564 * set x2apic destination mode to physical mode when x2apic is available
565 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs
566 * have 8-bit APIC id.
567 */
568 # ifdef CONFIG_X86_X2APIC
569 if (x2apic_supported())
570 x2apic_phys = 1;
571 # endif
572
573 /* Register Hyper-V specific clocksource */
574 hv_init_clocksource();
575 hv_vtl_init_platform();
576 #endif
577 /*
578 * TSC should be marked as unstable only after Hyper-V
579 * clocksource has been initialized. This ensures that the
580 * stability of the sched_clock is not altered.
581 */
582 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
583 mark_tsc_unstable("running on Hyper-V");
584
585 hardlockup_detector_disable();
586 }
587
ms_hyperv_x2apic_available(void)588 static bool __init ms_hyperv_x2apic_available(void)
589 {
590 return x2apic_supported();
591 }
592
593 /*
594 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping()
595 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the
596 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg().
597 *
598 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which
599 * (logically) generates MSIs directly to the system APIC irq domain.
600 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the
601 * pci-hyperv host bridge.
602 *
603 * Note: for a Hyper-V root partition, this will always return false.
604 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by
605 * default, they are implemented as intercepts by the Windows Hyper-V stack.
606 * Even a nested root partition (L2 root) will not get them because the
607 * nested (L1) hypervisor filters them out.
608 */
ms_hyperv_msi_ext_dest_id(void)609 static bool __init ms_hyperv_msi_ext_dest_id(void)
610 {
611 u32 eax;
612
613 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE);
614 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE)
615 return false;
616
617 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES);
618 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE;
619 }
620
621 #ifdef CONFIG_AMD_MEM_ENCRYPT
hv_sev_es_hcall_prepare(struct ghcb * ghcb,struct pt_regs * regs)622 static void hv_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs)
623 {
624 /* RAX and CPL are already in the GHCB */
625 ghcb_set_rcx(ghcb, regs->cx);
626 ghcb_set_rdx(ghcb, regs->dx);
627 ghcb_set_r8(ghcb, regs->r8);
628 }
629
hv_sev_es_hcall_finish(struct ghcb * ghcb,struct pt_regs * regs)630 static bool hv_sev_es_hcall_finish(struct ghcb *ghcb, struct pt_regs *regs)
631 {
632 /* No checking of the return state needed */
633 return true;
634 }
635 #endif
636
637 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
638 .name = "Microsoft Hyper-V",
639 .detect = ms_hyperv_platform,
640 .type = X86_HYPER_MS_HYPERV,
641 .init.x2apic_available = ms_hyperv_x2apic_available,
642 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id,
643 .init.init_platform = ms_hyperv_init_platform,
644 #ifdef CONFIG_AMD_MEM_ENCRYPT
645 .runtime.sev_es_hcall_prepare = hv_sev_es_hcall_prepare,
646 .runtime.sev_es_hcall_finish = hv_sev_es_hcall_finish,
647 #endif
648 };
649