1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 4 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 5 */ 6 7 #ifndef _ENIC_H_ 8 #define _ENIC_H_ 9 10 #include "vnic_enet.h" 11 #include "vnic_dev.h" 12 #include "vnic_wq.h" 13 #include "vnic_rq.h" 14 #include "vnic_cq.h" 15 #include "vnic_intr.h" 16 #include "vnic_stats.h" 17 #include "vnic_nic.h" 18 #include "vnic_rss.h" 19 #include <linux/irq.h> 20 21 #define DRV_NAME "enic" 22 #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 23 24 #define ENIC_BARS_MAX 6 25 26 #define ENIC_WQ_MAX 8 27 #define ENIC_RQ_MAX 8 28 #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 29 #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 30 31 #define ENIC_WQ_NAPI_BUDGET 256 32 33 #define ENIC_AIC_LARGE_PKT_DIFF 3 34 35 struct enic_msix_entry { 36 int requested; 37 char devname[IFNAMSIZ + 8]; 38 irqreturn_t (*isr)(int, void *); 39 void *devid; 40 cpumask_var_t affinity_mask; 41 }; 42 43 /* Store only the lower range. Higher range is given by fw. */ 44 struct enic_intr_mod_range { 45 u32 small_pkt_range_start; 46 u32 large_pkt_range_start; 47 }; 48 49 struct enic_intr_mod_table { 50 u32 rx_rate; 51 u32 range_percent; 52 }; 53 54 #define ENIC_MAX_LINK_SPEEDS 3 55 #define ENIC_LINK_SPEED_10G 10000 56 #define ENIC_LINK_SPEED_4G 4000 57 #define ENIC_LINK_40G_INDEX 2 58 #define ENIC_LINK_10G_INDEX 1 59 #define ENIC_LINK_4G_INDEX 0 60 #define ENIC_RX_COALESCE_RANGE_END 125 61 #define ENIC_AIC_TS_BREAK 100 62 63 struct enic_rx_coal { 64 u32 small_pkt_range_start; 65 u32 large_pkt_range_start; 66 u32 range_end; 67 u32 use_adaptive_rx_coalesce; 68 }; 69 70 /* priv_flags */ 71 #define ENIC_SRIOV_ENABLED (1 << 0) 72 73 /* enic port profile set flags */ 74 #define ENIC_PORT_REQUEST_APPLIED (1 << 0) 75 #define ENIC_SET_REQUEST (1 << 1) 76 #define ENIC_SET_NAME (1 << 2) 77 #define ENIC_SET_INSTANCE (1 << 3) 78 #define ENIC_SET_HOST (1 << 4) 79 80 struct enic_port_profile { 81 u32 set; 82 u8 request; 83 char name[PORT_PROFILE_MAX]; 84 u8 instance_uuid[PORT_UUID_MAX]; 85 u8 host_uuid[PORT_UUID_MAX]; 86 u8 vf_mac[ETH_ALEN]; 87 u8 mac_addr[ETH_ALEN]; 88 }; 89 90 /* enic_rfs_fltr_node - rfs filter node in hash table 91 * @@keys: IPv4 5 tuple 92 * @flow_id: flow_id of clsf filter provided by kernel 93 * @fltr_id: filter id of clsf filter returned by adaptor 94 * @rq_id: desired rq index 95 * @node: hlist_node 96 */ 97 struct enic_rfs_fltr_node { 98 struct flow_keys keys; 99 u32 flow_id; 100 u16 fltr_id; 101 u16 rq_id; 102 struct hlist_node node; 103 }; 104 105 /* enic_rfs_flw_tbl - rfs flow table 106 * @max: Maximum number of filters vNIC supports 107 * @free: Number of free filters available 108 * @toclean: hash table index to clean next 109 * @ht_head: hash table list head 110 * @lock: spin lock 111 * @rfs_may_expire: timer function for enic_rps_may_expire_flow 112 */ 113 struct enic_rfs_flw_tbl { 114 u16 max; 115 int free; 116 117 #define ENIC_RFS_FLW_BITSHIFT (10) 118 #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1) 119 u16 toclean:ENIC_RFS_FLW_BITSHIFT; 120 struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT]; 121 spinlock_t lock; 122 struct timer_list rfs_may_expire; 123 }; 124 125 struct vxlan_offload { 126 u16 vxlan_udp_port_number; 127 u8 patch_level; 128 u8 flags; 129 }; 130 131 /* Per-instance private data structure */ 132 struct enic { 133 struct net_device *netdev; 134 struct pci_dev *pdev; 135 struct vnic_enet_config config; 136 struct vnic_dev_bar bar[ENIC_BARS_MAX]; 137 struct vnic_dev *vdev; 138 struct timer_list notify_timer; 139 struct work_struct reset; 140 struct work_struct tx_hang_reset; 141 struct work_struct change_mtu_work; 142 struct msix_entry msix_entry[ENIC_INTR_MAX]; 143 struct enic_msix_entry msix[ENIC_INTR_MAX]; 144 u32 msg_enable; 145 spinlock_t devcmd_lock; 146 u8 mac_addr[ETH_ALEN]; 147 unsigned int flags; 148 unsigned int priv_flags; 149 unsigned int mc_count; 150 unsigned int uc_count; 151 u32 port_mtu; 152 struct enic_rx_coal rx_coalesce_setting; 153 u32 rx_coalesce_usecs; 154 u32 tx_coalesce_usecs; 155 #ifdef CONFIG_PCI_IOV 156 u16 num_vfs; 157 #endif 158 spinlock_t enic_api_lock; 159 bool enic_api_busy; 160 struct enic_port_profile *pp; 161 162 /* work queue cache line section */ 163 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 164 spinlock_t wq_lock[ENIC_WQ_MAX]; 165 unsigned int wq_count; 166 u16 loop_enable; 167 u16 loop_tag; 168 169 /* receive queue cache line section */ 170 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 171 unsigned int rq_count; 172 struct vxlan_offload vxlan; 173 u64 rq_truncated_pkts; 174 u64 rq_bad_fcs; 175 struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX]; 176 177 /* interrupt resource cache line section */ 178 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 179 unsigned int intr_count; 180 u32 __iomem *legacy_pba; /* memory-mapped */ 181 182 /* completion queue cache line section */ 183 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX]; 184 unsigned int cq_count; 185 struct enic_rfs_flw_tbl rfs_h; 186 u32 rx_copybreak; 187 u8 rss_key[ENIC_RSS_LEN]; 188 struct vnic_gen_stats gen_stats; 189 }; 190 vnic_get_netdev(struct vnic_dev * vdev)191 static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev) 192 { 193 struct enic *enic = vdev->priv; 194 195 return enic->netdev; 196 } 197 198 /* wrappers function for kernel log 199 */ 200 #define vdev_err(vdev, fmt, ...) \ 201 dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 202 #define vdev_warn(vdev, fmt, ...) \ 203 dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 204 #define vdev_info(vdev, fmt, ...) \ 205 dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 206 207 #define vdev_neterr(vdev, fmt, ...) \ 208 netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 209 #define vdev_netwarn(vdev, fmt, ...) \ 210 netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 211 #define vdev_netinfo(vdev, fmt, ...) \ 212 netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 213 enic_get_dev(struct enic * enic)214 static inline struct device *enic_get_dev(struct enic *enic) 215 { 216 return &(enic->pdev->dev); 217 } 218 enic_cq_rq(struct enic * enic,unsigned int rq)219 static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq) 220 { 221 return rq; 222 } 223 enic_cq_wq(struct enic * enic,unsigned int wq)224 static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq) 225 { 226 return enic->rq_count + wq; 227 } 228 enic_msix_rq_intr(struct enic * enic,unsigned int rq)229 static inline unsigned int enic_msix_rq_intr(struct enic *enic, 230 unsigned int rq) 231 { 232 return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset; 233 } 234 enic_msix_wq_intr(struct enic * enic,unsigned int wq)235 static inline unsigned int enic_msix_wq_intr(struct enic *enic, 236 unsigned int wq) 237 { 238 return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset; 239 } 240 enic_msix_err_intr(struct enic * enic)241 static inline unsigned int enic_msix_err_intr(struct enic *enic) 242 { 243 return enic->rq_count + enic->wq_count; 244 } 245 246 #define ENIC_LEGACY_IO_INTR 0 247 #define ENIC_LEGACY_ERR_INTR 1 248 #define ENIC_LEGACY_NOTIFY_INTR 2 249 enic_msix_notify_intr(struct enic * enic)250 static inline unsigned int enic_msix_notify_intr(struct enic *enic) 251 { 252 return enic->rq_count + enic->wq_count + 1; 253 } 254 enic_is_err_intr(struct enic * enic,int intr)255 static inline bool enic_is_err_intr(struct enic *enic, int intr) 256 { 257 switch (vnic_dev_get_intr_mode(enic->vdev)) { 258 case VNIC_DEV_INTR_MODE_INTX: 259 return intr == ENIC_LEGACY_ERR_INTR; 260 case VNIC_DEV_INTR_MODE_MSIX: 261 return intr == enic_msix_err_intr(enic); 262 case VNIC_DEV_INTR_MODE_MSI: 263 default: 264 return false; 265 } 266 } 267 enic_is_notify_intr(struct enic * enic,int intr)268 static inline bool enic_is_notify_intr(struct enic *enic, int intr) 269 { 270 switch (vnic_dev_get_intr_mode(enic->vdev)) { 271 case VNIC_DEV_INTR_MODE_INTX: 272 return intr == ENIC_LEGACY_NOTIFY_INTR; 273 case VNIC_DEV_INTR_MODE_MSIX: 274 return intr == enic_msix_notify_intr(enic); 275 case VNIC_DEV_INTR_MODE_MSI: 276 default: 277 return false; 278 } 279 } 280 enic_dma_map_check(struct enic * enic,dma_addr_t dma_addr)281 static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr) 282 { 283 if (unlikely(dma_mapping_error(&enic->pdev->dev, dma_addr))) { 284 net_warn_ratelimited("%s: PCI dma mapping failed!\n", 285 enic->netdev->name); 286 enic->gen_stats.dma_map_error++; 287 288 return -ENOMEM; 289 } 290 291 return 0; 292 } 293 294 void enic_reset_addr_lists(struct enic *enic); 295 int enic_sriov_enabled(struct enic *enic); 296 int enic_is_valid_vf(struct enic *enic, int vf); 297 int enic_is_dynamic(struct enic *enic); 298 void enic_set_ethtool_ops(struct net_device *netdev); 299 int __enic_set_rsskey(struct enic *enic); 300 301 #endif /* _ENIC_H_ */ 302