1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/bitops.h>
5 #include <linux/debugfs.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/topology.h>
13 #include <linux/uacce.h>
14 #include "hpre.h"
15
16 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0)
17 #define HPRE_CTRL_CNT_CLR_CE 0x301000
18 #define HPRE_FSM_MAX_CNT 0x301008
19 #define HPRE_VFG_AXQOS 0x30100c
20 #define HPRE_VFG_AXCACHE 0x301010
21 #define HPRE_RDCHN_INI_CFG 0x301014
22 #define HPRE_AWUSR_FP_CFG 0x301018
23 #define HPRE_BD_ENDIAN 0x301020
24 #define HPRE_ECC_BYPASS 0x301024
25 #define HPRE_RAS_WIDTH_CFG 0x301028
26 #define HPRE_POISON_BYPASS 0x30102c
27 #define HPRE_BD_ARUSR_CFG 0x301030
28 #define HPRE_BD_AWUSR_CFG 0x301034
29 #define HPRE_TYPES_ENB 0x301038
30 #define HPRE_RSA_ENB BIT(0)
31 #define HPRE_ECC_ENB BIT(1)
32 #define HPRE_DATA_RUSER_CFG 0x30103c
33 #define HPRE_DATA_WUSER_CFG 0x301040
34 #define HPRE_INT_MASK 0x301400
35 #define HPRE_INT_STATUS 0x301800
36 #define HPRE_HAC_INT_MSK 0x301400
37 #define HPRE_HAC_RAS_CE_ENB 0x301410
38 #define HPRE_HAC_RAS_NFE_ENB 0x301414
39 #define HPRE_HAC_RAS_FE_ENB 0x301418
40 #define HPRE_HAC_INT_SET 0x301500
41 #define HPRE_RNG_TIMEOUT_NUM 0x301A34
42 #define HPRE_CORE_INT_ENABLE 0
43 #define HPRE_RDCHN_INI_ST 0x301a00
44 #define HPRE_CLSTR_BASE 0x302000
45 #define HPRE_CORE_EN_OFFSET 0x04
46 #define HPRE_CORE_INI_CFG_OFFSET 0x20
47 #define HPRE_CORE_INI_STATUS_OFFSET 0x80
48 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c
49 #define HPRE_CORE_IS_SCHD_OFFSET 0x90
50
51 #define HPRE_RAS_CE_ENB 0x301410
52 #define HPRE_RAS_NFE_ENB 0x301414
53 #define HPRE_RAS_FE_ENB 0x301418
54 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c
55 #define HPRE_HAC_RAS_FE_ENABLE 0
56
57 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET)
58 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET)
59 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET)
60 #define HPRE_HAC_ECC1_CNT 0x301a04
61 #define HPRE_HAC_ECC2_CNT 0x301a08
62 #define HPRE_HAC_SOURCE_INT 0x301600
63 #define HPRE_CLSTR_ADDR_INTRVL 0x1000
64 #define HPRE_CLUSTER_INQURY 0x100
65 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104
66 #define HPRE_PASID_EN_BIT 9
67 #define HPRE_REG_RD_INTVRL_US 10
68 #define HPRE_REG_RD_TMOUT_US 1000
69 #define HPRE_DBGFS_VAL_MAX_LEN 20
70 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258
71 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1)
72 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0)
73 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0)
74 #define HPRE_BD_USR_MASK GENMASK(1, 0)
75 #define HPRE_PREFETCH_CFG 0x301130
76 #define HPRE_SVA_PREFTCH_DFX 0x30115C
77 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30)))
78 #define HPRE_PREFETCH_DISABLE BIT(30)
79 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8))
80
81 /* clock gate */
82 #define HPRE_CLKGATE_CTL 0x301a10
83 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c
84 #define HPRE_CLUSTER_DYN_CTL 0x302010
85 #define HPRE_CORE_SHB_CFG 0x302088
86 #define HPRE_CLKGATE_CTL_EN BIT(0)
87 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0)
88 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0)
89 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31))
90
91 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044
92 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0)
93 #define HPRE_WR_MSI_PORT BIT(2)
94
95 #define HPRE_CORE_ECC_2BIT_ERR BIT(1)
96 #define HPRE_OOO_ECC_2BIT_ERR BIT(5)
97
98 #define HPRE_QM_BME_FLR BIT(7)
99 #define HPRE_QM_PM_FLR BIT(11)
100 #define HPRE_QM_SRIOV_FLR BIT(12)
101
102 #define HPRE_SHAPER_TYPE_RATE 640
103 #define HPRE_VIA_MSI_DSM 1
104 #define HPRE_SQE_MASK_OFFSET 8
105 #define HPRE_SQE_MASK_LEN 24
106
107 #define HPRE_DFX_BASE 0x301000
108 #define HPRE_DFX_COMMON1 0x301400
109 #define HPRE_DFX_COMMON2 0x301A00
110 #define HPRE_DFX_CORE 0x302000
111 #define HPRE_DFX_BASE_LEN 0x55
112 #define HPRE_DFX_COMMON1_LEN 0x41
113 #define HPRE_DFX_COMMON2_LEN 0xE
114 #define HPRE_DFX_CORE_LEN 0x43
115
116 static const char hpre_name[] = "hisi_hpre";
117 static struct dentry *hpre_debugfs_root;
118 static const struct pci_device_id hpre_dev_ids[] = {
119 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) },
120 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) },
121 { 0, }
122 };
123
124 MODULE_DEVICE_TABLE(pci, hpre_dev_ids);
125
126 struct hpre_hw_error {
127 u32 int_msk;
128 const char *msg;
129 };
130
131 static const struct qm_dev_alg hpre_dev_algs[] = {
132 {
133 .alg_msk = BIT(0),
134 .alg = "rsa\n"
135 }, {
136 .alg_msk = BIT(1),
137 .alg = "dh\n"
138 }, {
139 .alg_msk = BIT(2),
140 .alg = "ecdh\n"
141 }, {
142 .alg_msk = BIT(3),
143 .alg = "ecdsa\n"
144 }, {
145 .alg_msk = BIT(4),
146 .alg = "sm2\n"
147 }, {
148 .alg_msk = BIT(5),
149 .alg = "x25519\n"
150 }, {
151 .alg_msk = BIT(6),
152 .alg = "x448\n"
153 }, {
154 /* sentinel */
155 }
156 };
157
158 static struct hisi_qm_list hpre_devices = {
159 .register_to_crypto = hpre_algs_register,
160 .unregister_from_crypto = hpre_algs_unregister,
161 };
162
163 static const char * const hpre_debug_file_name[] = {
164 [HPRE_CLEAR_ENABLE] = "rdclr_en",
165 [HPRE_CLUSTER_CTRL] = "cluster_ctrl",
166 };
167
168 enum hpre_cap_type {
169 HPRE_QM_NFE_MASK_CAP,
170 HPRE_QM_RESET_MASK_CAP,
171 HPRE_QM_OOO_SHUTDOWN_MASK_CAP,
172 HPRE_QM_CE_MASK_CAP,
173 HPRE_NFE_MASK_CAP,
174 HPRE_RESET_MASK_CAP,
175 HPRE_OOO_SHUTDOWN_MASK_CAP,
176 HPRE_CE_MASK_CAP,
177 HPRE_CLUSTER_NUM_CAP,
178 HPRE_CORE_TYPE_NUM_CAP,
179 HPRE_CORE_NUM_CAP,
180 HPRE_CLUSTER_CORE_NUM_CAP,
181 HPRE_CORE_ENABLE_BITMAP_CAP,
182 HPRE_DRV_ALG_BITMAP_CAP,
183 HPRE_DEV_ALG_BITMAP_CAP,
184 HPRE_CORE1_ALG_BITMAP_CAP,
185 HPRE_CORE2_ALG_BITMAP_CAP,
186 HPRE_CORE3_ALG_BITMAP_CAP,
187 HPRE_CORE4_ALG_BITMAP_CAP,
188 HPRE_CORE5_ALG_BITMAP_CAP,
189 HPRE_CORE6_ALG_BITMAP_CAP,
190 HPRE_CORE7_ALG_BITMAP_CAP,
191 HPRE_CORE8_ALG_BITMAP_CAP,
192 HPRE_CORE9_ALG_BITMAP_CAP,
193 HPRE_CORE10_ALG_BITMAP_CAP
194 };
195
196 static const struct hisi_qm_cap_info hpre_basic_info[] = {
197 {HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37},
198 {HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},
199 {HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},
200 {HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
201 {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFC3E},
202 {HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFC3E},
203 {HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFC3E},
204 {HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
205 {HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1},
206 {HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},
207 {HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA},
208 {HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA},
209 {HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF},
210 {HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27},
211 {HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F},
212 {HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
213 {HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
214 {HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
215 {HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
216 {HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
217 {HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
218 {HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
219 {HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
220 {HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10},
221 {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
222 };
223
224 enum hpre_pre_store_cap_idx {
225 HPRE_CLUSTER_NUM_CAP_IDX = 0x0,
226 HPRE_CORE_ENABLE_BITMAP_CAP_IDX,
227 HPRE_DRV_ALG_BITMAP_CAP_IDX,
228 HPRE_DEV_ALG_BITMAP_CAP_IDX,
229 };
230
231 static const u32 hpre_pre_store_caps[] = {
232 HPRE_CLUSTER_NUM_CAP,
233 HPRE_CORE_ENABLE_BITMAP_CAP,
234 HPRE_DRV_ALG_BITMAP_CAP,
235 HPRE_DEV_ALG_BITMAP_CAP,
236 };
237
238 static const struct hpre_hw_error hpre_hw_errors[] = {
239 {
240 .int_msk = BIT(0),
241 .msg = "core_ecc_1bit_err_int_set"
242 }, {
243 .int_msk = BIT(1),
244 .msg = "core_ecc_2bit_err_int_set"
245 }, {
246 .int_msk = BIT(2),
247 .msg = "dat_wb_poison_int_set"
248 }, {
249 .int_msk = BIT(3),
250 .msg = "dat_rd_poison_int_set"
251 }, {
252 .int_msk = BIT(4),
253 .msg = "bd_rd_poison_int_set"
254 }, {
255 .int_msk = BIT(5),
256 .msg = "ooo_ecc_2bit_err_int_set"
257 }, {
258 .int_msk = BIT(6),
259 .msg = "cluster1_shb_timeout_int_set"
260 }, {
261 .int_msk = BIT(7),
262 .msg = "cluster2_shb_timeout_int_set"
263 }, {
264 .int_msk = BIT(8),
265 .msg = "cluster3_shb_timeout_int_set"
266 }, {
267 .int_msk = BIT(9),
268 .msg = "cluster4_shb_timeout_int_set"
269 }, {
270 .int_msk = GENMASK(15, 10),
271 .msg = "ooo_rdrsp_err_int_set"
272 }, {
273 .int_msk = GENMASK(21, 16),
274 .msg = "ooo_wrrsp_err_int_set"
275 }, {
276 .int_msk = BIT(22),
277 .msg = "pt_rng_timeout_int_set"
278 }, {
279 .int_msk = BIT(23),
280 .msg = "sva_fsm_timeout_int_set"
281 }, {
282 .int_msk = BIT(24),
283 .msg = "sva_int_set"
284 }, {
285 /* sentinel */
286 }
287 };
288
289 static const u64 hpre_cluster_offsets[] = {
290 [HPRE_CLUSTER0] =
291 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL,
292 [HPRE_CLUSTER1] =
293 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL,
294 [HPRE_CLUSTER2] =
295 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL,
296 [HPRE_CLUSTER3] =
297 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL,
298 };
299
300 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = {
301 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET},
302 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET},
303 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET},
304 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET},
305 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET},
306 };
307
308 static const struct debugfs_reg32 hpre_com_dfx_regs[] = {
309 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE},
310 {"AXQOS ", HPRE_VFG_AXQOS},
311 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG},
312 {"BD_ENDIAN ", HPRE_BD_ENDIAN},
313 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS},
314 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG},
315 {"POISON_BYPASS ", HPRE_POISON_BYPASS},
316 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG},
317 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG},
318 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG},
319 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG},
320 {"INT_STATUS ", HPRE_INT_STATUS},
321 {"INT_MASK ", HPRE_HAC_INT_MSK},
322 {"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB},
323 {"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB},
324 {"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB},
325 {"INT_SET ", HPRE_HAC_INT_SET},
326 {"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM},
327 };
328
329 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = {
330 "send_cnt",
331 "recv_cnt",
332 "send_fail_cnt",
333 "send_busy_cnt",
334 "over_thrhld_cnt",
335 "overtime_thrhld",
336 "invalid_req_cnt"
337 };
338
339 /* define the HPRE's dfx regs region and region length */
340 static struct dfx_diff_registers hpre_diff_regs[] = {
341 {
342 .reg_offset = HPRE_DFX_BASE,
343 .reg_len = HPRE_DFX_BASE_LEN,
344 }, {
345 .reg_offset = HPRE_DFX_COMMON1,
346 .reg_len = HPRE_DFX_COMMON1_LEN,
347 }, {
348 .reg_offset = HPRE_DFX_COMMON2,
349 .reg_len = HPRE_DFX_COMMON2_LEN,
350 }, {
351 .reg_offset = HPRE_DFX_CORE,
352 .reg_len = HPRE_DFX_CORE_LEN,
353 },
354 };
355
356 static const struct hisi_qm_err_ini hpre_err_ini;
357
hpre_check_alg_support(struct hisi_qm * qm,u32 alg)358 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)
359 {
360 u32 cap_val;
361
362 cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val;
363 if (alg & cap_val)
364 return true;
365
366 return false;
367 }
368
hpre_diff_regs_show(struct seq_file * s,void * unused)369 static int hpre_diff_regs_show(struct seq_file *s, void *unused)
370 {
371 struct hisi_qm *qm = s->private;
372
373 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
374 ARRAY_SIZE(hpre_diff_regs));
375
376 return 0;
377 }
378
379 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs);
380
hpre_com_regs_show(struct seq_file * s,void * unused)381 static int hpre_com_regs_show(struct seq_file *s, void *unused)
382 {
383 hisi_qm_regs_dump(s, s->private);
384
385 return 0;
386 }
387
388 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs);
389
hpre_cluster_regs_show(struct seq_file * s,void * unused)390 static int hpre_cluster_regs_show(struct seq_file *s, void *unused)
391 {
392 hisi_qm_regs_dump(s, s->private);
393
394 return 0;
395 }
396
397 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs);
398
399 static const struct kernel_param_ops hpre_uacce_mode_ops = {
400 .set = uacce_mode_set,
401 .get = param_get_int,
402 };
403
404 /*
405 * uacce_mode = 0 means hpre only register to crypto,
406 * uacce_mode = 1 means hpre both register to crypto and uacce.
407 */
408 static u32 uacce_mode = UACCE_MODE_NOUACCE;
409 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444);
410 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
411
412 static bool pf_q_num_flag;
pf_q_num_set(const char * val,const struct kernel_param * kp)413 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
414 {
415 pf_q_num_flag = true;
416
417 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF);
418 }
419
420 static const struct kernel_param_ops hpre_pf_q_num_ops = {
421 .set = pf_q_num_set,
422 .get = param_get_int,
423 };
424
425 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM;
426 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444);
427 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)");
428
429 static const struct kernel_param_ops vfs_num_ops = {
430 .set = vfs_num_set,
431 .get = param_get_int,
432 };
433
434 static u32 vfs_num;
435 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
436 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
437
hpre_create_qp(u8 type)438 struct hisi_qp *hpre_create_qp(u8 type)
439 {
440 int node = cpu_to_node(smp_processor_id());
441 struct hisi_qp *qp = NULL;
442 int ret;
443
444 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE)
445 return NULL;
446
447 /*
448 * type: 0 - RSA/DH. algorithm supported in V2,
449 * 1 - ECC algorithm in V3.
450 */
451 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp);
452 if (!ret)
453 return qp;
454
455 return NULL;
456 }
457
hpre_config_pasid(struct hisi_qm * qm)458 static void hpre_config_pasid(struct hisi_qm *qm)
459 {
460 u32 val1, val2;
461
462 if (qm->ver >= QM_HW_V3)
463 return;
464
465 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG);
466 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG);
467 if (qm->use_sva) {
468 val1 |= BIT(HPRE_PASID_EN_BIT);
469 val2 |= BIT(HPRE_PASID_EN_BIT);
470 } else {
471 val1 &= ~BIT(HPRE_PASID_EN_BIT);
472 val2 &= ~BIT(HPRE_PASID_EN_BIT);
473 }
474 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG);
475 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG);
476 }
477
hpre_cfg_by_dsm(struct hisi_qm * qm)478 static int hpre_cfg_by_dsm(struct hisi_qm *qm)
479 {
480 struct device *dev = &qm->pdev->dev;
481 union acpi_object *obj;
482 guid_t guid;
483
484 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) {
485 dev_err(dev, "Hpre GUID failed\n");
486 return -EINVAL;
487 }
488
489 /* Switch over to MSI handling due to non-standard PCI implementation */
490 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid,
491 0, HPRE_VIA_MSI_DSM, NULL);
492 if (!obj) {
493 dev_err(dev, "ACPI handle failed!\n");
494 return -EIO;
495 }
496
497 ACPI_FREE(obj);
498
499 return 0;
500 }
501
hpre_set_cluster(struct hisi_qm * qm)502 static int hpre_set_cluster(struct hisi_qm *qm)
503 {
504 struct device *dev = &qm->pdev->dev;
505 unsigned long offset;
506 u32 cluster_core_mask;
507 u8 clusters_num;
508 u32 val = 0;
509 int ret, i;
510
511 cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val;
512 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
513 for (i = 0; i < clusters_num; i++) {
514 offset = i * HPRE_CLSTR_ADDR_INTRVL;
515
516 /* clusters initiating */
517 writel(cluster_core_mask,
518 qm->io_base + offset + HPRE_CORE_ENB);
519 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG);
520 ret = readl_relaxed_poll_timeout(qm->io_base + offset +
521 HPRE_CORE_INI_STATUS, val,
522 ((val & cluster_core_mask) ==
523 cluster_core_mask),
524 HPRE_REG_RD_INTVRL_US,
525 HPRE_REG_RD_TMOUT_US);
526 if (ret) {
527 dev_err(dev,
528 "cluster %d int st status timeout!\n", i);
529 return -ETIMEDOUT;
530 }
531 }
532
533 return 0;
534 }
535
536 /*
537 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV).
538 * Or it may stay in D3 state when we bind and unbind hpre quickly,
539 * as it does FLR triggered by hardware.
540 */
disable_flr_of_bme(struct hisi_qm * qm)541 static void disable_flr_of_bme(struct hisi_qm *qm)
542 {
543 u32 val;
544
545 val = readl(qm->io_base + QM_PEH_AXUSER_CFG);
546 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR);
547 val |= HPRE_QM_PM_FLR;
548 writel(val, qm->io_base + QM_PEH_AXUSER_CFG);
549 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
550 }
551
hpre_open_sva_prefetch(struct hisi_qm * qm)552 static void hpre_open_sva_prefetch(struct hisi_qm *qm)
553 {
554 u32 val;
555 int ret;
556
557 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
558 return;
559
560 /* Enable prefetch */
561 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);
562 val &= HPRE_PREFETCH_ENABLE;
563 writel(val, qm->io_base + HPRE_PREFETCH_CFG);
564
565 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG,
566 val, !(val & HPRE_PREFETCH_DISABLE),
567 HPRE_REG_RD_INTVRL_US,
568 HPRE_REG_RD_TMOUT_US);
569 if (ret)
570 pci_err(qm->pdev, "failed to open sva prefetch\n");
571 }
572
hpre_close_sva_prefetch(struct hisi_qm * qm)573 static void hpre_close_sva_prefetch(struct hisi_qm *qm)
574 {
575 u32 val;
576 int ret;
577
578 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
579 return;
580
581 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);
582 val |= HPRE_PREFETCH_DISABLE;
583 writel(val, qm->io_base + HPRE_PREFETCH_CFG);
584
585 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX,
586 val, !(val & HPRE_SVA_DISABLE_READY),
587 HPRE_REG_RD_INTVRL_US,
588 HPRE_REG_RD_TMOUT_US);
589 if (ret)
590 pci_err(qm->pdev, "failed to close sva prefetch\n");
591 }
592
hpre_enable_clock_gate(struct hisi_qm * qm)593 static void hpre_enable_clock_gate(struct hisi_qm *qm)
594 {
595 u32 val;
596
597 if (qm->ver < QM_HW_V3)
598 return;
599
600 val = readl(qm->io_base + HPRE_CLKGATE_CTL);
601 val |= HPRE_CLKGATE_CTL_EN;
602 writel(val, qm->io_base + HPRE_CLKGATE_CTL);
603
604 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
605 val |= HPRE_PEH_CFG_AUTO_GATE_EN;
606 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
607
608 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
609 val |= HPRE_CLUSTER_DYN_CTL_EN;
610 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
611
612 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
613 val |= HPRE_CORE_GATE_EN;
614 writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
615 }
616
hpre_disable_clock_gate(struct hisi_qm * qm)617 static void hpre_disable_clock_gate(struct hisi_qm *qm)
618 {
619 u32 val;
620
621 if (qm->ver < QM_HW_V3)
622 return;
623
624 val = readl(qm->io_base + HPRE_CLKGATE_CTL);
625 val &= ~HPRE_CLKGATE_CTL_EN;
626 writel(val, qm->io_base + HPRE_CLKGATE_CTL);
627
628 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
629 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN;
630 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
631
632 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
633 val &= ~HPRE_CLUSTER_DYN_CTL_EN;
634 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
635
636 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
637 val &= ~HPRE_CORE_GATE_EN;
638 writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
639 }
640
hpre_set_user_domain_and_cache(struct hisi_qm * qm)641 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)
642 {
643 struct device *dev = &qm->pdev->dev;
644 u32 val;
645 int ret;
646
647 /* disabel dynamic clock gate before sram init */
648 hpre_disable_clock_gate(qm);
649
650 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
651 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
652 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);
653
654 if (qm->ver >= QM_HW_V3)
655 writel(HPRE_RSA_ENB | HPRE_ECC_ENB,
656 qm->io_base + HPRE_TYPES_ENB);
657 else
658 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB);
659
660 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);
661 writel(0x0, qm->io_base + HPRE_BD_ENDIAN);
662 writel(0x0, qm->io_base + HPRE_POISON_BYPASS);
663 writel(0x0, qm->io_base + HPRE_ECC_BYPASS);
664
665 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);
666 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG);
667 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG);
668 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val,
669 val & BIT(0),
670 HPRE_REG_RD_INTVRL_US,
671 HPRE_REG_RD_TMOUT_US);
672 if (ret) {
673 dev_err(dev, "read rd channel timeout fail!\n");
674 return -ETIMEDOUT;
675 }
676
677 ret = hpre_set_cluster(qm);
678 if (ret)
679 return -ETIMEDOUT;
680
681 /* This setting is only needed by Kunpeng 920. */
682 if (qm->ver == QM_HW_V2) {
683 ret = hpre_cfg_by_dsm(qm);
684 if (ret)
685 return ret;
686
687 disable_flr_of_bme(qm);
688 }
689
690 /* Config data buffer pasid needed by Kunpeng 920 */
691 hpre_config_pasid(qm);
692
693 hpre_enable_clock_gate(qm);
694
695 return ret;
696 }
697
hpre_cnt_regs_clear(struct hisi_qm * qm)698 static void hpre_cnt_regs_clear(struct hisi_qm *qm)
699 {
700 unsigned long offset;
701 u8 clusters_num;
702 int i;
703
704 /* clear clusterX/cluster_ctrl */
705 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
706 for (i = 0; i < clusters_num; i++) {
707 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
708 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
709 }
710
711 /* clear rdclr_en */
712 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
713
714 hisi_qm_debug_regs_clear(qm);
715 }
716
hpre_master_ooo_ctrl(struct hisi_qm * qm,bool enable)717 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
718 {
719 u32 val1, val2;
720
721 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
722 if (enable) {
723 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE;
724 val2 = hisi_qm_get_hw_info(qm, hpre_basic_info,
725 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
726 } else {
727 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE;
728 val2 = 0x0;
729 }
730
731 if (qm->ver > QM_HW_V2)
732 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);
733
734 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
735 }
736
hpre_hw_error_disable(struct hisi_qm * qm)737 static void hpre_hw_error_disable(struct hisi_qm *qm)
738 {
739 u32 ce, nfe;
740
741 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);
742 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
743
744 /* disable hpre hw error interrupts */
745 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK);
746 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */
747 hpre_master_ooo_ctrl(qm, false);
748 }
749
hpre_hw_error_enable(struct hisi_qm * qm)750 static void hpre_hw_error_enable(struct hisi_qm *qm)
751 {
752 u32 ce, nfe, err_en;
753
754 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);
755 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
756
757 /* clear HPRE hw error source if having */
758 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT);
759
760 /* configure error type */
761 writel(ce, qm->io_base + HPRE_RAS_CE_ENB);
762 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);
763 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB);
764
765 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */
766 hpre_master_ooo_ctrl(qm, true);
767
768 /* enable hpre hw error interrupts */
769 err_en = ce | nfe | HPRE_HAC_RAS_FE_ENABLE;
770 writel(~err_en, qm->io_base + HPRE_INT_MASK);
771 }
772
hpre_file_to_qm(struct hpre_debugfs_file * file)773 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file)
774 {
775 struct hpre *hpre = container_of(file->debug, struct hpre, debug);
776
777 return &hpre->qm;
778 }
779
hpre_clear_enable_read(struct hpre_debugfs_file * file)780 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file)
781 {
782 struct hisi_qm *qm = hpre_file_to_qm(file);
783
784 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
785 HPRE_CTRL_CNT_CLR_CE_BIT;
786 }
787
hpre_clear_enable_write(struct hpre_debugfs_file * file,u32 val)788 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val)
789 {
790 struct hisi_qm *qm = hpre_file_to_qm(file);
791 u32 tmp;
792
793 if (val != 1 && val != 0)
794 return -EINVAL;
795
796 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
797 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val;
798 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
799
800 return 0;
801 }
802
hpre_cluster_inqry_read(struct hpre_debugfs_file * file)803 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file)
804 {
805 struct hisi_qm *qm = hpre_file_to_qm(file);
806 int cluster_index = file->index - HPRE_CLUSTER_CTRL;
807 unsigned long offset = HPRE_CLSTR_BASE +
808 cluster_index * HPRE_CLSTR_ADDR_INTRVL;
809
810 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT);
811 }
812
hpre_cluster_inqry_write(struct hpre_debugfs_file * file,u32 val)813 static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val)
814 {
815 struct hisi_qm *qm = hpre_file_to_qm(file);
816 int cluster_index = file->index - HPRE_CLUSTER_CTRL;
817 unsigned long offset = HPRE_CLSTR_BASE + cluster_index *
818 HPRE_CLSTR_ADDR_INTRVL;
819
820 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY);
821 }
822
hpre_ctrl_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)823 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf,
824 size_t count, loff_t *pos)
825 {
826 struct hpre_debugfs_file *file = filp->private_data;
827 struct hisi_qm *qm = hpre_file_to_qm(file);
828 char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
829 u32 val;
830 int ret;
831
832 ret = hisi_qm_get_dfx_access(qm);
833 if (ret)
834 return ret;
835
836 spin_lock_irq(&file->lock);
837 switch (file->type) {
838 case HPRE_CLEAR_ENABLE:
839 val = hpre_clear_enable_read(file);
840 break;
841 case HPRE_CLUSTER_CTRL:
842 val = hpre_cluster_inqry_read(file);
843 break;
844 default:
845 goto err_input;
846 }
847 spin_unlock_irq(&file->lock);
848
849 hisi_qm_put_dfx_access(qm);
850 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val);
851 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
852
853 err_input:
854 spin_unlock_irq(&file->lock);
855 hisi_qm_put_dfx_access(qm);
856 return -EINVAL;
857 }
858
hpre_ctrl_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)859 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf,
860 size_t count, loff_t *pos)
861 {
862 struct hpre_debugfs_file *file = filp->private_data;
863 struct hisi_qm *qm = hpre_file_to_qm(file);
864 char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
865 unsigned long val;
866 int len, ret;
867
868 if (*pos != 0)
869 return 0;
870
871 if (count >= HPRE_DBGFS_VAL_MAX_LEN)
872 return -ENOSPC;
873
874 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1,
875 pos, buf, count);
876 if (len < 0)
877 return len;
878
879 tbuf[len] = '\0';
880 if (kstrtoul(tbuf, 0, &val))
881 return -EFAULT;
882
883 ret = hisi_qm_get_dfx_access(qm);
884 if (ret)
885 return ret;
886
887 spin_lock_irq(&file->lock);
888 switch (file->type) {
889 case HPRE_CLEAR_ENABLE:
890 ret = hpre_clear_enable_write(file, val);
891 if (ret)
892 goto err_input;
893 break;
894 case HPRE_CLUSTER_CTRL:
895 hpre_cluster_inqry_write(file, val);
896 break;
897 default:
898 ret = -EINVAL;
899 goto err_input;
900 }
901
902 ret = count;
903
904 err_input:
905 spin_unlock_irq(&file->lock);
906 hisi_qm_put_dfx_access(qm);
907 return ret;
908 }
909
910 static const struct file_operations hpre_ctrl_debug_fops = {
911 .owner = THIS_MODULE,
912 .open = simple_open,
913 .read = hpre_ctrl_debug_read,
914 .write = hpre_ctrl_debug_write,
915 };
916
hpre_debugfs_atomic64_get(void * data,u64 * val)917 static int hpre_debugfs_atomic64_get(void *data, u64 *val)
918 {
919 struct hpre_dfx *dfx_item = data;
920
921 *val = atomic64_read(&dfx_item->value);
922
923 return 0;
924 }
925
hpre_debugfs_atomic64_set(void * data,u64 val)926 static int hpre_debugfs_atomic64_set(void *data, u64 val)
927 {
928 struct hpre_dfx *dfx_item = data;
929 struct hpre_dfx *hpre_dfx = NULL;
930
931 if (dfx_item->type == HPRE_OVERTIME_THRHLD) {
932 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD;
933 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0);
934 } else if (val) {
935 return -EINVAL;
936 }
937
938 atomic64_set(&dfx_item->value, val);
939
940 return 0;
941 }
942
943 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get,
944 hpre_debugfs_atomic64_set, "%llu\n");
945
hpre_create_debugfs_file(struct hisi_qm * qm,struct dentry * dir,enum hpre_ctrl_dbgfs_file type,int indx)946 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,
947 enum hpre_ctrl_dbgfs_file type, int indx)
948 {
949 struct hpre *hpre = container_of(qm, struct hpre, qm);
950 struct hpre_debug *dbg = &hpre->debug;
951 struct dentry *file_dir;
952
953 if (dir)
954 file_dir = dir;
955 else
956 file_dir = qm->debug.debug_root;
957
958 if (type >= HPRE_DEBUG_FILE_NUM)
959 return -EINVAL;
960
961 spin_lock_init(&dbg->files[indx].lock);
962 dbg->files[indx].debug = dbg;
963 dbg->files[indx].type = type;
964 dbg->files[indx].index = indx;
965 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir,
966 dbg->files + indx, &hpre_ctrl_debug_fops);
967
968 return 0;
969 }
970
hpre_pf_comm_regs_debugfs_init(struct hisi_qm * qm)971 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm)
972 {
973 struct device *dev = &qm->pdev->dev;
974 struct debugfs_regset32 *regset;
975
976 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
977 if (!regset)
978 return -ENOMEM;
979
980 regset->regs = hpre_com_dfx_regs;
981 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs);
982 regset->base = qm->io_base;
983 regset->dev = dev;
984
985 debugfs_create_file("regs", 0444, qm->debug.debug_root,
986 regset, &hpre_com_regs_fops);
987
988 return 0;
989 }
990
hpre_cluster_debugfs_init(struct hisi_qm * qm)991 static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
992 {
993 struct device *dev = &qm->pdev->dev;
994 char buf[HPRE_DBGFS_VAL_MAX_LEN];
995 struct debugfs_regset32 *regset;
996 struct dentry *tmp_d;
997 u8 clusters_num;
998 int i, ret;
999
1000 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
1001 for (i = 0; i < clusters_num; i++) {
1002 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
1003 if (ret >= HPRE_DBGFS_VAL_MAX_LEN)
1004 return -EINVAL;
1005 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
1006
1007 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
1008 if (!regset)
1009 return -ENOMEM;
1010
1011 regset->regs = hpre_cluster_dfx_regs;
1012 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs);
1013 regset->base = qm->io_base + hpre_cluster_offsets[i];
1014 regset->dev = dev;
1015
1016 debugfs_create_file("regs", 0444, tmp_d, regset,
1017 &hpre_cluster_regs_fops);
1018 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL,
1019 i + HPRE_CLUSTER_CTRL);
1020 if (ret)
1021 return ret;
1022 }
1023
1024 return 0;
1025 }
1026
hpre_ctrl_debug_init(struct hisi_qm * qm)1027 static int hpre_ctrl_debug_init(struct hisi_qm *qm)
1028 {
1029 int ret;
1030
1031 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE,
1032 HPRE_CLEAR_ENABLE);
1033 if (ret)
1034 return ret;
1035
1036 ret = hpre_pf_comm_regs_debugfs_init(qm);
1037 if (ret)
1038 return ret;
1039
1040 return hpre_cluster_debugfs_init(qm);
1041 }
1042
hpre_dfx_debug_init(struct hisi_qm * qm)1043 static void hpre_dfx_debug_init(struct hisi_qm *qm)
1044 {
1045 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs;
1046 struct hpre *hpre = container_of(qm, struct hpre, qm);
1047 struct hpre_dfx *dfx = hpre->debug.dfx;
1048 struct dentry *parent;
1049 int i;
1050
1051 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root);
1052 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) {
1053 dfx[i].type = i;
1054 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i],
1055 &hpre_atomic64_ops);
1056 }
1057
1058 if (qm->fun_type == QM_HW_PF && hpre_regs)
1059 debugfs_create_file("diff_regs", 0444, parent,
1060 qm, &hpre_diff_regs_fops);
1061 }
1062
hpre_debugfs_init(struct hisi_qm * qm)1063 static int hpre_debugfs_init(struct hisi_qm *qm)
1064 {
1065 struct device *dev = &qm->pdev->dev;
1066 int ret;
1067
1068 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
1069 hpre_debugfs_root);
1070
1071 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET;
1072 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN;
1073 ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs));
1074 if (ret) {
1075 dev_warn(dev, "Failed to init HPRE diff regs!\n");
1076 goto debugfs_remove;
1077 }
1078
1079 hisi_qm_debug_init(qm);
1080
1081 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) {
1082 ret = hpre_ctrl_debug_init(qm);
1083 if (ret)
1084 goto failed_to_create;
1085 }
1086
1087 hpre_dfx_debug_init(qm);
1088
1089 return 0;
1090
1091 failed_to_create:
1092 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));
1093 debugfs_remove:
1094 debugfs_remove_recursive(qm->debug.debug_root);
1095 return ret;
1096 }
1097
hpre_debugfs_exit(struct hisi_qm * qm)1098 static void hpre_debugfs_exit(struct hisi_qm *qm)
1099 {
1100 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));
1101
1102 debugfs_remove_recursive(qm->debug.debug_root);
1103 }
1104
hpre_pre_store_cap_reg(struct hisi_qm * qm)1105 static int hpre_pre_store_cap_reg(struct hisi_qm *qm)
1106 {
1107 struct hisi_qm_cap_record *hpre_cap;
1108 struct device *dev = &qm->pdev->dev;
1109 size_t i, size;
1110
1111 size = ARRAY_SIZE(hpre_pre_store_caps);
1112 hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL);
1113 if (!hpre_cap)
1114 return -ENOMEM;
1115
1116 for (i = 0; i < size; i++) {
1117 hpre_cap[i].type = hpre_pre_store_caps[i];
1118 hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info,
1119 hpre_pre_store_caps[i], qm->cap_ver);
1120 }
1121
1122 if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val > HPRE_CLUSTERS_NUM_MAX) {
1123 dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n",
1124 hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX);
1125 return -EINVAL;
1126 }
1127
1128 qm->cap_tables.dev_cap_table = hpre_cap;
1129
1130 return 0;
1131 }
1132
hpre_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)1133 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1134 {
1135 u64 alg_msk;
1136 int ret;
1137
1138 if (pdev->revision == QM_HW_V1) {
1139 pci_warn(pdev, "HPRE version 1 is not supported!\n");
1140 return -EINVAL;
1141 }
1142
1143 qm->mode = uacce_mode;
1144 qm->pdev = pdev;
1145 qm->ver = pdev->revision;
1146 qm->sqe_size = HPRE_SQE_SIZE;
1147 qm->dev_name = hpre_name;
1148
1149 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ?
1150 QM_HW_PF : QM_HW_VF;
1151 if (qm->fun_type == QM_HW_PF) {
1152 qm->qp_base = HPRE_PF_DEF_Q_BASE;
1153 qm->qp_num = pf_q_num;
1154 qm->debug.curr_qm_qp_num = pf_q_num;
1155 qm->qm_list = &hpre_devices;
1156 qm->err_ini = &hpre_err_ini;
1157 if (pf_q_num_flag)
1158 set_bit(QM_MODULE_PARAM, &qm->misc_ctl);
1159 }
1160
1161 ret = hisi_qm_init(qm);
1162 if (ret) {
1163 pci_err(pdev, "Failed to init hpre qm configures!\n");
1164 return ret;
1165 }
1166
1167 /* Fetch and save the value of capability registers */
1168 ret = hpre_pre_store_cap_reg(qm);
1169 if (ret) {
1170 pci_err(pdev, "Failed to pre-store capability registers!\n");
1171 hisi_qm_uninit(qm);
1172 return ret;
1173 }
1174
1175 alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val;
1176 ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));
1177 if (ret) {
1178 pci_err(pdev, "Failed to set hpre algs!\n");
1179 hisi_qm_uninit(qm);
1180 }
1181
1182 return ret;
1183 }
1184
hpre_show_last_regs_init(struct hisi_qm * qm)1185 static int hpre_show_last_regs_init(struct hisi_qm *qm)
1186 {
1187 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
1188 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1189 struct qm_debug *debug = &qm->debug;
1190 void __iomem *io_base;
1191 u8 clusters_num;
1192 int i, j, idx;
1193
1194 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
1195 debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
1196 com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
1197 if (!debug->last_words)
1198 return -ENOMEM;
1199
1200 for (i = 0; i < com_dfx_regs_num; i++)
1201 debug->last_words[i] = readl_relaxed(qm->io_base +
1202 hpre_com_dfx_regs[i].offset);
1203
1204 for (i = 0; i < clusters_num; i++) {
1205 io_base = qm->io_base + hpre_cluster_offsets[i];
1206 for (j = 0; j < cluster_dfx_regs_num; j++) {
1207 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
1208 debug->last_words[idx] = readl_relaxed(
1209 io_base + hpre_cluster_dfx_regs[j].offset);
1210 }
1211 }
1212
1213 return 0;
1214 }
1215
hpre_show_last_regs_uninit(struct hisi_qm * qm)1216 static void hpre_show_last_regs_uninit(struct hisi_qm *qm)
1217 {
1218 struct qm_debug *debug = &qm->debug;
1219
1220 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1221 return;
1222
1223 kfree(debug->last_words);
1224 debug->last_words = NULL;
1225 }
1226
hpre_show_last_dfx_regs(struct hisi_qm * qm)1227 static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
1228 {
1229 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
1230 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1231 struct qm_debug *debug = &qm->debug;
1232 struct pci_dev *pdev = qm->pdev;
1233 void __iomem *io_base;
1234 u8 clusters_num;
1235 int i, j, idx;
1236 u32 val;
1237
1238 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1239 return;
1240
1241 /* dumps last word of the debugging registers during controller reset */
1242 for (i = 0; i < com_dfx_regs_num; i++) {
1243 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset);
1244 if (debug->last_words[i] != val)
1245 pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n",
1246 hpre_com_dfx_regs[i].name, debug->last_words[i], val);
1247 }
1248
1249 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
1250 for (i = 0; i < clusters_num; i++) {
1251 io_base = qm->io_base + hpre_cluster_offsets[i];
1252 for (j = 0; j < cluster_dfx_regs_num; j++) {
1253 val = readl_relaxed(io_base +
1254 hpre_cluster_dfx_regs[j].offset);
1255 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
1256 if (debug->last_words[idx] != val)
1257 pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n",
1258 i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val);
1259 }
1260 }
1261 }
1262
hpre_log_hw_error(struct hisi_qm * qm,u32 err_sts)1263 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts)
1264 {
1265 const struct hpre_hw_error *err = hpre_hw_errors;
1266 struct device *dev = &qm->pdev->dev;
1267
1268 while (err->msg) {
1269 if (err->int_msk & err_sts)
1270 dev_warn(dev, "%s [error status=0x%x] found\n",
1271 err->msg, err->int_msk);
1272 err++;
1273 }
1274 }
1275
hpre_get_hw_err_status(struct hisi_qm * qm)1276 static u32 hpre_get_hw_err_status(struct hisi_qm *qm)
1277 {
1278 return readl(qm->io_base + HPRE_INT_STATUS);
1279 }
1280
hpre_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)1281 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1282 {
1283 u32 nfe;
1284
1285 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT);
1286 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
1287 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);
1288 }
1289
hpre_open_axi_master_ooo(struct hisi_qm * qm)1290 static void hpre_open_axi_master_ooo(struct hisi_qm *qm)
1291 {
1292 u32 value;
1293
1294 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1295 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE,
1296 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1297 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE,
1298 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1299 }
1300
hpre_err_info_init(struct hisi_qm * qm)1301 static void hpre_err_info_init(struct hisi_qm *qm)
1302 {
1303 struct hisi_qm_err_info *err_info = &qm->err_info;
1304
1305 err_info->fe = HPRE_HAC_RAS_FE_ENABLE;
1306 err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver);
1307 err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver);
1308 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR;
1309 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1310 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1311 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1312 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1313 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1314 HPRE_QM_RESET_MASK_CAP, qm->cap_ver);
1315 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1316 HPRE_RESET_MASK_CAP, qm->cap_ver);
1317 err_info->msi_wr_port = HPRE_WR_MSI_PORT;
1318 err_info->acpi_rst = "HRST";
1319 }
1320
1321 static const struct hisi_qm_err_ini hpre_err_ini = {
1322 .hw_init = hpre_set_user_domain_and_cache,
1323 .hw_err_enable = hpre_hw_error_enable,
1324 .hw_err_disable = hpre_hw_error_disable,
1325 .get_dev_hw_err_status = hpre_get_hw_err_status,
1326 .clear_dev_hw_err_status = hpre_clear_hw_err_status,
1327 .log_dev_hw_err = hpre_log_hw_error,
1328 .open_axi_master_ooo = hpre_open_axi_master_ooo,
1329 .open_sva_prefetch = hpre_open_sva_prefetch,
1330 .close_sva_prefetch = hpre_close_sva_prefetch,
1331 .show_last_dfx_regs = hpre_show_last_dfx_regs,
1332 .err_info_init = hpre_err_info_init,
1333 };
1334
hpre_pf_probe_init(struct hpre * hpre)1335 static int hpre_pf_probe_init(struct hpre *hpre)
1336 {
1337 struct hisi_qm *qm = &hpre->qm;
1338 int ret;
1339
1340 ret = hpre_set_user_domain_and_cache(qm);
1341 if (ret)
1342 return ret;
1343
1344 hpre_open_sva_prefetch(qm);
1345
1346 hisi_qm_dev_err_init(qm);
1347 ret = hpre_show_last_regs_init(qm);
1348 if (ret)
1349 pci_err(qm->pdev, "Failed to init last word regs!\n");
1350
1351 return ret;
1352 }
1353
hpre_probe_init(struct hpre * hpre)1354 static int hpre_probe_init(struct hpre *hpre)
1355 {
1356 u32 type_rate = HPRE_SHAPER_TYPE_RATE;
1357 struct hisi_qm *qm = &hpre->qm;
1358 int ret;
1359
1360 if (qm->fun_type == QM_HW_PF) {
1361 ret = hpre_pf_probe_init(hpre);
1362 if (ret)
1363 return ret;
1364 /* Enable shaper type 0 */
1365 if (qm->ver >= QM_HW_V3) {
1366 type_rate |= QM_SHAPER_ENABLE;
1367 qm->type_rate = type_rate;
1368 }
1369 }
1370
1371 return 0;
1372 }
1373
hpre_probe_uninit(struct hisi_qm * qm)1374 static void hpre_probe_uninit(struct hisi_qm *qm)
1375 {
1376 if (qm->fun_type == QM_HW_VF)
1377 return;
1378
1379 hpre_cnt_regs_clear(qm);
1380 qm->debug.curr_qm_qp_num = 0;
1381 hpre_show_last_regs_uninit(qm);
1382 hpre_close_sva_prefetch(qm);
1383 hisi_qm_dev_err_uninit(qm);
1384 }
1385
hpre_probe(struct pci_dev * pdev,const struct pci_device_id * id)1386 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1387 {
1388 struct hisi_qm *qm;
1389 struct hpre *hpre;
1390 int ret;
1391
1392 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL);
1393 if (!hpre)
1394 return -ENOMEM;
1395
1396 qm = &hpre->qm;
1397 ret = hpre_qm_init(qm, pdev);
1398 if (ret) {
1399 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret);
1400 return ret;
1401 }
1402
1403 ret = hpre_probe_init(hpre);
1404 if (ret) {
1405 pci_err(pdev, "Failed to probe (%d)!\n", ret);
1406 goto err_with_qm_init;
1407 }
1408
1409 ret = hisi_qm_start(qm);
1410 if (ret)
1411 goto err_with_probe_init;
1412
1413 ret = hpre_debugfs_init(qm);
1414 if (ret)
1415 dev_warn(&pdev->dev, "init debugfs fail!\n");
1416
1417 ret = hisi_qm_alg_register(qm, &hpre_devices);
1418 if (ret < 0) {
1419 pci_err(pdev, "fail to register algs to crypto!\n");
1420 goto err_with_qm_start;
1421 }
1422
1423 if (qm->uacce) {
1424 ret = uacce_register(qm->uacce);
1425 if (ret) {
1426 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1427 goto err_with_alg_register;
1428 }
1429 }
1430
1431 if (qm->fun_type == QM_HW_PF && vfs_num) {
1432 ret = hisi_qm_sriov_enable(pdev, vfs_num);
1433 if (ret < 0)
1434 goto err_with_alg_register;
1435 }
1436
1437 hisi_qm_pm_init(qm);
1438
1439 return 0;
1440
1441 err_with_alg_register:
1442 hisi_qm_alg_unregister(qm, &hpre_devices);
1443
1444 err_with_qm_start:
1445 hpre_debugfs_exit(qm);
1446 hisi_qm_stop(qm, QM_NORMAL);
1447
1448 err_with_probe_init:
1449 hpre_probe_uninit(qm);
1450
1451 err_with_qm_init:
1452 hisi_qm_uninit(qm);
1453
1454 return ret;
1455 }
1456
hpre_remove(struct pci_dev * pdev)1457 static void hpre_remove(struct pci_dev *pdev)
1458 {
1459 struct hisi_qm *qm = pci_get_drvdata(pdev);
1460
1461 hisi_qm_pm_uninit(qm);
1462 hisi_qm_wait_task_finish(qm, &hpre_devices);
1463 hisi_qm_alg_unregister(qm, &hpre_devices);
1464 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1465 hisi_qm_sriov_disable(pdev, true);
1466
1467 hpre_debugfs_exit(qm);
1468 hisi_qm_stop(qm, QM_NORMAL);
1469
1470 hpre_probe_uninit(qm);
1471 hisi_qm_uninit(qm);
1472 }
1473
1474 static const struct dev_pm_ops hpre_pm_ops = {
1475 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1476 };
1477
1478 static const struct pci_error_handlers hpre_err_handler = {
1479 .error_detected = hisi_qm_dev_err_detected,
1480 .slot_reset = hisi_qm_dev_slot_reset,
1481 .reset_prepare = hisi_qm_reset_prepare,
1482 .reset_done = hisi_qm_reset_done,
1483 };
1484
1485 static struct pci_driver hpre_pci_driver = {
1486 .name = hpre_name,
1487 .id_table = hpre_dev_ids,
1488 .probe = hpre_probe,
1489 .remove = hpre_remove,
1490 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ?
1491 hisi_qm_sriov_configure : NULL,
1492 .err_handler = &hpre_err_handler,
1493 .shutdown = hisi_qm_dev_shutdown,
1494 .driver.pm = &hpre_pm_ops,
1495 };
1496
hisi_hpre_get_pf_driver(void)1497 struct pci_driver *hisi_hpre_get_pf_driver(void)
1498 {
1499 return &hpre_pci_driver;
1500 }
1501 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver);
1502
hpre_register_debugfs(void)1503 static void hpre_register_debugfs(void)
1504 {
1505 if (!debugfs_initialized())
1506 return;
1507
1508 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL);
1509 }
1510
hpre_unregister_debugfs(void)1511 static void hpre_unregister_debugfs(void)
1512 {
1513 debugfs_remove_recursive(hpre_debugfs_root);
1514 }
1515
hpre_init(void)1516 static int __init hpre_init(void)
1517 {
1518 int ret;
1519
1520 hisi_qm_init_list(&hpre_devices);
1521 hpre_register_debugfs();
1522
1523 ret = pci_register_driver(&hpre_pci_driver);
1524 if (ret) {
1525 hpre_unregister_debugfs();
1526 pr_err("hpre: can't register hisi hpre driver.\n");
1527 }
1528
1529 return ret;
1530 }
1531
hpre_exit(void)1532 static void __exit hpre_exit(void)
1533 {
1534 pci_unregister_driver(&hpre_pci_driver);
1535 hpre_unregister_debugfs();
1536 }
1537
1538 module_init(hpre_init);
1539 module_exit(hpre_exit);
1540
1541 MODULE_LICENSE("GPL v2");
1542 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1543 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>");
1544 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator");
1545