1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2023 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_de.h"
9 #include "intel_display_irq.h"
10 #include "intel_display_types.h"
11 #include "intel_dp_aux.h"
12 #include "intel_gmbus.h"
13 #include "intel_hotplug.h"
14 #include "intel_hotplug_irq.h"
15
16 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
17 typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder);
18 typedef u32 (*hotplug_mask_func)(enum hpd_pin pin);
19
20 static const u32 hpd_ilk[HPD_NUM_PINS] = {
21 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
22 };
23
24 static const u32 hpd_ivb[HPD_NUM_PINS] = {
25 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
26 };
27
28 static const u32 hpd_bdw[HPD_NUM_PINS] = {
29 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
30 };
31
32 static const u32 hpd_ibx[HPD_NUM_PINS] = {
33 [HPD_CRT] = SDE_CRT_HOTPLUG,
34 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
35 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
36 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
37 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
38 };
39
40 static const u32 hpd_cpt[HPD_NUM_PINS] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
46 };
47
48 static const u32 hpd_spt[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
53 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
54 };
55
56 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
63 };
64
65 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
72 };
73
74 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
81 };
82
83 static const u32 hpd_bxt[HPD_NUM_PINS] = {
84 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
85 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
86 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
87 };
88
89 static const u32 hpd_gen11[HPD_NUM_PINS] = {
90 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
91 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
92 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
93 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
94 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
95 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
96 };
97
98 static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
99 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
100 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
101 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
102 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
103 };
104
105 static const u32 hpd_icp[HPD_NUM_PINS] = {
106 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
107 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
108 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
109 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
110 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
111 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
112 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
113 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
114 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
115 };
116
117 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
118 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
119 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
120 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
121 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
122 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
123 };
124
125 static const u32 hpd_mtp[HPD_NUM_PINS] = {
126 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
127 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
128 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
129 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
130 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
131 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
132 };
133
intel_hpd_init_pins(struct drm_i915_private * dev_priv)134 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
135 {
136 struct intel_hotplug *hpd = &dev_priv->display.hotplug;
137
138 if (HAS_GMCH(dev_priv)) {
139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
140 IS_CHERRYVIEW(dev_priv))
141 hpd->hpd = hpd_status_g4x;
142 else
143 hpd->hpd = hpd_status_i915;
144 return;
145 }
146
147 if (DISPLAY_VER(dev_priv) >= 14)
148 hpd->hpd = hpd_xelpdp;
149 else if (DISPLAY_VER(dev_priv) >= 11)
150 hpd->hpd = hpd_gen11;
151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
152 hpd->hpd = hpd_bxt;
153 else if (DISPLAY_VER(dev_priv) == 9)
154 hpd->hpd = NULL; /* no north HPD on SKL */
155 else if (DISPLAY_VER(dev_priv) >= 8)
156 hpd->hpd = hpd_bdw;
157 else if (DISPLAY_VER(dev_priv) >= 7)
158 hpd->hpd = hpd_ivb;
159 else
160 hpd->hpd = hpd_ilk;
161
162 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
164 return;
165
166 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
167 hpd->pch_hpd = hpd_sde_dg1;
168 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
169 hpd->pch_hpd = hpd_mtp;
170 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
171 hpd->pch_hpd = hpd_icp;
172 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
173 hpd->pch_hpd = hpd_spt;
174 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
175 hpd->pch_hpd = hpd_cpt;
176 else if (HAS_PCH_IBX(dev_priv))
177 hpd->pch_hpd = hpd_ibx;
178 else
179 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
180 }
181
182 /* For display hotplug interrupt */
i915_hotplug_interrupt_update_locked(struct drm_i915_private * dev_priv,u32 mask,u32 bits)183 void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
184 u32 mask, u32 bits)
185 {
186 lockdep_assert_held(&dev_priv->irq_lock);
187 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
188
189 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN, mask, bits);
190 }
191
192 /**
193 * i915_hotplug_interrupt_update - update hotplug interrupt enable
194 * @dev_priv: driver private
195 * @mask: bits to update
196 * @bits: bits to enable
197 * NOTE: the HPD enable bits are modified both inside and outside
198 * of an interrupt context. To avoid that read-modify-write cycles
199 * interfer, these bits are protected by a spinlock. Since this
200 * function is usually not called from a context where the lock is
201 * held already, this function acquires the lock itself. A non-locking
202 * version is also available.
203 */
i915_hotplug_interrupt_update(struct drm_i915_private * dev_priv,u32 mask,u32 bits)204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
205 u32 mask,
206 u32 bits)
207 {
208 spin_lock_irq(&dev_priv->irq_lock);
209 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
210 spin_unlock_irq(&dev_priv->irq_lock);
211 }
212
gen11_port_hotplug_long_detect(enum hpd_pin pin,u32 val)213 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
214 {
215 switch (pin) {
216 case HPD_PORT_TC1:
217 case HPD_PORT_TC2:
218 case HPD_PORT_TC3:
219 case HPD_PORT_TC4:
220 case HPD_PORT_TC5:
221 case HPD_PORT_TC6:
222 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
223 default:
224 return false;
225 }
226 }
227
bxt_port_hotplug_long_detect(enum hpd_pin pin,u32 val)228 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
229 {
230 switch (pin) {
231 case HPD_PORT_A:
232 return val & PORTA_HOTPLUG_LONG_DETECT;
233 case HPD_PORT_B:
234 return val & PORTB_HOTPLUG_LONG_DETECT;
235 case HPD_PORT_C:
236 return val & PORTC_HOTPLUG_LONG_DETECT;
237 default:
238 return false;
239 }
240 }
241
icp_ddi_port_hotplug_long_detect(enum hpd_pin pin,u32 val)242 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
243 {
244 switch (pin) {
245 case HPD_PORT_A:
246 case HPD_PORT_B:
247 case HPD_PORT_C:
248 case HPD_PORT_D:
249 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
250 default:
251 return false;
252 }
253 }
254
icp_tc_port_hotplug_long_detect(enum hpd_pin pin,u32 val)255 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
256 {
257 switch (pin) {
258 case HPD_PORT_TC1:
259 case HPD_PORT_TC2:
260 case HPD_PORT_TC3:
261 case HPD_PORT_TC4:
262 case HPD_PORT_TC5:
263 case HPD_PORT_TC6:
264 return val & ICP_TC_HPD_LONG_DETECT(pin);
265 default:
266 return false;
267 }
268 }
269
spt_port_hotplug2_long_detect(enum hpd_pin pin,u32 val)270 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
271 {
272 switch (pin) {
273 case HPD_PORT_E:
274 return val & PORTE_HOTPLUG_LONG_DETECT;
275 default:
276 return false;
277 }
278 }
279
spt_port_hotplug_long_detect(enum hpd_pin pin,u32 val)280 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
281 {
282 switch (pin) {
283 case HPD_PORT_A:
284 return val & PORTA_HOTPLUG_LONG_DETECT;
285 case HPD_PORT_B:
286 return val & PORTB_HOTPLUG_LONG_DETECT;
287 case HPD_PORT_C:
288 return val & PORTC_HOTPLUG_LONG_DETECT;
289 case HPD_PORT_D:
290 return val & PORTD_HOTPLUG_LONG_DETECT;
291 default:
292 return false;
293 }
294 }
295
ilk_port_hotplug_long_detect(enum hpd_pin pin,u32 val)296 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
297 {
298 switch (pin) {
299 case HPD_PORT_A:
300 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
301 default:
302 return false;
303 }
304 }
305
pch_port_hotplug_long_detect(enum hpd_pin pin,u32 val)306 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
307 {
308 switch (pin) {
309 case HPD_PORT_B:
310 return val & PORTB_HOTPLUG_LONG_DETECT;
311 case HPD_PORT_C:
312 return val & PORTC_HOTPLUG_LONG_DETECT;
313 case HPD_PORT_D:
314 return val & PORTD_HOTPLUG_LONG_DETECT;
315 default:
316 return false;
317 }
318 }
319
i9xx_port_hotplug_long_detect(enum hpd_pin pin,u32 val)320 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
321 {
322 switch (pin) {
323 case HPD_PORT_B:
324 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
325 case HPD_PORT_C:
326 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
327 case HPD_PORT_D:
328 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
329 default:
330 return false;
331 }
332 }
333
334 /*
335 * Get a bit mask of pins that have triggered, and which ones may be long.
336 * This can be called multiple times with the same masks to accumulate
337 * hotplug detection results from several registers.
338 *
339 * Note that the caller is expected to zero out the masks initially.
340 */
intel_get_hpd_pins(struct drm_i915_private * dev_priv,u32 * pin_mask,u32 * long_mask,u32 hotplug_trigger,u32 dig_hotplug_reg,const u32 hpd[HPD_NUM_PINS],bool long_pulse_detect (enum hpd_pin pin,u32 val))341 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
342 u32 *pin_mask, u32 *long_mask,
343 u32 hotplug_trigger, u32 dig_hotplug_reg,
344 const u32 hpd[HPD_NUM_PINS],
345 bool long_pulse_detect(enum hpd_pin pin, u32 val))
346 {
347 enum hpd_pin pin;
348
349 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
350
351 for_each_hpd_pin(pin) {
352 if ((hpd[pin] & hotplug_trigger) == 0)
353 continue;
354
355 *pin_mask |= BIT(pin);
356
357 if (long_pulse_detect(pin, dig_hotplug_reg))
358 *long_mask |= BIT(pin);
359 }
360
361 drm_dbg(&dev_priv->drm,
362 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
363 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
364 }
365
intel_hpd_enabled_irqs(struct drm_i915_private * dev_priv,const u32 hpd[HPD_NUM_PINS])366 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
367 const u32 hpd[HPD_NUM_PINS])
368 {
369 struct intel_encoder *encoder;
370 u32 enabled_irqs = 0;
371
372 for_each_intel_encoder(&dev_priv->drm, encoder)
373 if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
374 enabled_irqs |= hpd[encoder->hpd_pin];
375
376 return enabled_irqs;
377 }
378
intel_hpd_hotplug_irqs(struct drm_i915_private * dev_priv,const u32 hpd[HPD_NUM_PINS])379 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
380 const u32 hpd[HPD_NUM_PINS])
381 {
382 struct intel_encoder *encoder;
383 u32 hotplug_irqs = 0;
384
385 for_each_intel_encoder(&dev_priv->drm, encoder)
386 hotplug_irqs |= hpd[encoder->hpd_pin];
387
388 return hotplug_irqs;
389 }
390
intel_hpd_hotplug_mask(struct drm_i915_private * i915,hotplug_mask_func hotplug_mask)391 static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915,
392 hotplug_mask_func hotplug_mask)
393 {
394 enum hpd_pin pin;
395 u32 hotplug = 0;
396
397 for_each_hpd_pin(pin)
398 hotplug |= hotplug_mask(pin);
399
400 return hotplug;
401 }
402
intel_hpd_hotplug_enables(struct drm_i915_private * i915,hotplug_enables_func hotplug_enables)403 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
404 hotplug_enables_func hotplug_enables)
405 {
406 struct intel_encoder *encoder;
407 u32 hotplug = 0;
408
409 for_each_intel_encoder(&i915->drm, encoder)
410 hotplug |= hotplug_enables(encoder);
411
412 return hotplug;
413 }
414
i9xx_hpd_irq_ack(struct drm_i915_private * dev_priv)415 u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
416 {
417 u32 hotplug_status = 0, hotplug_status_mask;
418 int i;
419
420 if (IS_G4X(dev_priv) ||
421 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
422 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
423 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
424 else
425 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
426
427 /*
428 * We absolutely have to clear all the pending interrupt
429 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
430 * interrupt bit won't have an edge, and the i965/g4x
431 * edge triggered IIR will not notice that an interrupt
432 * is still pending. We can't use PORT_HOTPLUG_EN to
433 * guarantee the edge as the act of toggling the enable
434 * bits can itself generate a new hotplug interrupt :(
435 */
436 for (i = 0; i < 10; i++) {
437 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
438
439 if (tmp == 0)
440 return hotplug_status;
441
442 hotplug_status |= tmp;
443 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
444 }
445
446 drm_WARN_ONCE(&dev_priv->drm, 1,
447 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
448 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
449
450 return hotplug_status;
451 }
452
i9xx_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_status)453 void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status)
454 {
455 u32 pin_mask = 0, long_mask = 0;
456 u32 hotplug_trigger;
457
458 if (IS_G4X(dev_priv) ||
459 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
460 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
461 else
462 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
463
464 if (hotplug_trigger) {
465 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
466 hotplug_trigger, hotplug_trigger,
467 dev_priv->display.hotplug.hpd,
468 i9xx_port_hotplug_long_detect);
469
470 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
471 }
472
473 if ((IS_G4X(dev_priv) ||
474 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
475 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
476 intel_dp_aux_irq_handler(dev_priv);
477 }
478
ibx_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_trigger)479 void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
480 {
481 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
482
483 /*
484 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
485 * unless we touch the hotplug register, even if hotplug_trigger is
486 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
487 * errors.
488 */
489 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
490 if (!hotplug_trigger) {
491 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
492 PORTD_HOTPLUG_STATUS_MASK |
493 PORTC_HOTPLUG_STATUS_MASK |
494 PORTB_HOTPLUG_STATUS_MASK;
495 dig_hotplug_reg &= ~mask;
496 }
497
498 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
499 if (!hotplug_trigger)
500 return;
501
502 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
503 hotplug_trigger, dig_hotplug_reg,
504 dev_priv->display.hotplug.pch_hpd,
505 pch_port_hotplug_long_detect);
506
507 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
508 }
509
xelpdp_pica_irq_handler(struct drm_i915_private * i915,u32 iir)510 void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
511 {
512 enum hpd_pin pin;
513 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);
514 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
515 u32 pin_mask = 0, long_mask = 0;
516
517 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
518 u32 val;
519
520 if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger))
521 continue;
522
523 pin_mask |= BIT(pin);
524
525 val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin));
526 intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val);
527
528 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
529 long_mask |= BIT(pin);
530 }
531
532 if (pin_mask) {
533 drm_dbg(&i915->drm,
534 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
535 hotplug_trigger, pin_mask, long_mask);
536
537 intel_hpd_irq_handler(i915, pin_mask, long_mask);
538 }
539
540 if (trigger_aux)
541 intel_dp_aux_irq_handler(i915);
542
543 if (!pin_mask && !trigger_aux)
544 drm_err(&i915->drm,
545 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
546 }
547
icp_irq_handler(struct drm_i915_private * dev_priv,u32 pch_iir)548 void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
549 {
550 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
551 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
552 u32 pin_mask = 0, long_mask = 0;
553
554 if (ddi_hotplug_trigger) {
555 u32 dig_hotplug_reg;
556
557 /* Locking due to DSI native GPIO sequences */
558 spin_lock(&dev_priv->irq_lock);
559 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 0, 0);
560 spin_unlock(&dev_priv->irq_lock);
561
562 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
563 ddi_hotplug_trigger, dig_hotplug_reg,
564 dev_priv->display.hotplug.pch_hpd,
565 icp_ddi_port_hotplug_long_detect);
566 }
567
568 if (tc_hotplug_trigger) {
569 u32 dig_hotplug_reg;
570
571 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC, 0, 0);
572
573 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
574 tc_hotplug_trigger, dig_hotplug_reg,
575 dev_priv->display.hotplug.pch_hpd,
576 icp_tc_port_hotplug_long_detect);
577 }
578
579 if (pin_mask)
580 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
581
582 if (pch_iir & SDE_GMBUS_ICP)
583 intel_gmbus_irq_handler(dev_priv);
584 }
585
spt_irq_handler(struct drm_i915_private * dev_priv,u32 pch_iir)586 void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
587 {
588 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
589 ~SDE_PORTE_HOTPLUG_SPT;
590 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
591 u32 pin_mask = 0, long_mask = 0;
592
593 if (hotplug_trigger) {
594 u32 dig_hotplug_reg;
595
596 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
597
598 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
599 hotplug_trigger, dig_hotplug_reg,
600 dev_priv->display.hotplug.pch_hpd,
601 spt_port_hotplug_long_detect);
602 }
603
604 if (hotplug2_trigger) {
605 u32 dig_hotplug_reg;
606
607 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2, 0, 0);
608
609 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
610 hotplug2_trigger, dig_hotplug_reg,
611 dev_priv->display.hotplug.pch_hpd,
612 spt_port_hotplug2_long_detect);
613 }
614
615 if (pin_mask)
616 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
617
618 if (pch_iir & SDE_GMBUS_CPT)
619 intel_gmbus_irq_handler(dev_priv);
620 }
621
ilk_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_trigger)622 void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
623 {
624 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
625
626 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0);
627
628 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
629 hotplug_trigger, dig_hotplug_reg,
630 dev_priv->display.hotplug.hpd,
631 ilk_port_hotplug_long_detect);
632
633 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
634 }
635
bxt_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 hotplug_trigger)636 void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
637 {
638 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
639
640 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG, 0, 0);
641
642 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
643 hotplug_trigger, dig_hotplug_reg,
644 dev_priv->display.hotplug.hpd,
645 bxt_port_hotplug_long_detect);
646
647 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
648 }
649
gen11_hpd_irq_handler(struct drm_i915_private * dev_priv,u32 iir)650 void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
651 {
652 u32 pin_mask = 0, long_mask = 0;
653 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
654 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
655
656 if (trigger_tc) {
657 u32 dig_hotplug_reg;
658
659 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, 0, 0);
660
661 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
662 trigger_tc, dig_hotplug_reg,
663 dev_priv->display.hotplug.hpd,
664 gen11_port_hotplug_long_detect);
665 }
666
667 if (trigger_tbt) {
668 u32 dig_hotplug_reg;
669
670 dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, 0, 0);
671
672 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
673 trigger_tbt, dig_hotplug_reg,
674 dev_priv->display.hotplug.hpd,
675 gen11_port_hotplug_long_detect);
676 }
677
678 if (pin_mask)
679 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
680 else
681 drm_err(&dev_priv->drm,
682 "Unexpected DE HPD interrupt 0x%08x\n", iir);
683 }
684
ibx_hotplug_mask(enum hpd_pin hpd_pin)685 static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin)
686 {
687 switch (hpd_pin) {
688 case HPD_PORT_A:
689 return PORTA_HOTPLUG_ENABLE;
690 case HPD_PORT_B:
691 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK;
692 case HPD_PORT_C:
693 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK;
694 case HPD_PORT_D:
695 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK;
696 default:
697 return 0;
698 }
699 }
700
ibx_hotplug_enables(struct intel_encoder * encoder)701 static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
702 {
703 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
704
705 switch (encoder->hpd_pin) {
706 case HPD_PORT_A:
707 /*
708 * When CPU and PCH are on the same package, port A
709 * HPD must be enabled in both north and south.
710 */
711 return HAS_PCH_LPT_LP(i915) ?
712 PORTA_HOTPLUG_ENABLE : 0;
713 case HPD_PORT_B:
714 return PORTB_HOTPLUG_ENABLE |
715 PORTB_PULSE_DURATION_2ms;
716 case HPD_PORT_C:
717 return PORTC_HOTPLUG_ENABLE |
718 PORTC_PULSE_DURATION_2ms;
719 case HPD_PORT_D:
720 return PORTD_HOTPLUG_ENABLE |
721 PORTD_PULSE_DURATION_2ms;
722 default:
723 return 0;
724 }
725 }
726
ibx_hpd_detection_setup(struct drm_i915_private * dev_priv)727 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
728 {
729 /*
730 * Enable digital hotplug on the PCH, and configure the DP short pulse
731 * duration to 2ms (which is the minimum in the Display Port spec).
732 * The pulse duration bits are reserved on LPT+.
733 */
734 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
735 intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask),
736 intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables));
737 }
738
ibx_hpd_enable_detection(struct intel_encoder * encoder)739 static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
740 {
741 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
742
743 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
744 ibx_hotplug_mask(encoder->hpd_pin),
745 ibx_hotplug_enables(encoder));
746 }
747
ibx_hpd_irq_setup(struct drm_i915_private * dev_priv)748 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
749 {
750 u32 hotplug_irqs, enabled_irqs;
751
752 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
753 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
754
755 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
756
757 ibx_hpd_detection_setup(dev_priv);
758 }
759
icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)760 static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
761 {
762 switch (hpd_pin) {
763 case HPD_PORT_A:
764 case HPD_PORT_B:
765 case HPD_PORT_C:
766 case HPD_PORT_D:
767 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
768 default:
769 return 0;
770 }
771 }
772
icp_ddi_hotplug_enables(struct intel_encoder * encoder)773 static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder)
774 {
775 return icp_ddi_hotplug_mask(encoder->hpd_pin);
776 }
777
icp_tc_hotplug_mask(enum hpd_pin hpd_pin)778 static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin)
779 {
780 switch (hpd_pin) {
781 case HPD_PORT_TC1:
782 case HPD_PORT_TC2:
783 case HPD_PORT_TC3:
784 case HPD_PORT_TC4:
785 case HPD_PORT_TC5:
786 case HPD_PORT_TC6:
787 return ICP_TC_HPD_ENABLE(hpd_pin);
788 default:
789 return 0;
790 }
791 }
792
icp_tc_hotplug_enables(struct intel_encoder * encoder)793 static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
794 {
795 return icp_tc_hotplug_mask(encoder->hpd_pin);
796 }
797
icp_ddi_hpd_detection_setup(struct drm_i915_private * dev_priv)798 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
799 {
800 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI,
801 intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask),
802 intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables));
803 }
804
icp_ddi_hpd_enable_detection(struct intel_encoder * encoder)805 static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
806 {
807 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
808
809 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_DDI,
810 icp_ddi_hotplug_mask(encoder->hpd_pin),
811 icp_ddi_hotplug_enables(encoder));
812 }
813
icp_tc_hpd_detection_setup(struct drm_i915_private * dev_priv)814 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
815 {
816 intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_TC,
817 intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask),
818 intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables));
819 }
820
icp_tc_hpd_enable_detection(struct intel_encoder * encoder)821 static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
822 {
823 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
824
825 intel_uncore_rmw(&i915->uncore, SHOTPLUG_CTL_TC,
826 icp_tc_hotplug_mask(encoder->hpd_pin),
827 icp_tc_hotplug_enables(encoder));
828 }
829
icp_hpd_enable_detection(struct intel_encoder * encoder)830 static void icp_hpd_enable_detection(struct intel_encoder *encoder)
831 {
832 icp_ddi_hpd_enable_detection(encoder);
833 icp_tc_hpd_enable_detection(encoder);
834 }
835
icp_hpd_irq_setup(struct drm_i915_private * dev_priv)836 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
837 {
838 u32 hotplug_irqs, enabled_irqs;
839
840 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
841 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
842
843 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
844 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
845 else
846 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
847
848 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
849
850 icp_ddi_hpd_detection_setup(dev_priv);
851 icp_tc_hpd_detection_setup(dev_priv);
852 }
853
gen11_hotplug_mask(enum hpd_pin hpd_pin)854 static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
855 {
856 switch (hpd_pin) {
857 case HPD_PORT_TC1:
858 case HPD_PORT_TC2:
859 case HPD_PORT_TC3:
860 case HPD_PORT_TC4:
861 case HPD_PORT_TC5:
862 case HPD_PORT_TC6:
863 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin);
864 default:
865 return 0;
866 }
867 }
868
gen11_hotplug_enables(struct intel_encoder * encoder)869 static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
870 {
871 return gen11_hotplug_mask(encoder->hpd_pin);
872 }
873
dg1_hpd_invert(struct drm_i915_private * i915)874 static void dg1_hpd_invert(struct drm_i915_private *i915)
875 {
876 u32 val = (INVERT_DDIA_HPD |
877 INVERT_DDIB_HPD |
878 INVERT_DDIC_HPD |
879 INVERT_DDID_HPD);
880 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
881 }
882
dg1_hpd_enable_detection(struct intel_encoder * encoder)883 static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
884 {
885 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
886
887 dg1_hpd_invert(i915);
888 icp_hpd_enable_detection(encoder);
889 }
890
dg1_hpd_irq_setup(struct drm_i915_private * dev_priv)891 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
892 {
893 dg1_hpd_invert(dev_priv);
894 icp_hpd_irq_setup(dev_priv);
895 }
896
gen11_tc_hpd_detection_setup(struct drm_i915_private * dev_priv)897 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
898 {
899 intel_uncore_rmw(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL,
900 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
901 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
902 }
903
gen11_tc_hpd_enable_detection(struct intel_encoder * encoder)904 static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
905 {
906 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
907
908 intel_uncore_rmw(&i915->uncore, GEN11_TC_HOTPLUG_CTL,
909 gen11_hotplug_mask(encoder->hpd_pin),
910 gen11_hotplug_enables(encoder));
911 }
912
gen11_tbt_hpd_detection_setup(struct drm_i915_private * dev_priv)913 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
914 {
915 intel_uncore_rmw(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL,
916 intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask),
917 intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables));
918 }
919
gen11_tbt_hpd_enable_detection(struct intel_encoder * encoder)920 static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
921 {
922 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
923
924 intel_uncore_rmw(&i915->uncore, GEN11_TBT_HOTPLUG_CTL,
925 gen11_hotplug_mask(encoder->hpd_pin),
926 gen11_hotplug_enables(encoder));
927 }
928
gen11_hpd_enable_detection(struct intel_encoder * encoder)929 static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
930 {
931 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
932
933 gen11_tc_hpd_enable_detection(encoder);
934 gen11_tbt_hpd_enable_detection(encoder);
935
936 if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
937 icp_hpd_enable_detection(encoder);
938 }
939
gen11_hpd_irq_setup(struct drm_i915_private * dev_priv)940 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
941 {
942 u32 hotplug_irqs, enabled_irqs;
943
944 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
945 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
946
947 intel_uncore_rmw(&dev_priv->uncore, GEN11_DE_HPD_IMR, hotplug_irqs,
948 ~enabled_irqs & hotplug_irqs);
949 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
950
951 gen11_tc_hpd_detection_setup(dev_priv);
952 gen11_tbt_hpd_detection_setup(dev_priv);
953
954 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
955 icp_hpd_irq_setup(dev_priv);
956 }
957
mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)958 static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
959 {
960 switch (hpd_pin) {
961 case HPD_PORT_A:
962 case HPD_PORT_B:
963 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
964 default:
965 return 0;
966 }
967 }
968
mtp_ddi_hotplug_enables(struct intel_encoder * encoder)969 static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder)
970 {
971 return mtp_ddi_hotplug_mask(encoder->hpd_pin);
972 }
973
mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)974 static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)
975 {
976 switch (hpd_pin) {
977 case HPD_PORT_TC1:
978 case HPD_PORT_TC2:
979 case HPD_PORT_TC3:
980 case HPD_PORT_TC4:
981 return ICP_TC_HPD_ENABLE(hpd_pin);
982 default:
983 return 0;
984 }
985 }
986
mtp_tc_hotplug_enables(struct intel_encoder * encoder)987 static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder)
988 {
989 return mtp_tc_hotplug_mask(encoder->hpd_pin);
990 }
991
mtp_ddi_hpd_detection_setup(struct drm_i915_private * i915)992 static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915)
993 {
994 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
995 intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask),
996 intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables));
997 }
998
mtp_ddi_hpd_enable_detection(struct intel_encoder * encoder)999 static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
1000 {
1001 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1002
1003 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1004 mtp_ddi_hotplug_mask(encoder->hpd_pin),
1005 mtp_ddi_hotplug_enables(encoder));
1006 }
1007
mtp_tc_hpd_detection_setup(struct drm_i915_private * i915)1008 static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915)
1009 {
1010 intel_de_rmw(i915, SHOTPLUG_CTL_TC,
1011 intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask),
1012 intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables));
1013 }
1014
mtp_tc_hpd_enable_detection(struct intel_encoder * encoder)1015 static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder)
1016 {
1017 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1018
1019 intel_de_rmw(i915, SHOTPLUG_CTL_DDI,
1020 mtp_tc_hotplug_mask(encoder->hpd_pin),
1021 mtp_tc_hotplug_enables(encoder));
1022 }
1023
mtp_hpd_invert(struct drm_i915_private * i915)1024 static void mtp_hpd_invert(struct drm_i915_private *i915)
1025 {
1026 u32 val = (INVERT_DDIA_HPD |
1027 INVERT_DDIB_HPD |
1028 INVERT_DDIC_HPD |
1029 INVERT_TC1_HPD |
1030 INVERT_TC2_HPD |
1031 INVERT_TC3_HPD |
1032 INVERT_TC4_HPD |
1033 INVERT_DDID_HPD_MTP |
1034 INVERT_DDIE_HPD);
1035 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val);
1036 }
1037
mtp_hpd_enable_detection(struct intel_encoder * encoder)1038 static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
1039 {
1040 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1041
1042 mtp_hpd_invert(i915);
1043 mtp_ddi_hpd_enable_detection(encoder);
1044 mtp_tc_hpd_enable_detection(encoder);
1045 }
1046
mtp_hpd_irq_setup(struct drm_i915_private * i915)1047 static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
1048 {
1049 u32 hotplug_irqs, enabled_irqs;
1050
1051 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
1052 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
1053
1054 intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
1055
1056 mtp_hpd_invert(i915);
1057 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
1058
1059 mtp_ddi_hpd_detection_setup(i915);
1060 mtp_tc_hpd_detection_setup(i915);
1061 }
1062
is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)1063 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
1064 {
1065 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
1066 }
1067
_xelpdp_pica_hpd_detection_setup(struct drm_i915_private * i915,enum hpd_pin hpd_pin,bool enable)1068 static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915,
1069 enum hpd_pin hpd_pin, bool enable)
1070 {
1071 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |
1072 XELPDP_DP_ALT_HOTPLUG_ENABLE;
1073
1074 if (!is_xelpdp_pica_hpd_pin(hpd_pin))
1075 return;
1076
1077 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
1078 mask, enable ? mask : 0);
1079 }
1080
xelpdp_pica_hpd_enable_detection(struct intel_encoder * encoder)1081 static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder)
1082 {
1083 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1084
1085 _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true);
1086 }
1087
xelpdp_pica_hpd_detection_setup(struct drm_i915_private * i915)1088 static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915)
1089 {
1090 struct intel_encoder *encoder;
1091 u32 available_pins = 0;
1092 enum hpd_pin pin;
1093
1094 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
1095
1096 for_each_intel_encoder(&i915->drm, encoder)
1097 available_pins |= BIT(encoder->hpd_pin);
1098
1099 for_each_hpd_pin(pin)
1100 _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins & BIT(pin));
1101 }
1102
xelpdp_hpd_enable_detection(struct intel_encoder * encoder)1103 static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
1104 {
1105 xelpdp_pica_hpd_enable_detection(encoder);
1106 mtp_hpd_enable_detection(encoder);
1107 }
1108
xelpdp_hpd_irq_setup(struct drm_i915_private * i915)1109 static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
1110 {
1111 u32 hotplug_irqs, enabled_irqs;
1112
1113 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd);
1114 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd);
1115
1116 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs,
1117 ~enabled_irqs & hotplug_irqs);
1118 intel_uncore_posting_read(&i915->uncore, PICAINTERRUPT_IMR);
1119
1120 xelpdp_pica_hpd_detection_setup(i915);
1121
1122 if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
1123 mtp_hpd_irq_setup(i915);
1124 }
1125
spt_hotplug_mask(enum hpd_pin hpd_pin)1126 static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
1127 {
1128 switch (hpd_pin) {
1129 case HPD_PORT_A:
1130 return PORTA_HOTPLUG_ENABLE;
1131 case HPD_PORT_B:
1132 return PORTB_HOTPLUG_ENABLE;
1133 case HPD_PORT_C:
1134 return PORTC_HOTPLUG_ENABLE;
1135 case HPD_PORT_D:
1136 return PORTD_HOTPLUG_ENABLE;
1137 default:
1138 return 0;
1139 }
1140 }
1141
spt_hotplug_enables(struct intel_encoder * encoder)1142 static u32 spt_hotplug_enables(struct intel_encoder *encoder)
1143 {
1144 return spt_hotplug_mask(encoder->hpd_pin);
1145 }
1146
spt_hotplug2_mask(enum hpd_pin hpd_pin)1147 static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin)
1148 {
1149 switch (hpd_pin) {
1150 case HPD_PORT_E:
1151 return PORTE_HOTPLUG_ENABLE;
1152 default:
1153 return 0;
1154 }
1155 }
1156
spt_hotplug2_enables(struct intel_encoder * encoder)1157 static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
1158 {
1159 return spt_hotplug2_mask(encoder->hpd_pin);
1160 }
1161
spt_hpd_detection_setup(struct drm_i915_private * dev_priv)1162 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1163 {
1164 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1165 if (HAS_PCH_CNP(dev_priv)) {
1166 intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
1167 CHASSIS_CLK_REQ_DURATION(0xf));
1168 }
1169
1170 /* Enable digital hotplug on the PCH */
1171 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1172 intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask),
1173 intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables));
1174
1175 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG2,
1176 intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask),
1177 intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables));
1178 }
1179
spt_hpd_enable_detection(struct intel_encoder * encoder)1180 static void spt_hpd_enable_detection(struct intel_encoder *encoder)
1181 {
1182 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1183
1184 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1185 if (HAS_PCH_CNP(i915)) {
1186 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1,
1187 CHASSIS_CLK_REQ_DURATION_MASK,
1188 CHASSIS_CLK_REQ_DURATION(0xf));
1189 }
1190
1191 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1192 spt_hotplug_mask(encoder->hpd_pin),
1193 spt_hotplug_enables(encoder));
1194
1195 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG2,
1196 spt_hotplug2_mask(encoder->hpd_pin),
1197 spt_hotplug2_enables(encoder));
1198 }
1199
spt_hpd_irq_setup(struct drm_i915_private * dev_priv)1200 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1201 {
1202 u32 hotplug_irqs, enabled_irqs;
1203
1204 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1205 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
1206
1207 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1208 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
1209
1210 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
1211
1212 spt_hpd_detection_setup(dev_priv);
1213 }
1214
ilk_hotplug_mask(enum hpd_pin hpd_pin)1215 static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
1216 {
1217 switch (hpd_pin) {
1218 case HPD_PORT_A:
1219 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1220 DIGITAL_PORTA_PULSE_DURATION_MASK;
1221 default:
1222 return 0;
1223 }
1224 }
1225
ilk_hotplug_enables(struct intel_encoder * encoder)1226 static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
1227 {
1228 switch (encoder->hpd_pin) {
1229 case HPD_PORT_A:
1230 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1231 DIGITAL_PORTA_PULSE_DURATION_2ms;
1232 default:
1233 return 0;
1234 }
1235 }
1236
ilk_hpd_detection_setup(struct drm_i915_private * dev_priv)1237 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
1238 {
1239 /*
1240 * Enable digital hotplug on the CPU, and configure the DP short pulse
1241 * duration to 2ms (which is the minimum in the Display Port spec)
1242 * The pulse duration bits are reserved on HSW+.
1243 */
1244 intel_uncore_rmw(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1245 intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask),
1246 intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables));
1247 }
1248
ilk_hpd_enable_detection(struct intel_encoder * encoder)1249 static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
1250 {
1251 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1252
1253 intel_uncore_rmw(&i915->uncore, DIGITAL_PORT_HOTPLUG_CNTRL,
1254 ilk_hotplug_mask(encoder->hpd_pin),
1255 ilk_hotplug_enables(encoder));
1256
1257 ibx_hpd_enable_detection(encoder);
1258 }
1259
ilk_hpd_irq_setup(struct drm_i915_private * dev_priv)1260 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
1261 {
1262 u32 hotplug_irqs, enabled_irqs;
1263
1264 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1265 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1266
1267 if (DISPLAY_VER(dev_priv) >= 8)
1268 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1269 else
1270 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
1271
1272 ilk_hpd_detection_setup(dev_priv);
1273
1274 ibx_hpd_irq_setup(dev_priv);
1275 }
1276
bxt_hotplug_mask(enum hpd_pin hpd_pin)1277 static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
1278 {
1279 switch (hpd_pin) {
1280 case HPD_PORT_A:
1281 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT;
1282 case HPD_PORT_B:
1283 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT;
1284 case HPD_PORT_C:
1285 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT;
1286 default:
1287 return 0;
1288 }
1289 }
1290
bxt_hotplug_enables(struct intel_encoder * encoder)1291 static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
1292 {
1293 u32 hotplug;
1294
1295 switch (encoder->hpd_pin) {
1296 case HPD_PORT_A:
1297 hotplug = PORTA_HOTPLUG_ENABLE;
1298 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1299 hotplug |= BXT_DDIA_HPD_INVERT;
1300 return hotplug;
1301 case HPD_PORT_B:
1302 hotplug = PORTB_HOTPLUG_ENABLE;
1303 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1304 hotplug |= BXT_DDIB_HPD_INVERT;
1305 return hotplug;
1306 case HPD_PORT_C:
1307 hotplug = PORTC_HOTPLUG_ENABLE;
1308 if (intel_bios_encoder_hpd_invert(encoder->devdata))
1309 hotplug |= BXT_DDIC_HPD_INVERT;
1310 return hotplug;
1311 default:
1312 return 0;
1313 }
1314 }
1315
bxt_hpd_detection_setup(struct drm_i915_private * dev_priv)1316 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
1317 {
1318 intel_uncore_rmw(&dev_priv->uncore, PCH_PORT_HOTPLUG,
1319 intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask),
1320 intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables));
1321 }
1322
bxt_hpd_enable_detection(struct intel_encoder * encoder)1323 static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
1324 {
1325 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1326
1327 intel_uncore_rmw(&i915->uncore, PCH_PORT_HOTPLUG,
1328 bxt_hotplug_mask(encoder->hpd_pin),
1329 bxt_hotplug_enables(encoder));
1330 }
1331
bxt_hpd_irq_setup(struct drm_i915_private * dev_priv)1332 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
1333 {
1334 u32 hotplug_irqs, enabled_irqs;
1335
1336 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1337 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
1338
1339 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
1340
1341 bxt_hpd_detection_setup(dev_priv);
1342 }
1343
i915_hpd_enable_detection(struct intel_encoder * encoder)1344 static void i915_hpd_enable_detection(struct intel_encoder *encoder)
1345 {
1346 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1347 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
1348
1349 /* HPD sense and interrupt enable are one and the same */
1350 i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en);
1351 }
1352
i915_hpd_irq_setup(struct drm_i915_private * dev_priv)1353 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
1354 {
1355 u32 hotplug_en;
1356
1357 lockdep_assert_held(&dev_priv->irq_lock);
1358
1359 /*
1360 * Note HDMI and DP share hotplug bits. Enable bits are the same for all
1361 * generations.
1362 */
1363 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
1364 /*
1365 * Programming the CRT detection parameters tends to generate a spurious
1366 * hotplug event about three seconds later. So just do it once.
1367 */
1368 if (IS_G4X(dev_priv))
1369 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1370 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1371
1372 /* Ignore TV since it's buggy */
1373 i915_hotplug_interrupt_update_locked(dev_priv,
1374 HOTPLUG_INT_EN_MASK |
1375 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
1376 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
1377 hotplug_en);
1378 }
1379
1380 struct intel_hotplug_funcs {
1381 /* Enable HPD sense and interrupts for all present encoders */
1382 void (*hpd_irq_setup)(struct drm_i915_private *i915);
1383 /* Enable HPD sense for a single encoder */
1384 void (*hpd_enable_detection)(struct intel_encoder *encoder);
1385 };
1386
1387 #define HPD_FUNCS(platform) \
1388 static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
1389 .hpd_irq_setup = platform##_hpd_irq_setup, \
1390 .hpd_enable_detection = platform##_hpd_enable_detection, \
1391 }
1392
1393 HPD_FUNCS(i915);
1394 HPD_FUNCS(xelpdp);
1395 HPD_FUNCS(dg1);
1396 HPD_FUNCS(gen11);
1397 HPD_FUNCS(bxt);
1398 HPD_FUNCS(icp);
1399 HPD_FUNCS(spt);
1400 HPD_FUNCS(ilk);
1401 #undef HPD_FUNCS
1402
intel_hpd_enable_detection(struct intel_encoder * encoder)1403 void intel_hpd_enable_detection(struct intel_encoder *encoder)
1404 {
1405 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1406
1407 if (i915->display.funcs.hotplug)
1408 i915->display.funcs.hotplug->hpd_enable_detection(encoder);
1409 }
1410
intel_hpd_irq_setup(struct drm_i915_private * i915)1411 void intel_hpd_irq_setup(struct drm_i915_private *i915)
1412 {
1413 if (i915->display_irqs_enabled && i915->display.funcs.hotplug)
1414 i915->display.funcs.hotplug->hpd_irq_setup(i915);
1415 }
1416
intel_hotplug_irq_init(struct drm_i915_private * i915)1417 void intel_hotplug_irq_init(struct drm_i915_private *i915)
1418 {
1419 intel_hpd_init_pins(i915);
1420
1421 intel_hpd_init_early(i915);
1422
1423 if (HAS_GMCH(i915)) {
1424 if (I915_HAS_HOTPLUG(i915))
1425 i915->display.funcs.hotplug = &i915_hpd_funcs;
1426 } else {
1427 if (HAS_PCH_DG2(i915))
1428 i915->display.funcs.hotplug = &icp_hpd_funcs;
1429 else if (HAS_PCH_DG1(i915))
1430 i915->display.funcs.hotplug = &dg1_hpd_funcs;
1431 else if (DISPLAY_VER(i915) >= 14)
1432 i915->display.funcs.hotplug = &xelpdp_hpd_funcs;
1433 else if (DISPLAY_VER(i915) >= 11)
1434 i915->display.funcs.hotplug = &gen11_hpd_funcs;
1435 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1436 i915->display.funcs.hotplug = &bxt_hpd_funcs;
1437 else if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
1438 i915->display.funcs.hotplug = &icp_hpd_funcs;
1439 else if (INTEL_PCH_TYPE(i915) >= PCH_SPT)
1440 i915->display.funcs.hotplug = &spt_hpd_funcs;
1441 else
1442 i915->display.funcs.hotplug = &ilk_hpd_funcs;
1443 }
1444 }
1445