1 /* 2 * QEMU CXL Support 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_H 11 #define CXL_H 12 13 14 #include "qapi/qapi-types-machine.h" 15 #include "qapi/qapi-visit-machine.h" 16 #include "hw/pci/pci_host.h" 17 #include "cxl_pci.h" 18 #include "cxl_component.h" 19 #include "cxl_device.h" 20 21 #define CXL_CACHE_LINE_SIZE 64 22 #define CXL_COMPONENT_REG_BAR_IDX 0 23 #define CXL_DEVICE_REG_BAR_IDX 2 24 25 #define CXL_WINDOW_MAX 10 26 #define CXL_NUM_EXTENTS_SUPPORTED 512 27 28 typedef struct PXBCXLDev PXBCXLDev; 29 30 typedef struct CXLFixedWindow { 31 SysBusDevice parent_obj; 32 int index; 33 uint64_t size; 34 char **targets; 35 PXBCXLDev *target_hbs[16]; 36 uint8_t num_targets; 37 uint8_t enc_int_ways; 38 uint8_t enc_int_gran; 39 /* Todo: XOR based interleaving */ 40 MemoryRegion mr; 41 hwaddr base; 42 } CXLFixedWindow; 43 #define TYPE_CXL_FMW "cxl-fmw" 44 OBJECT_DECLARE_SIMPLE_TYPE(CXLFixedWindow, CXL_FMW) 45 46 typedef struct CXLState { 47 bool is_enabled; 48 MemoryRegion host_mr; 49 unsigned int next_mr_idx; 50 CXLFixedMemoryWindowOptionsList *cfmw_list; 51 } CXLState; 52 53 struct CXLHost { 54 PCIHostState parent_obj; 55 56 CXLComponentState cxl_cstate; 57 bool passthrough; 58 }; 59 60 #define TYPE_PXB_CXL_HOST "pxb-cxl-host" 61 OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST) 62 63 #define TYPE_CXL_USP "cxl-upstream" 64 65 typedef struct CXLUpstreamPort CXLUpstreamPort; 66 DECLARE_INSTANCE_CHECKER(CXLUpstreamPort, CXL_USP, TYPE_CXL_USP) 67 CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp); 68 69 #define TYPE_CXL_DSP "cxl-downstream" 70 71 typedef struct CXLDownstreamPort CXLDownstreamPort; 72 DECLARE_INSTANCE_CHECKER(CXLDownstreamPort, CXL_DSP, TYPE_CXL_DSP) 73 74 #endif 75