1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hnae3.h"
41 #include "hns_roce_common.h"
42 #include "hns_roce_device.h"
43 #include "hns_roce_hem.h"
44
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u32 port,const u8 * addr)45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
46 const u8 *addr)
47 {
48 u8 phy_port;
49 u32 i;
50
51 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
52 return 0;
53
54 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
55 return 0;
56
57 for (i = 0; i < ETH_ALEN; i++)
58 hr_dev->dev_addr[port][i] = addr[i];
59
60 phy_port = hr_dev->iboe.phy_port[port];
61 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
62 }
63
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)64 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
65 {
66 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
67 u32 port = attr->port_num - 1;
68 int ret;
69
70 if (port >= hr_dev->caps.num_ports)
71 return -EINVAL;
72
73 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
74
75 return ret;
76 }
77
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)78 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
79 {
80 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
81 u32 port = attr->port_num - 1;
82 int ret;
83
84 if (port >= hr_dev->caps.num_ports)
85 return -EINVAL;
86
87 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
88
89 return ret;
90 }
91
handle_en_event(struct hns_roce_dev * hr_dev,u32 port,unsigned long event)92 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
93 unsigned long event)
94 {
95 struct device *dev = hr_dev->dev;
96 struct net_device *netdev;
97 int ret = 0;
98
99 netdev = hr_dev->iboe.netdevs[port];
100 if (!netdev) {
101 dev_err(dev, "can't find netdev on port(%u)!\n", port);
102 return -ENODEV;
103 }
104
105 switch (event) {
106 case NETDEV_UP:
107 case NETDEV_CHANGE:
108 case NETDEV_REGISTER:
109 case NETDEV_CHANGEADDR:
110 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
111 break;
112 case NETDEV_DOWN:
113 /*
114 * In v1 engine, only support all ports closed together.
115 */
116 break;
117 default:
118 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
119 break;
120 }
121
122 return ret;
123 }
124
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)125 static int hns_roce_netdev_event(struct notifier_block *self,
126 unsigned long event, void *ptr)
127 {
128 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
129 struct hns_roce_ib_iboe *iboe = NULL;
130 struct hns_roce_dev *hr_dev = NULL;
131 int ret;
132 u32 port;
133
134 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
135 iboe = &hr_dev->iboe;
136
137 for (port = 0; port < hr_dev->caps.num_ports; port++) {
138 if (dev == iboe->netdevs[port]) {
139 ret = handle_en_event(hr_dev, port, event);
140 if (ret)
141 return NOTIFY_DONE;
142 break;
143 }
144 }
145
146 return NOTIFY_DONE;
147 }
148
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)149 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
150 {
151 int ret;
152 u8 i;
153
154 for (i = 0; i < hr_dev->caps.num_ports; i++) {
155 ret = hns_roce_set_mac(hr_dev, i,
156 hr_dev->iboe.netdevs[i]->dev_addr);
157 if (ret)
158 return ret;
159 }
160
161 return 0;
162 }
163
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)164 static int hns_roce_query_device(struct ib_device *ib_dev,
165 struct ib_device_attr *props,
166 struct ib_udata *uhw)
167 {
168 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
169
170 memset(props, 0, sizeof(*props));
171
172 props->fw_ver = hr_dev->caps.fw_ver;
173 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
174 props->max_mr_size = (u64)(~(0ULL));
175 props->page_size_cap = hr_dev->caps.page_size_cap;
176 props->vendor_id = hr_dev->vendor_id;
177 props->vendor_part_id = hr_dev->vendor_part_id;
178 props->hw_ver = hr_dev->hw_rev;
179 props->max_qp = hr_dev->caps.num_qps;
180 props->max_qp_wr = hr_dev->caps.max_wqes;
181 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
182 IB_DEVICE_RC_RNR_NAK_GEN;
183 props->max_send_sge = hr_dev->caps.max_sq_sg;
184 props->max_recv_sge = hr_dev->caps.max_rq_sg;
185 props->max_sge_rd = 1;
186 props->max_cq = hr_dev->caps.num_cqs;
187 props->max_cqe = hr_dev->caps.max_cqes;
188 props->max_mr = hr_dev->caps.num_mtpts;
189 props->max_pd = hr_dev->caps.num_pds;
190 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
191 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
192 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
193 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
194 props->max_pkeys = 1;
195 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
196 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
197 props->max_srq = hr_dev->caps.num_srqs;
198 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
199 props->max_srq_sge = hr_dev->caps.max_srq_sges;
200 }
201
202 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
203 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
204 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
205 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
206 }
207
208 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
209 props->device_cap_flags |= IB_DEVICE_XRC;
210
211 return 0;
212 }
213
hns_roce_query_port(struct ib_device * ib_dev,u32 port_num,struct ib_port_attr * props)214 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
215 struct ib_port_attr *props)
216 {
217 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
218 struct device *dev = hr_dev->dev;
219 struct net_device *net_dev;
220 unsigned long flags;
221 enum ib_mtu mtu;
222 u32 port;
223 int ret;
224
225 port = port_num - 1;
226
227 /* props being zeroed by the caller, avoid zeroing it here */
228
229 props->max_mtu = hr_dev->caps.max_mtu;
230 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
231 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
232 IB_PORT_VENDOR_CLASS_SUP |
233 IB_PORT_BOOT_MGMT_SUP;
234 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
235 props->pkey_tbl_len = 1;
236 ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed,
237 &props->active_width);
238 if (ret)
239 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret);
240
241 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
242
243 net_dev = hr_dev->iboe.netdevs[port];
244 if (!net_dev) {
245 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
246 dev_err(dev, "find netdev %u failed!\n", port);
247 return -EINVAL;
248 }
249
250 mtu = iboe_get_mtu(net_dev->mtu);
251 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
252 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
253 IB_PORT_ACTIVE :
254 IB_PORT_DOWN;
255 props->phys_state = props->state == IB_PORT_ACTIVE ?
256 IB_PORT_PHYS_STATE_LINK_UP :
257 IB_PORT_PHYS_STATE_DISABLED;
258
259 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
260
261 return 0;
262 }
263
hns_roce_get_link_layer(struct ib_device * device,u32 port_num)264 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
265 u32 port_num)
266 {
267 return IB_LINK_LAYER_ETHERNET;
268 }
269
hns_roce_query_pkey(struct ib_device * ib_dev,u32 port,u16 index,u16 * pkey)270 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
271 u16 *pkey)
272 {
273 if (index > 0)
274 return -EINVAL;
275
276 *pkey = PKEY_ID;
277
278 return 0;
279 }
280
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)281 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
282 struct ib_device_modify *props)
283 {
284 unsigned long flags;
285
286 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
287 return -EOPNOTSUPP;
288
289 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
290 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
291 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
292 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
293 }
294
295 return 0;
296 }
297
298 struct hns_user_mmap_entry *
hns_roce_user_mmap_entry_insert(struct ib_ucontext * ucontext,u64 address,size_t length,enum hns_roce_mmap_type mmap_type)299 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
300 size_t length,
301 enum hns_roce_mmap_type mmap_type)
302 {
303 struct hns_user_mmap_entry *entry;
304 int ret;
305
306 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
307 if (!entry)
308 return NULL;
309
310 entry->address = address;
311 entry->mmap_type = mmap_type;
312
313 switch (mmap_type) {
314 /* pgoff 0 must be used by DB for compatibility */
315 case HNS_ROCE_MMAP_TYPE_DB:
316 ret = rdma_user_mmap_entry_insert_exact(
317 ucontext, &entry->rdma_entry, length, 0);
318 break;
319 case HNS_ROCE_MMAP_TYPE_DWQE:
320 ret = rdma_user_mmap_entry_insert_range(
321 ucontext, &entry->rdma_entry, length, 1,
322 U32_MAX);
323 break;
324 default:
325 ret = -EINVAL;
326 break;
327 }
328
329 if (ret) {
330 kfree(entry);
331 return NULL;
332 }
333
334 return entry;
335 }
336
hns_roce_dealloc_uar_entry(struct hns_roce_ucontext * context)337 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
338 {
339 if (context->db_mmap_entry)
340 rdma_user_mmap_entry_remove(
341 &context->db_mmap_entry->rdma_entry);
342 }
343
hns_roce_alloc_uar_entry(struct ib_ucontext * uctx)344 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
345 {
346 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
347 u64 address;
348
349 address = context->uar.pfn << PAGE_SHIFT;
350 context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
351 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
352 if (!context->db_mmap_entry)
353 return -ENOMEM;
354
355 return 0;
356 }
357
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)358 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
359 struct ib_udata *udata)
360 {
361 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
362 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
363 struct hns_roce_ib_alloc_ucontext_resp resp = {};
364 struct hns_roce_ib_alloc_ucontext ucmd = {};
365 int ret;
366
367 if (!hr_dev->active)
368 return -EAGAIN;
369
370 resp.qp_tab_size = hr_dev->caps.num_qps;
371 resp.srq_tab_size = hr_dev->caps.num_srqs;
372
373 ret = ib_copy_from_udata(&ucmd, udata,
374 min(udata->inlen, sizeof(ucmd)));
375 if (ret)
376 return ret;
377
378 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
379 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS;
380
381 if (context->config & HNS_ROCE_EXSGE_FLAGS) {
382 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS;
383 resp.max_inline_data = hr_dev->caps.max_sq_inline;
384 }
385
386 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
387 context->config |= ucmd.config & HNS_ROCE_RQ_INLINE_FLAGS;
388 if (context->config & HNS_ROCE_RQ_INLINE_FLAGS)
389 resp.config |= HNS_ROCE_RSP_RQ_INLINE_FLAGS;
390 }
391
392 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQE_INLINE) {
393 context->config |= ucmd.config & HNS_ROCE_CQE_INLINE_FLAGS;
394 if (context->config & HNS_ROCE_CQE_INLINE_FLAGS)
395 resp.config |= HNS_ROCE_RSP_CQE_INLINE_FLAGS;
396 }
397
398 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
399 if (ret)
400 goto error_fail_uar_alloc;
401
402 ret = hns_roce_alloc_uar_entry(uctx);
403 if (ret)
404 goto error_fail_uar_entry;
405
406 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
407 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
408 INIT_LIST_HEAD(&context->page_list);
409 mutex_init(&context->page_mutex);
410 }
411
412 resp.cqe_size = hr_dev->caps.cqe_sz;
413
414 ret = ib_copy_to_udata(udata, &resp,
415 min(udata->outlen, sizeof(resp)));
416 if (ret)
417 goto error_fail_copy_to_udata;
418
419 return 0;
420
421 error_fail_copy_to_udata:
422 hns_roce_dealloc_uar_entry(context);
423
424 error_fail_uar_entry:
425 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
426
427 error_fail_uar_alloc:
428 return ret;
429 }
430
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)431 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
432 {
433 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
434 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
435
436 hns_roce_dealloc_uar_entry(context);
437
438 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
439 }
440
hns_roce_mmap(struct ib_ucontext * uctx,struct vm_area_struct * vma)441 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
442 {
443 struct rdma_user_mmap_entry *rdma_entry;
444 struct hns_user_mmap_entry *entry;
445 phys_addr_t pfn;
446 pgprot_t prot;
447 int ret;
448
449 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
450 if (!rdma_entry)
451 return -EINVAL;
452
453 entry = to_hns_mmap(rdma_entry);
454 pfn = entry->address >> PAGE_SHIFT;
455
456 switch (entry->mmap_type) {
457 case HNS_ROCE_MMAP_TYPE_DB:
458 case HNS_ROCE_MMAP_TYPE_DWQE:
459 prot = pgprot_device(vma->vm_page_prot);
460 break;
461 default:
462 ret = -EINVAL;
463 goto out;
464 }
465
466 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
467 prot, rdma_entry);
468
469 out:
470 rdma_user_mmap_entry_put(rdma_entry);
471 return ret;
472 }
473
hns_roce_free_mmap(struct rdma_user_mmap_entry * rdma_entry)474 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
475 {
476 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
477
478 kfree(entry);
479 }
480
hns_roce_port_immutable(struct ib_device * ib_dev,u32 port_num,struct ib_port_immutable * immutable)481 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
482 struct ib_port_immutable *immutable)
483 {
484 struct ib_port_attr attr;
485 int ret;
486
487 ret = ib_query_port(ib_dev, port_num, &attr);
488 if (ret)
489 return ret;
490
491 immutable->pkey_tbl_len = attr.pkey_tbl_len;
492 immutable->gid_tbl_len = attr.gid_tbl_len;
493
494 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
495 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
496 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
497 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
498
499 return 0;
500 }
501
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)502 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
503 {
504 }
505
hns_roce_get_fw_ver(struct ib_device * device,char * str)506 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
507 {
508 u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
509 unsigned int major, minor, sub_minor;
510
511 major = upper_32_bits(fw_ver);
512 minor = high_16_bits(lower_32_bits(fw_ver));
513 sub_minor = low_16_bits(fw_ver);
514
515 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
516 sub_minor);
517 }
518
519 #define HNS_ROCE_HW_CNT(ename, cname) \
520 [HNS_ROCE_HW_##ename##_CNT].name = cname
521
522 static const struct rdma_stat_desc hns_roce_port_stats_descs[] = {
523 HNS_ROCE_HW_CNT(RX_RC_PKT, "rx_rc_pkt"),
524 HNS_ROCE_HW_CNT(RX_UC_PKT, "rx_uc_pkt"),
525 HNS_ROCE_HW_CNT(RX_UD_PKT, "rx_ud_pkt"),
526 HNS_ROCE_HW_CNT(RX_XRC_PKT, "rx_xrc_pkt"),
527 HNS_ROCE_HW_CNT(RX_PKT, "rx_pkt"),
528 HNS_ROCE_HW_CNT(RX_ERR_PKT, "rx_err_pkt"),
529 HNS_ROCE_HW_CNT(RX_CNP_PKT, "rx_cnp_pkt"),
530 HNS_ROCE_HW_CNT(TX_RC_PKT, "tx_rc_pkt"),
531 HNS_ROCE_HW_CNT(TX_UC_PKT, "tx_uc_pkt"),
532 HNS_ROCE_HW_CNT(TX_UD_PKT, "tx_ud_pkt"),
533 HNS_ROCE_HW_CNT(TX_XRC_PKT, "tx_xrc_pkt"),
534 HNS_ROCE_HW_CNT(TX_PKT, "tx_pkt"),
535 HNS_ROCE_HW_CNT(TX_ERR_PKT, "tx_err_pkt"),
536 HNS_ROCE_HW_CNT(TX_CNP_PKT, "tx_cnp_pkt"),
537 HNS_ROCE_HW_CNT(TRP_GET_MPT_ERR_PKT, "trp_get_mpt_err_pkt"),
538 HNS_ROCE_HW_CNT(TRP_GET_IRRL_ERR_PKT, "trp_get_irrl_err_pkt"),
539 HNS_ROCE_HW_CNT(ECN_DB, "ecn_doorbell"),
540 HNS_ROCE_HW_CNT(RX_BUF, "rx_buffer"),
541 HNS_ROCE_HW_CNT(TRP_RX_SOF, "trp_rx_sof"),
542 HNS_ROCE_HW_CNT(CQ_CQE, "cq_cqe"),
543 HNS_ROCE_HW_CNT(CQ_POE, "cq_poe"),
544 HNS_ROCE_HW_CNT(CQ_NOTIFY, "cq_notify"),
545 };
546
hns_roce_alloc_hw_port_stats(struct ib_device * device,u32 port_num)547 static struct rdma_hw_stats *hns_roce_alloc_hw_port_stats(
548 struct ib_device *device, u32 port_num)
549 {
550 struct hns_roce_dev *hr_dev = to_hr_dev(device);
551
552 if (port_num > hr_dev->caps.num_ports) {
553 ibdev_err(device, "invalid port num.\n");
554 return NULL;
555 }
556
557 return rdma_alloc_hw_stats_struct(hns_roce_port_stats_descs,
558 ARRAY_SIZE(hns_roce_port_stats_descs),
559 RDMA_HW_STATS_DEFAULT_LIFESPAN);
560 }
561
hns_roce_get_hw_stats(struct ib_device * device,struct rdma_hw_stats * stats,u32 port,int index)562 static int hns_roce_get_hw_stats(struct ib_device *device,
563 struct rdma_hw_stats *stats,
564 u32 port, int index)
565 {
566 struct hns_roce_dev *hr_dev = to_hr_dev(device);
567 int num_counters = HNS_ROCE_HW_CNT_TOTAL;
568 int ret;
569
570 if (port == 0)
571 return 0;
572
573 if (port > hr_dev->caps.num_ports)
574 return -EINVAL;
575
576 ret = hr_dev->hw->query_hw_counter(hr_dev, stats->value, port,
577 &num_counters);
578 if (ret) {
579 ibdev_err(device, "failed to query hw counter, ret = %d\n",
580 ret);
581 return ret;
582 }
583
584 return num_counters;
585 }
586
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)587 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
588 {
589 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
590
591 hr_dev->active = false;
592 unregister_netdevice_notifier(&iboe->nb);
593 ib_unregister_device(&hr_dev->ib_dev);
594 }
595
596 static const struct ib_device_ops hns_roce_dev_ops = {
597 .owner = THIS_MODULE,
598 .driver_id = RDMA_DRIVER_HNS,
599 .uverbs_abi_ver = 1,
600 .uverbs_no_driver_id_binding = 1,
601
602 .get_dev_fw_str = hns_roce_get_fw_ver,
603 .add_gid = hns_roce_add_gid,
604 .alloc_pd = hns_roce_alloc_pd,
605 .alloc_ucontext = hns_roce_alloc_ucontext,
606 .create_ah = hns_roce_create_ah,
607 .create_user_ah = hns_roce_create_ah,
608 .create_cq = hns_roce_create_cq,
609 .create_qp = hns_roce_create_qp,
610 .dealloc_pd = hns_roce_dealloc_pd,
611 .dealloc_ucontext = hns_roce_dealloc_ucontext,
612 .del_gid = hns_roce_del_gid,
613 .dereg_mr = hns_roce_dereg_mr,
614 .destroy_ah = hns_roce_destroy_ah,
615 .destroy_cq = hns_roce_destroy_cq,
616 .disassociate_ucontext = hns_roce_disassociate_ucontext,
617 .get_dma_mr = hns_roce_get_dma_mr,
618 .get_link_layer = hns_roce_get_link_layer,
619 .get_port_immutable = hns_roce_port_immutable,
620 .mmap = hns_roce_mmap,
621 .mmap_free = hns_roce_free_mmap,
622 .modify_device = hns_roce_modify_device,
623 .modify_qp = hns_roce_modify_qp,
624 .query_ah = hns_roce_query_ah,
625 .query_device = hns_roce_query_device,
626 .query_pkey = hns_roce_query_pkey,
627 .query_port = hns_roce_query_port,
628 .reg_user_mr = hns_roce_reg_user_mr,
629
630 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
631 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
632 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
633 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
634 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
635 };
636
637 static const struct ib_device_ops hns_roce_dev_hw_stats_ops = {
638 .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats,
639 .get_hw_stats = hns_roce_get_hw_stats,
640 };
641
642 static const struct ib_device_ops hns_roce_dev_mr_ops = {
643 .rereg_user_mr = hns_roce_rereg_user_mr,
644 };
645
646 static const struct ib_device_ops hns_roce_dev_mw_ops = {
647 .alloc_mw = hns_roce_alloc_mw,
648 .dealloc_mw = hns_roce_dealloc_mw,
649
650 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
651 };
652
653 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
654 .alloc_mr = hns_roce_alloc_mr,
655 .map_mr_sg = hns_roce_map_mr_sg,
656 };
657
658 static const struct ib_device_ops hns_roce_dev_srq_ops = {
659 .create_srq = hns_roce_create_srq,
660 .destroy_srq = hns_roce_destroy_srq,
661
662 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
663 };
664
665 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
666 .alloc_xrcd = hns_roce_alloc_xrcd,
667 .dealloc_xrcd = hns_roce_dealloc_xrcd,
668
669 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
670 };
671
672 static const struct ib_device_ops hns_roce_dev_restrack_ops = {
673 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
674 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw,
675 .fill_res_qp_entry = hns_roce_fill_res_qp_entry,
676 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw,
677 .fill_res_mr_entry = hns_roce_fill_res_mr_entry,
678 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw,
679 };
680
hns_roce_register_device(struct hns_roce_dev * hr_dev)681 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
682 {
683 int ret;
684 struct hns_roce_ib_iboe *iboe = NULL;
685 struct ib_device *ib_dev = NULL;
686 struct device *dev = hr_dev->dev;
687 unsigned int i;
688
689 iboe = &hr_dev->iboe;
690 spin_lock_init(&iboe->lock);
691
692 ib_dev = &hr_dev->ib_dev;
693
694 ib_dev->node_type = RDMA_NODE_IB_CA;
695 ib_dev->dev.parent = dev;
696
697 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
698 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
699 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
700
701 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
702 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
703
704 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
705 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
706
707 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
708 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
709
710 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
711 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
712 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
713 }
714
715 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
716 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
717
718 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09 &&
719 !hr_dev->is_vf)
720 ib_set_device_ops(ib_dev, &hns_roce_dev_hw_stats_ops);
721
722 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
723 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
724 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops);
725 for (i = 0; i < hr_dev->caps.num_ports; i++) {
726 if (!hr_dev->iboe.netdevs[i])
727 continue;
728
729 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
730 i + 1);
731 if (ret)
732 return ret;
733 }
734 dma_set_max_seg_size(dev, UINT_MAX);
735 ret = ib_register_device(ib_dev, "hns_%d", dev);
736 if (ret) {
737 dev_err(dev, "ib_register_device failed!\n");
738 return ret;
739 }
740
741 ret = hns_roce_setup_mtu_mac(hr_dev);
742 if (ret) {
743 dev_err(dev, "setup_mtu_mac failed!\n");
744 goto error_failed_setup_mtu_mac;
745 }
746
747 iboe->nb.notifier_call = hns_roce_netdev_event;
748 ret = register_netdevice_notifier(&iboe->nb);
749 if (ret) {
750 dev_err(dev, "register_netdevice_notifier failed!\n");
751 goto error_failed_setup_mtu_mac;
752 }
753
754 hr_dev->active = true;
755 return 0;
756
757 error_failed_setup_mtu_mac:
758 ib_unregister_device(ib_dev);
759
760 return ret;
761 }
762
hns_roce_init_hem(struct hns_roce_dev * hr_dev)763 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
764 {
765 struct device *dev = hr_dev->dev;
766 int ret;
767
768 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
769 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
770 hr_dev->caps.num_mtpts);
771 if (ret) {
772 dev_err(dev, "failed to init MTPT context memory, aborting.\n");
773 return ret;
774 }
775
776 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
777 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
778 hr_dev->caps.num_qps);
779 if (ret) {
780 dev_err(dev, "failed to init QP context memory, aborting.\n");
781 goto err_unmap_dmpt;
782 }
783
784 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
785 HEM_TYPE_IRRL,
786 hr_dev->caps.irrl_entry_sz *
787 hr_dev->caps.max_qp_init_rdma,
788 hr_dev->caps.num_qps);
789 if (ret) {
790 dev_err(dev, "failed to init irrl_table memory, aborting.\n");
791 goto err_unmap_qp;
792 }
793
794 if (hr_dev->caps.trrl_entry_sz) {
795 ret = hns_roce_init_hem_table(hr_dev,
796 &hr_dev->qp_table.trrl_table,
797 HEM_TYPE_TRRL,
798 hr_dev->caps.trrl_entry_sz *
799 hr_dev->caps.max_qp_dest_rdma,
800 hr_dev->caps.num_qps);
801 if (ret) {
802 dev_err(dev,
803 "failed to init trrl_table memory, aborting.\n");
804 goto err_unmap_irrl;
805 }
806 }
807
808 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
809 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
810 hr_dev->caps.num_cqs);
811 if (ret) {
812 dev_err(dev, "failed to init CQ context memory, aborting.\n");
813 goto err_unmap_trrl;
814 }
815
816 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
817 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
818 HEM_TYPE_SRQC,
819 hr_dev->caps.srqc_entry_sz,
820 hr_dev->caps.num_srqs);
821 if (ret) {
822 dev_err(dev,
823 "failed to init SRQ context memory, aborting.\n");
824 goto err_unmap_cq;
825 }
826 }
827
828 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
829 ret = hns_roce_init_hem_table(hr_dev,
830 &hr_dev->qp_table.sccc_table,
831 HEM_TYPE_SCCC,
832 hr_dev->caps.sccc_sz,
833 hr_dev->caps.num_qps);
834 if (ret) {
835 dev_err(dev,
836 "failed to init SCC context memory, aborting.\n");
837 goto err_unmap_srq;
838 }
839 }
840
841 if (hr_dev->caps.qpc_timer_entry_sz) {
842 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
843 HEM_TYPE_QPC_TIMER,
844 hr_dev->caps.qpc_timer_entry_sz,
845 hr_dev->caps.qpc_timer_bt_num);
846 if (ret) {
847 dev_err(dev,
848 "failed to init QPC timer memory, aborting.\n");
849 goto err_unmap_ctx;
850 }
851 }
852
853 if (hr_dev->caps.cqc_timer_entry_sz) {
854 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
855 HEM_TYPE_CQC_TIMER,
856 hr_dev->caps.cqc_timer_entry_sz,
857 hr_dev->caps.cqc_timer_bt_num);
858 if (ret) {
859 dev_err(dev,
860 "failed to init CQC timer memory, aborting.\n");
861 goto err_unmap_qpc_timer;
862 }
863 }
864
865 if (hr_dev->caps.gmv_entry_sz) {
866 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
867 HEM_TYPE_GMV,
868 hr_dev->caps.gmv_entry_sz,
869 hr_dev->caps.gmv_entry_num);
870 if (ret) {
871 dev_err(dev,
872 "failed to init gmv table memory, ret = %d\n",
873 ret);
874 goto err_unmap_cqc_timer;
875 }
876 }
877
878 return 0;
879
880 err_unmap_cqc_timer:
881 if (hr_dev->caps.cqc_timer_entry_sz)
882 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
883
884 err_unmap_qpc_timer:
885 if (hr_dev->caps.qpc_timer_entry_sz)
886 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
887
888 err_unmap_ctx:
889 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
890 hns_roce_cleanup_hem_table(hr_dev,
891 &hr_dev->qp_table.sccc_table);
892 err_unmap_srq:
893 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
894 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
895
896 err_unmap_cq:
897 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
898
899 err_unmap_trrl:
900 if (hr_dev->caps.trrl_entry_sz)
901 hns_roce_cleanup_hem_table(hr_dev,
902 &hr_dev->qp_table.trrl_table);
903
904 err_unmap_irrl:
905 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
906
907 err_unmap_qp:
908 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
909
910 err_unmap_dmpt:
911 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
912
913 return ret;
914 }
915
916 /**
917 * hns_roce_setup_hca - setup host channel adapter
918 * @hr_dev: pointer to hns roce device
919 * Return : int
920 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)921 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
922 {
923 struct device *dev = hr_dev->dev;
924 int ret;
925
926 spin_lock_init(&hr_dev->sm_lock);
927
928 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
929 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
930 INIT_LIST_HEAD(&hr_dev->pgdir_list);
931 mutex_init(&hr_dev->pgdir_mutex);
932 }
933
934 hns_roce_init_uar_table(hr_dev);
935
936 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
937 if (ret) {
938 dev_err(dev, "failed to allocate priv_uar.\n");
939 goto err_uar_table_free;
940 }
941
942 ret = hns_roce_init_qp_table(hr_dev);
943 if (ret) {
944 dev_err(dev, "failed to init qp_table.\n");
945 goto err_uar_table_free;
946 }
947
948 hns_roce_init_pd_table(hr_dev);
949
950 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
951 hns_roce_init_xrcd_table(hr_dev);
952
953 hns_roce_init_mr_table(hr_dev);
954
955 hns_roce_init_cq_table(hr_dev);
956
957 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
958 hns_roce_init_srq_table(hr_dev);
959
960 return 0;
961
962 err_uar_table_free:
963 ida_destroy(&hr_dev->uar_ida.ida);
964 return ret;
965 }
966
check_and_get_armed_cq(struct list_head * cq_list,struct ib_cq * cq)967 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
968 {
969 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
970 unsigned long flags;
971
972 spin_lock_irqsave(&hr_cq->lock, flags);
973 if (cq->comp_handler) {
974 if (!hr_cq->is_armed) {
975 hr_cq->is_armed = 1;
976 list_add_tail(&hr_cq->node, cq_list);
977 }
978 }
979 spin_unlock_irqrestore(&hr_cq->lock, flags);
980 }
981
hns_roce_handle_device_err(struct hns_roce_dev * hr_dev)982 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
983 {
984 struct hns_roce_qp *hr_qp;
985 struct hns_roce_cq *hr_cq;
986 struct list_head cq_list;
987 unsigned long flags_qp;
988 unsigned long flags;
989
990 INIT_LIST_HEAD(&cq_list);
991
992 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
993 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
994 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
995 if (hr_qp->sq.tail != hr_qp->sq.head)
996 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
997 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
998
999 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
1000 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
1001 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
1002 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
1003 }
1004
1005 list_for_each_entry(hr_cq, &cq_list, node)
1006 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
1007
1008 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
1009 }
1010
hns_roce_init(struct hns_roce_dev * hr_dev)1011 int hns_roce_init(struct hns_roce_dev *hr_dev)
1012 {
1013 struct device *dev = hr_dev->dev;
1014 int ret;
1015
1016 hr_dev->is_reset = false;
1017
1018 if (hr_dev->hw->cmq_init) {
1019 ret = hr_dev->hw->cmq_init(hr_dev);
1020 if (ret) {
1021 dev_err(dev, "init RoCE Command Queue failed!\n");
1022 return ret;
1023 }
1024 }
1025
1026 ret = hr_dev->hw->hw_profile(hr_dev);
1027 if (ret) {
1028 dev_err(dev, "get RoCE engine profile failed!\n");
1029 goto error_failed_cmd_init;
1030 }
1031
1032 ret = hns_roce_cmd_init(hr_dev);
1033 if (ret) {
1034 dev_err(dev, "cmd init failed!\n");
1035 goto error_failed_cmd_init;
1036 }
1037
1038 /* EQ depends on poll mode, event mode depends on EQ */
1039 ret = hr_dev->hw->init_eq(hr_dev);
1040 if (ret) {
1041 dev_err(dev, "eq init failed!\n");
1042 goto error_failed_eq_table;
1043 }
1044
1045 if (hr_dev->cmd_mod) {
1046 ret = hns_roce_cmd_use_events(hr_dev);
1047 if (ret)
1048 dev_warn(dev,
1049 "Cmd event mode failed, set back to poll!\n");
1050 }
1051
1052 ret = hns_roce_init_hem(hr_dev);
1053 if (ret) {
1054 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
1055 goto error_failed_init_hem;
1056 }
1057
1058 ret = hns_roce_setup_hca(hr_dev);
1059 if (ret) {
1060 dev_err(dev, "setup hca failed!\n");
1061 goto error_failed_setup_hca;
1062 }
1063
1064 if (hr_dev->hw->hw_init) {
1065 ret = hr_dev->hw->hw_init(hr_dev);
1066 if (ret) {
1067 dev_err(dev, "hw_init failed!\n");
1068 goto error_failed_engine_init;
1069 }
1070 }
1071
1072 INIT_LIST_HEAD(&hr_dev->qp_list);
1073 spin_lock_init(&hr_dev->qp_list_lock);
1074 INIT_LIST_HEAD(&hr_dev->dip_list);
1075 spin_lock_init(&hr_dev->dip_list_lock);
1076
1077 ret = hns_roce_register_device(hr_dev);
1078 if (ret)
1079 goto error_failed_register_device;
1080
1081 return 0;
1082
1083 error_failed_register_device:
1084 if (hr_dev->hw->hw_exit)
1085 hr_dev->hw->hw_exit(hr_dev);
1086
1087 error_failed_engine_init:
1088 hns_roce_cleanup_bitmap(hr_dev);
1089
1090 error_failed_setup_hca:
1091 hns_roce_cleanup_hem(hr_dev);
1092
1093 error_failed_init_hem:
1094 if (hr_dev->cmd_mod)
1095 hns_roce_cmd_use_polling(hr_dev);
1096 hr_dev->hw->cleanup_eq(hr_dev);
1097
1098 error_failed_eq_table:
1099 hns_roce_cmd_cleanup(hr_dev);
1100
1101 error_failed_cmd_init:
1102 if (hr_dev->hw->cmq_exit)
1103 hr_dev->hw->cmq_exit(hr_dev);
1104
1105 return ret;
1106 }
1107
hns_roce_exit(struct hns_roce_dev * hr_dev)1108 void hns_roce_exit(struct hns_roce_dev *hr_dev)
1109 {
1110 hns_roce_unregister_device(hr_dev);
1111
1112 if (hr_dev->hw->hw_exit)
1113 hr_dev->hw->hw_exit(hr_dev);
1114 hns_roce_cleanup_bitmap(hr_dev);
1115 hns_roce_cleanup_hem(hr_dev);
1116
1117 if (hr_dev->cmd_mod)
1118 hns_roce_cmd_use_polling(hr_dev);
1119
1120 hr_dev->hw->cleanup_eq(hr_dev);
1121 hns_roce_cmd_cleanup(hr_dev);
1122 if (hr_dev->hw->cmq_exit)
1123 hr_dev->hw->cmq_exit(hr_dev);
1124 }
1125
1126 MODULE_LICENSE("Dual BSD/GPL");
1127 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1128 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1129 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1130 MODULE_DESCRIPTION("HNS RoCE Driver");
1131