1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/iommu.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/skbuff.h>
18 #include <linux/sctp.h>
19 #include <net/gre.h>
20 #include <net/gro.h>
21 #include <net/ip6_checksum.h>
22 #include <net/page_pool/helpers.h>
23 #include <net/pkt_cls.h>
24 #include <net/pkt_sched.h>
25 #include <net/tcp.h>
26 #include <net/vxlan.h>
27 #include <net/geneve.h>
28
29 #include "hnae3.h"
30 #include "hns3_enet.h"
31 /* All hns3 tracepoints are defined by the include below, which
32 * must be included exactly once across the whole kernel with
33 * CREATE_TRACE_POINTS defined
34 */
35 #define CREATE_TRACE_POINTS
36 #include "hns3_trace.h"
37
38 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
39 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
40
41 #define hns3_rl_err(fmt, ...) \
42 do { \
43 if (net_ratelimit()) \
44 netdev_err(fmt, ##__VA_ARGS__); \
45 } while (0)
46
47 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
48
49 static const char hns3_driver_name[] = "hns3";
50 static const char hns3_driver_string[] =
51 "Hisilicon Ethernet Network Driver for Hip08 Family";
52 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
53 static struct hnae3_client client;
54
55 static int debug = -1;
56 module_param(debug, int, 0);
57 MODULE_PARM_DESC(debug, " Network interface message level setting");
58
59 static unsigned int tx_sgl = 1;
60 module_param(tx_sgl, uint, 0600);
61 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
62
63 static bool page_pool_enabled = true;
64 module_param(page_pool_enabled, bool, 0400);
65
66 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
67 sizeof(struct sg_table))
68 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
69 dma_get_cache_alignment())
70
71 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
72 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
73
74 #define HNS3_INNER_VLAN_TAG 1
75 #define HNS3_OUTER_VLAN_TAG 2
76
77 #define HNS3_MIN_TX_LEN 33U
78 #define HNS3_MIN_TUN_PKT_LEN 65U
79
80 /* hns3_pci_tbl - PCI Device ID Table
81 *
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id hns3_pci_tbl[] = {
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
91 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
92 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
93 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
94 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
95 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
96 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
97 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
98 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
99 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
101 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
104 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
105 /* required last entry */
106 {0,}
107 };
108 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
109
110 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
111 { ptype, \
112 l, \
113 CHECKSUM_##s, \
114 HNS3_L3_TYPE_##t, \
115 1, \
116 h}
117
118 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
120 PKT_HASH_TYPE_NONE }
121
122 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
123 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
124 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
131 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
138 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
139 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
142 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
143 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
144 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
145 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
146 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
147 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
148 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
151 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
152 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
153 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
154 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
155 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
156 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
159 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
160 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
161 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
162 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
164 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
166 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
167 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
168 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
233 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
234 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
235 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
236 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
237 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
238 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
239 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
240 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
241 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
242 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
245 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
246 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
247 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
248 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
249 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
250 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
253 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
255 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
256 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
258 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
260 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
261 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
262 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
378 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
379 };
380
381 #define HNS3_INVALID_PTYPE \
382 ARRAY_SIZE(hns3_rx_ptype_tbl)
383
hns3_irq_handle(int irq,void * vector)384 static irqreturn_t hns3_irq_handle(int irq, void *vector)
385 {
386 struct hns3_enet_tqp_vector *tqp_vector = vector;
387
388 napi_schedule_irqoff(&tqp_vector->napi);
389 tqp_vector->event_cnt++;
390
391 return IRQ_HANDLED;
392 }
393
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)394 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
395 {
396 struct hns3_enet_tqp_vector *tqp_vectors;
397 unsigned int i;
398
399 for (i = 0; i < priv->vector_num; i++) {
400 tqp_vectors = &priv->tqp_vector[i];
401
402 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
403 continue;
404
405 /* clear the affinity mask */
406 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
407
408 /* release the irq resource */
409 free_irq(tqp_vectors->vector_irq, tqp_vectors);
410 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
411 }
412 }
413
hns3_nic_init_irq(struct hns3_nic_priv * priv)414 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
415 {
416 struct hns3_enet_tqp_vector *tqp_vectors;
417 int txrx_int_idx = 0;
418 int rx_int_idx = 0;
419 int tx_int_idx = 0;
420 unsigned int i;
421 int ret;
422
423 for (i = 0; i < priv->vector_num; i++) {
424 tqp_vectors = &priv->tqp_vector[i];
425
426 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
427 continue;
428
429 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
430 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
431 "%s-%s-%s-%d", hns3_driver_name,
432 pci_name(priv->ae_handle->pdev),
433 "TxRx", txrx_int_idx++);
434 txrx_int_idx++;
435 } else if (tqp_vectors->rx_group.ring) {
436 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
437 "%s-%s-%s-%d", hns3_driver_name,
438 pci_name(priv->ae_handle->pdev),
439 "Rx", rx_int_idx++);
440 } else if (tqp_vectors->tx_group.ring) {
441 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
442 "%s-%s-%s-%d", hns3_driver_name,
443 pci_name(priv->ae_handle->pdev),
444 "Tx", tx_int_idx++);
445 } else {
446 /* Skip this unused q_vector */
447 continue;
448 }
449
450 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
451
452 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
453 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
454 tqp_vectors->name, tqp_vectors);
455 if (ret) {
456 netdev_err(priv->netdev, "request irq(%d) fail\n",
457 tqp_vectors->vector_irq);
458 hns3_nic_uninit_irq(priv);
459 return ret;
460 }
461
462 irq_set_affinity_hint(tqp_vectors->vector_irq,
463 &tqp_vectors->affinity_mask);
464
465 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
466 }
467
468 return 0;
469 }
470
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)471 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
472 u32 mask_en)
473 {
474 writel(mask_en, tqp_vector->mask_addr);
475 }
476
hns3_irq_enable(struct hns3_enet_tqp_vector * tqp_vector)477 static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector)
478 {
479 napi_enable(&tqp_vector->napi);
480 enable_irq(tqp_vector->vector_irq);
481 }
482
hns3_irq_disable(struct hns3_enet_tqp_vector * tqp_vector)483 static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector)
484 {
485 disable_irq(tqp_vector->vector_irq);
486 napi_disable(&tqp_vector->napi);
487 cancel_work_sync(&tqp_vector->rx_group.dim.work);
488 cancel_work_sync(&tqp_vector->tx_group.dim.work);
489 }
490
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)491 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
492 u32 rl_value)
493 {
494 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
495
496 /* this defines the configuration for RL (Interrupt Rate Limiter).
497 * Rl defines rate of interrupts i.e. number of interrupts-per-second
498 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
499 */
500 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
501 !tqp_vector->rx_group.coal.adapt_enable)
502 /* According to the hardware, the range of rl_reg is
503 * 0-59 and the unit is 4.
504 */
505 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
506
507 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
508 }
509
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)510 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
511 u32 gl_value)
512 {
513 u32 new_val;
514
515 if (tqp_vector->rx_group.coal.unit_1us)
516 new_val = gl_value | HNS3_INT_GL_1US;
517 else
518 new_val = hns3_gl_usec_to_reg(gl_value);
519
520 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
521 }
522
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)523 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
524 u32 gl_value)
525 {
526 u32 new_val;
527
528 if (tqp_vector->tx_group.coal.unit_1us)
529 new_val = gl_value | HNS3_INT_GL_1US;
530 else
531 new_val = hns3_gl_usec_to_reg(gl_value);
532
533 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
534 }
535
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)536 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
537 u32 ql_value)
538 {
539 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
540 }
541
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)542 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
543 u32 ql_value)
544 {
545 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
546 }
547
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)548 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
549 struct hns3_nic_priv *priv)
550 {
551 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
552 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
553 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
554 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
555 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
556
557 tx_coal->adapt_enable = ptx_coal->adapt_enable;
558 rx_coal->adapt_enable = prx_coal->adapt_enable;
559
560 tx_coal->int_gl = ptx_coal->int_gl;
561 rx_coal->int_gl = prx_coal->int_gl;
562
563 rx_coal->flow_level = prx_coal->flow_level;
564 tx_coal->flow_level = ptx_coal->flow_level;
565
566 /* device version above V3(include V3), GL can configure 1us
567 * unit, so uses 1us unit.
568 */
569 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
570 tx_coal->unit_1us = 1;
571 rx_coal->unit_1us = 1;
572 }
573
574 if (ae_dev->dev_specs.int_ql_max) {
575 tx_coal->ql_enable = 1;
576 rx_coal->ql_enable = 1;
577 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
578 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
579 tx_coal->int_ql = ptx_coal->int_ql;
580 rx_coal->int_ql = prx_coal->int_ql;
581 }
582 }
583
584 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)585 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
586 struct hns3_nic_priv *priv)
587 {
588 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
589 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
590 struct hnae3_handle *h = priv->ae_handle;
591
592 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
593 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
594 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
595
596 if (tx_coal->ql_enable)
597 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
598
599 if (rx_coal->ql_enable)
600 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
601 }
602
hns3_nic_set_real_num_queue(struct net_device * netdev)603 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
604 {
605 struct hnae3_handle *h = hns3_get_handle(netdev);
606 struct hnae3_knic_private_info *kinfo = &h->kinfo;
607 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
608 unsigned int queue_size = kinfo->num_tqps;
609 int i, ret;
610
611 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
612 netdev_reset_tc(netdev);
613 } else {
614 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
615 if (ret) {
616 netdev_err(netdev,
617 "netdev_set_num_tc fail, ret=%d!\n", ret);
618 return ret;
619 }
620
621 for (i = 0; i < tc_info->num_tc; i++)
622 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
623 tc_info->tqp_offset[i]);
624 }
625
626 ret = netif_set_real_num_tx_queues(netdev, queue_size);
627 if (ret) {
628 netdev_err(netdev,
629 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
630 return ret;
631 }
632
633 ret = netif_set_real_num_rx_queues(netdev, queue_size);
634 if (ret) {
635 netdev_err(netdev,
636 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
637 return ret;
638 }
639
640 return 0;
641 }
642
hns3_get_max_available_channels(struct hnae3_handle * h)643 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
644 {
645 u16 alloc_tqps, max_rss_size, rss_size;
646
647 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
648 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
649
650 return min_t(u16, rss_size, max_rss_size);
651 }
652
hns3_tqp_enable(struct hnae3_queue * tqp)653 static void hns3_tqp_enable(struct hnae3_queue *tqp)
654 {
655 u32 rcb_reg;
656
657 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
658 rcb_reg |= BIT(HNS3_RING_EN_B);
659 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
660 }
661
hns3_tqp_disable(struct hnae3_queue * tqp)662 static void hns3_tqp_disable(struct hnae3_queue *tqp)
663 {
664 u32 rcb_reg;
665
666 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
667 rcb_reg &= ~BIT(HNS3_RING_EN_B);
668 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
669 }
670
hns3_free_rx_cpu_rmap(struct net_device * netdev)671 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
672 {
673 #ifdef CONFIG_RFS_ACCEL
674 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
675 netdev->rx_cpu_rmap = NULL;
676 #endif
677 }
678
hns3_set_rx_cpu_rmap(struct net_device * netdev)679 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
680 {
681 #ifdef CONFIG_RFS_ACCEL
682 struct hns3_nic_priv *priv = netdev_priv(netdev);
683 struct hns3_enet_tqp_vector *tqp_vector;
684 int i, ret;
685
686 if (!netdev->rx_cpu_rmap) {
687 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
688 if (!netdev->rx_cpu_rmap)
689 return -ENOMEM;
690 }
691
692 for (i = 0; i < priv->vector_num; i++) {
693 tqp_vector = &priv->tqp_vector[i];
694 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
695 tqp_vector->vector_irq);
696 if (ret) {
697 hns3_free_rx_cpu_rmap(netdev);
698 return ret;
699 }
700 }
701 #endif
702 return 0;
703 }
704
hns3_enable_irqs_and_tqps(struct net_device * netdev)705 static void hns3_enable_irqs_and_tqps(struct net_device *netdev)
706 {
707 struct hns3_nic_priv *priv = netdev_priv(netdev);
708 struct hnae3_handle *h = priv->ae_handle;
709 u16 i;
710
711 for (i = 0; i < priv->vector_num; i++)
712 hns3_irq_enable(&priv->tqp_vector[i]);
713
714 for (i = 0; i < priv->vector_num; i++)
715 hns3_mask_vector_irq(&priv->tqp_vector[i], 1);
716
717 for (i = 0; i < h->kinfo.num_tqps; i++)
718 hns3_tqp_enable(h->kinfo.tqp[i]);
719 }
720
hns3_disable_irqs_and_tqps(struct net_device * netdev)721 static void hns3_disable_irqs_and_tqps(struct net_device *netdev)
722 {
723 struct hns3_nic_priv *priv = netdev_priv(netdev);
724 struct hnae3_handle *h = priv->ae_handle;
725 u16 i;
726
727 for (i = 0; i < h->kinfo.num_tqps; i++)
728 hns3_tqp_disable(h->kinfo.tqp[i]);
729
730 for (i = 0; i < priv->vector_num; i++)
731 hns3_mask_vector_irq(&priv->tqp_vector[i], 0);
732
733 for (i = 0; i < priv->vector_num; i++)
734 hns3_irq_disable(&priv->tqp_vector[i]);
735 }
736
hns3_nic_net_up(struct net_device * netdev)737 static int hns3_nic_net_up(struct net_device *netdev)
738 {
739 struct hns3_nic_priv *priv = netdev_priv(netdev);
740 struct hnae3_handle *h = priv->ae_handle;
741 int ret;
742
743 ret = hns3_nic_reset_all_ring(h);
744 if (ret)
745 return ret;
746
747 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
748
749 hns3_enable_irqs_and_tqps(netdev);
750
751 /* start the ae_dev */
752 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
753 if (ret) {
754 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
755 hns3_disable_irqs_and_tqps(netdev);
756 }
757
758 return ret;
759 }
760
hns3_config_xps(struct hns3_nic_priv * priv)761 static void hns3_config_xps(struct hns3_nic_priv *priv)
762 {
763 int i;
764
765 for (i = 0; i < priv->vector_num; i++) {
766 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
767 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
768
769 while (ring) {
770 int ret;
771
772 ret = netif_set_xps_queue(priv->netdev,
773 &tqp_vector->affinity_mask,
774 ring->tqp->tqp_index);
775 if (ret)
776 netdev_warn(priv->netdev,
777 "set xps queue failed: %d", ret);
778
779 ring = ring->next;
780 }
781 }
782 }
783
hns3_nic_net_open(struct net_device * netdev)784 static int hns3_nic_net_open(struct net_device *netdev)
785 {
786 struct hns3_nic_priv *priv = netdev_priv(netdev);
787 struct hnae3_handle *h = hns3_get_handle(netdev);
788 struct hnae3_knic_private_info *kinfo;
789 int i, ret;
790
791 if (hns3_nic_resetting(netdev))
792 return -EBUSY;
793
794 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
795 netdev_warn(netdev, "net open repeatedly!\n");
796 return 0;
797 }
798
799 netif_carrier_off(netdev);
800
801 ret = hns3_nic_set_real_num_queue(netdev);
802 if (ret)
803 return ret;
804
805 ret = hns3_nic_net_up(netdev);
806 if (ret) {
807 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
808 return ret;
809 }
810
811 kinfo = &h->kinfo;
812 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
813 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
814
815 if (h->ae_algo->ops->set_timer_task)
816 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
817
818 hns3_config_xps(priv);
819
820 netif_dbg(h, drv, netdev, "net open\n");
821
822 return 0;
823 }
824
hns3_reset_tx_queue(struct hnae3_handle * h)825 static void hns3_reset_tx_queue(struct hnae3_handle *h)
826 {
827 struct net_device *ndev = h->kinfo.netdev;
828 struct hns3_nic_priv *priv = netdev_priv(ndev);
829 struct netdev_queue *dev_queue;
830 u32 i;
831
832 for (i = 0; i < h->kinfo.num_tqps; i++) {
833 dev_queue = netdev_get_tx_queue(ndev,
834 priv->ring[i].queue_index);
835 netdev_tx_reset_queue(dev_queue);
836 }
837 }
838
hns3_nic_net_down(struct net_device * netdev)839 static void hns3_nic_net_down(struct net_device *netdev)
840 {
841 struct hns3_nic_priv *priv = netdev_priv(netdev);
842 const struct hnae3_ae_ops *ops;
843
844 hns3_disable_irqs_and_tqps(netdev);
845
846 /* stop ae_dev */
847 ops = priv->ae_handle->ae_algo->ops;
848 if (ops->stop)
849 ops->stop(priv->ae_handle);
850
851 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
852 * during reset process, because driver may not be able
853 * to disable the ring through firmware when downing the netdev.
854 */
855 if (!hns3_nic_resetting(netdev))
856 hns3_clear_all_ring(priv->ae_handle, false);
857
858 hns3_reset_tx_queue(priv->ae_handle);
859 }
860
hns3_nic_net_stop(struct net_device * netdev)861 static int hns3_nic_net_stop(struct net_device *netdev)
862 {
863 struct hns3_nic_priv *priv = netdev_priv(netdev);
864 struct hnae3_handle *h = hns3_get_handle(netdev);
865
866 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
867 return 0;
868
869 netif_dbg(h, drv, netdev, "net stop\n");
870
871 if (h->ae_algo->ops->set_timer_task)
872 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
873
874 netif_carrier_off(netdev);
875 netif_tx_disable(netdev);
876
877 hns3_nic_net_down(netdev);
878
879 return 0;
880 }
881
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)882 static int hns3_nic_uc_sync(struct net_device *netdev,
883 const unsigned char *addr)
884 {
885 struct hnae3_handle *h = hns3_get_handle(netdev);
886
887 if (h->ae_algo->ops->add_uc_addr)
888 return h->ae_algo->ops->add_uc_addr(h, addr);
889
890 return 0;
891 }
892
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)893 static int hns3_nic_uc_unsync(struct net_device *netdev,
894 const unsigned char *addr)
895 {
896 struct hnae3_handle *h = hns3_get_handle(netdev);
897
898 /* need ignore the request of removing device address, because
899 * we store the device address and other addresses of uc list
900 * in the function's mac filter list.
901 */
902 if (ether_addr_equal(addr, netdev->dev_addr))
903 return 0;
904
905 if (h->ae_algo->ops->rm_uc_addr)
906 return h->ae_algo->ops->rm_uc_addr(h, addr);
907
908 return 0;
909 }
910
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)911 static int hns3_nic_mc_sync(struct net_device *netdev,
912 const unsigned char *addr)
913 {
914 struct hnae3_handle *h = hns3_get_handle(netdev);
915
916 if (h->ae_algo->ops->add_mc_addr)
917 return h->ae_algo->ops->add_mc_addr(h, addr);
918
919 return 0;
920 }
921
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)922 static int hns3_nic_mc_unsync(struct net_device *netdev,
923 const unsigned char *addr)
924 {
925 struct hnae3_handle *h = hns3_get_handle(netdev);
926
927 if (h->ae_algo->ops->rm_mc_addr)
928 return h->ae_algo->ops->rm_mc_addr(h, addr);
929
930 return 0;
931 }
932
hns3_get_netdev_flags(struct net_device * netdev)933 static u8 hns3_get_netdev_flags(struct net_device *netdev)
934 {
935 u8 flags = 0;
936
937 if (netdev->flags & IFF_PROMISC)
938 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
939 else if (netdev->flags & IFF_ALLMULTI)
940 flags = HNAE3_USER_MPE;
941
942 return flags;
943 }
944
hns3_nic_set_rx_mode(struct net_device * netdev)945 static void hns3_nic_set_rx_mode(struct net_device *netdev)
946 {
947 struct hnae3_handle *h = hns3_get_handle(netdev);
948 u8 new_flags;
949
950 new_flags = hns3_get_netdev_flags(netdev);
951
952 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
953 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
954
955 /* User mode Promisc mode enable and vlan filtering is disabled to
956 * let all packets in.
957 */
958 h->netdev_flags = new_flags;
959 hns3_request_update_promisc_mode(h);
960 }
961
hns3_request_update_promisc_mode(struct hnae3_handle * handle)962 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
963 {
964 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
965
966 if (ops->request_update_promisc_mode)
967 ops->request_update_promisc_mode(handle);
968 }
969
hns3_tx_spare_space(struct hns3_enet_ring * ring)970 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
971 {
972 struct hns3_tx_spare *tx_spare = ring->tx_spare;
973 u32 ntc, ntu;
974
975 /* This smp_load_acquire() pairs with smp_store_release() in
976 * hns3_tx_spare_update() called in tx desc cleaning process.
977 */
978 ntc = smp_load_acquire(&tx_spare->last_to_clean);
979 ntu = tx_spare->next_to_use;
980
981 if (ntc > ntu)
982 return ntc - ntu - 1;
983
984 /* The free tx buffer is divided into two part, so pick the
985 * larger one.
986 */
987 return max(ntc, tx_spare->len - ntu) - 1;
988 }
989
hns3_tx_spare_update(struct hns3_enet_ring * ring)990 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
991 {
992 struct hns3_tx_spare *tx_spare = ring->tx_spare;
993
994 if (!tx_spare ||
995 tx_spare->last_to_clean == tx_spare->next_to_clean)
996 return;
997
998 /* This smp_store_release() pairs with smp_load_acquire() in
999 * hns3_tx_spare_space() called in xmit process.
1000 */
1001 smp_store_release(&tx_spare->last_to_clean,
1002 tx_spare->next_to_clean);
1003 }
1004
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1005 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
1006 struct sk_buff *skb,
1007 u32 space)
1008 {
1009 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1010 skb_headlen(skb);
1011
1012 if (len > ring->tx_copybreak)
1013 return false;
1014
1015 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1016 hns3_ring_stats_update(ring, tx_spare_full);
1017 return false;
1018 }
1019
1020 return true;
1021 }
1022
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1023 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1024 struct sk_buff *skb,
1025 u32 space)
1026 {
1027 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1028 (!skb_has_frag_list(skb) &&
1029 skb_shinfo(skb)->nr_frags < tx_sgl))
1030 return false;
1031
1032 if (space < HNS3_MAX_SGL_SIZE) {
1033 hns3_ring_stats_update(ring, tx_spare_full);
1034 return false;
1035 }
1036
1037 return true;
1038 }
1039
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1040 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1041 {
1042 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1043 struct net_device *netdev = ring_to_netdev(ring);
1044 struct hns3_nic_priv *priv = netdev_priv(netdev);
1045 struct hns3_tx_spare *tx_spare;
1046 struct page *page;
1047 dma_addr_t dma;
1048 int order;
1049
1050 if (!alloc_size)
1051 return;
1052
1053 order = get_order(alloc_size);
1054 if (order > MAX_ORDER) {
1055 if (net_ratelimit())
1056 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1057 return;
1058 }
1059
1060 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1061 GFP_KERNEL);
1062 if (!tx_spare) {
1063 /* The driver still work without the tx spare buffer */
1064 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1065 goto devm_kzalloc_error;
1066 }
1067
1068 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1069 GFP_KERNEL, order);
1070 if (!page) {
1071 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1072 goto alloc_pages_error;
1073 }
1074
1075 dma = dma_map_page(ring_to_dev(ring), page, 0,
1076 PAGE_SIZE << order, DMA_TO_DEVICE);
1077 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1078 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1079 goto dma_mapping_error;
1080 }
1081
1082 tx_spare->dma = dma;
1083 tx_spare->buf = page_address(page);
1084 tx_spare->len = PAGE_SIZE << order;
1085 ring->tx_spare = tx_spare;
1086 ring->tx_copybreak = priv->tx_copybreak;
1087 return;
1088
1089 dma_mapping_error:
1090 put_page(page);
1091 alloc_pages_error:
1092 devm_kfree(ring_to_dev(ring), tx_spare);
1093 devm_kzalloc_error:
1094 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1095 }
1096
1097 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1098 * before calling below function to allocate tx buffer.
1099 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1100 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1101 unsigned int size, dma_addr_t *dma,
1102 u32 *cb_len)
1103 {
1104 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1105 u32 ntu = tx_spare->next_to_use;
1106
1107 size = ALIGN(size, dma_get_cache_alignment());
1108 *cb_len = size;
1109
1110 /* Tx spare buffer wraps back here because the end of
1111 * freed tx buffer is not enough.
1112 */
1113 if (ntu + size > tx_spare->len) {
1114 *cb_len += (tx_spare->len - ntu);
1115 ntu = 0;
1116 }
1117
1118 tx_spare->next_to_use = ntu + size;
1119 if (tx_spare->next_to_use == tx_spare->len)
1120 tx_spare->next_to_use = 0;
1121
1122 *dma = tx_spare->dma + ntu;
1123
1124 return tx_spare->buf + ntu;
1125 }
1126
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1127 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1128 {
1129 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1130
1131 if (len > tx_spare->next_to_use) {
1132 len -= tx_spare->next_to_use;
1133 tx_spare->next_to_use = tx_spare->len - len;
1134 } else {
1135 tx_spare->next_to_use -= len;
1136 }
1137 }
1138
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1139 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1140 struct hns3_desc_cb *cb)
1141 {
1142 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1143 u32 ntc = tx_spare->next_to_clean;
1144 u32 len = cb->length;
1145
1146 tx_spare->next_to_clean += len;
1147
1148 if (tx_spare->next_to_clean >= tx_spare->len) {
1149 tx_spare->next_to_clean -= tx_spare->len;
1150
1151 if (tx_spare->next_to_clean) {
1152 ntc = 0;
1153 len = tx_spare->next_to_clean;
1154 }
1155 }
1156
1157 /* This tx spare buffer is only really reclaimed after calling
1158 * hns3_tx_spare_update(), so it is still safe to use the info in
1159 * the tx buffer to do the dma sync or sg unmapping after
1160 * tx_spare->next_to_clean is moved forword.
1161 */
1162 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1163 dma_addr_t dma = tx_spare->dma + ntc;
1164
1165 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1166 DMA_TO_DEVICE);
1167 } else {
1168 struct sg_table *sgt = tx_spare->buf + ntc;
1169
1170 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1171 DMA_TO_DEVICE);
1172 }
1173 }
1174
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1175 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1176 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1177 {
1178 u32 l4_offset, hdr_len;
1179 union l3_hdr_info l3;
1180 union l4_hdr_info l4;
1181 u32 l4_paylen;
1182 int ret;
1183
1184 if (!skb_is_gso(skb))
1185 return 0;
1186
1187 ret = skb_cow_head(skb, 0);
1188 if (unlikely(ret < 0))
1189 return ret;
1190
1191 l3.hdr = skb_network_header(skb);
1192 l4.hdr = skb_transport_header(skb);
1193
1194 /* Software should clear the IPv4's checksum field when tso is
1195 * needed.
1196 */
1197 if (l3.v4->version == 4)
1198 l3.v4->check = 0;
1199
1200 /* tunnel packet */
1201 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1202 SKB_GSO_GRE_CSUM |
1203 SKB_GSO_UDP_TUNNEL |
1204 SKB_GSO_UDP_TUNNEL_CSUM)) {
1205 /* reset l3&l4 pointers from outer to inner headers */
1206 l3.hdr = skb_inner_network_header(skb);
1207 l4.hdr = skb_inner_transport_header(skb);
1208
1209 /* Software should clear the IPv4's checksum field when
1210 * tso is needed.
1211 */
1212 if (l3.v4->version == 4)
1213 l3.v4->check = 0;
1214 }
1215
1216 /* normal or tunnel packet */
1217 l4_offset = l4.hdr - skb->data;
1218
1219 /* remove payload length from inner pseudo checksum when tso */
1220 l4_paylen = skb->len - l4_offset;
1221
1222 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1223 hdr_len = sizeof(*l4.udp) + l4_offset;
1224 csum_replace_by_diff(&l4.udp->check,
1225 (__force __wsum)htonl(l4_paylen));
1226 } else {
1227 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1228 csum_replace_by_diff(&l4.tcp->check,
1229 (__force __wsum)htonl(l4_paylen));
1230 }
1231
1232 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1233
1234 /* find the txbd field values */
1235 *paylen_fdop_ol4cs = skb->len - hdr_len;
1236 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1237
1238 /* offload outer UDP header checksum */
1239 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1240 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1241
1242 /* get MSS for TSO */
1243 *mss = skb_shinfo(skb)->gso_size;
1244
1245 trace_hns3_tso(skb);
1246
1247 return 0;
1248 }
1249
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1250 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1251 u8 *il4_proto)
1252 {
1253 union l3_hdr_info l3;
1254 unsigned char *l4_hdr;
1255 unsigned char *exthdr;
1256 u8 l4_proto_tmp;
1257 __be16 frag_off;
1258
1259 /* find outer header point */
1260 l3.hdr = skb_network_header(skb);
1261 l4_hdr = skb_transport_header(skb);
1262
1263 if (skb->protocol == htons(ETH_P_IPV6)) {
1264 exthdr = l3.hdr + sizeof(*l3.v6);
1265 l4_proto_tmp = l3.v6->nexthdr;
1266 if (l4_hdr != exthdr)
1267 ipv6_skip_exthdr(skb, exthdr - skb->data,
1268 &l4_proto_tmp, &frag_off);
1269 } else if (skb->protocol == htons(ETH_P_IP)) {
1270 l4_proto_tmp = l3.v4->protocol;
1271 } else {
1272 return -EINVAL;
1273 }
1274
1275 *ol4_proto = l4_proto_tmp;
1276
1277 /* tunnel packet */
1278 if (!skb->encapsulation) {
1279 *il4_proto = 0;
1280 return 0;
1281 }
1282
1283 /* find inner header point */
1284 l3.hdr = skb_inner_network_header(skb);
1285 l4_hdr = skb_inner_transport_header(skb);
1286
1287 if (l3.v6->version == 6) {
1288 exthdr = l3.hdr + sizeof(*l3.v6);
1289 l4_proto_tmp = l3.v6->nexthdr;
1290 if (l4_hdr != exthdr)
1291 ipv6_skip_exthdr(skb, exthdr - skb->data,
1292 &l4_proto_tmp, &frag_off);
1293 } else if (l3.v4->version == 4) {
1294 l4_proto_tmp = l3.v4->protocol;
1295 }
1296
1297 *il4_proto = l4_proto_tmp;
1298
1299 return 0;
1300 }
1301
1302 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1303 * and it is udp packet, which has a dest port as the IANA assigned.
1304 * the hardware is expected to do the checksum offload, but the
1305 * hardware will not do the checksum offload when udp dest port is
1306 * 4789, 4790 or 6081.
1307 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1308 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1309 {
1310 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1311 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1312 union l4_hdr_info l4;
1313
1314 /* device version above V3(include V3), the hardware can
1315 * do this checksum offload.
1316 */
1317 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1318 return false;
1319
1320 l4.hdr = skb_transport_header(skb);
1321
1322 if (!(!skb->encapsulation &&
1323 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1324 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1325 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1326 return false;
1327
1328 return true;
1329 }
1330
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1331 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1332 u32 *ol_type_vlan_len_msec)
1333 {
1334 u32 l2_len, l3_len, l4_len;
1335 unsigned char *il2_hdr;
1336 union l3_hdr_info l3;
1337 union l4_hdr_info l4;
1338
1339 l3.hdr = skb_network_header(skb);
1340 l4.hdr = skb_transport_header(skb);
1341
1342 /* compute OL2 header size, defined in 2 Bytes */
1343 l2_len = l3.hdr - skb->data;
1344 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1345
1346 /* compute OL3 header size, defined in 4 Bytes */
1347 l3_len = l4.hdr - l3.hdr;
1348 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1349
1350 il2_hdr = skb_inner_mac_header(skb);
1351 /* compute OL4 header size, defined in 4 Bytes */
1352 l4_len = il2_hdr - l4.hdr;
1353 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1354
1355 /* define outer network header type */
1356 if (skb->protocol == htons(ETH_P_IP)) {
1357 if (skb_is_gso(skb))
1358 hns3_set_field(*ol_type_vlan_len_msec,
1359 HNS3_TXD_OL3T_S,
1360 HNS3_OL3T_IPV4_CSUM);
1361 else
1362 hns3_set_field(*ol_type_vlan_len_msec,
1363 HNS3_TXD_OL3T_S,
1364 HNS3_OL3T_IPV4_NO_CSUM);
1365 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1366 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1367 HNS3_OL3T_IPV6);
1368 }
1369
1370 if (ol4_proto == IPPROTO_UDP)
1371 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1372 HNS3_TUN_MAC_IN_UDP);
1373 else if (ol4_proto == IPPROTO_GRE)
1374 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1375 HNS3_TUN_NVGRE);
1376 }
1377
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1378 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1379 u32 *type_cs_vlan_tso)
1380 {
1381 if (l3.v4->version == 4) {
1382 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1383 HNS3_L3T_IPV4);
1384
1385 /* the stack computes the IP header already, the only time we
1386 * need the hardware to recompute it is in the case of TSO.
1387 */
1388 if (skb_is_gso(skb))
1389 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1390 } else if (l3.v6->version == 6) {
1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1392 HNS3_L3T_IPV6);
1393 }
1394 }
1395
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1396 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1397 u32 l4_proto, u32 *type_cs_vlan_tso)
1398 {
1399 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1400 switch (l4_proto) {
1401 case IPPROTO_TCP:
1402 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1403 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1404 HNS3_L4T_TCP);
1405 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1406 l4.tcp->doff);
1407 break;
1408 case IPPROTO_UDP:
1409 if (hns3_tunnel_csum_bug(skb)) {
1410 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1411
1412 return ret ? ret : skb_checksum_help(skb);
1413 }
1414
1415 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1417 HNS3_L4T_UDP);
1418 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1419 (sizeof(struct udphdr) >> 2));
1420 break;
1421 case IPPROTO_SCTP:
1422 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1423 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1424 HNS3_L4T_SCTP);
1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1426 (sizeof(struct sctphdr) >> 2));
1427 break;
1428 default:
1429 /* drop the skb tunnel packet if hardware don't support,
1430 * because hardware can't calculate csum when TSO.
1431 */
1432 if (skb_is_gso(skb))
1433 return -EDOM;
1434
1435 /* the stack computes the IP header already,
1436 * driver calculate l4 checksum when not TSO.
1437 */
1438 return skb_checksum_help(skb);
1439 }
1440
1441 return 0;
1442 }
1443
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1444 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1445 u8 il4_proto, u32 *type_cs_vlan_tso,
1446 u32 *ol_type_vlan_len_msec)
1447 {
1448 unsigned char *l2_hdr = skb->data;
1449 u32 l4_proto = ol4_proto;
1450 union l4_hdr_info l4;
1451 union l3_hdr_info l3;
1452 u32 l2_len, l3_len;
1453
1454 l4.hdr = skb_transport_header(skb);
1455 l3.hdr = skb_network_header(skb);
1456
1457 /* handle encapsulation skb */
1458 if (skb->encapsulation) {
1459 /* If this is a not UDP/GRE encapsulation skb */
1460 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1461 /* drop the skb tunnel packet if hardware don't support,
1462 * because hardware can't calculate csum when TSO.
1463 */
1464 if (skb_is_gso(skb))
1465 return -EDOM;
1466
1467 /* the stack computes the IP header already,
1468 * driver calculate l4 checksum when not TSO.
1469 */
1470 return skb_checksum_help(skb);
1471 }
1472
1473 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1474
1475 /* switch to inner header */
1476 l2_hdr = skb_inner_mac_header(skb);
1477 l3.hdr = skb_inner_network_header(skb);
1478 l4.hdr = skb_inner_transport_header(skb);
1479 l4_proto = il4_proto;
1480 }
1481
1482 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1483
1484 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1485 l2_len = l3.hdr - l2_hdr;
1486 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1487
1488 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1489 l3_len = l4.hdr - l3.hdr;
1490 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1491
1492 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1493 }
1494
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1495 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1496 struct sk_buff *skb)
1497 {
1498 struct hnae3_handle *handle = tx_ring->tqp->handle;
1499 struct hnae3_ae_dev *ae_dev;
1500 struct vlan_ethhdr *vhdr;
1501 int rc;
1502
1503 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1504 skb_vlan_tag_present(skb)))
1505 return 0;
1506
1507 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1508 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1509 * will cause RAS error.
1510 */
1511 ae_dev = pci_get_drvdata(handle->pdev);
1512 if (unlikely(skb_vlan_tagged_multi(skb) &&
1513 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1514 handle->port_base_vlan_state ==
1515 HNAE3_PORT_BASE_VLAN_ENABLE))
1516 return -EINVAL;
1517
1518 if (skb->protocol == htons(ETH_P_8021Q) &&
1519 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1520 /* When HW VLAN acceleration is turned off, and the stack
1521 * sets the protocol to 802.1q, the driver just need to
1522 * set the protocol to the encapsulated ethertype.
1523 */
1524 skb->protocol = vlan_get_protocol(skb);
1525 return 0;
1526 }
1527
1528 if (skb_vlan_tag_present(skb)) {
1529 /* Based on hw strategy, use out_vtag in two layer tag case,
1530 * and use inner_vtag in one tag case.
1531 */
1532 if (skb->protocol == htons(ETH_P_8021Q) &&
1533 handle->port_base_vlan_state ==
1534 HNAE3_PORT_BASE_VLAN_DISABLE)
1535 rc = HNS3_OUTER_VLAN_TAG;
1536 else
1537 rc = HNS3_INNER_VLAN_TAG;
1538
1539 skb->protocol = vlan_get_protocol(skb);
1540 return rc;
1541 }
1542
1543 rc = skb_cow_head(skb, 0);
1544 if (unlikely(rc < 0))
1545 return rc;
1546
1547 vhdr = skb_vlan_eth_hdr(skb);
1548 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1549 & VLAN_PRIO_MASK);
1550
1551 skb->protocol = vlan_get_protocol(skb);
1552 return 0;
1553 }
1554
1555 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1556 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1557 {
1558 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1559
1560 /* Kindly note, due to backward compatibility of the TX descriptor,
1561 * HW checksum of the non-IP packets and GSO packets is handled at
1562 * different place in the following code
1563 */
1564 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1565 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1566 return false;
1567
1568 return true;
1569 }
1570
1571 struct hns3_desc_param {
1572 u32 paylen_ol4cs;
1573 u32 ol_type_vlan_len_msec;
1574 u32 type_cs_vlan_tso;
1575 u16 mss_hw_csum;
1576 u16 inner_vtag;
1577 u16 out_vtag;
1578 };
1579
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1580 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1581 {
1582 pa->paylen_ol4cs = skb->len;
1583 pa->ol_type_vlan_len_msec = 0;
1584 pa->type_cs_vlan_tso = 0;
1585 pa->mss_hw_csum = 0;
1586 pa->inner_vtag = 0;
1587 pa->out_vtag = 0;
1588 }
1589
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1590 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1591 struct sk_buff *skb,
1592 struct hns3_desc_param *param)
1593 {
1594 int ret;
1595
1596 ret = hns3_handle_vtags(ring, skb);
1597 if (unlikely(ret < 0)) {
1598 hns3_ring_stats_update(ring, tx_vlan_err);
1599 return ret;
1600 } else if (ret == HNS3_INNER_VLAN_TAG) {
1601 param->inner_vtag = skb_vlan_tag_get(skb);
1602 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1603 VLAN_PRIO_MASK;
1604 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1605 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1606 param->out_vtag = skb_vlan_tag_get(skb);
1607 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1608 VLAN_PRIO_MASK;
1609 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1610 1);
1611 }
1612 return 0;
1613 }
1614
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1615 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1616 struct sk_buff *skb,
1617 struct hns3_desc_cb *desc_cb,
1618 struct hns3_desc_param *param)
1619 {
1620 u8 ol4_proto, il4_proto;
1621 int ret;
1622
1623 if (hns3_check_hw_tx_csum(skb)) {
1624 /* set checksum start and offset, defined in 2 Bytes */
1625 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1626 skb_checksum_start_offset(skb) >> 1);
1627 hns3_set_field(param->ol_type_vlan_len_msec,
1628 HNS3_TXD_CSUM_OFFSET_S,
1629 skb->csum_offset >> 1);
1630 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1631 return 0;
1632 }
1633
1634 skb_reset_mac_len(skb);
1635
1636 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1637 if (unlikely(ret < 0)) {
1638 hns3_ring_stats_update(ring, tx_l4_proto_err);
1639 return ret;
1640 }
1641
1642 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1643 ¶m->type_cs_vlan_tso,
1644 ¶m->ol_type_vlan_len_msec);
1645 if (unlikely(ret < 0)) {
1646 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1647 return ret;
1648 }
1649
1650 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1651 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1652 if (unlikely(ret < 0)) {
1653 hns3_ring_stats_update(ring, tx_tso_err);
1654 return ret;
1655 }
1656 return 0;
1657 }
1658
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1659 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1660 struct sk_buff *skb, struct hns3_desc *desc,
1661 struct hns3_desc_cb *desc_cb)
1662 {
1663 struct hns3_desc_param param;
1664 int ret;
1665
1666 hns3_init_desc_data(skb, ¶m);
1667 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1668 if (unlikely(ret < 0))
1669 return ret;
1670
1671 desc_cb->send_bytes = skb->len;
1672
1673 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1674 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1675 if (ret)
1676 return ret;
1677 }
1678
1679 /* Set txbd */
1680 desc->tx.ol_type_vlan_len_msec =
1681 cpu_to_le32(param.ol_type_vlan_len_msec);
1682 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1683 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1684 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1685 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1686 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1687
1688 return 0;
1689 }
1690
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1691 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1692 unsigned int size)
1693 {
1694 #define HNS3_LIKELY_BD_NUM 1
1695
1696 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1697 unsigned int frag_buf_num;
1698 int k, sizeoflast;
1699
1700 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1701 desc->addr = cpu_to_le64(dma);
1702 desc->tx.send_size = cpu_to_le16(size);
1703 desc->tx.bdtp_fe_sc_vld_ra_ri =
1704 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1705
1706 trace_hns3_tx_desc(ring, ring->next_to_use);
1707 ring_ptr_move_fw(ring, next_to_use);
1708 return HNS3_LIKELY_BD_NUM;
1709 }
1710
1711 frag_buf_num = hns3_tx_bd_count(size);
1712 sizeoflast = size % HNS3_MAX_BD_SIZE;
1713 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1714
1715 /* When frag size is bigger than hardware limit, split this frag */
1716 for (k = 0; k < frag_buf_num; k++) {
1717 /* now, fill the descriptor */
1718 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1719 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1720 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1721 desc->tx.bdtp_fe_sc_vld_ra_ri =
1722 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1723
1724 trace_hns3_tx_desc(ring, ring->next_to_use);
1725 /* move ring pointer to next */
1726 ring_ptr_move_fw(ring, next_to_use);
1727
1728 desc = &ring->desc[ring->next_to_use];
1729 }
1730
1731 return frag_buf_num;
1732 }
1733
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1734 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1735 unsigned int type)
1736 {
1737 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1738 struct device *dev = ring_to_dev(ring);
1739 unsigned int size;
1740 dma_addr_t dma;
1741
1742 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1743 struct sk_buff *skb = (struct sk_buff *)priv;
1744
1745 size = skb_headlen(skb);
1746 if (!size)
1747 return 0;
1748
1749 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1750 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1751 /* Head data has been filled in hns3_handle_tx_bounce(),
1752 * just return 0 here.
1753 */
1754 return 0;
1755 } else {
1756 skb_frag_t *frag = (skb_frag_t *)priv;
1757
1758 size = skb_frag_size(frag);
1759 if (!size)
1760 return 0;
1761
1762 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1763 }
1764
1765 if (unlikely(dma_mapping_error(dev, dma))) {
1766 hns3_ring_stats_update(ring, sw_err_cnt);
1767 return -ENOMEM;
1768 }
1769
1770 desc_cb->priv = priv;
1771 desc_cb->length = size;
1772 desc_cb->dma = dma;
1773 desc_cb->type = type;
1774
1775 return hns3_fill_desc(ring, dma, size);
1776 }
1777
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1778 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1779 unsigned int bd_num)
1780 {
1781 unsigned int size;
1782 int i;
1783
1784 size = skb_headlen(skb);
1785 while (size > HNS3_MAX_BD_SIZE) {
1786 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1787 size -= HNS3_MAX_BD_SIZE;
1788
1789 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1790 return bd_num;
1791 }
1792
1793 if (size) {
1794 bd_size[bd_num++] = size;
1795 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1796 return bd_num;
1797 }
1798
1799 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1800 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1801 size = skb_frag_size(frag);
1802 if (!size)
1803 continue;
1804
1805 while (size > HNS3_MAX_BD_SIZE) {
1806 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1807 size -= HNS3_MAX_BD_SIZE;
1808
1809 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1810 return bd_num;
1811 }
1812
1813 bd_size[bd_num++] = size;
1814 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1815 return bd_num;
1816 }
1817
1818 return bd_num;
1819 }
1820
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1821 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1822 u8 max_non_tso_bd_num, unsigned int bd_num,
1823 unsigned int recursion_level)
1824 {
1825 #define HNS3_MAX_RECURSION_LEVEL 24
1826
1827 struct sk_buff *frag_skb;
1828
1829 /* If the total len is within the max bd limit */
1830 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1831 !skb_has_frag_list(skb) &&
1832 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1833 return skb_shinfo(skb)->nr_frags + 1U;
1834
1835 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1836 return UINT_MAX;
1837
1838 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1839 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1840 return bd_num;
1841
1842 skb_walk_frags(skb, frag_skb) {
1843 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1844 bd_num, recursion_level + 1);
1845 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1846 return bd_num;
1847 }
1848
1849 return bd_num;
1850 }
1851
hns3_gso_hdr_len(struct sk_buff * skb)1852 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1853 {
1854 if (!skb->encapsulation)
1855 return skb_tcp_all_headers(skb);
1856
1857 return skb_inner_tcp_all_headers(skb);
1858 }
1859
1860 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1861 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1862 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1863 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1864 * than MSS except the last max_non_tso_bd_num - 1 frags.
1865 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1866 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1867 unsigned int bd_num, u8 max_non_tso_bd_num)
1868 {
1869 unsigned int tot_len = 0;
1870 int i;
1871
1872 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1873 tot_len += bd_size[i];
1874
1875 /* ensure the first max_non_tso_bd_num frags is greater than
1876 * mss + header
1877 */
1878 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1879 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1880 return true;
1881
1882 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1883 * than mss except the last one.
1884 */
1885 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1886 tot_len -= bd_size[i];
1887 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1888
1889 if (tot_len < skb_shinfo(skb)->gso_size)
1890 return true;
1891 }
1892
1893 return false;
1894 }
1895
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1896 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1897 {
1898 int i;
1899
1900 for (i = 0; i < MAX_SKB_FRAGS; i++)
1901 size[i] = skb_frag_size(&shinfo->frags[i]);
1902 }
1903
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1904 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1905 struct sk_buff *skb,
1906 unsigned int bd_num)
1907 {
1908 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1909 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1910 */
1911 if (bd_num == UINT_MAX) {
1912 hns3_ring_stats_update(ring, over_max_recursion);
1913 return -ENOMEM;
1914 }
1915
1916 /* The skb->len has exceeded the hw limitation, linearization
1917 * will not help.
1918 */
1919 if (skb->len > HNS3_MAX_TSO_SIZE ||
1920 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1921 hns3_ring_stats_update(ring, hw_limitation);
1922 return -ENOMEM;
1923 }
1924
1925 if (__skb_linearize(skb)) {
1926 hns3_ring_stats_update(ring, sw_err_cnt);
1927 return -ENOMEM;
1928 }
1929
1930 return 0;
1931 }
1932
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1933 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1934 struct net_device *netdev,
1935 struct sk_buff *skb)
1936 {
1937 struct hns3_nic_priv *priv = netdev_priv(netdev);
1938 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1939 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1940 unsigned int bd_num;
1941
1942 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1943 if (unlikely(bd_num > max_non_tso_bd_num)) {
1944 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1945 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1946 max_non_tso_bd_num)) {
1947 trace_hns3_over_max_bd(skb);
1948 goto out;
1949 }
1950
1951 if (hns3_skb_linearize(ring, skb, bd_num))
1952 return -ENOMEM;
1953
1954 bd_num = hns3_tx_bd_count(skb->len);
1955
1956 hns3_ring_stats_update(ring, tx_copy);
1957 }
1958
1959 out:
1960 if (likely(ring_space(ring) >= bd_num))
1961 return bd_num;
1962
1963 netif_stop_subqueue(netdev, ring->queue_index);
1964 smp_mb(); /* Memory barrier before checking ring_space */
1965
1966 /* Start queue in case hns3_clean_tx_ring has just made room
1967 * available and has not seen the queue stopped state performed
1968 * by netif_stop_subqueue above.
1969 */
1970 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1971 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1972 netif_start_subqueue(netdev, ring->queue_index);
1973 return bd_num;
1974 }
1975
1976 hns3_ring_stats_update(ring, tx_busy);
1977
1978 return -EBUSY;
1979 }
1980
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)1981 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1982 {
1983 struct device *dev = ring_to_dev(ring);
1984 unsigned int i;
1985
1986 for (i = 0; i < ring->desc_num; i++) {
1987 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1988 struct hns3_desc_cb *desc_cb;
1989
1990 memset(desc, 0, sizeof(*desc));
1991
1992 /* check if this is where we started */
1993 if (ring->next_to_use == next_to_use_orig)
1994 break;
1995
1996 /* rollback one */
1997 ring_ptr_move_bw(ring, next_to_use);
1998
1999 desc_cb = &ring->desc_cb[ring->next_to_use];
2000
2001 if (!desc_cb->dma)
2002 continue;
2003
2004 /* unmap the descriptor dma address */
2005 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
2006 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
2007 DMA_TO_DEVICE);
2008 else if (desc_cb->type &
2009 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
2010 hns3_tx_spare_rollback(ring, desc_cb->length);
2011 else if (desc_cb->length)
2012 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2013 DMA_TO_DEVICE);
2014
2015 desc_cb->length = 0;
2016 desc_cb->dma = 0;
2017 desc_cb->type = DESC_TYPE_UNKNOWN;
2018 }
2019 }
2020
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2021 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2022 struct sk_buff *skb, unsigned int type)
2023 {
2024 struct sk_buff *frag_skb;
2025 int i, ret, bd_num = 0;
2026
2027 ret = hns3_map_and_fill_desc(ring, skb, type);
2028 if (unlikely(ret < 0))
2029 return ret;
2030
2031 bd_num += ret;
2032
2033 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2034 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2035
2036 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2037 if (unlikely(ret < 0))
2038 return ret;
2039
2040 bd_num += ret;
2041 }
2042
2043 skb_walk_frags(skb, frag_skb) {
2044 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2045 DESC_TYPE_FRAGLIST_SKB);
2046 if (unlikely(ret < 0))
2047 return ret;
2048
2049 bd_num += ret;
2050 }
2051
2052 return bd_num;
2053 }
2054
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2055 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2056 {
2057 #define HNS3_BYTES_PER_64BIT 8
2058
2059 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2060 int offset = 0;
2061
2062 /* make sure everything is visible to device before
2063 * excuting tx push or updating doorbell
2064 */
2065 dma_wmb();
2066
2067 do {
2068 int idx = (ring->next_to_use - num + ring->desc_num) %
2069 ring->desc_num;
2070
2071 u64_stats_update_begin(&ring->syncp);
2072 ring->stats.tx_push++;
2073 u64_stats_update_end(&ring->syncp);
2074 memcpy(&desc[offset], &ring->desc[idx],
2075 sizeof(struct hns3_desc));
2076 offset++;
2077 } while (--num);
2078
2079 __iowrite64_copy(ring->tqp->mem_base, desc,
2080 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2081 HNS3_BYTES_PER_64BIT);
2082
2083 io_stop_wc();
2084 }
2085
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2086 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2087 {
2088 #define HNS3_MEM_DOORBELL_OFFSET 64
2089
2090 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2091
2092 /* make sure everything is visible to device before
2093 * excuting tx push or updating doorbell
2094 */
2095 dma_wmb();
2096
2097 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2098 &bd_num, 1);
2099 u64_stats_update_begin(&ring->syncp);
2100 ring->stats.tx_mem_doorbell += ring->pending_buf;
2101 u64_stats_update_end(&ring->syncp);
2102
2103 io_stop_wc();
2104 }
2105
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2106 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2107 bool doorbell)
2108 {
2109 struct net_device *netdev = ring_to_netdev(ring);
2110 struct hns3_nic_priv *priv = netdev_priv(netdev);
2111
2112 /* when tx push is enabled, the packet whose number of BD below
2113 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2114 */
2115 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2116 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2117 /* This smp_store_release() pairs with smp_load_aquire() in
2118 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2119 * is updated.
2120 */
2121 smp_store_release(&ring->last_to_use, ring->next_to_use);
2122 hns3_tx_push_bd(ring, num);
2123 return;
2124 }
2125
2126 ring->pending_buf += num;
2127
2128 if (!doorbell) {
2129 hns3_ring_stats_update(ring, tx_more);
2130 return;
2131 }
2132
2133 /* This smp_store_release() pairs with smp_load_aquire() in
2134 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2135 */
2136 smp_store_release(&ring->last_to_use, ring->next_to_use);
2137
2138 if (ring->tqp->mem_base)
2139 hns3_tx_mem_doorbell(ring);
2140 else
2141 writel(ring->pending_buf,
2142 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2143
2144 ring->pending_buf = 0;
2145 }
2146
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2147 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2148 struct hns3_desc *desc)
2149 {
2150 struct hnae3_handle *h = hns3_get_handle(netdev);
2151
2152 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2153 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2154 return;
2155
2156 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2157 }
2158
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2159 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2160 struct sk_buff *skb)
2161 {
2162 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2163 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2164 unsigned int size = skb_headlen(skb);
2165 dma_addr_t dma;
2166 int bd_num = 0;
2167 u32 cb_len;
2168 void *buf;
2169 int ret;
2170
2171 if (skb->len <= ring->tx_copybreak) {
2172 size = skb->len;
2173 type = DESC_TYPE_BOUNCE_ALL;
2174 }
2175
2176 /* hns3_can_use_tx_bounce() is called to ensure the below
2177 * function can always return the tx buffer.
2178 */
2179 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2180
2181 ret = skb_copy_bits(skb, 0, buf, size);
2182 if (unlikely(ret < 0)) {
2183 hns3_tx_spare_rollback(ring, cb_len);
2184 hns3_ring_stats_update(ring, copy_bits_err);
2185 return ret;
2186 }
2187
2188 desc_cb->priv = skb;
2189 desc_cb->length = cb_len;
2190 desc_cb->dma = dma;
2191 desc_cb->type = type;
2192
2193 bd_num += hns3_fill_desc(ring, dma, size);
2194
2195 if (type == DESC_TYPE_BOUNCE_HEAD) {
2196 ret = hns3_fill_skb_to_desc(ring, skb,
2197 DESC_TYPE_BOUNCE_HEAD);
2198 if (unlikely(ret < 0))
2199 return ret;
2200
2201 bd_num += ret;
2202 }
2203
2204 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2205 DMA_TO_DEVICE);
2206
2207 hns3_ring_stats_update(ring, tx_bounce);
2208
2209 return bd_num;
2210 }
2211
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2212 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2213 struct sk_buff *skb)
2214 {
2215 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2216 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2217 struct sg_table *sgt;
2218 int i, bd_num = 0;
2219 dma_addr_t dma;
2220 u32 cb_len;
2221 int nents;
2222
2223 if (skb_has_frag_list(skb))
2224 nfrag = HNS3_MAX_TSO_BD_NUM;
2225
2226 /* hns3_can_use_tx_sgl() is called to ensure the below
2227 * function can always return the tx buffer.
2228 */
2229 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2230 &dma, &cb_len);
2231
2232 /* scatterlist follows by the sg table */
2233 sgt->sgl = (struct scatterlist *)(sgt + 1);
2234 sg_init_table(sgt->sgl, nfrag);
2235 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2236 if (unlikely(nents < 0)) {
2237 hns3_tx_spare_rollback(ring, cb_len);
2238 hns3_ring_stats_update(ring, skb2sgl_err);
2239 return -ENOMEM;
2240 }
2241
2242 sgt->orig_nents = nents;
2243 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2244 DMA_TO_DEVICE);
2245 if (unlikely(!sgt->nents)) {
2246 hns3_tx_spare_rollback(ring, cb_len);
2247 hns3_ring_stats_update(ring, map_sg_err);
2248 return -ENOMEM;
2249 }
2250
2251 desc_cb->priv = skb;
2252 desc_cb->length = cb_len;
2253 desc_cb->dma = dma;
2254 desc_cb->type = DESC_TYPE_SGL_SKB;
2255
2256 for (i = 0; i < sgt->nents; i++)
2257 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2258 sg_dma_len(sgt->sgl + i));
2259 hns3_ring_stats_update(ring, tx_sgl);
2260
2261 return bd_num;
2262 }
2263
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2264 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2265 struct sk_buff *skb)
2266 {
2267 u32 space;
2268
2269 if (!ring->tx_spare)
2270 goto out;
2271
2272 space = hns3_tx_spare_space(ring);
2273
2274 if (hns3_can_use_tx_sgl(ring, skb, space))
2275 return hns3_handle_tx_sgl(ring, skb);
2276
2277 if (hns3_can_use_tx_bounce(ring, skb, space))
2278 return hns3_handle_tx_bounce(ring, skb);
2279
2280 out:
2281 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2282 }
2283
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2284 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2285 struct sk_buff *skb,
2286 struct hns3_desc_cb *desc_cb,
2287 int next_to_use_head)
2288 {
2289 int ret;
2290
2291 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2292 desc_cb);
2293 if (unlikely(ret < 0))
2294 goto fill_err;
2295
2296 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2297 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2298 * need to be notified to the hw.
2299 */
2300 ret = hns3_handle_desc_filling(ring, skb);
2301 if (likely(ret > 0))
2302 return ret;
2303
2304 fill_err:
2305 hns3_clear_desc(ring, next_to_use_head);
2306 return ret;
2307 }
2308
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2309 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2310 {
2311 struct hns3_nic_priv *priv = netdev_priv(netdev);
2312 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2313 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2314 struct netdev_queue *dev_queue;
2315 int pre_ntu, ret;
2316 bool doorbell;
2317
2318 /* Hardware can only handle short frames above 32 bytes */
2319 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2320 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2321
2322 hns3_ring_stats_update(ring, sw_err_cnt);
2323
2324 return NETDEV_TX_OK;
2325 }
2326
2327 /* Prefetch the data used later */
2328 prefetch(skb->data);
2329
2330 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2331 if (unlikely(ret <= 0)) {
2332 if (ret == -EBUSY) {
2333 hns3_tx_doorbell(ring, 0, true);
2334 return NETDEV_TX_BUSY;
2335 }
2336
2337 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2338 goto out_err_tx_ok;
2339 }
2340
2341 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2342 if (unlikely(ret <= 0))
2343 goto out_err_tx_ok;
2344
2345 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2346 (ring->desc_num - 1);
2347
2348 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2349 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2350
2351 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2352 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2353 trace_hns3_tx_desc(ring, pre_ntu);
2354
2355 skb_tx_timestamp(skb);
2356
2357 /* Complete translate all packets */
2358 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2359 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2360 netdev_xmit_more());
2361 hns3_tx_doorbell(ring, ret, doorbell);
2362
2363 return NETDEV_TX_OK;
2364
2365 out_err_tx_ok:
2366 dev_kfree_skb_any(skb);
2367 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2368 return NETDEV_TX_OK;
2369 }
2370
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2371 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2372 {
2373 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2374 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2375 struct hnae3_handle *h = hns3_get_handle(netdev);
2376 struct sockaddr *mac_addr = p;
2377 int ret;
2378
2379 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2380 return -EADDRNOTAVAIL;
2381
2382 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2383 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2384 netdev_info(netdev, "already using mac address %s\n",
2385 format_mac_addr_sa);
2386 return 0;
2387 }
2388
2389 /* For VF device, if there is a perm_addr, then the user will not
2390 * be allowed to change the address.
2391 */
2392 if (!hns3_is_phys_func(h->pdev) &&
2393 !is_zero_ether_addr(netdev->perm_addr)) {
2394 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2395 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2396 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2397 format_mac_addr_perm, format_mac_addr_sa);
2398 return -EPERM;
2399 }
2400
2401 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2402 if (ret) {
2403 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2404 return ret;
2405 }
2406
2407 eth_hw_addr_set(netdev, mac_addr->sa_data);
2408
2409 return 0;
2410 }
2411
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2412 static int hns3_nic_do_ioctl(struct net_device *netdev,
2413 struct ifreq *ifr, int cmd)
2414 {
2415 struct hnae3_handle *h = hns3_get_handle(netdev);
2416
2417 if (!netif_running(netdev))
2418 return -EINVAL;
2419
2420 if (!h->ae_algo->ops->do_ioctl)
2421 return -EOPNOTSUPP;
2422
2423 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2424 }
2425
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2426 static int hns3_nic_set_features(struct net_device *netdev,
2427 netdev_features_t features)
2428 {
2429 netdev_features_t changed = netdev->features ^ features;
2430 struct hns3_nic_priv *priv = netdev_priv(netdev);
2431 struct hnae3_handle *h = priv->ae_handle;
2432 bool enable;
2433 int ret;
2434
2435 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2436 enable = !!(features & NETIF_F_GRO_HW);
2437 ret = h->ae_algo->ops->set_gro_en(h, enable);
2438 if (ret)
2439 return ret;
2440 }
2441
2442 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2443 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2444 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2445 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2446 if (ret)
2447 return ret;
2448 }
2449
2450 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2451 enable = !!(features & NETIF_F_NTUPLE);
2452 h->ae_algo->ops->enable_fd(h, enable);
2453 }
2454
2455 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2456 h->ae_algo->ops->cls_flower_active(h)) {
2457 netdev_err(netdev,
2458 "there are offloaded TC filters active, cannot disable HW TC offload");
2459 return -EINVAL;
2460 }
2461
2462 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2463 h->ae_algo->ops->enable_vlan_filter) {
2464 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2465 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2466 if (ret)
2467 return ret;
2468 }
2469
2470 netdev->features = features;
2471 return 0;
2472 }
2473
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2474 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2475 struct net_device *dev,
2476 netdev_features_t features)
2477 {
2478 #define HNS3_MAX_HDR_LEN 480U
2479 #define HNS3_MAX_L4_HDR_LEN 60U
2480
2481 size_t len;
2482
2483 if (skb->ip_summed != CHECKSUM_PARTIAL)
2484 return features;
2485
2486 if (skb->encapsulation)
2487 len = skb_inner_transport_header(skb) - skb->data;
2488 else
2489 len = skb_transport_header(skb) - skb->data;
2490
2491 /* Assume L4 is 60 byte as TCP is the only protocol with a
2492 * a flexible value, and it's max len is 60 bytes.
2493 */
2494 len += HNS3_MAX_L4_HDR_LEN;
2495
2496 /* Hardware only supports checksum on the skb with a max header
2497 * len of 480 bytes.
2498 */
2499 if (len > HNS3_MAX_HDR_LEN)
2500 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2501
2502 return features;
2503 }
2504
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2505 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2506 struct hns3_enet_ring *ring, bool is_tx)
2507 {
2508 unsigned int start;
2509
2510 do {
2511 start = u64_stats_fetch_begin(&ring->syncp);
2512 if (is_tx) {
2513 stats->tx_bytes += ring->stats.tx_bytes;
2514 stats->tx_packets += ring->stats.tx_pkts;
2515 stats->tx_dropped += ring->stats.sw_err_cnt;
2516 stats->tx_dropped += ring->stats.tx_vlan_err;
2517 stats->tx_dropped += ring->stats.tx_l4_proto_err;
2518 stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2519 stats->tx_dropped += ring->stats.tx_tso_err;
2520 stats->tx_dropped += ring->stats.over_max_recursion;
2521 stats->tx_dropped += ring->stats.hw_limitation;
2522 stats->tx_dropped += ring->stats.copy_bits_err;
2523 stats->tx_dropped += ring->stats.skb2sgl_err;
2524 stats->tx_dropped += ring->stats.map_sg_err;
2525 stats->tx_errors += ring->stats.sw_err_cnt;
2526 stats->tx_errors += ring->stats.tx_vlan_err;
2527 stats->tx_errors += ring->stats.tx_l4_proto_err;
2528 stats->tx_errors += ring->stats.tx_l2l3l4_err;
2529 stats->tx_errors += ring->stats.tx_tso_err;
2530 stats->tx_errors += ring->stats.over_max_recursion;
2531 stats->tx_errors += ring->stats.hw_limitation;
2532 stats->tx_errors += ring->stats.copy_bits_err;
2533 stats->tx_errors += ring->stats.skb2sgl_err;
2534 stats->tx_errors += ring->stats.map_sg_err;
2535 } else {
2536 stats->rx_bytes += ring->stats.rx_bytes;
2537 stats->rx_packets += ring->stats.rx_pkts;
2538 stats->rx_dropped += ring->stats.l2_err;
2539 stats->rx_errors += ring->stats.l2_err;
2540 stats->rx_errors += ring->stats.l3l4_csum_err;
2541 stats->rx_crc_errors += ring->stats.l2_err;
2542 stats->multicast += ring->stats.rx_multicast;
2543 stats->rx_length_errors += ring->stats.err_pkt_len;
2544 }
2545 } while (u64_stats_fetch_retry(&ring->syncp, start));
2546 }
2547
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2548 static void hns3_nic_get_stats64(struct net_device *netdev,
2549 struct rtnl_link_stats64 *stats)
2550 {
2551 struct hns3_nic_priv *priv = netdev_priv(netdev);
2552 int queue_num = priv->ae_handle->kinfo.num_tqps;
2553 struct hnae3_handle *handle = priv->ae_handle;
2554 struct rtnl_link_stats64 ring_total_stats;
2555 struct hns3_enet_ring *ring;
2556 unsigned int idx;
2557
2558 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2559 return;
2560
2561 handle->ae_algo->ops->update_stats(handle);
2562
2563 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2564 for (idx = 0; idx < queue_num; idx++) {
2565 /* fetch the tx stats */
2566 ring = &priv->ring[idx];
2567 hns3_fetch_stats(&ring_total_stats, ring, true);
2568
2569 /* fetch the rx stats */
2570 ring = &priv->ring[idx + queue_num];
2571 hns3_fetch_stats(&ring_total_stats, ring, false);
2572 }
2573
2574 stats->tx_bytes = ring_total_stats.tx_bytes;
2575 stats->tx_packets = ring_total_stats.tx_packets;
2576 stats->rx_bytes = ring_total_stats.rx_bytes;
2577 stats->rx_packets = ring_total_stats.rx_packets;
2578
2579 stats->rx_errors = ring_total_stats.rx_errors;
2580 stats->multicast = ring_total_stats.multicast;
2581 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2582 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2583 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2584
2585 stats->tx_errors = ring_total_stats.tx_errors;
2586 stats->rx_dropped = ring_total_stats.rx_dropped;
2587 stats->tx_dropped = ring_total_stats.tx_dropped;
2588 stats->collisions = netdev->stats.collisions;
2589 stats->rx_over_errors = netdev->stats.rx_over_errors;
2590 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2591 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2592 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2593 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2594 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2595 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2596 stats->tx_window_errors = netdev->stats.tx_window_errors;
2597 stats->rx_compressed = netdev->stats.rx_compressed;
2598 stats->tx_compressed = netdev->stats.tx_compressed;
2599 }
2600
hns3_setup_tc(struct net_device * netdev,void * type_data)2601 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2602 {
2603 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2604 struct hnae3_knic_private_info *kinfo;
2605 u8 tc = mqprio_qopt->qopt.num_tc;
2606 u16 mode = mqprio_qopt->mode;
2607 u8 hw = mqprio_qopt->qopt.hw;
2608 struct hnae3_handle *h;
2609
2610 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2611 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2612 return -EOPNOTSUPP;
2613
2614 if (tc > HNAE3_MAX_TC)
2615 return -EINVAL;
2616
2617 if (!netdev)
2618 return -EINVAL;
2619
2620 h = hns3_get_handle(netdev);
2621 kinfo = &h->kinfo;
2622
2623 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2624
2625 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2626 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2627 }
2628
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2629 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2630 struct flow_cls_offload *flow)
2631 {
2632 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2633 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2634
2635 switch (flow->command) {
2636 case FLOW_CLS_REPLACE:
2637 if (h->ae_algo->ops->add_cls_flower)
2638 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2639 break;
2640 case FLOW_CLS_DESTROY:
2641 if (h->ae_algo->ops->del_cls_flower)
2642 return h->ae_algo->ops->del_cls_flower(h, flow);
2643 break;
2644 default:
2645 break;
2646 }
2647
2648 return -EOPNOTSUPP;
2649 }
2650
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2651 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2652 void *cb_priv)
2653 {
2654 struct hns3_nic_priv *priv = cb_priv;
2655
2656 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2657 return -EOPNOTSUPP;
2658
2659 switch (type) {
2660 case TC_SETUP_CLSFLOWER:
2661 return hns3_setup_tc_cls_flower(priv, type_data);
2662 default:
2663 return -EOPNOTSUPP;
2664 }
2665 }
2666
2667 static LIST_HEAD(hns3_block_cb_list);
2668
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2669 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2670 void *type_data)
2671 {
2672 struct hns3_nic_priv *priv = netdev_priv(dev);
2673 int ret;
2674
2675 switch (type) {
2676 case TC_SETUP_QDISC_MQPRIO:
2677 ret = hns3_setup_tc(dev, type_data);
2678 break;
2679 case TC_SETUP_BLOCK:
2680 ret = flow_block_cb_setup_simple(type_data,
2681 &hns3_block_cb_list,
2682 hns3_setup_tc_block_cb,
2683 priv, priv, true);
2684 break;
2685 default:
2686 return -EOPNOTSUPP;
2687 }
2688
2689 return ret;
2690 }
2691
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2692 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2693 __be16 proto, u16 vid)
2694 {
2695 struct hnae3_handle *h = hns3_get_handle(netdev);
2696 int ret = -EIO;
2697
2698 if (h->ae_algo->ops->set_vlan_filter)
2699 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2700
2701 return ret;
2702 }
2703
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2704 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2705 __be16 proto, u16 vid)
2706 {
2707 struct hnae3_handle *h = hns3_get_handle(netdev);
2708 int ret = -EIO;
2709
2710 if (h->ae_algo->ops->set_vlan_filter)
2711 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2712
2713 return ret;
2714 }
2715
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2716 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2717 u8 qos, __be16 vlan_proto)
2718 {
2719 struct hnae3_handle *h = hns3_get_handle(netdev);
2720 int ret = -EIO;
2721
2722 netif_dbg(h, drv, netdev,
2723 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2724 vf, vlan, qos, ntohs(vlan_proto));
2725
2726 if (h->ae_algo->ops->set_vf_vlan_filter)
2727 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2728 qos, vlan_proto);
2729
2730 return ret;
2731 }
2732
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2733 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2734 {
2735 struct hnae3_handle *handle = hns3_get_handle(netdev);
2736
2737 if (hns3_nic_resetting(netdev))
2738 return -EBUSY;
2739
2740 if (!handle->ae_algo->ops->set_vf_spoofchk)
2741 return -EOPNOTSUPP;
2742
2743 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2744 }
2745
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2746 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2747 {
2748 struct hnae3_handle *handle = hns3_get_handle(netdev);
2749
2750 if (!handle->ae_algo->ops->set_vf_trust)
2751 return -EOPNOTSUPP;
2752
2753 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2754 }
2755
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2756 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2757 {
2758 struct hnae3_handle *h = hns3_get_handle(netdev);
2759 int ret;
2760
2761 if (hns3_nic_resetting(netdev))
2762 return -EBUSY;
2763
2764 if (!h->ae_algo->ops->set_mtu)
2765 return -EOPNOTSUPP;
2766
2767 netif_dbg(h, drv, netdev,
2768 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2769
2770 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2771 if (ret)
2772 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2773 ret);
2774 else
2775 netdev->mtu = new_mtu;
2776
2777 return ret;
2778 }
2779
hns3_get_timeout_queue(struct net_device * ndev)2780 static int hns3_get_timeout_queue(struct net_device *ndev)
2781 {
2782 int i;
2783
2784 /* Find the stopped queue the same way the stack does */
2785 for (i = 0; i < ndev->num_tx_queues; i++) {
2786 struct netdev_queue *q;
2787 unsigned long trans_start;
2788
2789 q = netdev_get_tx_queue(ndev, i);
2790 trans_start = READ_ONCE(q->trans_start);
2791 if (netif_xmit_stopped(q) &&
2792 time_after(jiffies,
2793 (trans_start + ndev->watchdog_timeo))) {
2794 #ifdef CONFIG_BQL
2795 struct dql *dql = &q->dql;
2796
2797 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2798 dql->last_obj_cnt, dql->num_queued,
2799 dql->adj_limit, dql->num_completed);
2800 #endif
2801 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2802 q->state,
2803 jiffies_to_msecs(jiffies - trans_start));
2804 break;
2805 }
2806 }
2807
2808 return i;
2809 }
2810
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2811 static void hns3_dump_queue_stats(struct net_device *ndev,
2812 struct hns3_enet_ring *tx_ring,
2813 int timeout_queue)
2814 {
2815 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2816 struct hns3_nic_priv *priv = netdev_priv(ndev);
2817
2818 netdev_info(ndev,
2819 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2820 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2821 tx_ring->next_to_clean, napi->state);
2822
2823 netdev_info(ndev,
2824 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2825 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2826 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2827
2828 netdev_info(ndev,
2829 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2830 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2831 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2832
2833 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2834 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2835 }
2836
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2837 static void hns3_dump_queue_reg(struct net_device *ndev,
2838 struct hns3_enet_ring *tx_ring)
2839 {
2840 netdev_info(ndev,
2841 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2842 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2843 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2844 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2845 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2846 readl(tx_ring->tqp_vector->mask_addr));
2847 netdev_info(ndev,
2848 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2849 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2850 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2851 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2852 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2853 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2854 hns3_tqp_read_reg(tx_ring,
2855 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2856 }
2857
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2858 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2859 {
2860 struct hns3_nic_priv *priv = netdev_priv(ndev);
2861 struct hnae3_handle *h = hns3_get_handle(ndev);
2862 struct hns3_enet_ring *tx_ring;
2863 int timeout_queue;
2864
2865 timeout_queue = hns3_get_timeout_queue(ndev);
2866 if (timeout_queue >= ndev->num_tx_queues) {
2867 netdev_info(ndev,
2868 "no netdev TX timeout queue found, timeout count: %llu\n",
2869 priv->tx_timeout_count);
2870 return false;
2871 }
2872
2873 priv->tx_timeout_count++;
2874
2875 tx_ring = &priv->ring[timeout_queue];
2876 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2877
2878 /* When mac received many pause frames continuous, it's unable to send
2879 * packets, which may cause tx timeout
2880 */
2881 if (h->ae_algo->ops->get_mac_stats) {
2882 struct hns3_mac_stats mac_stats;
2883
2884 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2885 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2886 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2887 }
2888
2889 hns3_dump_queue_reg(ndev, tx_ring);
2890
2891 return true;
2892 }
2893
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2894 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2895 {
2896 struct hns3_nic_priv *priv = netdev_priv(ndev);
2897 struct hnae3_handle *h = priv->ae_handle;
2898
2899 if (!hns3_get_tx_timeo_queue_info(ndev))
2900 return;
2901
2902 /* request the reset, and let the hclge to determine
2903 * which reset level should be done
2904 */
2905 if (h->ae_algo->ops->reset_event)
2906 h->ae_algo->ops->reset_event(h->pdev, h);
2907 }
2908
2909 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2910 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2911 u16 rxq_index, u32 flow_id)
2912 {
2913 struct hnae3_handle *h = hns3_get_handle(dev);
2914 struct flow_keys fkeys;
2915
2916 if (!h->ae_algo->ops->add_arfs_entry)
2917 return -EOPNOTSUPP;
2918
2919 if (skb->encapsulation)
2920 return -EPROTONOSUPPORT;
2921
2922 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2923 return -EPROTONOSUPPORT;
2924
2925 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2926 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2927 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2928 fkeys.basic.ip_proto != IPPROTO_UDP))
2929 return -EPROTONOSUPPORT;
2930
2931 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2932 }
2933 #endif
2934
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2935 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2936 struct ifla_vf_info *ivf)
2937 {
2938 struct hnae3_handle *h = hns3_get_handle(ndev);
2939
2940 if (!h->ae_algo->ops->get_vf_config)
2941 return -EOPNOTSUPP;
2942
2943 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2944 }
2945
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2946 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2947 int link_state)
2948 {
2949 struct hnae3_handle *h = hns3_get_handle(ndev);
2950
2951 if (!h->ae_algo->ops->set_vf_link_state)
2952 return -EOPNOTSUPP;
2953
2954 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2955 }
2956
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2957 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2958 int min_tx_rate, int max_tx_rate)
2959 {
2960 struct hnae3_handle *h = hns3_get_handle(ndev);
2961
2962 if (!h->ae_algo->ops->set_vf_rate)
2963 return -EOPNOTSUPP;
2964
2965 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2966 false);
2967 }
2968
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2969 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2970 {
2971 struct hnae3_handle *h = hns3_get_handle(netdev);
2972 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2973
2974 if (!h->ae_algo->ops->set_vf_mac)
2975 return -EOPNOTSUPP;
2976
2977 if (is_multicast_ether_addr(mac)) {
2978 hnae3_format_mac_addr(format_mac_addr, mac);
2979 netdev_err(netdev,
2980 "Invalid MAC:%s specified. Could not set MAC\n",
2981 format_mac_addr);
2982 return -EINVAL;
2983 }
2984
2985 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2986 }
2987
2988 #define HNS3_INVALID_DSCP 0xff
2989 #define HNS3_DSCP_SHIFT 2
2990
hns3_get_skb_dscp(struct sk_buff * skb)2991 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
2992 {
2993 __be16 protocol = skb->protocol;
2994 u8 dscp = HNS3_INVALID_DSCP;
2995
2996 if (protocol == htons(ETH_P_8021Q))
2997 protocol = vlan_get_protocol(skb);
2998
2999 if (protocol == htons(ETH_P_IP))
3000 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
3001 else if (protocol == htons(ETH_P_IPV6))
3002 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
3003
3004 return dscp;
3005 }
3006
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)3007 static u16 hns3_nic_select_queue(struct net_device *netdev,
3008 struct sk_buff *skb,
3009 struct net_device *sb_dev)
3010 {
3011 struct hnae3_handle *h = hns3_get_handle(netdev);
3012 u8 dscp;
3013
3014 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3015 !h->ae_algo->ops->get_dscp_prio)
3016 goto out;
3017
3018 dscp = hns3_get_skb_dscp(skb);
3019 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3020 goto out;
3021
3022 skb->priority = h->kinfo.dscp_prio[dscp];
3023 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3024 skb->priority = 0;
3025
3026 out:
3027 return netdev_pick_tx(netdev, skb, sb_dev);
3028 }
3029
3030 static const struct net_device_ops hns3_nic_netdev_ops = {
3031 .ndo_open = hns3_nic_net_open,
3032 .ndo_stop = hns3_nic_net_stop,
3033 .ndo_start_xmit = hns3_nic_net_xmit,
3034 .ndo_tx_timeout = hns3_nic_net_timeout,
3035 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3036 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3037 .ndo_change_mtu = hns3_nic_change_mtu,
3038 .ndo_set_features = hns3_nic_set_features,
3039 .ndo_features_check = hns3_features_check,
3040 .ndo_get_stats64 = hns3_nic_get_stats64,
3041 .ndo_setup_tc = hns3_nic_setup_tc,
3042 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3043 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3044 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3045 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3046 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3047 .ndo_set_vf_trust = hns3_set_vf_trust,
3048 #ifdef CONFIG_RFS_ACCEL
3049 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3050 #endif
3051 .ndo_get_vf_config = hns3_nic_get_vf_config,
3052 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3053 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3054 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3055 .ndo_select_queue = hns3_nic_select_queue,
3056 };
3057
hns3_is_phys_func(struct pci_dev * pdev)3058 bool hns3_is_phys_func(struct pci_dev *pdev)
3059 {
3060 u32 dev_id = pdev->device;
3061
3062 switch (dev_id) {
3063 case HNAE3_DEV_ID_GE:
3064 case HNAE3_DEV_ID_25GE:
3065 case HNAE3_DEV_ID_25GE_RDMA:
3066 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3067 case HNAE3_DEV_ID_50GE_RDMA:
3068 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3069 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3070 case HNAE3_DEV_ID_200G_RDMA:
3071 return true;
3072 case HNAE3_DEV_ID_VF:
3073 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3074 return false;
3075 default:
3076 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3077 dev_id);
3078 }
3079
3080 return false;
3081 }
3082
hns3_disable_sriov(struct pci_dev * pdev)3083 static void hns3_disable_sriov(struct pci_dev *pdev)
3084 {
3085 /* If our VFs are assigned we cannot shut down SR-IOV
3086 * without causing issues, so just leave the hardware
3087 * available but disabled
3088 */
3089 if (pci_vfs_assigned(pdev)) {
3090 dev_warn(&pdev->dev,
3091 "disabling driver while VFs are assigned\n");
3092 return;
3093 }
3094
3095 pci_disable_sriov(pdev);
3096 }
3097
3098 /* hns3_probe - Device initialization routine
3099 * @pdev: PCI device information struct
3100 * @ent: entry in hns3_pci_tbl
3101 *
3102 * hns3_probe initializes a PF identified by a pci_dev structure.
3103 * The OS initialization, configuring of the PF private structure,
3104 * and a hardware reset occur.
3105 *
3106 * Returns 0 on success, negative on failure
3107 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3108 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3109 {
3110 struct hnae3_ae_dev *ae_dev;
3111 int ret;
3112
3113 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3114 if (!ae_dev)
3115 return -ENOMEM;
3116
3117 ae_dev->pdev = pdev;
3118 ae_dev->flag = ent->driver_data;
3119 pci_set_drvdata(pdev, ae_dev);
3120
3121 ret = hnae3_register_ae_dev(ae_dev);
3122 if (ret)
3123 pci_set_drvdata(pdev, NULL);
3124
3125 return ret;
3126 }
3127
3128 /**
3129 * hns3_clean_vf_config
3130 * @pdev: pointer to a pci_dev structure
3131 * @num_vfs: number of VFs allocated
3132 *
3133 * Clean residual vf config after disable sriov
3134 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3135 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3136 {
3137 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3138
3139 if (ae_dev->ops->clean_vf_config)
3140 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3141 }
3142
3143 /* hns3_remove - Device removal routine
3144 * @pdev: PCI device information struct
3145 */
hns3_remove(struct pci_dev * pdev)3146 static void hns3_remove(struct pci_dev *pdev)
3147 {
3148 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3149
3150 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3151 hns3_disable_sriov(pdev);
3152
3153 hnae3_unregister_ae_dev(ae_dev);
3154 pci_set_drvdata(pdev, NULL);
3155 }
3156
3157 /**
3158 * hns3_pci_sriov_configure
3159 * @pdev: pointer to a pci_dev structure
3160 * @num_vfs: number of VFs to allocate
3161 *
3162 * Enable or change the number of VFs. Called when the user updates the number
3163 * of VFs in sysfs.
3164 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3165 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3166 {
3167 int ret;
3168
3169 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3170 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3171 return -EINVAL;
3172 }
3173
3174 if (num_vfs) {
3175 ret = pci_enable_sriov(pdev, num_vfs);
3176 if (ret)
3177 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3178 else
3179 return num_vfs;
3180 } else if (!pci_vfs_assigned(pdev)) {
3181 int num_vfs_pre = pci_num_vf(pdev);
3182
3183 pci_disable_sriov(pdev);
3184 hns3_clean_vf_config(pdev, num_vfs_pre);
3185 } else {
3186 dev_warn(&pdev->dev,
3187 "Unable to free VFs because some are assigned to VMs.\n");
3188 }
3189
3190 return 0;
3191 }
3192
hns3_shutdown(struct pci_dev * pdev)3193 static void hns3_shutdown(struct pci_dev *pdev)
3194 {
3195 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3196
3197 hnae3_unregister_ae_dev(ae_dev);
3198 pci_set_drvdata(pdev, NULL);
3199
3200 if (system_state == SYSTEM_POWER_OFF)
3201 pci_set_power_state(pdev, PCI_D3hot);
3202 }
3203
hns3_suspend(struct device * dev)3204 static int __maybe_unused hns3_suspend(struct device *dev)
3205 {
3206 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3207
3208 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3209 dev_info(dev, "Begin to suspend.\n");
3210 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3211 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3212 }
3213
3214 return 0;
3215 }
3216
hns3_resume(struct device * dev)3217 static int __maybe_unused hns3_resume(struct device *dev)
3218 {
3219 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3220
3221 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3222 dev_info(dev, "Begin to resume.\n");
3223 if (ae_dev->ops && ae_dev->ops->reset_done)
3224 ae_dev->ops->reset_done(ae_dev);
3225 }
3226
3227 return 0;
3228 }
3229
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3230 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3231 pci_channel_state_t state)
3232 {
3233 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3234 pci_ers_result_t ret;
3235
3236 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3237
3238 if (state == pci_channel_io_perm_failure)
3239 return PCI_ERS_RESULT_DISCONNECT;
3240
3241 if (!ae_dev || !ae_dev->ops) {
3242 dev_err(&pdev->dev,
3243 "Can't recover - error happened before device initialized\n");
3244 return PCI_ERS_RESULT_NONE;
3245 }
3246
3247 if (ae_dev->ops->handle_hw_ras_error)
3248 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3249 else
3250 return PCI_ERS_RESULT_NONE;
3251
3252 return ret;
3253 }
3254
hns3_slot_reset(struct pci_dev * pdev)3255 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3256 {
3257 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3258 const struct hnae3_ae_ops *ops;
3259 enum hnae3_reset_type reset_type;
3260 struct device *dev = &pdev->dev;
3261
3262 if (!ae_dev || !ae_dev->ops)
3263 return PCI_ERS_RESULT_NONE;
3264
3265 ops = ae_dev->ops;
3266 /* request the reset */
3267 if (ops->reset_event && ops->get_reset_level &&
3268 ops->set_default_reset_request) {
3269 if (ae_dev->hw_err_reset_req) {
3270 reset_type = ops->get_reset_level(ae_dev,
3271 &ae_dev->hw_err_reset_req);
3272 ops->set_default_reset_request(ae_dev, reset_type);
3273 dev_info(dev, "requesting reset due to PCI error\n");
3274 ops->reset_event(pdev, NULL);
3275 }
3276
3277 return PCI_ERS_RESULT_RECOVERED;
3278 }
3279
3280 return PCI_ERS_RESULT_DISCONNECT;
3281 }
3282
hns3_reset_prepare(struct pci_dev * pdev)3283 static void hns3_reset_prepare(struct pci_dev *pdev)
3284 {
3285 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3286
3287 dev_info(&pdev->dev, "FLR prepare\n");
3288 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3289 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3290 }
3291
hns3_reset_done(struct pci_dev * pdev)3292 static void hns3_reset_done(struct pci_dev *pdev)
3293 {
3294 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3295
3296 dev_info(&pdev->dev, "FLR done\n");
3297 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3298 ae_dev->ops->reset_done(ae_dev);
3299 }
3300
3301 static const struct pci_error_handlers hns3_err_handler = {
3302 .error_detected = hns3_error_detected,
3303 .slot_reset = hns3_slot_reset,
3304 .reset_prepare = hns3_reset_prepare,
3305 .reset_done = hns3_reset_done,
3306 };
3307
3308 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3309
3310 static struct pci_driver hns3_driver = {
3311 .name = hns3_driver_name,
3312 .id_table = hns3_pci_tbl,
3313 .probe = hns3_probe,
3314 .remove = hns3_remove,
3315 .shutdown = hns3_shutdown,
3316 .driver.pm = &hns3_pm_ops,
3317 .sriov_configure = hns3_pci_sriov_configure,
3318 .err_handler = &hns3_err_handler,
3319 };
3320
3321 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3322 static void hns3_set_default_feature(struct net_device *netdev)
3323 {
3324 struct hnae3_handle *h = hns3_get_handle(netdev);
3325 struct pci_dev *pdev = h->pdev;
3326 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3327
3328 netdev->priv_flags |= IFF_UNICAST_FLT;
3329
3330 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3331 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3332 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3333 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3334 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3335 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3336
3337 if (hnae3_ae_dev_gro_supported(ae_dev))
3338 netdev->features |= NETIF_F_GRO_HW;
3339
3340 if (hnae3_ae_dev_fd_supported(ae_dev))
3341 netdev->features |= NETIF_F_NTUPLE;
3342
3343 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3344 netdev->features |= NETIF_F_GSO_UDP_L4;
3345
3346 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3347 netdev->features |= NETIF_F_HW_CSUM;
3348 else
3349 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3350
3351 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3352 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3353
3354 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3355 netdev->features |= NETIF_F_HW_TC;
3356
3357 netdev->hw_features |= netdev->features;
3358 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3359 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3360
3361 netdev->vlan_features |= netdev->features &
3362 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3363 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3364 NETIF_F_HW_TC);
3365
3366 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3367
3368 /* The device_version V3 hardware can't offload the checksum for IP in
3369 * GRE packets, but can do it for NvGRE. So default to disable the
3370 * checksum and GSO offload for GRE.
3371 */
3372 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3373 netdev->features &= ~NETIF_F_GSO_GRE;
3374 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3375 }
3376 }
3377
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3378 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3379 struct hns3_desc_cb *cb)
3380 {
3381 unsigned int order = hns3_page_order(ring);
3382 struct page *p;
3383
3384 if (ring->page_pool) {
3385 p = page_pool_dev_alloc_frag(ring->page_pool,
3386 &cb->page_offset,
3387 hns3_buf_size(ring));
3388 if (unlikely(!p))
3389 return -ENOMEM;
3390
3391 cb->priv = p;
3392 cb->buf = page_address(p);
3393 cb->dma = page_pool_get_dma_addr(p);
3394 cb->type = DESC_TYPE_PP_FRAG;
3395 cb->reuse_flag = 0;
3396 return 0;
3397 }
3398
3399 p = dev_alloc_pages(order);
3400 if (!p)
3401 return -ENOMEM;
3402
3403 cb->priv = p;
3404 cb->page_offset = 0;
3405 cb->reuse_flag = 0;
3406 cb->buf = page_address(p);
3407 cb->length = hns3_page_size(ring);
3408 cb->type = DESC_TYPE_PAGE;
3409 page_ref_add(p, USHRT_MAX - 1);
3410 cb->pagecnt_bias = USHRT_MAX;
3411
3412 return 0;
3413 }
3414
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3415 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3416 struct hns3_desc_cb *cb, int budget)
3417 {
3418 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3419 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3420 napi_consume_skb(cb->priv, budget);
3421 else if (!HNAE3_IS_TX_RING(ring)) {
3422 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3423 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3424 else if (cb->type & DESC_TYPE_PP_FRAG)
3425 page_pool_put_full_page(ring->page_pool, cb->priv,
3426 false);
3427 }
3428 memset(cb, 0, sizeof(*cb));
3429 }
3430
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3431 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3432 {
3433 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3434 cb->length, ring_to_dma_dir(ring));
3435
3436 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3437 return -EIO;
3438
3439 return 0;
3440 }
3441
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3442 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3443 struct hns3_desc_cb *cb)
3444 {
3445 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3446 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3447 ring_to_dma_dir(ring));
3448 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3449 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3450 ring_to_dma_dir(ring));
3451 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3452 DESC_TYPE_SGL_SKB))
3453 hns3_tx_spare_reclaim_cb(ring, cb);
3454 }
3455
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3456 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3457 {
3458 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3459 ring->desc[i].addr = 0;
3460 ring->desc_cb[i].refill = 0;
3461 }
3462
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3463 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3464 int budget)
3465 {
3466 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3467
3468 if (!ring->desc_cb[i].dma)
3469 return;
3470
3471 hns3_buffer_detach(ring, i);
3472 hns3_free_buffer(ring, cb, budget);
3473 }
3474
hns3_free_buffers(struct hns3_enet_ring * ring)3475 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3476 {
3477 int i;
3478
3479 for (i = 0; i < ring->desc_num; i++)
3480 hns3_free_buffer_detach(ring, i, 0);
3481 }
3482
3483 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3484 static void hns3_free_desc(struct hns3_enet_ring *ring)
3485 {
3486 int size = ring->desc_num * sizeof(ring->desc[0]);
3487
3488 hns3_free_buffers(ring);
3489
3490 if (ring->desc) {
3491 dma_free_coherent(ring_to_dev(ring), size,
3492 ring->desc, ring->desc_dma_addr);
3493 ring->desc = NULL;
3494 }
3495 }
3496
hns3_alloc_desc(struct hns3_enet_ring * ring)3497 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3498 {
3499 int size = ring->desc_num * sizeof(ring->desc[0]);
3500
3501 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3502 &ring->desc_dma_addr, GFP_KERNEL);
3503 if (!ring->desc)
3504 return -ENOMEM;
3505
3506 return 0;
3507 }
3508
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3509 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3510 struct hns3_desc_cb *cb)
3511 {
3512 int ret;
3513
3514 ret = hns3_alloc_buffer(ring, cb);
3515 if (ret || ring->page_pool)
3516 goto out;
3517
3518 ret = hns3_map_buffer(ring, cb);
3519 if (ret)
3520 goto out_with_buf;
3521
3522 return 0;
3523
3524 out_with_buf:
3525 hns3_free_buffer(ring, cb, 0);
3526 out:
3527 return ret;
3528 }
3529
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3530 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3531 {
3532 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3533
3534 if (ret)
3535 return ret;
3536
3537 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3538 ring->desc_cb[i].page_offset);
3539 ring->desc_cb[i].refill = 1;
3540
3541 return 0;
3542 }
3543
3544 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3545 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3546 {
3547 int i, j, ret;
3548
3549 for (i = 0; i < ring->desc_num; i++) {
3550 ret = hns3_alloc_and_attach_buffer(ring, i);
3551 if (ret)
3552 goto out_buffer_fail;
3553
3554 if (!(i % HNS3_RESCHED_BD_NUM))
3555 cond_resched();
3556 }
3557
3558 return 0;
3559
3560 out_buffer_fail:
3561 for (j = i - 1; j >= 0; j--)
3562 hns3_free_buffer_detach(ring, j, 0);
3563 return ret;
3564 }
3565
3566 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3567 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3568 struct hns3_desc_cb *res_cb)
3569 {
3570 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3571 ring->desc_cb[i] = *res_cb;
3572 ring->desc_cb[i].refill = 1;
3573 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3574 ring->desc_cb[i].page_offset);
3575 ring->desc[i].rx.bd_base_info = 0;
3576 }
3577
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3578 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3579 {
3580 ring->desc_cb[i].reuse_flag = 0;
3581 ring->desc_cb[i].refill = 1;
3582 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3583 ring->desc_cb[i].page_offset);
3584 ring->desc[i].rx.bd_base_info = 0;
3585
3586 dma_sync_single_for_device(ring_to_dev(ring),
3587 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3588 hns3_buf_size(ring),
3589 DMA_FROM_DEVICE);
3590 }
3591
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3592 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3593 int *bytes, int *pkts, int budget)
3594 {
3595 /* This smp_load_acquire() pairs with smp_store_release() in
3596 * hns3_tx_doorbell().
3597 */
3598 int ltu = smp_load_acquire(&ring->last_to_use);
3599 int ntc = ring->next_to_clean;
3600 struct hns3_desc_cb *desc_cb;
3601 bool reclaimed = false;
3602 struct hns3_desc *desc;
3603
3604 while (ltu != ntc) {
3605 desc = &ring->desc[ntc];
3606
3607 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3608 BIT(HNS3_TXD_VLD_B))
3609 break;
3610
3611 desc_cb = &ring->desc_cb[ntc];
3612
3613 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3614 DESC_TYPE_BOUNCE_HEAD |
3615 DESC_TYPE_SGL_SKB)) {
3616 (*pkts)++;
3617 (*bytes) += desc_cb->send_bytes;
3618 }
3619
3620 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3621 hns3_free_buffer_detach(ring, ntc, budget);
3622
3623 if (++ntc == ring->desc_num)
3624 ntc = 0;
3625
3626 /* Issue prefetch for next Tx descriptor */
3627 prefetch(&ring->desc_cb[ntc]);
3628 reclaimed = true;
3629 }
3630
3631 if (unlikely(!reclaimed))
3632 return false;
3633
3634 /* This smp_store_release() pairs with smp_load_acquire() in
3635 * ring_space called by hns3_nic_net_xmit.
3636 */
3637 smp_store_release(&ring->next_to_clean, ntc);
3638
3639 hns3_tx_spare_update(ring);
3640
3641 return true;
3642 }
3643
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3644 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3645 {
3646 struct net_device *netdev = ring_to_netdev(ring);
3647 struct hns3_nic_priv *priv = netdev_priv(netdev);
3648 struct netdev_queue *dev_queue;
3649 int bytes, pkts;
3650
3651 bytes = 0;
3652 pkts = 0;
3653
3654 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3655 return;
3656
3657 ring->tqp_vector->tx_group.total_bytes += bytes;
3658 ring->tqp_vector->tx_group.total_packets += pkts;
3659
3660 u64_stats_update_begin(&ring->syncp);
3661 ring->stats.tx_bytes += bytes;
3662 ring->stats.tx_pkts += pkts;
3663 u64_stats_update_end(&ring->syncp);
3664
3665 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3666 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3667
3668 if (unlikely(netif_carrier_ok(netdev) &&
3669 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3670 /* Make sure that anybody stopping the queue after this
3671 * sees the new next_to_clean.
3672 */
3673 smp_mb();
3674 if (netif_tx_queue_stopped(dev_queue) &&
3675 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3676 netif_tx_wake_queue(dev_queue);
3677 ring->stats.restart_queue++;
3678 }
3679 }
3680 }
3681
hns3_desc_unused(struct hns3_enet_ring * ring)3682 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3683 {
3684 int ntc = ring->next_to_clean;
3685 int ntu = ring->next_to_use;
3686
3687 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3688 return ring->desc_num;
3689
3690 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3691 }
3692
3693 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3694 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3695 int cleand_count)
3696 {
3697 struct hns3_desc_cb *desc_cb;
3698 struct hns3_desc_cb res_cbs;
3699 int i, ret;
3700
3701 for (i = 0; i < cleand_count; i++) {
3702 desc_cb = &ring->desc_cb[ring->next_to_use];
3703 if (desc_cb->reuse_flag) {
3704 hns3_ring_stats_update(ring, reuse_pg_cnt);
3705
3706 hns3_reuse_buffer(ring, ring->next_to_use);
3707 } else {
3708 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3709 if (ret) {
3710 hns3_ring_stats_update(ring, sw_err_cnt);
3711
3712 hns3_rl_err(ring_to_netdev(ring),
3713 "alloc rx buffer failed: %d\n",
3714 ret);
3715
3716 writel(i, ring->tqp->io_base +
3717 HNS3_RING_RX_RING_HEAD_REG);
3718 return true;
3719 }
3720 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3721
3722 hns3_ring_stats_update(ring, non_reuse_pg);
3723 }
3724
3725 ring_ptr_move_fw(ring, next_to_use);
3726 }
3727
3728 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3729 return false;
3730 }
3731
hns3_can_reuse_page(struct hns3_desc_cb * cb)3732 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3733 {
3734 return page_count(cb->priv) == cb->pagecnt_bias;
3735 }
3736
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3737 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3738 struct hns3_enet_ring *ring,
3739 int pull_len,
3740 struct hns3_desc_cb *desc_cb)
3741 {
3742 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3743 u32 frag_offset = desc_cb->page_offset + pull_len;
3744 int size = le16_to_cpu(desc->rx.size);
3745 u32 frag_size = size - pull_len;
3746 void *frag = napi_alloc_frag(frag_size);
3747
3748 if (unlikely(!frag)) {
3749 hns3_ring_stats_update(ring, frag_alloc_err);
3750
3751 hns3_rl_err(ring_to_netdev(ring),
3752 "failed to allocate rx frag\n");
3753 return -ENOMEM;
3754 }
3755
3756 desc_cb->reuse_flag = 1;
3757 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3758 skb_add_rx_frag(skb, i, virt_to_page(frag),
3759 offset_in_page(frag), frag_size, frag_size);
3760
3761 hns3_ring_stats_update(ring, frag_alloc);
3762 return 0;
3763 }
3764
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3765 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3766 struct hns3_enet_ring *ring, int pull_len,
3767 struct hns3_desc_cb *desc_cb)
3768 {
3769 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3770 u32 frag_offset = desc_cb->page_offset + pull_len;
3771 int size = le16_to_cpu(desc->rx.size);
3772 u32 truesize = hns3_buf_size(ring);
3773 u32 frag_size = size - pull_len;
3774 int ret = 0;
3775 bool reused;
3776
3777 if (ring->page_pool) {
3778 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3779 frag_size, truesize);
3780 return;
3781 }
3782
3783 /* Avoid re-using remote or pfmem page */
3784 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3785 goto out;
3786
3787 reused = hns3_can_reuse_page(desc_cb);
3788
3789 /* Rx page can be reused when:
3790 * 1. Rx page is only owned by the driver when page_offset
3791 * is zero, which means 0 @ truesize will be used by
3792 * stack after skb_add_rx_frag() is called, and the rest
3793 * of rx page can be reused by driver.
3794 * Or
3795 * 2. Rx page is only owned by the driver when page_offset
3796 * is non-zero, which means page_offset @ truesize will
3797 * be used by stack after skb_add_rx_frag() is called,
3798 * and 0 @ truesize can be reused by driver.
3799 */
3800 if ((!desc_cb->page_offset && reused) ||
3801 ((desc_cb->page_offset + truesize + truesize) <=
3802 hns3_page_size(ring) && desc_cb->page_offset)) {
3803 desc_cb->page_offset += truesize;
3804 desc_cb->reuse_flag = 1;
3805 } else if (desc_cb->page_offset && reused) {
3806 desc_cb->page_offset = 0;
3807 desc_cb->reuse_flag = 1;
3808 } else if (frag_size <= ring->rx_copybreak) {
3809 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3810 if (!ret)
3811 return;
3812 }
3813
3814 out:
3815 desc_cb->pagecnt_bias--;
3816
3817 if (unlikely(!desc_cb->pagecnt_bias)) {
3818 page_ref_add(desc_cb->priv, USHRT_MAX);
3819 desc_cb->pagecnt_bias = USHRT_MAX;
3820 }
3821
3822 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3823 frag_size, truesize);
3824
3825 if (unlikely(!desc_cb->reuse_flag))
3826 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3827 }
3828
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3829 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3830 {
3831 __be16 type = skb->protocol;
3832 struct tcphdr *th;
3833 int depth = 0;
3834
3835 while (eth_type_vlan(type)) {
3836 struct vlan_hdr *vh;
3837
3838 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3839 return -EFAULT;
3840
3841 vh = (struct vlan_hdr *)(skb->data + depth);
3842 type = vh->h_vlan_encapsulated_proto;
3843 depth += VLAN_HLEN;
3844 }
3845
3846 skb_set_network_header(skb, depth);
3847
3848 if (type == htons(ETH_P_IP)) {
3849 const struct iphdr *iph = ip_hdr(skb);
3850
3851 depth += sizeof(struct iphdr);
3852 skb_set_transport_header(skb, depth);
3853 th = tcp_hdr(skb);
3854 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3855 iph->daddr, 0);
3856 } else if (type == htons(ETH_P_IPV6)) {
3857 const struct ipv6hdr *iph = ipv6_hdr(skb);
3858
3859 depth += sizeof(struct ipv6hdr);
3860 skb_set_transport_header(skb, depth);
3861 th = tcp_hdr(skb);
3862 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3863 &iph->daddr, 0);
3864 } else {
3865 hns3_rl_err(skb->dev,
3866 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3867 be16_to_cpu(type), depth);
3868 return -EFAULT;
3869 }
3870
3871 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3872 if (th->cwr)
3873 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3874
3875 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3876 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3877
3878 skb->csum_start = (unsigned char *)th - skb->head;
3879 skb->csum_offset = offsetof(struct tcphdr, check);
3880 skb->ip_summed = CHECKSUM_PARTIAL;
3881
3882 trace_hns3_gro(skb);
3883
3884 return 0;
3885 }
3886
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3887 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3888 struct sk_buff *skb, u32 ptype, u16 csum)
3889 {
3890 if (ptype == HNS3_INVALID_PTYPE ||
3891 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3892 return;
3893
3894 hns3_ring_stats_update(ring, csum_complete);
3895 skb->ip_summed = CHECKSUM_COMPLETE;
3896 skb->csum = csum_unfold((__force __sum16)csum);
3897 }
3898
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3899 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3900 u32 ol_info, u32 ptype)
3901 {
3902 int l3_type, l4_type;
3903 int ol4_type;
3904
3905 if (ptype != HNS3_INVALID_PTYPE) {
3906 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3907 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3908
3909 return;
3910 }
3911
3912 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3913 HNS3_RXD_OL4ID_S);
3914 switch (ol4_type) {
3915 case HNS3_OL4_TYPE_MAC_IN_UDP:
3916 case HNS3_OL4_TYPE_NVGRE:
3917 skb->csum_level = 1;
3918 fallthrough;
3919 case HNS3_OL4_TYPE_NO_TUN:
3920 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3921 HNS3_RXD_L3ID_S);
3922 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3923 HNS3_RXD_L4ID_S);
3924 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3925 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3926 l3_type == HNS3_L3_TYPE_IPV6) &&
3927 (l4_type == HNS3_L4_TYPE_UDP ||
3928 l4_type == HNS3_L4_TYPE_TCP ||
3929 l4_type == HNS3_L4_TYPE_SCTP))
3930 skb->ip_summed = CHECKSUM_UNNECESSARY;
3931 break;
3932 default:
3933 break;
3934 }
3935 }
3936
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3937 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3938 u32 l234info, u32 bd_base_info, u32 ol_info,
3939 u16 csum)
3940 {
3941 struct net_device *netdev = ring_to_netdev(ring);
3942 struct hns3_nic_priv *priv = netdev_priv(netdev);
3943 u32 ptype = HNS3_INVALID_PTYPE;
3944
3945 skb->ip_summed = CHECKSUM_NONE;
3946
3947 skb_checksum_none_assert(skb);
3948
3949 if (!(netdev->features & NETIF_F_RXCSUM))
3950 return;
3951
3952 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3953 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3954 HNS3_RXD_PTYPE_S);
3955
3956 hns3_checksum_complete(ring, skb, ptype, csum);
3957
3958 /* check if hardware has done checksum */
3959 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3960 return;
3961
3962 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3963 BIT(HNS3_RXD_OL3E_B) |
3964 BIT(HNS3_RXD_OL4E_B)))) {
3965 skb->ip_summed = CHECKSUM_NONE;
3966 hns3_ring_stats_update(ring, l3l4_csum_err);
3967
3968 return;
3969 }
3970
3971 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3972 }
3973
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)3974 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3975 {
3976 if (skb_has_frag_list(skb))
3977 napi_gro_flush(&ring->tqp_vector->napi, false);
3978
3979 napi_gro_receive(&ring->tqp_vector->napi, skb);
3980 }
3981
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)3982 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3983 struct hns3_desc *desc, u32 l234info,
3984 u16 *vlan_tag)
3985 {
3986 struct hnae3_handle *handle = ring->tqp->handle;
3987 struct pci_dev *pdev = ring->tqp->handle->pdev;
3988 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3989
3990 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3991 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3992 if (!(*vlan_tag & VLAN_VID_MASK))
3993 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3994
3995 return (*vlan_tag != 0);
3996 }
3997
3998 #define HNS3_STRP_OUTER_VLAN 0x1
3999 #define HNS3_STRP_INNER_VLAN 0x2
4000 #define HNS3_STRP_BOTH 0x3
4001
4002 /* Hardware always insert VLAN tag into RX descriptor when
4003 * remove the tag from packet, driver needs to determine
4004 * reporting which tag to stack.
4005 */
4006 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
4007 HNS3_RXD_STRP_TAGP_S)) {
4008 case HNS3_STRP_OUTER_VLAN:
4009 if (handle->port_base_vlan_state !=
4010 HNAE3_PORT_BASE_VLAN_DISABLE)
4011 return false;
4012
4013 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4014 return true;
4015 case HNS3_STRP_INNER_VLAN:
4016 if (handle->port_base_vlan_state !=
4017 HNAE3_PORT_BASE_VLAN_DISABLE)
4018 return false;
4019
4020 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4021 return true;
4022 case HNS3_STRP_BOTH:
4023 if (handle->port_base_vlan_state ==
4024 HNAE3_PORT_BASE_VLAN_DISABLE)
4025 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4026 else
4027 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4028
4029 return true;
4030 default:
4031 return false;
4032 }
4033 }
4034
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4035 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4036 {
4037 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4038 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4039 ring->desc_cb[ring->next_to_clean].refill = 0;
4040 ring->next_to_clean += 1;
4041
4042 if (unlikely(ring->next_to_clean == ring->desc_num))
4043 ring->next_to_clean = 0;
4044 }
4045
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4046 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4047 unsigned char *va)
4048 {
4049 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4050 struct net_device *netdev = ring_to_netdev(ring);
4051 struct sk_buff *skb;
4052
4053 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4054 skb = ring->skb;
4055 if (unlikely(!skb)) {
4056 hns3_rl_err(netdev, "alloc rx skb fail\n");
4057 hns3_ring_stats_update(ring, sw_err_cnt);
4058
4059 return -ENOMEM;
4060 }
4061
4062 trace_hns3_rx_desc(ring);
4063 prefetchw(skb->data);
4064
4065 ring->pending_buf = 1;
4066 ring->frag_num = 0;
4067 ring->tail_skb = NULL;
4068 if (length <= HNS3_RX_HEAD_SIZE) {
4069 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4070
4071 /* We can reuse buffer as-is, just make sure it is reusable */
4072 if (dev_page_is_reusable(desc_cb->priv))
4073 desc_cb->reuse_flag = 1;
4074 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4075 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4076 false);
4077 else /* This page cannot be reused so discard it */
4078 __page_frag_cache_drain(desc_cb->priv,
4079 desc_cb->pagecnt_bias);
4080
4081 hns3_rx_ring_move_fw(ring);
4082 return 0;
4083 }
4084
4085 if (ring->page_pool)
4086 skb_mark_for_recycle(skb);
4087
4088 hns3_ring_stats_update(ring, seg_pkt_cnt);
4089
4090 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4091 __skb_put(skb, ring->pull_len);
4092 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4093 desc_cb);
4094 hns3_rx_ring_move_fw(ring);
4095
4096 return 0;
4097 }
4098
hns3_add_frag(struct hns3_enet_ring * ring)4099 static int hns3_add_frag(struct hns3_enet_ring *ring)
4100 {
4101 struct sk_buff *skb = ring->skb;
4102 struct sk_buff *head_skb = skb;
4103 struct sk_buff *new_skb;
4104 struct hns3_desc_cb *desc_cb;
4105 struct hns3_desc *desc;
4106 u32 bd_base_info;
4107
4108 do {
4109 desc = &ring->desc[ring->next_to_clean];
4110 desc_cb = &ring->desc_cb[ring->next_to_clean];
4111 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4112 /* make sure HW write desc complete */
4113 dma_rmb();
4114 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4115 return -ENXIO;
4116
4117 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4118 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4119 if (unlikely(!new_skb)) {
4120 hns3_rl_err(ring_to_netdev(ring),
4121 "alloc rx fraglist skb fail\n");
4122 return -ENXIO;
4123 }
4124
4125 if (ring->page_pool)
4126 skb_mark_for_recycle(new_skb);
4127
4128 ring->frag_num = 0;
4129
4130 if (ring->tail_skb) {
4131 ring->tail_skb->next = new_skb;
4132 ring->tail_skb = new_skb;
4133 } else {
4134 skb_shinfo(skb)->frag_list = new_skb;
4135 ring->tail_skb = new_skb;
4136 }
4137 }
4138
4139 if (ring->tail_skb) {
4140 head_skb->truesize += hns3_buf_size(ring);
4141 head_skb->data_len += le16_to_cpu(desc->rx.size);
4142 head_skb->len += le16_to_cpu(desc->rx.size);
4143 skb = ring->tail_skb;
4144 }
4145
4146 dma_sync_single_for_cpu(ring_to_dev(ring),
4147 desc_cb->dma + desc_cb->page_offset,
4148 hns3_buf_size(ring),
4149 DMA_FROM_DEVICE);
4150
4151 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4152 trace_hns3_rx_desc(ring);
4153 hns3_rx_ring_move_fw(ring);
4154 ring->pending_buf++;
4155 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4156
4157 return 0;
4158 }
4159
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4160 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4161 struct sk_buff *skb, u32 l234info,
4162 u32 bd_base_info, u32 ol_info, u16 csum)
4163 {
4164 struct net_device *netdev = ring_to_netdev(ring);
4165 struct hns3_nic_priv *priv = netdev_priv(netdev);
4166 u32 l3_type;
4167
4168 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4169 HNS3_RXD_GRO_SIZE_M,
4170 HNS3_RXD_GRO_SIZE_S);
4171 /* if there is no HW GRO, do not set gro params */
4172 if (!skb_shinfo(skb)->gso_size) {
4173 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4174 csum);
4175 return 0;
4176 }
4177
4178 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4179 HNS3_RXD_GRO_COUNT_M,
4180 HNS3_RXD_GRO_COUNT_S);
4181
4182 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4183 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4184 HNS3_RXD_PTYPE_S);
4185
4186 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4187 } else {
4188 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4189 HNS3_RXD_L3ID_S);
4190 }
4191
4192 if (l3_type == HNS3_L3_TYPE_IPV4)
4193 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4194 else if (l3_type == HNS3_L3_TYPE_IPV6)
4195 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4196 else
4197 return -EFAULT;
4198
4199 return hns3_gro_complete(skb, l234info);
4200 }
4201
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4202 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4203 struct sk_buff *skb, u32 rss_hash,
4204 u32 l234info, u32 ol_info)
4205 {
4206 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4207 struct net_device *netdev = ring_to_netdev(ring);
4208 struct hns3_nic_priv *priv = netdev_priv(netdev);
4209
4210 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4211 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4212 HNS3_RXD_PTYPE_S);
4213
4214 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4215 } else {
4216 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4217 HNS3_RXD_L3ID_S);
4218 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4219 HNS3_RXD_L4ID_S);
4220
4221 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4222 l3_type == HNS3_L3_TYPE_IPV6) {
4223 if (l4_type == HNS3_L4_TYPE_UDP ||
4224 l4_type == HNS3_L4_TYPE_TCP ||
4225 l4_type == HNS3_L4_TYPE_SCTP)
4226 rss_type = PKT_HASH_TYPE_L4;
4227 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4228 l4_type == HNS3_L4_TYPE_ICMP)
4229 rss_type = PKT_HASH_TYPE_L3;
4230 }
4231 }
4232
4233 skb_set_hash(skb, rss_hash, rss_type);
4234 }
4235
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4236 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4237 struct hns3_desc *desc, struct sk_buff *skb,
4238 u32 bd_base_info)
4239 {
4240 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4241 struct hnae3_handle *h = hns3_get_handle(netdev);
4242 u32 nsec = le32_to_cpu(desc->ts_nsec);
4243 u32 sec = le32_to_cpu(desc->ts_sec);
4244
4245 if (h->ae_algo->ops->get_rx_hwts)
4246 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4247 }
4248 }
4249
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4250 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4251 struct hns3_desc *desc, struct sk_buff *skb,
4252 u32 l234info)
4253 {
4254 struct net_device *netdev = ring_to_netdev(ring);
4255
4256 /* Based on hw strategy, the tag offloaded will be stored at
4257 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4258 * in one layer tag case.
4259 */
4260 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4261 u16 vlan_tag;
4262
4263 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4264 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4265 vlan_tag);
4266 }
4267 }
4268
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4269 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4270 {
4271 struct net_device *netdev = ring_to_netdev(ring);
4272 enum hns3_pkt_l2t_type l2_frame_type;
4273 u32 bd_base_info, l234info, ol_info;
4274 struct hns3_desc *desc;
4275 unsigned int len;
4276 int pre_ntc, ret;
4277 u16 csum;
4278
4279 /* bdinfo handled below is only valid on the last BD of the
4280 * current packet, and ring->next_to_clean indicates the first
4281 * descriptor of next packet, so need - 1 below.
4282 */
4283 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4284 (ring->desc_num - 1);
4285 desc = &ring->desc[pre_ntc];
4286 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4287 l234info = le32_to_cpu(desc->rx.l234_info);
4288 ol_info = le32_to_cpu(desc->rx.ol_info);
4289 csum = le16_to_cpu(desc->csum);
4290
4291 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4292
4293 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4294
4295 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4296 BIT(HNS3_RXD_L2E_B))))) {
4297 u64_stats_update_begin(&ring->syncp);
4298 if (l234info & BIT(HNS3_RXD_L2E_B))
4299 ring->stats.l2_err++;
4300 else
4301 ring->stats.err_pkt_len++;
4302 u64_stats_update_end(&ring->syncp);
4303
4304 return -EFAULT;
4305 }
4306
4307 len = skb->len;
4308
4309 /* Do update ip stack process */
4310 skb->protocol = eth_type_trans(skb, netdev);
4311
4312 /* This is needed in order to enable forwarding support */
4313 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4314 bd_base_info, ol_info, csum);
4315 if (unlikely(ret)) {
4316 hns3_ring_stats_update(ring, rx_err_cnt);
4317 return ret;
4318 }
4319
4320 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4321 HNS3_RXD_DMAC_S);
4322
4323 u64_stats_update_begin(&ring->syncp);
4324 ring->stats.rx_pkts++;
4325 ring->stats.rx_bytes += len;
4326
4327 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4328 ring->stats.rx_multicast++;
4329
4330 u64_stats_update_end(&ring->syncp);
4331
4332 ring->tqp_vector->rx_group.total_bytes += len;
4333
4334 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4335 l234info, ol_info);
4336 return 0;
4337 }
4338
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4339 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4340 {
4341 struct sk_buff *skb = ring->skb;
4342 struct hns3_desc_cb *desc_cb;
4343 struct hns3_desc *desc;
4344 unsigned int length;
4345 u32 bd_base_info;
4346 int ret;
4347
4348 desc = &ring->desc[ring->next_to_clean];
4349 desc_cb = &ring->desc_cb[ring->next_to_clean];
4350
4351 prefetch(desc);
4352
4353 if (!skb) {
4354 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4355 /* Check valid BD */
4356 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4357 return -ENXIO;
4358
4359 dma_rmb();
4360 length = le16_to_cpu(desc->rx.size);
4361
4362 ring->va = desc_cb->buf + desc_cb->page_offset;
4363
4364 dma_sync_single_for_cpu(ring_to_dev(ring),
4365 desc_cb->dma + desc_cb->page_offset,
4366 hns3_buf_size(ring),
4367 DMA_FROM_DEVICE);
4368
4369 /* Prefetch first cache line of first page.
4370 * Idea is to cache few bytes of the header of the packet.
4371 * Our L1 Cache line size is 64B so need to prefetch twice to make
4372 * it 128B. But in actual we can have greater size of caches with
4373 * 128B Level 1 cache lines. In such a case, single fetch would
4374 * suffice to cache in the relevant part of the header.
4375 */
4376 net_prefetch(ring->va);
4377
4378 ret = hns3_alloc_skb(ring, length, ring->va);
4379 skb = ring->skb;
4380
4381 if (ret < 0) /* alloc buffer fail */
4382 return ret;
4383 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4384 ret = hns3_add_frag(ring);
4385 if (ret)
4386 return ret;
4387 }
4388 } else {
4389 ret = hns3_add_frag(ring);
4390 if (ret)
4391 return ret;
4392 }
4393
4394 /* As the head data may be changed when GRO enable, copy
4395 * the head data in after other data rx completed
4396 */
4397 if (skb->len > HNS3_RX_HEAD_SIZE)
4398 memcpy(skb->data, ring->va,
4399 ALIGN(ring->pull_len, sizeof(long)));
4400
4401 ret = hns3_handle_bdinfo(ring, skb);
4402 if (unlikely(ret)) {
4403 dev_kfree_skb_any(skb);
4404 return ret;
4405 }
4406
4407 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4408 return 0;
4409 }
4410
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4411 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4412 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4413 {
4414 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4415 int unused_count = hns3_desc_unused(ring);
4416 bool failure = false;
4417 int recv_pkts = 0;
4418 int err;
4419
4420 unused_count -= ring->pending_buf;
4421
4422 while (recv_pkts < budget) {
4423 /* Reuse or realloc buffers */
4424 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4425 failure = failure ||
4426 hns3_nic_alloc_rx_buffers(ring, unused_count);
4427 unused_count = 0;
4428 }
4429
4430 /* Poll one pkt */
4431 err = hns3_handle_rx_bd(ring);
4432 /* Do not get FE for the packet or failed to alloc skb */
4433 if (unlikely(!ring->skb || err == -ENXIO)) {
4434 goto out;
4435 } else if (likely(!err)) {
4436 rx_fn(ring, ring->skb);
4437 recv_pkts++;
4438 }
4439
4440 unused_count += ring->pending_buf;
4441 ring->skb = NULL;
4442 ring->pending_buf = 0;
4443 }
4444
4445 out:
4446 /* sync head pointer before exiting, since hardware will calculate
4447 * FBD number with head pointer
4448 */
4449 if (unused_count > 0)
4450 failure = failure ||
4451 hns3_nic_alloc_rx_buffers(ring, unused_count);
4452
4453 return failure ? budget : recv_pkts;
4454 }
4455
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4456 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4457 {
4458 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4459 struct dim_sample sample = {};
4460
4461 if (!rx_group->coal.adapt_enable)
4462 return;
4463
4464 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4465 rx_group->total_bytes, &sample);
4466 net_dim(&rx_group->dim, sample);
4467 }
4468
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4469 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4470 {
4471 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4472 struct dim_sample sample = {};
4473
4474 if (!tx_group->coal.adapt_enable)
4475 return;
4476
4477 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4478 tx_group->total_bytes, &sample);
4479 net_dim(&tx_group->dim, sample);
4480 }
4481
hns3_nic_common_poll(struct napi_struct * napi,int budget)4482 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4483 {
4484 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4485 struct hns3_enet_ring *ring;
4486 int rx_pkt_total = 0;
4487
4488 struct hns3_enet_tqp_vector *tqp_vector =
4489 container_of(napi, struct hns3_enet_tqp_vector, napi);
4490 bool clean_complete = true;
4491 int rx_budget = budget;
4492
4493 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4494 napi_complete(napi);
4495 return 0;
4496 }
4497
4498 /* Since the actual Tx work is minimal, we can give the Tx a larger
4499 * budget and be more aggressive about cleaning up the Tx descriptors.
4500 */
4501 hns3_for_each_ring(ring, tqp_vector->tx_group)
4502 hns3_clean_tx_ring(ring, budget);
4503
4504 /* make sure rx ring budget not smaller than 1 */
4505 if (tqp_vector->num_tqps > 1)
4506 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4507
4508 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4509 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4510 hns3_rx_skb);
4511 if (rx_cleaned >= rx_budget)
4512 clean_complete = false;
4513
4514 rx_pkt_total += rx_cleaned;
4515 }
4516
4517 tqp_vector->rx_group.total_packets += rx_pkt_total;
4518
4519 if (!clean_complete)
4520 return budget;
4521
4522 if (napi_complete(napi) &&
4523 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4524 hns3_update_rx_int_coalesce(tqp_vector);
4525 hns3_update_tx_int_coalesce(tqp_vector);
4526
4527 hns3_mask_vector_irq(tqp_vector, 1);
4528 }
4529
4530 return rx_pkt_total;
4531 }
4532
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4533 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4534 struct hnae3_ring_chain_node **head,
4535 bool is_tx)
4536 {
4537 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4538 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4539 struct hnae3_ring_chain_node *cur_chain = *head;
4540 struct pci_dev *pdev = tqp_vector->handle->pdev;
4541 struct hnae3_ring_chain_node *chain;
4542 struct hns3_enet_ring *ring;
4543
4544 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4545
4546 if (cur_chain) {
4547 while (cur_chain->next)
4548 cur_chain = cur_chain->next;
4549 }
4550
4551 while (ring) {
4552 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4553 if (!chain)
4554 return -ENOMEM;
4555 if (cur_chain)
4556 cur_chain->next = chain;
4557 else
4558 *head = chain;
4559 chain->tqp_index = ring->tqp->tqp_index;
4560 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4561 bit_value);
4562 hnae3_set_field(chain->int_gl_idx,
4563 HNAE3_RING_GL_IDX_M,
4564 HNAE3_RING_GL_IDX_S, field_value);
4565
4566 cur_chain = chain;
4567
4568 ring = ring->next;
4569 }
4570
4571 return 0;
4572 }
4573
4574 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4575 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4576 {
4577 struct pci_dev *pdev = tqp_vector->handle->pdev;
4578 struct hnae3_ring_chain_node *cur_chain = NULL;
4579 struct hnae3_ring_chain_node *chain;
4580
4581 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4582 goto err_free_chain;
4583
4584 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4585 goto err_free_chain;
4586
4587 return cur_chain;
4588
4589 err_free_chain:
4590 while (cur_chain) {
4591 chain = cur_chain->next;
4592 devm_kfree(&pdev->dev, cur_chain);
4593 cur_chain = chain;
4594 }
4595
4596 return NULL;
4597 }
4598
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4599 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4600 struct hnae3_ring_chain_node *head)
4601 {
4602 struct pci_dev *pdev = tqp_vector->handle->pdev;
4603 struct hnae3_ring_chain_node *chain_tmp, *chain;
4604
4605 chain = head;
4606
4607 while (chain) {
4608 chain_tmp = chain->next;
4609 devm_kfree(&pdev->dev, chain);
4610 chain = chain_tmp;
4611 }
4612 }
4613
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4614 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4615 struct hns3_enet_ring *ring)
4616 {
4617 ring->next = group->ring;
4618 group->ring = ring;
4619
4620 group->count++;
4621 }
4622
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4623 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4624 {
4625 struct pci_dev *pdev = priv->ae_handle->pdev;
4626 struct hns3_enet_tqp_vector *tqp_vector;
4627 int num_vectors = priv->vector_num;
4628 int numa_node;
4629 int vector_i;
4630
4631 numa_node = dev_to_node(&pdev->dev);
4632
4633 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4634 tqp_vector = &priv->tqp_vector[vector_i];
4635 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4636 &tqp_vector->affinity_mask);
4637 }
4638 }
4639
hns3_rx_dim_work(struct work_struct * work)4640 static void hns3_rx_dim_work(struct work_struct *work)
4641 {
4642 struct dim *dim = container_of(work, struct dim, work);
4643 struct hns3_enet_ring_group *group = container_of(dim,
4644 struct hns3_enet_ring_group, dim);
4645 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4646 struct dim_cq_moder cur_moder =
4647 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4648
4649 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4650 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4651
4652 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4653 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4654 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4655 }
4656
4657 dim->state = DIM_START_MEASURE;
4658 }
4659
hns3_tx_dim_work(struct work_struct * work)4660 static void hns3_tx_dim_work(struct work_struct *work)
4661 {
4662 struct dim *dim = container_of(work, struct dim, work);
4663 struct hns3_enet_ring_group *group = container_of(dim,
4664 struct hns3_enet_ring_group, dim);
4665 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4666 struct dim_cq_moder cur_moder =
4667 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4668
4669 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4670 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4671
4672 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4673 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4674 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4675 }
4676
4677 dim->state = DIM_START_MEASURE;
4678 }
4679
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4680 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4681 {
4682 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4683 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4684 }
4685
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4686 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4687 {
4688 struct hnae3_handle *h = priv->ae_handle;
4689 struct hns3_enet_tqp_vector *tqp_vector;
4690 int ret;
4691 int i;
4692
4693 hns3_nic_set_cpumask(priv);
4694
4695 for (i = 0; i < priv->vector_num; i++) {
4696 tqp_vector = &priv->tqp_vector[i];
4697 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4698 tqp_vector->num_tqps = 0;
4699 hns3_nic_init_dim(tqp_vector);
4700 }
4701
4702 for (i = 0; i < h->kinfo.num_tqps; i++) {
4703 u16 vector_i = i % priv->vector_num;
4704 u16 tqp_num = h->kinfo.num_tqps;
4705
4706 tqp_vector = &priv->tqp_vector[vector_i];
4707
4708 hns3_add_ring_to_group(&tqp_vector->tx_group,
4709 &priv->ring[i]);
4710
4711 hns3_add_ring_to_group(&tqp_vector->rx_group,
4712 &priv->ring[i + tqp_num]);
4713
4714 priv->ring[i].tqp_vector = tqp_vector;
4715 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4716 tqp_vector->num_tqps++;
4717 }
4718
4719 for (i = 0; i < priv->vector_num; i++) {
4720 struct hnae3_ring_chain_node *vector_ring_chain;
4721
4722 tqp_vector = &priv->tqp_vector[i];
4723
4724 tqp_vector->rx_group.total_bytes = 0;
4725 tqp_vector->rx_group.total_packets = 0;
4726 tqp_vector->tx_group.total_bytes = 0;
4727 tqp_vector->tx_group.total_packets = 0;
4728 tqp_vector->handle = h;
4729
4730 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4731 if (!vector_ring_chain) {
4732 ret = -ENOMEM;
4733 goto map_ring_fail;
4734 }
4735
4736 ret = h->ae_algo->ops->map_ring_to_vector(h,
4737 tqp_vector->vector_irq, vector_ring_chain);
4738
4739 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4740
4741 if (ret)
4742 goto map_ring_fail;
4743
4744 netif_napi_add(priv->netdev, &tqp_vector->napi,
4745 hns3_nic_common_poll);
4746 }
4747
4748 return 0;
4749
4750 map_ring_fail:
4751 while (i--)
4752 netif_napi_del(&priv->tqp_vector[i].napi);
4753
4754 return ret;
4755 }
4756
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4757 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4758 {
4759 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4760 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4761 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4762
4763 /* initialize the configuration for interrupt coalescing.
4764 * 1. GL (Interrupt Gap Limiter)
4765 * 2. RL (Interrupt Rate Limiter)
4766 * 3. QL (Interrupt Quantity Limiter)
4767 *
4768 * Default: enable interrupt coalescing self-adaptive and GL
4769 */
4770 tx_coal->adapt_enable = 1;
4771 rx_coal->adapt_enable = 1;
4772
4773 tx_coal->int_gl = HNS3_INT_GL_50K;
4774 rx_coal->int_gl = HNS3_INT_GL_50K;
4775
4776 rx_coal->flow_level = HNS3_FLOW_LOW;
4777 tx_coal->flow_level = HNS3_FLOW_LOW;
4778
4779 if (ae_dev->dev_specs.int_ql_max) {
4780 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4781 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4782 }
4783 }
4784
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4785 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4786 {
4787 struct hnae3_handle *h = priv->ae_handle;
4788 struct hns3_enet_tqp_vector *tqp_vector;
4789 struct hnae3_vector_info *vector;
4790 struct pci_dev *pdev = h->pdev;
4791 u16 tqp_num = h->kinfo.num_tqps;
4792 u16 vector_num;
4793 int ret = 0;
4794 u16 i;
4795
4796 /* RSS size, cpu online and vector_num should be the same */
4797 /* Should consider 2p/4p later */
4798 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4799
4800 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4801 GFP_KERNEL);
4802 if (!vector)
4803 return -ENOMEM;
4804
4805 /* save the actual available vector number */
4806 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4807
4808 priv->vector_num = vector_num;
4809 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4810 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4811 GFP_KERNEL);
4812 if (!priv->tqp_vector) {
4813 ret = -ENOMEM;
4814 goto out;
4815 }
4816
4817 for (i = 0; i < priv->vector_num; i++) {
4818 tqp_vector = &priv->tqp_vector[i];
4819 tqp_vector->idx = i;
4820 tqp_vector->mask_addr = vector[i].io_addr;
4821 tqp_vector->vector_irq = vector[i].vector;
4822 hns3_vector_coalesce_init(tqp_vector, priv);
4823 }
4824
4825 out:
4826 devm_kfree(&pdev->dev, vector);
4827 return ret;
4828 }
4829
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4830 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4831 {
4832 group->ring = NULL;
4833 group->count = 0;
4834 }
4835
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4836 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4837 {
4838 struct hnae3_ring_chain_node *vector_ring_chain;
4839 struct hnae3_handle *h = priv->ae_handle;
4840 struct hns3_enet_tqp_vector *tqp_vector;
4841 int i;
4842
4843 for (i = 0; i < priv->vector_num; i++) {
4844 tqp_vector = &priv->tqp_vector[i];
4845
4846 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4847 continue;
4848
4849 /* Since the mapping can be overwritten, when fail to get the
4850 * chain between vector and ring, we should go on to deal with
4851 * the remaining options.
4852 */
4853 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4854 if (!vector_ring_chain)
4855 dev_warn(priv->dev, "failed to get ring chain\n");
4856
4857 h->ae_algo->ops->unmap_ring_from_vector(h,
4858 tqp_vector->vector_irq, vector_ring_chain);
4859
4860 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4861
4862 hns3_clear_ring_group(&tqp_vector->rx_group);
4863 hns3_clear_ring_group(&tqp_vector->tx_group);
4864 netif_napi_del(&priv->tqp_vector[i].napi);
4865 }
4866 }
4867
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4868 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4869 {
4870 struct hnae3_handle *h = priv->ae_handle;
4871 struct pci_dev *pdev = h->pdev;
4872 int i, ret;
4873
4874 for (i = 0; i < priv->vector_num; i++) {
4875 struct hns3_enet_tqp_vector *tqp_vector;
4876
4877 tqp_vector = &priv->tqp_vector[i];
4878 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4879 if (ret)
4880 return;
4881 }
4882
4883 devm_kfree(&pdev->dev, priv->tqp_vector);
4884 }
4885
hns3_update_tx_spare_buf_config(struct hns3_nic_priv * priv)4886 static void hns3_update_tx_spare_buf_config(struct hns3_nic_priv *priv)
4887 {
4888 #define HNS3_MIN_SPARE_BUF_SIZE (2 * 1024 * 1024)
4889 #define HNS3_MAX_PACKET_SIZE (64 * 1024)
4890
4891 struct iommu_domain *domain = iommu_get_domain_for_dev(priv->dev);
4892 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4893 struct hnae3_handle *handle = priv->ae_handle;
4894
4895 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3)
4896 return;
4897
4898 if (!(domain && iommu_is_dma_domain(domain)))
4899 return;
4900
4901 priv->min_tx_copybreak = HNS3_MAX_PACKET_SIZE;
4902 priv->min_tx_spare_buf_size = HNS3_MIN_SPARE_BUF_SIZE;
4903
4904 if (priv->tx_copybreak < priv->min_tx_copybreak)
4905 priv->tx_copybreak = priv->min_tx_copybreak;
4906 if (handle->kinfo.tx_spare_buf_size < priv->min_tx_spare_buf_size)
4907 handle->kinfo.tx_spare_buf_size = priv->min_tx_spare_buf_size;
4908 }
4909
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4910 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4911 unsigned int ring_type)
4912 {
4913 int queue_num = priv->ae_handle->kinfo.num_tqps;
4914 struct hns3_enet_ring *ring;
4915 int desc_num;
4916
4917 if (ring_type == HNAE3_RING_TYPE_TX) {
4918 ring = &priv->ring[q->tqp_index];
4919 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4920 ring->queue_index = q->tqp_index;
4921 ring->tx_copybreak = priv->tx_copybreak;
4922 ring->last_to_use = 0;
4923 } else {
4924 ring = &priv->ring[q->tqp_index + queue_num];
4925 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4926 ring->queue_index = q->tqp_index;
4927 ring->rx_copybreak = priv->rx_copybreak;
4928 }
4929
4930 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4931
4932 ring->tqp = q;
4933 ring->desc = NULL;
4934 ring->desc_cb = NULL;
4935 ring->dev = priv->dev;
4936 ring->desc_dma_addr = 0;
4937 ring->buf_size = q->buf_size;
4938 ring->desc_num = desc_num;
4939 ring->next_to_use = 0;
4940 ring->next_to_clean = 0;
4941 }
4942
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4943 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4944 struct hns3_nic_priv *priv)
4945 {
4946 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4947 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4948 }
4949
hns3_get_ring_config(struct hns3_nic_priv * priv)4950 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4951 {
4952 struct hnae3_handle *h = priv->ae_handle;
4953 struct pci_dev *pdev = h->pdev;
4954 int i;
4955
4956 priv->ring = devm_kzalloc(&pdev->dev,
4957 array3_size(h->kinfo.num_tqps,
4958 sizeof(*priv->ring), 2),
4959 GFP_KERNEL);
4960 if (!priv->ring)
4961 return -ENOMEM;
4962
4963 for (i = 0; i < h->kinfo.num_tqps; i++)
4964 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4965
4966 return 0;
4967 }
4968
hns3_put_ring_config(struct hns3_nic_priv * priv)4969 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4970 {
4971 if (!priv->ring)
4972 return;
4973
4974 devm_kfree(priv->dev, priv->ring);
4975 priv->ring = NULL;
4976 }
4977
hns3_alloc_page_pool(struct hns3_enet_ring * ring)4978 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4979 {
4980 struct page_pool_params pp_params = {
4981 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4982 PP_FLAG_DMA_SYNC_DEV,
4983 .order = hns3_page_order(ring),
4984 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4985 (PAGE_SIZE << hns3_page_order(ring)),
4986 .nid = dev_to_node(ring_to_dev(ring)),
4987 .dev = ring_to_dev(ring),
4988 .dma_dir = DMA_FROM_DEVICE,
4989 .offset = 0,
4990 .max_len = PAGE_SIZE << hns3_page_order(ring),
4991 };
4992
4993 ring->page_pool = page_pool_create(&pp_params);
4994 if (IS_ERR(ring->page_pool)) {
4995 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4996 PTR_ERR(ring->page_pool));
4997 ring->page_pool = NULL;
4998 }
4999 }
5000
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)5001 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
5002 {
5003 int ret;
5004
5005 if (ring->desc_num <= 0 || ring->buf_size <= 0)
5006 return -EINVAL;
5007
5008 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
5009 sizeof(ring->desc_cb[0]), GFP_KERNEL);
5010 if (!ring->desc_cb) {
5011 ret = -ENOMEM;
5012 goto out;
5013 }
5014
5015 ret = hns3_alloc_desc(ring);
5016 if (ret)
5017 goto out_with_desc_cb;
5018
5019 if (!HNAE3_IS_TX_RING(ring)) {
5020 if (page_pool_enabled)
5021 hns3_alloc_page_pool(ring);
5022
5023 ret = hns3_alloc_ring_buffers(ring);
5024 if (ret)
5025 goto out_with_desc;
5026 } else {
5027 hns3_init_tx_spare_buffer(ring);
5028 }
5029
5030 return 0;
5031
5032 out_with_desc:
5033 hns3_free_desc(ring);
5034 out_with_desc_cb:
5035 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5036 ring->desc_cb = NULL;
5037 out:
5038 return ret;
5039 }
5040
hns3_fini_ring(struct hns3_enet_ring * ring)5041 void hns3_fini_ring(struct hns3_enet_ring *ring)
5042 {
5043 hns3_free_desc(ring);
5044 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5045 ring->desc_cb = NULL;
5046 ring->next_to_clean = 0;
5047 ring->next_to_use = 0;
5048 ring->last_to_use = 0;
5049 ring->pending_buf = 0;
5050 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5051 dev_kfree_skb_any(ring->skb);
5052 ring->skb = NULL;
5053 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5054 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5055
5056 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5057 DMA_TO_DEVICE);
5058 free_pages((unsigned long)tx_spare->buf,
5059 get_order(tx_spare->len));
5060 devm_kfree(ring_to_dev(ring), tx_spare);
5061 ring->tx_spare = NULL;
5062 }
5063
5064 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5065 page_pool_destroy(ring->page_pool);
5066 ring->page_pool = NULL;
5067 }
5068 }
5069
hns3_buf_size2type(u32 buf_size)5070 static int hns3_buf_size2type(u32 buf_size)
5071 {
5072 int bd_size_type;
5073
5074 switch (buf_size) {
5075 case 512:
5076 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5077 break;
5078 case 1024:
5079 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5080 break;
5081 case 2048:
5082 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5083 break;
5084 case 4096:
5085 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5086 break;
5087 default:
5088 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5089 }
5090
5091 return bd_size_type;
5092 }
5093
hns3_init_ring_hw(struct hns3_enet_ring * ring)5094 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5095 {
5096 dma_addr_t dma = ring->desc_dma_addr;
5097 struct hnae3_queue *q = ring->tqp;
5098
5099 if (!HNAE3_IS_TX_RING(ring)) {
5100 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5101 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5102 (u32)((dma >> 31) >> 1));
5103
5104 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5105 hns3_buf_size2type(ring->buf_size));
5106 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5107 ring->desc_num / 8 - 1);
5108 } else {
5109 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5110 (u32)dma);
5111 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5112 (u32)((dma >> 31) >> 1));
5113
5114 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5115 ring->desc_num / 8 - 1);
5116 }
5117 }
5118
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5119 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5120 {
5121 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5122 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5123 int i;
5124
5125 for (i = 0; i < tc_info->num_tc; i++) {
5126 int j;
5127
5128 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5129 struct hnae3_queue *q;
5130
5131 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5132 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5133 }
5134 }
5135 }
5136
hns3_init_all_ring(struct hns3_nic_priv * priv)5137 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5138 {
5139 struct hnae3_handle *h = priv->ae_handle;
5140 int ring_num = h->kinfo.num_tqps * 2;
5141 int i, j;
5142 int ret;
5143
5144 hns3_update_tx_spare_buf_config(priv);
5145 for (i = 0; i < ring_num; i++) {
5146 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5147 if (ret) {
5148 dev_err(priv->dev,
5149 "Alloc ring memory fail! ret=%d\n", ret);
5150 goto out_when_alloc_ring_memory;
5151 }
5152
5153 u64_stats_init(&priv->ring[i].syncp);
5154 cond_resched();
5155 }
5156
5157 return 0;
5158
5159 out_when_alloc_ring_memory:
5160 for (j = i - 1; j >= 0; j--)
5161 hns3_fini_ring(&priv->ring[j]);
5162
5163 return -ENOMEM;
5164 }
5165
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5166 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5167 {
5168 struct hnae3_handle *h = priv->ae_handle;
5169 int i;
5170
5171 for (i = 0; i < h->kinfo.num_tqps; i++) {
5172 hns3_fini_ring(&priv->ring[i]);
5173 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5174 }
5175 }
5176
5177 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5178 static int hns3_init_mac_addr(struct net_device *netdev)
5179 {
5180 struct hns3_nic_priv *priv = netdev_priv(netdev);
5181 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5182 struct hnae3_handle *h = priv->ae_handle;
5183 u8 mac_addr_temp[ETH_ALEN] = {0};
5184 int ret = 0;
5185
5186 if (h->ae_algo->ops->get_mac_addr)
5187 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5188
5189 /* Check if the MAC address is valid, if not get a random one */
5190 if (!is_valid_ether_addr(mac_addr_temp)) {
5191 eth_hw_addr_random(netdev);
5192 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5193 dev_warn(priv->dev, "using random MAC address %s\n",
5194 format_mac_addr);
5195 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5196 eth_hw_addr_set(netdev, mac_addr_temp);
5197 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5198 } else {
5199 return 0;
5200 }
5201
5202 if (h->ae_algo->ops->set_mac_addr)
5203 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5204
5205 return ret;
5206 }
5207
hns3_init_phy(struct net_device * netdev)5208 static int hns3_init_phy(struct net_device *netdev)
5209 {
5210 struct hnae3_handle *h = hns3_get_handle(netdev);
5211 int ret = 0;
5212
5213 if (h->ae_algo->ops->mac_connect_phy)
5214 ret = h->ae_algo->ops->mac_connect_phy(h);
5215
5216 return ret;
5217 }
5218
hns3_uninit_phy(struct net_device * netdev)5219 static void hns3_uninit_phy(struct net_device *netdev)
5220 {
5221 struct hnae3_handle *h = hns3_get_handle(netdev);
5222
5223 if (h->ae_algo->ops->mac_disconnect_phy)
5224 h->ae_algo->ops->mac_disconnect_phy(h);
5225 }
5226
hns3_client_start(struct hnae3_handle * handle)5227 static int hns3_client_start(struct hnae3_handle *handle)
5228 {
5229 if (!handle->ae_algo->ops->client_start)
5230 return 0;
5231
5232 return handle->ae_algo->ops->client_start(handle);
5233 }
5234
hns3_client_stop(struct hnae3_handle * handle)5235 static void hns3_client_stop(struct hnae3_handle *handle)
5236 {
5237 if (!handle->ae_algo->ops->client_stop)
5238 return;
5239
5240 handle->ae_algo->ops->client_stop(handle);
5241 }
5242
hns3_info_show(struct hns3_nic_priv * priv)5243 static void hns3_info_show(struct hns3_nic_priv *priv)
5244 {
5245 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5246 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5247
5248 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5249 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5250 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5251 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5252 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5253 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5254 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5255 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5256 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5257 kinfo->tc_info.num_tc);
5258 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5259 }
5260
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5261 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5262 enum dim_cq_period_mode mode, bool is_tx)
5263 {
5264 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5265 struct hnae3_handle *handle = priv->ae_handle;
5266 int i;
5267
5268 if (is_tx) {
5269 priv->tx_cqe_mode = mode;
5270
5271 for (i = 0; i < priv->vector_num; i++)
5272 priv->tqp_vector[i].tx_group.dim.mode = mode;
5273 } else {
5274 priv->rx_cqe_mode = mode;
5275
5276 for (i = 0; i < priv->vector_num; i++)
5277 priv->tqp_vector[i].rx_group.dim.mode = mode;
5278 }
5279
5280 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5281 u32 new_mode;
5282 u64 reg;
5283
5284 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5285 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5286 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5287
5288 writel(new_mode, handle->kinfo.io_base + reg);
5289 }
5290 }
5291
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5292 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5293 enum dim_cq_period_mode tx_mode,
5294 enum dim_cq_period_mode rx_mode)
5295 {
5296 hns3_set_cq_period_mode(priv, tx_mode, true);
5297 hns3_set_cq_period_mode(priv, rx_mode, false);
5298 }
5299
hns3_state_init(struct hnae3_handle * handle)5300 static void hns3_state_init(struct hnae3_handle *handle)
5301 {
5302 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5303 struct net_device *netdev = handle->kinfo.netdev;
5304 struct hns3_nic_priv *priv = netdev_priv(netdev);
5305
5306 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5307
5308 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5309 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5310
5311 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5312 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5313
5314 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5315 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5316
5317 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5318 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5319 }
5320
hns3_state_uninit(struct hnae3_handle * handle)5321 static void hns3_state_uninit(struct hnae3_handle *handle)
5322 {
5323 struct hns3_nic_priv *priv = handle->priv;
5324
5325 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5326 }
5327
hns3_client_init(struct hnae3_handle * handle)5328 static int hns3_client_init(struct hnae3_handle *handle)
5329 {
5330 struct pci_dev *pdev = handle->pdev;
5331 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5332 u16 alloc_tqps, max_rss_size;
5333 struct hns3_nic_priv *priv;
5334 struct net_device *netdev;
5335 int ret;
5336
5337 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5338 &max_rss_size);
5339 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5340 if (!netdev)
5341 return -ENOMEM;
5342
5343 priv = netdev_priv(netdev);
5344 priv->dev = &pdev->dev;
5345 priv->netdev = netdev;
5346 priv->ae_handle = handle;
5347 priv->tx_timeout_count = 0;
5348 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5349 priv->min_tx_copybreak = 0;
5350 priv->min_tx_spare_buf_size = 0;
5351 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5352
5353 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5354
5355 handle->kinfo.netdev = netdev;
5356 handle->priv = (void *)priv;
5357
5358 hns3_init_mac_addr(netdev);
5359
5360 hns3_set_default_feature(netdev);
5361
5362 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5363 netdev->priv_flags |= IFF_UNICAST_FLT;
5364 netdev->netdev_ops = &hns3_nic_netdev_ops;
5365 SET_NETDEV_DEV(netdev, &pdev->dev);
5366 hns3_ethtool_set_ops(netdev);
5367
5368 /* Carrier off reporting is important to ethtool even BEFORE open */
5369 netif_carrier_off(netdev);
5370
5371 ret = hns3_get_ring_config(priv);
5372 if (ret) {
5373 ret = -ENOMEM;
5374 goto out_get_ring_cfg;
5375 }
5376
5377 hns3_nic_init_coal_cfg(priv);
5378
5379 ret = hns3_nic_alloc_vector_data(priv);
5380 if (ret) {
5381 ret = -ENOMEM;
5382 goto out_alloc_vector_data;
5383 }
5384
5385 ret = hns3_nic_init_vector_data(priv);
5386 if (ret) {
5387 ret = -ENOMEM;
5388 goto out_init_vector_data;
5389 }
5390
5391 ret = hns3_init_all_ring(priv);
5392 if (ret) {
5393 ret = -ENOMEM;
5394 goto out_init_ring;
5395 }
5396
5397 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5398 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5399
5400 ret = hns3_init_phy(netdev);
5401 if (ret)
5402 goto out_init_phy;
5403
5404 /* the device can work without cpu rmap, only aRFS needs it */
5405 ret = hns3_set_rx_cpu_rmap(netdev);
5406 if (ret)
5407 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5408
5409 ret = hns3_nic_init_irq(priv);
5410 if (ret) {
5411 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5412 hns3_free_rx_cpu_rmap(netdev);
5413 goto out_init_irq_fail;
5414 }
5415
5416 ret = hns3_client_start(handle);
5417 if (ret) {
5418 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5419 goto out_client_start;
5420 }
5421
5422 hns3_dcbnl_setup(handle);
5423
5424 ret = hns3_dbg_init(handle);
5425 if (ret) {
5426 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5427 ret);
5428 goto out_client_start;
5429 }
5430
5431 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5432
5433 hns3_state_init(handle);
5434
5435 ret = register_netdev(netdev);
5436 if (ret) {
5437 dev_err(priv->dev, "probe register netdev fail!\n");
5438 goto out_reg_netdev_fail;
5439 }
5440
5441 if (netif_msg_drv(handle))
5442 hns3_info_show(priv);
5443
5444 return ret;
5445
5446 out_reg_netdev_fail:
5447 hns3_state_uninit(handle);
5448 hns3_dbg_uninit(handle);
5449 hns3_client_stop(handle);
5450 out_client_start:
5451 hns3_free_rx_cpu_rmap(netdev);
5452 hns3_nic_uninit_irq(priv);
5453 out_init_irq_fail:
5454 hns3_uninit_phy(netdev);
5455 out_init_phy:
5456 hns3_uninit_all_ring(priv);
5457 out_init_ring:
5458 hns3_nic_uninit_vector_data(priv);
5459 out_init_vector_data:
5460 hns3_nic_dealloc_vector_data(priv);
5461 out_alloc_vector_data:
5462 priv->ring = NULL;
5463 out_get_ring_cfg:
5464 priv->ae_handle = NULL;
5465 free_netdev(netdev);
5466 return ret;
5467 }
5468
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5469 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5470 {
5471 struct net_device *netdev = handle->kinfo.netdev;
5472 struct hns3_nic_priv *priv = netdev_priv(netdev);
5473
5474 if (netdev->reg_state != NETREG_UNINITIALIZED)
5475 unregister_netdev(netdev);
5476
5477 hns3_client_stop(handle);
5478
5479 hns3_uninit_phy(netdev);
5480
5481 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5482 netdev_warn(netdev, "already uninitialized\n");
5483 goto out_netdev_free;
5484 }
5485
5486 hns3_free_rx_cpu_rmap(netdev);
5487
5488 hns3_nic_uninit_irq(priv);
5489
5490 hns3_clear_all_ring(handle, true);
5491
5492 hns3_nic_uninit_vector_data(priv);
5493
5494 hns3_nic_dealloc_vector_data(priv);
5495
5496 hns3_uninit_all_ring(priv);
5497
5498 hns3_put_ring_config(priv);
5499
5500 out_netdev_free:
5501 hns3_dbg_uninit(handle);
5502 free_netdev(netdev);
5503 }
5504
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5505 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5506 {
5507 struct net_device *netdev = handle->kinfo.netdev;
5508
5509 if (!netdev)
5510 return;
5511
5512 if (linkup) {
5513 netif_tx_wake_all_queues(netdev);
5514 netif_carrier_on(netdev);
5515 if (netif_msg_link(handle))
5516 netdev_info(netdev, "link up\n");
5517 } else {
5518 netif_carrier_off(netdev);
5519 netif_tx_stop_all_queues(netdev);
5520 if (netif_msg_link(handle))
5521 netdev_info(netdev, "link down\n");
5522 }
5523 }
5524
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5525 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5526 {
5527 while (ring->next_to_clean != ring->next_to_use) {
5528 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5529 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5530 ring_ptr_move_fw(ring, next_to_clean);
5531 }
5532
5533 ring->pending_buf = 0;
5534 }
5535
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5536 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5537 {
5538 struct hns3_desc_cb res_cbs;
5539 int ret;
5540
5541 while (ring->next_to_use != ring->next_to_clean) {
5542 /* When a buffer is not reused, it's memory has been
5543 * freed in hns3_handle_rx_bd or will be freed by
5544 * stack, so we need to replace the buffer here.
5545 */
5546 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5547 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5548 if (ret) {
5549 hns3_ring_stats_update(ring, sw_err_cnt);
5550 /* if alloc new buffer fail, exit directly
5551 * and reclear in up flow.
5552 */
5553 netdev_warn(ring_to_netdev(ring),
5554 "reserve buffer map failed, ret = %d\n",
5555 ret);
5556 return ret;
5557 }
5558 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5559 }
5560 ring_ptr_move_fw(ring, next_to_use);
5561 }
5562
5563 /* Free the pending skb in rx ring */
5564 if (ring->skb) {
5565 dev_kfree_skb_any(ring->skb);
5566 ring->skb = NULL;
5567 ring->pending_buf = 0;
5568 }
5569
5570 return 0;
5571 }
5572
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5573 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5574 {
5575 while (ring->next_to_use != ring->next_to_clean) {
5576 /* When a buffer is not reused, it's memory has been
5577 * freed in hns3_handle_rx_bd or will be freed by
5578 * stack, so only need to unmap the buffer here.
5579 */
5580 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5581 hns3_unmap_buffer(ring,
5582 &ring->desc_cb[ring->next_to_use]);
5583 ring->desc_cb[ring->next_to_use].dma = 0;
5584 }
5585
5586 ring_ptr_move_fw(ring, next_to_use);
5587 }
5588 }
5589
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5590 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5591 {
5592 struct net_device *ndev = h->kinfo.netdev;
5593 struct hns3_nic_priv *priv = netdev_priv(ndev);
5594 u32 i;
5595
5596 for (i = 0; i < h->kinfo.num_tqps; i++) {
5597 struct hns3_enet_ring *ring;
5598
5599 ring = &priv->ring[i];
5600 hns3_clear_tx_ring(ring);
5601
5602 ring = &priv->ring[i + h->kinfo.num_tqps];
5603 /* Continue to clear other rings even if clearing some
5604 * rings failed.
5605 */
5606 if (force)
5607 hns3_force_clear_rx_ring(ring);
5608 else
5609 hns3_clear_rx_ring(ring);
5610 }
5611 }
5612
hns3_nic_reset_all_ring(struct hnae3_handle * h)5613 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5614 {
5615 struct net_device *ndev = h->kinfo.netdev;
5616 struct hns3_nic_priv *priv = netdev_priv(ndev);
5617 struct hns3_enet_ring *rx_ring;
5618 int i, j;
5619 int ret;
5620
5621 ret = h->ae_algo->ops->reset_queue(h);
5622 if (ret)
5623 return ret;
5624
5625 for (i = 0; i < h->kinfo.num_tqps; i++) {
5626 hns3_init_ring_hw(&priv->ring[i]);
5627
5628 /* We need to clear tx ring here because self test will
5629 * use the ring and will not run down before up
5630 */
5631 hns3_clear_tx_ring(&priv->ring[i]);
5632 priv->ring[i].next_to_clean = 0;
5633 priv->ring[i].next_to_use = 0;
5634 priv->ring[i].last_to_use = 0;
5635
5636 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5637 hns3_init_ring_hw(rx_ring);
5638 ret = hns3_clear_rx_ring(rx_ring);
5639 if (ret)
5640 return ret;
5641
5642 /* We can not know the hardware head and tail when this
5643 * function is called in reset flow, so we reuse all desc.
5644 */
5645 for (j = 0; j < rx_ring->desc_num; j++)
5646 hns3_reuse_buffer(rx_ring, j);
5647
5648 rx_ring->next_to_clean = 0;
5649 rx_ring->next_to_use = 0;
5650 }
5651
5652 hns3_init_tx_ring_tc(priv);
5653
5654 return 0;
5655 }
5656
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5657 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5658 {
5659 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5660 struct net_device *ndev = kinfo->netdev;
5661 struct hns3_nic_priv *priv = netdev_priv(ndev);
5662
5663 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5664 return 0;
5665
5666 if (!netif_running(ndev))
5667 return 0;
5668
5669 return hns3_nic_net_stop(ndev);
5670 }
5671
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5672 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5673 {
5674 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5675 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5676 int ret = 0;
5677
5678 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5679 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5680 return -EFAULT;
5681 }
5682
5683 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5684
5685 if (netif_running(kinfo->netdev)) {
5686 ret = hns3_nic_net_open(kinfo->netdev);
5687 if (ret) {
5688 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5689 netdev_err(kinfo->netdev,
5690 "net up fail, ret=%d!\n", ret);
5691 return ret;
5692 }
5693 }
5694
5695 return ret;
5696 }
5697
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5698 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5699 {
5700 struct net_device *netdev = handle->kinfo.netdev;
5701 struct hns3_nic_priv *priv = netdev_priv(netdev);
5702 int ret;
5703
5704 /* Carrier off reporting is important to ethtool even BEFORE open */
5705 netif_carrier_off(netdev);
5706
5707 ret = hns3_get_ring_config(priv);
5708 if (ret)
5709 return ret;
5710
5711 ret = hns3_nic_alloc_vector_data(priv);
5712 if (ret)
5713 goto err_put_ring;
5714
5715 ret = hns3_nic_init_vector_data(priv);
5716 if (ret)
5717 goto err_dealloc_vector;
5718
5719 ret = hns3_init_all_ring(priv);
5720 if (ret)
5721 goto err_uninit_vector;
5722
5723 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5724
5725 /* the device can work without cpu rmap, only aRFS needs it */
5726 ret = hns3_set_rx_cpu_rmap(netdev);
5727 if (ret)
5728 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5729
5730 ret = hns3_nic_init_irq(priv);
5731 if (ret) {
5732 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5733 hns3_free_rx_cpu_rmap(netdev);
5734 goto err_init_irq_fail;
5735 }
5736
5737 if (!hns3_is_phys_func(handle->pdev))
5738 hns3_init_mac_addr(netdev);
5739
5740 ret = hns3_client_start(handle);
5741 if (ret) {
5742 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5743 goto err_client_start_fail;
5744 }
5745
5746 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5747
5748 return ret;
5749
5750 err_client_start_fail:
5751 hns3_free_rx_cpu_rmap(netdev);
5752 hns3_nic_uninit_irq(priv);
5753 err_init_irq_fail:
5754 hns3_uninit_all_ring(priv);
5755 err_uninit_vector:
5756 hns3_nic_uninit_vector_data(priv);
5757 err_dealloc_vector:
5758 hns3_nic_dealloc_vector_data(priv);
5759 err_put_ring:
5760 hns3_put_ring_config(priv);
5761
5762 return ret;
5763 }
5764
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5765 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5766 {
5767 struct net_device *netdev = handle->kinfo.netdev;
5768 struct hns3_nic_priv *priv = netdev_priv(netdev);
5769
5770 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5771 hns3_nic_net_stop(netdev);
5772
5773 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5774 netdev_warn(netdev, "already uninitialized\n");
5775 return 0;
5776 }
5777
5778 hns3_free_rx_cpu_rmap(netdev);
5779 hns3_nic_uninit_irq(priv);
5780 hns3_clear_all_ring(handle, true);
5781 hns3_reset_tx_queue(priv->ae_handle);
5782
5783 hns3_nic_uninit_vector_data(priv);
5784
5785 hns3_nic_dealloc_vector_data(priv);
5786
5787 hns3_uninit_all_ring(priv);
5788
5789 hns3_put_ring_config(priv);
5790
5791 return 0;
5792 }
5793
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5794 int hns3_reset_notify(struct hnae3_handle *handle,
5795 enum hnae3_reset_notify_type type)
5796 {
5797 int ret = 0;
5798
5799 switch (type) {
5800 case HNAE3_UP_CLIENT:
5801 ret = hns3_reset_notify_up_enet(handle);
5802 break;
5803 case HNAE3_DOWN_CLIENT:
5804 ret = hns3_reset_notify_down_enet(handle);
5805 break;
5806 case HNAE3_INIT_CLIENT:
5807 ret = hns3_reset_notify_init_enet(handle);
5808 break;
5809 case HNAE3_UNINIT_CLIENT:
5810 ret = hns3_reset_notify_uninit_enet(handle);
5811 break;
5812 default:
5813 break;
5814 }
5815
5816 return ret;
5817 }
5818
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5819 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5820 bool rxfh_configured)
5821 {
5822 int ret;
5823
5824 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5825 rxfh_configured);
5826 if (ret) {
5827 dev_err(&handle->pdev->dev,
5828 "Change tqp num(%u) fail.\n", new_tqp_num);
5829 return ret;
5830 }
5831
5832 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5833 if (ret)
5834 return ret;
5835
5836 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5837 if (ret)
5838 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5839
5840 return ret;
5841 }
5842
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5843 int hns3_set_channels(struct net_device *netdev,
5844 struct ethtool_channels *ch)
5845 {
5846 struct hnae3_handle *h = hns3_get_handle(netdev);
5847 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5848 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5849 u32 new_tqp_num = ch->combined_count;
5850 u16 org_tqp_num;
5851 int ret;
5852
5853 if (hns3_nic_resetting(netdev))
5854 return -EBUSY;
5855
5856 if (ch->rx_count || ch->tx_count)
5857 return -EINVAL;
5858
5859 if (kinfo->tc_info.mqprio_active) {
5860 dev_err(&netdev->dev,
5861 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5862 return -EINVAL;
5863 }
5864
5865 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5866 new_tqp_num < 1) {
5867 dev_err(&netdev->dev,
5868 "Change tqps fail, the tqp range is from 1 to %u",
5869 hns3_get_max_available_channels(h));
5870 return -EINVAL;
5871 }
5872
5873 if (kinfo->rss_size == new_tqp_num)
5874 return 0;
5875
5876 netif_dbg(h, drv, netdev,
5877 "set channels: tqp_num=%u, rxfh=%d\n",
5878 new_tqp_num, rxfh_configured);
5879
5880 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5881 if (ret)
5882 return ret;
5883
5884 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5885 if (ret)
5886 return ret;
5887
5888 org_tqp_num = h->kinfo.num_tqps;
5889 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5890 if (ret) {
5891 int ret1;
5892
5893 netdev_warn(netdev,
5894 "Change channels fail, revert to old value\n");
5895 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5896 if (ret1) {
5897 netdev_err(netdev,
5898 "revert to old channel fail\n");
5899 return ret1;
5900 }
5901
5902 return ret;
5903 }
5904
5905 return 0;
5906 }
5907
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5908 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5909 {
5910 struct hns3_nic_priv *priv = netdev_priv(ndev);
5911
5912 if (!if_running)
5913 return;
5914
5915 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5916 return;
5917
5918 netif_carrier_off(ndev);
5919 netif_tx_disable(ndev);
5920
5921 hns3_disable_irqs_and_tqps(ndev);
5922
5923 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5924 * during reset process, because driver may not be able
5925 * to disable the ring through firmware when downing the netdev.
5926 */
5927 if (!hns3_nic_resetting(ndev))
5928 hns3_nic_reset_all_ring(priv->ae_handle);
5929
5930 hns3_reset_tx_queue(priv->ae_handle);
5931 }
5932
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5933 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5934 {
5935 struct hns3_nic_priv *priv = netdev_priv(ndev);
5936 struct hnae3_handle *h = priv->ae_handle;
5937
5938 if (!if_running)
5939 return;
5940
5941 if (hns3_nic_resetting(ndev))
5942 return;
5943
5944 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5945 return;
5946
5947 if (hns3_nic_reset_all_ring(priv->ae_handle))
5948 return;
5949
5950 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5951
5952 hns3_enable_irqs_and_tqps(ndev);
5953
5954 netif_tx_wake_all_queues(ndev);
5955
5956 if (h->ae_algo->ops->get_status(h))
5957 netif_carrier_on(ndev);
5958 }
5959
5960 static const struct hns3_hw_error_info hns3_hw_err[] = {
5961 { .type = HNAE3_PPU_POISON_ERROR,
5962 .msg = "PPU poison" },
5963 { .type = HNAE3_CMDQ_ECC_ERROR,
5964 .msg = "IMP CMDQ error" },
5965 { .type = HNAE3_IMP_RD_POISON_ERROR,
5966 .msg = "IMP RD poison" },
5967 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5968 .msg = "ROCEE AXI RESP error" },
5969 };
5970
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)5971 static void hns3_process_hw_error(struct hnae3_handle *handle,
5972 enum hnae3_hw_error_type type)
5973 {
5974 int i;
5975
5976 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5977 if (hns3_hw_err[i].type == type) {
5978 dev_err(&handle->pdev->dev, "Detected %s!\n",
5979 hns3_hw_err[i].msg);
5980 break;
5981 }
5982 }
5983 }
5984
5985 static const struct hnae3_client_ops client_ops = {
5986 .init_instance = hns3_client_init,
5987 .uninit_instance = hns3_client_uninit,
5988 .link_status_change = hns3_link_status_change,
5989 .reset_notify = hns3_reset_notify,
5990 .process_hw_error = hns3_process_hw_error,
5991 };
5992
5993 /* hns3_init_module - Driver registration routine
5994 * hns3_init_module is the first routine called when the driver is
5995 * loaded. All it does is register with the PCI subsystem.
5996 */
hns3_init_module(void)5997 static int __init hns3_init_module(void)
5998 {
5999 int ret;
6000
6001 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
6002 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
6003
6004 client.type = HNAE3_CLIENT_KNIC;
6005 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
6006 hns3_driver_name);
6007
6008 client.ops = &client_ops;
6009
6010 INIT_LIST_HEAD(&client.node);
6011
6012 hns3_dbg_register_debugfs(hns3_driver_name);
6013
6014 ret = hnae3_register_client(&client);
6015 if (ret)
6016 goto err_reg_client;
6017
6018 ret = pci_register_driver(&hns3_driver);
6019 if (ret)
6020 goto err_reg_driver;
6021
6022 return ret;
6023
6024 err_reg_driver:
6025 hnae3_unregister_client(&client);
6026 err_reg_client:
6027 hns3_dbg_unregister_debugfs();
6028 return ret;
6029 }
6030 module_init(hns3_init_module);
6031
6032 /* hns3_exit_module - Driver exit cleanup routine
6033 * hns3_exit_module is called just before the driver is removed
6034 * from memory.
6035 */
hns3_exit_module(void)6036 static void __exit hns3_exit_module(void)
6037 {
6038 hnae3_acquire_unload_lock();
6039 pci_unregister_driver(&hns3_driver);
6040 hnae3_unregister_client(&client);
6041 hns3_dbg_unregister_debugfs();
6042 hnae3_release_unload_lock();
6043 }
6044 module_exit(hns3_exit_module);
6045
6046 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6047 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6048 MODULE_LICENSE("GPL");
6049 MODULE_ALIAS("pci:hns-nic");
6050