1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Copyright 2020-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8 #include "gaudi2P.h"
9 #include "../include/gaudi2/asic_reg/gaudi2_regs.h"
10
11 #define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))
12
13 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK
14 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK
15 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK
16 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK
17 #define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK
18 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \
19 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK
20 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \
21 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK
22 #define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \
23 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK
24
25 /* LBW RR */
26 #define SFT_NUM_OF_LBW_RTR 1
27 #define SFT_LBW_RTR_OFFSET 0
28 #define RR_LBW_LONG_MASK 0x7FFFFFFull
29 #define RR_LBW_SHORT_MASK 0x7FFF000ull
30
31 /* HBW RR */
32 #define SFT_NUM_OF_HBW_RTR 2
33 #define RR_HBW_SHORT_LO_MASK 0xFFFFFFFF000ull
34 #define RR_HBW_SHORT_HI_MASK 0xF00000000000ull
35 #define RR_HBW_LONG_LO_MASK 0xFFFFFFFF000ull
36 #define RR_HBW_LONG_HI_MASK 0xFFFFF00000000000ull
37
38 struct rr_config {
39 u64 min;
40 u64 max;
41 u32 index;
42 u8 type;
43 };
44
45 struct gaudi2_atypical_bp_blocks {
46 u32 mm_block_base_addr;
47 u32 block_size;
48 u32 glbl_sec_offset;
49 u32 glbl_sec_length;
50 };
51
52 static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {
53 mmDCORE0_SYNC_MNGR_OBJS_BASE,
54 128 * 1024,
55 SM_OBJS_PROT_BITS_OFFS,
56 640
57 };
58
59 static const u32 gaudi2_pb_sft0[] = {
60 mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
61 mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,
62 mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
63 mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,
64 mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
65 mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,
66 mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
67 mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,
68 mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,
69 mmSFT0_LBW_RTR_IF_RTR_H3_BASE,
70 mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,
71 mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,
72 mmSFT0_BASE,
73 };
74
75 static const u32 gaudi2_pb_dcr0_hif[] = {
76 mmDCORE0_HIF0_BASE,
77 };
78
79 static const u32 gaudi2_pb_dcr0_rtr0[] = {
80 mmDCORE0_RTR0_CTRL_BASE,
81 mmDCORE0_RTR0_H3_BASE,
82 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
83 mmDCORE0_RTR0_ADD_DEC_HBW_BASE,
84 mmDCORE0_RTR0_BASE,
85 mmDCORE0_RTR0_DBG_ADDR_BASE,
86 };
87
88 static const u32 gaudi2_pb_dcr0_hmmu0[] = {
89 mmDCORE0_HMMU0_MMU_BASE,
90 mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,
91 mmDCORE0_HMMU0_SCRAMB_OUT_BASE,
92 mmDCORE0_HMMU0_STLB_BASE,
93 };
94
95 static const u32 gaudi2_pb_cpu_if[] = {
96 mmCPU_IF_BASE,
97 };
98
99 static const u32 gaudi2_pb_cpu[] = {
100 mmCPU_CA53_CFG_BASE,
101 mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,
102 };
103
104 static const u32 gaudi2_pb_kdma[] = {
105 mmARC_FARM_KDMA_BASE,
106 mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,
107 };
108
109 static const u32 gaudi2_pb_pdma0[] = {
110 mmPDMA0_CORE_BASE,
111 mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
112 mmPDMA0_QM_BASE,
113 };
114
115 static const u32 gaudi2_pb_pdma0_arc[] = {
116 mmPDMA0_QM_ARC_AUX_BASE,
117 };
118
119 static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {
120 {mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},
121 {mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
122 {mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},
123 {mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
124 {mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
125 {mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
126 {mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
127 {mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
128 {mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
129 };
130
131 static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {
132 mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
133 mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,
134 mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,
135 mmPDMA0_CORE_CTX_WR_COMP_WDATA,
136 mmPDMA0_CORE_CTX_SRC_BASE_LO,
137 mmPDMA0_CORE_CTX_SRC_BASE_HI,
138 mmPDMA0_CORE_CTX_DST_BASE_LO,
139 mmPDMA0_CORE_CTX_DST_BASE_HI,
140 mmPDMA0_CORE_CTX_SRC_TSIZE_0,
141 mmPDMA0_CORE_CTX_SRC_TSIZE_1,
142 mmPDMA0_CORE_CTX_SRC_TSIZE_2,
143 mmPDMA0_CORE_CTX_SRC_TSIZE_3,
144 mmPDMA0_CORE_CTX_SRC_TSIZE_4,
145 mmPDMA0_CORE_CTX_SRC_STRIDE_1,
146 mmPDMA0_CORE_CTX_SRC_STRIDE_2,
147 mmPDMA0_CORE_CTX_SRC_STRIDE_3,
148 mmPDMA0_CORE_CTX_SRC_STRIDE_4,
149 mmPDMA0_CORE_CTX_SRC_OFFSET_LO,
150 mmPDMA0_CORE_CTX_SRC_OFFSET_HI,
151 mmPDMA0_CORE_CTX_DST_TSIZE_0,
152 mmPDMA0_CORE_CTX_DST_TSIZE_1,
153 mmPDMA0_CORE_CTX_DST_TSIZE_2,
154 mmPDMA0_CORE_CTX_DST_TSIZE_3,
155 mmPDMA0_CORE_CTX_DST_TSIZE_4,
156 mmPDMA0_CORE_CTX_DST_STRIDE_1,
157 mmPDMA0_CORE_CTX_DST_STRIDE_2,
158 mmPDMA0_CORE_CTX_DST_STRIDE_3,
159 mmPDMA0_CORE_CTX_DST_STRIDE_4,
160 mmPDMA0_CORE_CTX_DST_OFFSET_LO,
161 mmPDMA0_CORE_CTX_DST_OFFSET_HI,
162 mmPDMA0_CORE_CTX_COMMIT,
163 mmPDMA0_CORE_CTX_CTRL,
164 mmPDMA0_CORE_CTX_TE_NUMROWS,
165 mmPDMA0_CORE_CTX_IDX,
166 mmPDMA0_CORE_CTX_IDX_INC,
167 mmPDMA0_QM_CQ_CFG0_0,
168 mmPDMA0_QM_CQ_CFG0_1,
169 mmPDMA0_QM_CQ_CFG0_2,
170 mmPDMA0_QM_CQ_CFG0_3,
171 mmPDMA0_QM_CQ_CFG0_4,
172 mmPDMA0_QM_CP_FENCE0_RDATA_0,
173 mmPDMA0_QM_CP_FENCE0_RDATA_1,
174 mmPDMA0_QM_CP_FENCE0_RDATA_2,
175 mmPDMA0_QM_CP_FENCE0_RDATA_3,
176 mmPDMA0_QM_CP_FENCE0_RDATA_4,
177 mmPDMA0_QM_CP_FENCE1_RDATA_0,
178 mmPDMA0_QM_CP_FENCE1_RDATA_1,
179 mmPDMA0_QM_CP_FENCE1_RDATA_2,
180 mmPDMA0_QM_CP_FENCE1_RDATA_3,
181 mmPDMA0_QM_CP_FENCE1_RDATA_4,
182 mmPDMA0_QM_CP_FENCE2_RDATA_0,
183 mmPDMA0_QM_CP_FENCE2_RDATA_1,
184 mmPDMA0_QM_CP_FENCE2_RDATA_2,
185 mmPDMA0_QM_CP_FENCE2_RDATA_3,
186 mmPDMA0_QM_CP_FENCE2_RDATA_4,
187 mmPDMA0_QM_CP_FENCE3_RDATA_0,
188 mmPDMA0_QM_CP_FENCE3_RDATA_1,
189 mmPDMA0_QM_CP_FENCE3_RDATA_2,
190 mmPDMA0_QM_CP_FENCE3_RDATA_3,
191 mmPDMA0_QM_CP_FENCE3_RDATA_4,
192 mmPDMA0_QM_CP_FENCE0_CNT_0,
193 mmPDMA0_QM_CP_FENCE0_CNT_1,
194 mmPDMA0_QM_CP_FENCE0_CNT_2,
195 mmPDMA0_QM_CP_FENCE0_CNT_3,
196 mmPDMA0_QM_CP_FENCE0_CNT_4,
197 mmPDMA0_QM_CP_FENCE1_CNT_0,
198 mmPDMA0_QM_CP_FENCE1_CNT_1,
199 mmPDMA0_QM_CP_FENCE1_CNT_2,
200 mmPDMA0_QM_CP_FENCE1_CNT_3,
201 mmPDMA0_QM_CP_FENCE1_CNT_4,
202 mmPDMA0_QM_CP_FENCE2_CNT_0,
203 mmPDMA0_QM_CP_FENCE2_CNT_1,
204 mmPDMA0_QM_CP_FENCE2_CNT_2,
205 mmPDMA0_QM_CP_FENCE2_CNT_3,
206 mmPDMA0_QM_CP_FENCE2_CNT_4,
207 mmPDMA0_QM_CP_FENCE3_CNT_0,
208 mmPDMA0_QM_CP_FENCE3_CNT_1,
209 mmPDMA0_QM_CP_FENCE3_CNT_2,
210 mmPDMA0_QM_CP_FENCE3_CNT_3,
211 mmPDMA0_QM_CP_FENCE3_CNT_4,
212 mmPDMA0_QM_CQ_PTR_LO_0,
213 mmPDMA0_QM_CQ_PTR_HI_0,
214 mmPDMA0_QM_CQ_TSIZE_0,
215 mmPDMA0_QM_CQ_CTL_0,
216 mmPDMA0_QM_CQ_PTR_LO_1,
217 mmPDMA0_QM_CQ_PTR_HI_1,
218 mmPDMA0_QM_CQ_TSIZE_1,
219 mmPDMA0_QM_CQ_CTL_1,
220 mmPDMA0_QM_CQ_PTR_LO_2,
221 mmPDMA0_QM_CQ_PTR_HI_2,
222 mmPDMA0_QM_CQ_TSIZE_2,
223 mmPDMA0_QM_CQ_CTL_2,
224 mmPDMA0_QM_CQ_PTR_LO_3,
225 mmPDMA0_QM_CQ_PTR_HI_3,
226 mmPDMA0_QM_CQ_TSIZE_3,
227 mmPDMA0_QM_CQ_CTL_3,
228 mmPDMA0_QM_CQ_PTR_LO_4,
229 mmPDMA0_QM_CQ_PTR_HI_4,
230 mmPDMA0_QM_CQ_TSIZE_4,
231 mmPDMA0_QM_CQ_CTL_4,
232 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
233 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
234 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
235 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
236 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
237 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
238 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
239 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
240 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
241 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
242 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
243 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
244 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
245 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
246 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
247 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
248 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
249 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
250 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
251 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
252 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
253 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
254 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
255 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
256 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
257 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
258 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
259 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
260 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
261 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
262 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
263 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
264 mmPDMA0_QM_ARC_CQ_PTR_LO,
265 mmPDMA0_QM_ARC_CQ_PTR_LO_STS,
266 mmPDMA0_QM_ARC_CQ_PTR_HI,
267 mmPDMA0_QM_ARC_CQ_PTR_HI_STS,
268 mmPDMA0_QM_ARB_CFG_0,
269 mmPDMA0_QM_ARB_MST_QUIET_PER,
270 mmPDMA0_QM_ARB_CHOICE_Q_PUSH,
271 mmPDMA0_QM_ARB_WRR_WEIGHT_0,
272 mmPDMA0_QM_ARB_WRR_WEIGHT_1,
273 mmPDMA0_QM_ARB_WRR_WEIGHT_2,
274 mmPDMA0_QM_ARB_WRR_WEIGHT_3,
275 mmPDMA0_QM_ARB_BASE_LO,
276 mmPDMA0_QM_ARB_BASE_HI,
277 mmPDMA0_QM_ARB_MST_SLAVE_EN,
278 mmPDMA0_QM_ARB_MST_SLAVE_EN_1,
279 mmPDMA0_QM_ARB_MST_CRED_INC,
280 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
281 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
282 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
283 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
284 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
285 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
286 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
287 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
288 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
289 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
290 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
291 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
292 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
293 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
294 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
295 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
296 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
297 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
298 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
299 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
300 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
301 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
302 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
303 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
304 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
305 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
306 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
307 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
308 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
309 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
310 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
311 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
312 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
313 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
314 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
315 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
316 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
317 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
318 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
319 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
320 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
321 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
322 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
323 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
324 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
325 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
326 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
327 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
328 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
329 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
330 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
331 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
332 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
333 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
334 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
335 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
336 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
337 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
338 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
339 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
340 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
341 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
342 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
343 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
344 mmPDMA0_QM_ARB_SLV_ID,
345 mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
346 mmPDMA0_QM_ARC_CQ_CFG0,
347 mmPDMA0_QM_CQ_IFIFO_CI_0,
348 mmPDMA0_QM_CQ_IFIFO_CI_1,
349 mmPDMA0_QM_CQ_IFIFO_CI_2,
350 mmPDMA0_QM_CQ_IFIFO_CI_3,
351 mmPDMA0_QM_CQ_IFIFO_CI_4,
352 mmPDMA0_QM_ARC_CQ_IFIFO_CI,
353 mmPDMA0_QM_CQ_CTL_CI_0,
354 mmPDMA0_QM_CQ_CTL_CI_1,
355 mmPDMA0_QM_CQ_CTL_CI_2,
356 mmPDMA0_QM_CQ_CTL_CI_3,
357 mmPDMA0_QM_CQ_CTL_CI_4,
358 mmPDMA0_QM_ARC_CQ_CTL_CI,
359 mmPDMA0_QM_ARC_CQ_TSIZE,
360 mmPDMA0_QM_ARC_CQ_CTL,
361 mmPDMA0_QM_CP_SWITCH_WD_SET,
362 mmPDMA0_QM_CP_EXT_SWITCH,
363 mmPDMA0_QM_CP_PRED_0,
364 mmPDMA0_QM_CP_PRED_1,
365 mmPDMA0_QM_CP_PRED_2,
366 mmPDMA0_QM_CP_PRED_3,
367 mmPDMA0_QM_CP_PRED_4,
368 mmPDMA0_QM_CP_PRED_UPEN_0,
369 mmPDMA0_QM_CP_PRED_UPEN_1,
370 mmPDMA0_QM_CP_PRED_UPEN_2,
371 mmPDMA0_QM_CP_PRED_UPEN_3,
372 mmPDMA0_QM_CP_PRED_UPEN_4,
373 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
374 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
375 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
376 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
377 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
378 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
379 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
380 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
381 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
382 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
383 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
384 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
385 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
386 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
387 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
388 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
389 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
390 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
391 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
392 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
393 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
394 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
395 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
396 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
397 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
398 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
399 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
400 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
401 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
402 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
403 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
404 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
405 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
406 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
407 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
408 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
409 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
410 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
411 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
412 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
413 mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
414 mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
415 mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
416 mmPDMA0_QM_CQ_CTL_MSG_BASE_LO
417 };
418
419 static const u32 gaudi2_pb_dcr0_edma0[] = {
420 mmDCORE0_EDMA0_CORE_BASE,
421 mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
422 mmDCORE0_EDMA0_QM_BASE,
423 };
424
425 static const u32 gaudi2_pb_dcr0_edma0_arc[] = {
426 mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
427 };
428
429 static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {
430 {mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},
431 {mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
432 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},
433 {mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
434 {mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,
435 mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
436 {mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,
437 mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
438 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
439 mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
440 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
441 mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
442 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
443 mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
444 };
445
446 static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {
447 mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
448 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,
449 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,
450 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,
451 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,
452 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,
453 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,
454 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,
455 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,
456 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,
457 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,
458 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,
459 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,
460 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,
461 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,
462 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,
463 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,
464 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,
465 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,
466 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,
467 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,
468 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,
469 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,
470 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,
471 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,
472 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,
473 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,
474 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,
475 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,
476 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,
477 mmDCORE0_EDMA0_CORE_CTX_COMMIT,
478 mmDCORE0_EDMA0_CORE_CTX_CTRL,
479 mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,
480 mmDCORE0_EDMA0_CORE_CTX_IDX,
481 mmDCORE0_EDMA0_CORE_CTX_IDX_INC,
482 mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG,
483 mmDCORE0_EDMA0_QM_CQ_CFG0_0,
484 mmDCORE0_EDMA0_QM_CQ_CFG0_1,
485 mmDCORE0_EDMA0_QM_CQ_CFG0_2,
486 mmDCORE0_EDMA0_QM_CQ_CFG0_3,
487 mmDCORE0_EDMA0_QM_CQ_CFG0_4,
488 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,
489 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,
490 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,
491 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,
492 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,
493 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,
494 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,
495 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,
496 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,
497 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,
498 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,
499 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,
500 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,
501 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,
502 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,
503 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,
504 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,
505 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,
506 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,
507 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,
508 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,
509 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,
510 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,
511 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,
512 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,
513 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,
514 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,
515 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,
516 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,
517 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,
518 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,
519 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,
520 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,
521 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,
522 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,
523 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,
524 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,
525 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,
526 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,
527 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,
528 mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,
529 mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,
530 mmDCORE0_EDMA0_QM_CQ_TSIZE_0,
531 mmDCORE0_EDMA0_QM_CQ_CTL_0,
532 mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,
533 mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,
534 mmDCORE0_EDMA0_QM_CQ_TSIZE_1,
535 mmDCORE0_EDMA0_QM_CQ_CTL_1,
536 mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,
537 mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,
538 mmDCORE0_EDMA0_QM_CQ_TSIZE_2,
539 mmDCORE0_EDMA0_QM_CQ_CTL_2,
540 mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,
541 mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,
542 mmDCORE0_EDMA0_QM_CQ_TSIZE_3,
543 mmDCORE0_EDMA0_QM_CQ_CTL_3,
544 mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,
545 mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,
546 mmDCORE0_EDMA0_QM_CQ_TSIZE_4,
547 mmDCORE0_EDMA0_QM_CQ_CTL_4,
548 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
549 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
550 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
551 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
552 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
553 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
554 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
555 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
556 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
557 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
558 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
559 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
560 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
561 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
562 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
563 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
564 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
565 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
566 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
567 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
568 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
569 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
570 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
571 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
572 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
573 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
574 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
575 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
576 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
577 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
578 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
579 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
580 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,
581 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,
582 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,
583 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,
584 mmDCORE0_EDMA0_QM_ARB_CFG_0,
585 mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,
586 mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,
587 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,
588 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,
589 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,
590 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,
591 mmDCORE0_EDMA0_QM_ARB_BASE_LO,
592 mmDCORE0_EDMA0_QM_ARB_BASE_HI,
593 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,
594 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,
595 mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,
596 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
597 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
598 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
599 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
600 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
601 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
602 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
603 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
604 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
605 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
606 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
607 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
608 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
609 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
610 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
611 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
612 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
613 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
614 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
615 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
616 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
617 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
618 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
619 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
620 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
621 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
622 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
623 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
624 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
625 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
626 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
627 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
628 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
629 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
630 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
631 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
632 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
633 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
634 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
635 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
636 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
637 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
638 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
639 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
640 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
641 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
642 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
643 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
644 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
645 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
646 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
647 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
648 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
649 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
650 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
651 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
652 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
653 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
654 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
655 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
656 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
657 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
658 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
659 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
660 mmDCORE0_EDMA0_QM_ARB_SLV_ID,
661 mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
662 mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,
663 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,
664 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,
665 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,
666 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,
667 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,
668 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,
669 mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,
670 mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,
671 mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,
672 mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,
673 mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,
674 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,
675 mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,
676 mmDCORE0_EDMA0_QM_ARC_CQ_CTL,
677 mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,
678 mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,
679 mmDCORE0_EDMA0_QM_CP_PRED_0,
680 mmDCORE0_EDMA0_QM_CP_PRED_1,
681 mmDCORE0_EDMA0_QM_CP_PRED_2,
682 mmDCORE0_EDMA0_QM_CP_PRED_3,
683 mmDCORE0_EDMA0_QM_CP_PRED_4,
684 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,
685 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,
686 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,
687 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,
688 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,
689 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
690 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
691 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
692 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
693 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
694 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
695 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
696 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
697 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
698 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
699 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
700 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
701 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
702 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
703 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
704 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
705 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
706 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
707 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
708 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
709 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
710 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
711 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
712 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
713 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
714 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
715 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
716 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
717 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
718 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
719 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
720 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
721 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
722 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
723 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
724 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
725 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
726 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
727 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
728 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
729 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
730 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
731 mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
732 mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO
733 };
734
735 static const u32 gaudi2_pb_dcr0_mme_sbte[] = {
736 mmDCORE0_MME_SBTE0_BASE,
737 mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,
738 };
739
740 static const u32 gaudi2_pb_dcr0_mme_qm[] = {
741 mmDCORE0_MME_QM_BASE,
742 };
743
744 static const u32 gaudi2_pb_dcr0_mme_eng[] = {
745 mmDCORE0_MME_ACC_BASE,
746 mmDCORE0_MME_CTRL_HI_BASE,
747 mmDCORE0_MME_CTRL_LO_BASE,
748 mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,
749 mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,
750 mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,
751 };
752
753 static const u32 gaudi2_pb_dcr0_mme_arc[] = {
754 mmDCORE0_MME_QM_ARC_AUX_BASE,
755 mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,
756 };
757
758 static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {
759 {mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},
760 {mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},
761 {mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},
762 {mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
763 {mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
764 {mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
765 {mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
766 mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
767 {mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
768 mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
769 {mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
770 mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
771 {mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,
772 mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},
773 {mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,
774 mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},
775 };
776
777 static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {
778 mmDCORE0_MME_QM_CQ_CFG0_0,
779 mmDCORE0_MME_QM_CQ_CFG0_1,
780 mmDCORE0_MME_QM_CQ_CFG0_2,
781 mmDCORE0_MME_QM_CQ_CFG0_3,
782 mmDCORE0_MME_QM_CQ_CFG0_4,
783 mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,
784 mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,
785 mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,
786 mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,
787 mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,
788 mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,
789 mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,
790 mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,
791 mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,
792 mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,
793 mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,
794 mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,
795 mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,
796 mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,
797 mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,
798 mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,
799 mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,
800 mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,
801 mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,
802 mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,
803 mmDCORE0_MME_QM_CP_FENCE0_CNT_0,
804 mmDCORE0_MME_QM_CP_FENCE0_CNT_1,
805 mmDCORE0_MME_QM_CP_FENCE0_CNT_2,
806 mmDCORE0_MME_QM_CP_FENCE0_CNT_3,
807 mmDCORE0_MME_QM_CP_FENCE0_CNT_4,
808 mmDCORE0_MME_QM_CP_FENCE1_CNT_0,
809 mmDCORE0_MME_QM_CP_FENCE1_CNT_1,
810 mmDCORE0_MME_QM_CP_FENCE1_CNT_2,
811 mmDCORE0_MME_QM_CP_FENCE1_CNT_3,
812 mmDCORE0_MME_QM_CP_FENCE1_CNT_4,
813 mmDCORE0_MME_QM_CP_FENCE2_CNT_0,
814 mmDCORE0_MME_QM_CP_FENCE2_CNT_1,
815 mmDCORE0_MME_QM_CP_FENCE2_CNT_2,
816 mmDCORE0_MME_QM_CP_FENCE2_CNT_3,
817 mmDCORE0_MME_QM_CP_FENCE2_CNT_4,
818 mmDCORE0_MME_QM_CP_FENCE3_CNT_0,
819 mmDCORE0_MME_QM_CP_FENCE3_CNT_1,
820 mmDCORE0_MME_QM_CP_FENCE3_CNT_2,
821 mmDCORE0_MME_QM_CP_FENCE3_CNT_3,
822 mmDCORE0_MME_QM_CP_FENCE3_CNT_4,
823 mmDCORE0_MME_QM_CQ_PTR_LO_0,
824 mmDCORE0_MME_QM_CQ_PTR_HI_0,
825 mmDCORE0_MME_QM_CQ_TSIZE_0,
826 mmDCORE0_MME_QM_CQ_CTL_0,
827 mmDCORE0_MME_QM_CQ_PTR_LO_1,
828 mmDCORE0_MME_QM_CQ_PTR_HI_1,
829 mmDCORE0_MME_QM_CQ_TSIZE_1,
830 mmDCORE0_MME_QM_CQ_CTL_1,
831 mmDCORE0_MME_QM_CQ_PTR_LO_2,
832 mmDCORE0_MME_QM_CQ_PTR_HI_2,
833 mmDCORE0_MME_QM_CQ_TSIZE_2,
834 mmDCORE0_MME_QM_CQ_CTL_2,
835 mmDCORE0_MME_QM_CQ_PTR_LO_3,
836 mmDCORE0_MME_QM_CQ_PTR_HI_3,
837 mmDCORE0_MME_QM_CQ_TSIZE_3,
838 mmDCORE0_MME_QM_CQ_CTL_3,
839 mmDCORE0_MME_QM_CQ_PTR_LO_4,
840 mmDCORE0_MME_QM_CQ_PTR_HI_4,
841 mmDCORE0_MME_QM_CQ_TSIZE_4,
842 mmDCORE0_MME_QM_CQ_CTL_4,
843 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,
844 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
845 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,
846 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
847 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,
848 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
849 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,
850 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
851 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,
852 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
853 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,
854 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
855 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,
856 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
857 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,
858 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
859 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,
860 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
861 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,
862 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
863 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,
864 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
865 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,
866 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
867 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,
868 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
869 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,
870 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
871 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,
872 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
873 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,
874 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
875 mmDCORE0_MME_QM_ARC_CQ_PTR_LO,
876 mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,
877 mmDCORE0_MME_QM_ARC_CQ_PTR_HI,
878 mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,
879 mmDCORE0_MME_QM_ARB_CFG_0,
880 mmDCORE0_MME_QM_ARB_MST_QUIET_PER,
881 mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,
882 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,
883 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,
884 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,
885 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,
886 mmDCORE0_MME_QM_ARB_BASE_LO,
887 mmDCORE0_MME_QM_ARB_BASE_HI,
888 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,
889 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,
890 mmDCORE0_MME_QM_ARB_MST_CRED_INC,
891 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,
892 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,
893 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,
894 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,
895 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,
896 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,
897 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,
898 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,
899 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,
900 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,
901 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,
902 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,
903 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,
904 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,
905 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,
906 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,
907 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,
908 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,
909 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,
910 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,
911 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,
912 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,
913 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,
914 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,
915 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,
916 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,
917 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,
918 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,
919 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,
920 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,
921 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,
922 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,
923 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,
924 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,
925 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,
926 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,
927 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,
928 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,
929 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,
930 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,
931 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,
932 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,
933 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,
934 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,
935 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,
936 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,
937 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,
938 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,
939 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,
940 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,
941 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,
942 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,
943 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,
944 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,
945 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,
946 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,
947 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,
948 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,
949 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,
950 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,
951 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,
952 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,
953 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,
954 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,
955 mmDCORE0_MME_QM_ARB_SLV_ID,
956 mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,
957 mmDCORE0_MME_QM_ARC_CQ_CFG0,
958 mmDCORE0_MME_QM_CQ_IFIFO_CI_0,
959 mmDCORE0_MME_QM_CQ_IFIFO_CI_1,
960 mmDCORE0_MME_QM_CQ_IFIFO_CI_2,
961 mmDCORE0_MME_QM_CQ_IFIFO_CI_3,
962 mmDCORE0_MME_QM_CQ_IFIFO_CI_4,
963 mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,
964 mmDCORE0_MME_QM_CQ_CTL_CI_0,
965 mmDCORE0_MME_QM_CQ_CTL_CI_1,
966 mmDCORE0_MME_QM_CQ_CTL_CI_2,
967 mmDCORE0_MME_QM_CQ_CTL_CI_3,
968 mmDCORE0_MME_QM_CQ_CTL_CI_4,
969 mmDCORE0_MME_QM_ARC_CQ_CTL_CI,
970 mmDCORE0_MME_QM_ARC_CQ_TSIZE,
971 mmDCORE0_MME_QM_ARC_CQ_CTL,
972 mmDCORE0_MME_QM_CP_SWITCH_WD_SET,
973 mmDCORE0_MME_QM_CP_EXT_SWITCH,
974 mmDCORE0_MME_QM_CP_PRED_0,
975 mmDCORE0_MME_QM_CP_PRED_1,
976 mmDCORE0_MME_QM_CP_PRED_2,
977 mmDCORE0_MME_QM_CP_PRED_3,
978 mmDCORE0_MME_QM_CP_PRED_4,
979 mmDCORE0_MME_QM_CP_PRED_UPEN_0,
980 mmDCORE0_MME_QM_CP_PRED_UPEN_1,
981 mmDCORE0_MME_QM_CP_PRED_UPEN_2,
982 mmDCORE0_MME_QM_CP_PRED_UPEN_3,
983 mmDCORE0_MME_QM_CP_PRED_UPEN_4,
984 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,
985 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,
986 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,
987 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,
988 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,
989 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,
990 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,
991 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,
992 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,
993 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,
994 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,
995 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,
996 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,
997 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,
998 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,
999 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,
1000 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,
1001 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,
1002 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,
1003 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,
1004 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,
1005 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,
1006 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,
1007 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,
1008 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,
1009 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,
1010 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,
1011 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,
1012 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,
1013 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,
1014 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,
1015 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,
1016 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,
1017 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,
1018 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,
1019 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,
1020 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,
1021 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,
1022 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,
1023 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,
1024 mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1025 mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,
1026 mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,
1027 mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO
1028 };
1029
1030 static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {
1031 mmDCORE0_MME_CTRL_LO_CMD,
1032 mmDCORE0_MME_CTRL_LO_AGU,
1033 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,
1034 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,
1035 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,
1036 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,
1037 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,
1038 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,
1039 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,
1040 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,
1041 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,
1042 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,
1043 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,
1044 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,
1045 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,
1046 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,
1047 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,
1048 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,
1049 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,
1050 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,
1051 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,
1052 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,
1053 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,
1054 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,
1055 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,
1056 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,
1057 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,
1058 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,
1059 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,
1060 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,
1061 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,
1062 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,
1063 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,
1064 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,
1065 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,
1066 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,
1067 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,
1068 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,
1069 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,
1070 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,
1071 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,
1072 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,
1073 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,
1074 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,
1075 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,
1076 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,
1077 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,
1078 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,
1079 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,
1080 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,
1081 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,
1082 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,
1083 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,
1084 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,
1085 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,
1086 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,
1087 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,
1088 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,
1089 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,
1090 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,
1091 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,
1092 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,
1093 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,
1094 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,
1095 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,
1096 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,
1097 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,
1098 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,
1099 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,
1100 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,
1101 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,
1102 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,
1103 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,
1104 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,
1105 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,
1106 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,
1107 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,
1108 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,
1109 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,
1110 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,
1111 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,
1112 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,
1113 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,
1114 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,
1115 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,
1116 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,
1117 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,
1118 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,
1119 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,
1120 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,
1121 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,
1122 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,
1123 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,
1124 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,
1125 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,
1126 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,
1127 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,
1128 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,
1129 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,
1130 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,
1131 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,
1132 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,
1133 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,
1134 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,
1135 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,
1136 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,
1137 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,
1138 mmDCORE0_MME_CTRL_LO_ARCH_STATUS,
1139 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,
1140 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,
1141 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,
1142 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,
1143 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,
1144 mmDCORE0_MME_CTRL_LO_ARCH_A_SS,
1145 mmDCORE0_MME_CTRL_LO_ARCH_B_SS,
1146 mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,
1147 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,
1148 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,
1149 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,
1150 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,
1151 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,
1152 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,
1153 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,
1154 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,
1155 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,
1156 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,
1157 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,
1158 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,
1159 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,
1160 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,
1161 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,
1162 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,
1163 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,
1164 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,
1165 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,
1166 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,
1167 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,
1168 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,
1169 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,
1170 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,
1171 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,
1172 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,
1173 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,
1174 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,
1175 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,
1176 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,
1177 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,
1178 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,
1179 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,
1180 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,
1181 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,
1182 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,
1183 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,
1184 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,
1185 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,
1186 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,
1187 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,
1188 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,
1189 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,
1190 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,
1191 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,
1192 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,
1193 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,
1194 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,
1195 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,
1196 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,
1197 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,
1198 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,
1199 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,
1200 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,
1201 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,
1202 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,
1203 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,
1204 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,
1205 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,
1206 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,
1207 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,
1208 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,
1209 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,
1210 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,
1211 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,
1212 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,
1213 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,
1214 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,
1215 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,
1216 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,
1217 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,
1218 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,
1219 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,
1220 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,
1221 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,
1222 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,
1223 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,
1224 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,
1225 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,
1226 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,
1227 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,
1228 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,
1229 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,
1230 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,
1231 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,
1232 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,
1233 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,
1234 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,
1235 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,
1236 mmDCORE0_MME_ACC_AP_LFSR_POLY,
1237 mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,
1238 mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,
1239 mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,
1240 mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,
1241 mmDCORE0_MME_ACC_WBC_SRC_BP,
1242 };
1243
1244 static const u32 gaudi2_pb_dcr0_tpc0[] = {
1245 mmDCORE0_TPC0_QM_BASE,
1246 mmDCORE0_TPC0_CFG_BASE,
1247 mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,
1248 };
1249
1250 static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {
1251 mmDCORE0_TPC0_QM_ARC_AUX_BASE,
1252 };
1253
1254 static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {
1255 {mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},
1256 {mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},
1257 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},
1258 {mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
1259 {mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
1260 {mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
1261 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
1262 mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
1263 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
1264 mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
1265 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
1266 mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
1267 };
1268
1269 static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {
1270 mmDCORE0_TPC0_QM_CQ_CFG0_0,
1271 mmDCORE0_TPC0_QM_CQ_CFG0_1,
1272 mmDCORE0_TPC0_QM_CQ_CFG0_2,
1273 mmDCORE0_TPC0_QM_CQ_CFG0_3,
1274 mmDCORE0_TPC0_QM_CQ_CFG0_4,
1275 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,
1276 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,
1277 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,
1278 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,
1279 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,
1280 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,
1281 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,
1282 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,
1283 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,
1284 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,
1285 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,
1286 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,
1287 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,
1288 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,
1289 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,
1290 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,
1291 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,
1292 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,
1293 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,
1294 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,
1295 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,
1296 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,
1297 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,
1298 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,
1299 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,
1300 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,
1301 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,
1302 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,
1303 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,
1304 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,
1305 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,
1306 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,
1307 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,
1308 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,
1309 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,
1310 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,
1311 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,
1312 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,
1313 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,
1314 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,
1315 mmDCORE0_TPC0_QM_CQ_PTR_LO_0,
1316 mmDCORE0_TPC0_QM_CQ_PTR_HI_0,
1317 mmDCORE0_TPC0_QM_CQ_TSIZE_0,
1318 mmDCORE0_TPC0_QM_CQ_CTL_0,
1319 mmDCORE0_TPC0_QM_CQ_PTR_LO_1,
1320 mmDCORE0_TPC0_QM_CQ_PTR_HI_1,
1321 mmDCORE0_TPC0_QM_CQ_TSIZE_1,
1322 mmDCORE0_TPC0_QM_CQ_CTL_1,
1323 mmDCORE0_TPC0_QM_CQ_PTR_LO_2,
1324 mmDCORE0_TPC0_QM_CQ_PTR_HI_2,
1325 mmDCORE0_TPC0_QM_CQ_TSIZE_2,
1326 mmDCORE0_TPC0_QM_CQ_CTL_2,
1327 mmDCORE0_TPC0_QM_CQ_PTR_LO_3,
1328 mmDCORE0_TPC0_QM_CQ_PTR_HI_3,
1329 mmDCORE0_TPC0_QM_CQ_TSIZE_3,
1330 mmDCORE0_TPC0_QM_CQ_CTL_3,
1331 mmDCORE0_TPC0_QM_CQ_PTR_LO_4,
1332 mmDCORE0_TPC0_QM_CQ_PTR_HI_4,
1333 mmDCORE0_TPC0_QM_CQ_TSIZE_4,
1334 mmDCORE0_TPC0_QM_CQ_CTL_4,
1335 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,
1336 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
1337 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,
1338 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
1339 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,
1340 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
1341 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,
1342 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
1343 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,
1344 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
1345 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,
1346 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
1347 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,
1348 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
1349 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,
1350 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
1351 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,
1352 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
1353 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,
1354 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
1355 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,
1356 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
1357 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,
1358 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
1359 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,
1360 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
1361 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,
1362 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
1363 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,
1364 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
1365 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,
1366 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
1367 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,
1368 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,
1369 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,
1370 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,
1371 mmDCORE0_TPC0_QM_ARB_CFG_0,
1372 mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,
1373 mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,
1374 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,
1375 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,
1376 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,
1377 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,
1378 mmDCORE0_TPC0_QM_ARB_BASE_LO,
1379 mmDCORE0_TPC0_QM_ARB_BASE_HI,
1380 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,
1381 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,
1382 mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,
1383 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
1384 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
1385 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
1386 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
1387 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
1388 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
1389 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
1390 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
1391 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
1392 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
1393 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
1394 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
1395 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
1396 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
1397 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
1398 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
1399 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
1400 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
1401 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
1402 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
1403 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
1404 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
1405 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
1406 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
1407 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
1408 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
1409 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
1410 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
1411 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
1412 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
1413 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
1414 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
1415 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
1416 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
1417 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
1418 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
1419 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
1420 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
1421 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
1422 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
1423 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
1424 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
1425 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
1426 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
1427 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
1428 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
1429 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
1430 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
1431 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
1432 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
1433 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
1434 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
1435 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
1436 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
1437 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
1438 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
1439 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
1440 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
1441 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
1442 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
1443 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
1444 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
1445 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
1446 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
1447 mmDCORE0_TPC0_QM_ARB_SLV_ID,
1448 mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
1449 mmDCORE0_TPC0_QM_ARC_CQ_CFG0,
1450 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,
1451 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,
1452 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,
1453 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,
1454 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,
1455 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,
1456 mmDCORE0_TPC0_QM_CQ_CTL_CI_0,
1457 mmDCORE0_TPC0_QM_CQ_CTL_CI_1,
1458 mmDCORE0_TPC0_QM_CQ_CTL_CI_2,
1459 mmDCORE0_TPC0_QM_CQ_CTL_CI_3,
1460 mmDCORE0_TPC0_QM_CQ_CTL_CI_4,
1461 mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,
1462 mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,
1463 mmDCORE0_TPC0_QM_ARC_CQ_CTL,
1464 mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,
1465 mmDCORE0_TPC0_QM_CP_EXT_SWITCH,
1466 mmDCORE0_TPC0_QM_CP_PRED_0,
1467 mmDCORE0_TPC0_QM_CP_PRED_1,
1468 mmDCORE0_TPC0_QM_CP_PRED_2,
1469 mmDCORE0_TPC0_QM_CP_PRED_3,
1470 mmDCORE0_TPC0_QM_CP_PRED_4,
1471 mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,
1472 mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,
1473 mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,
1474 mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,
1475 mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,
1476 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,
1477 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,
1478 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,
1479 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,
1480 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,
1481 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,
1482 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,
1483 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,
1484 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,
1485 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,
1486 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,
1487 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,
1488 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,
1489 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,
1490 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,
1491 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,
1492 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,
1493 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,
1494 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,
1495 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,
1496 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,
1497 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,
1498 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,
1499 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,
1500 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,
1501 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,
1502 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,
1503 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,
1504 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,
1505 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,
1506 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,
1507 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,
1508 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,
1509 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,
1510 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,
1511 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,
1512 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,
1513 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,
1514 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,
1515 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,
1516 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1517 mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,
1518 mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,
1519 mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,
1520 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,
1521 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,
1522 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,
1523 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,
1524 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,
1525 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,
1526 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,
1527 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,
1528 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,
1529 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,
1530 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,
1531 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,
1532 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,
1533 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,
1534 mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,
1535 mmDCORE0_TPC0_CFG_QM_KERNEL_ID,
1536 mmDCORE0_TPC0_CFG_QM_POWER_LOOP,
1537 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0,
1538 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1,
1539 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2,
1540 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3,
1541 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,
1542 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,
1543 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,
1544 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,
1545 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,
1546 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,
1547 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,
1548 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,
1549 mmDCORE0_TPC0_CFG_FP8_143_BIAS,
1550 mmDCORE0_TPC0_CFG_ROUND_CSR,
1551 mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,
1552 mmDCORE0_TPC0_CFG_SEMAPHORE,
1553 mmDCORE0_TPC0_CFG_LFSR_POLYNOM,
1554 mmDCORE0_TPC0_CFG_STATUS,
1555 mmDCORE0_TPC0_CFG_TPC_CMD,
1556 mmDCORE0_TPC0_CFG_TPC_EXECUTE,
1557 mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,
1558 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,
1559 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,
1560 mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,
1561 mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,
1562 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,
1563 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,
1564 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,
1565 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,
1566 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,
1567 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,
1568 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,
1569 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,
1570 mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG,
1571 mmDCORE0_TPC0_CFG_KERNEL_SRF_0,
1572 mmDCORE0_TPC0_CFG_KERNEL_SRF_1,
1573 mmDCORE0_TPC0_CFG_KERNEL_SRF_2,
1574 mmDCORE0_TPC0_CFG_KERNEL_SRF_3,
1575 mmDCORE0_TPC0_CFG_KERNEL_SRF_4,
1576 mmDCORE0_TPC0_CFG_KERNEL_SRF_5,
1577 mmDCORE0_TPC0_CFG_KERNEL_SRF_6,
1578 mmDCORE0_TPC0_CFG_KERNEL_SRF_7,
1579 mmDCORE0_TPC0_CFG_KERNEL_SRF_8,
1580 mmDCORE0_TPC0_CFG_KERNEL_SRF_9,
1581 mmDCORE0_TPC0_CFG_KERNEL_SRF_10,
1582 mmDCORE0_TPC0_CFG_KERNEL_SRF_11,
1583 mmDCORE0_TPC0_CFG_KERNEL_SRF_12,
1584 mmDCORE0_TPC0_CFG_KERNEL_SRF_13,
1585 mmDCORE0_TPC0_CFG_KERNEL_SRF_14,
1586 mmDCORE0_TPC0_CFG_KERNEL_SRF_15,
1587 mmDCORE0_TPC0_CFG_KERNEL_SRF_16,
1588 mmDCORE0_TPC0_CFG_KERNEL_SRF_17,
1589 mmDCORE0_TPC0_CFG_KERNEL_SRF_18,
1590 mmDCORE0_TPC0_CFG_KERNEL_SRF_19,
1591 mmDCORE0_TPC0_CFG_KERNEL_SRF_20,
1592 mmDCORE0_TPC0_CFG_KERNEL_SRF_21,
1593 mmDCORE0_TPC0_CFG_KERNEL_SRF_22,
1594 mmDCORE0_TPC0_CFG_KERNEL_SRF_23,
1595 mmDCORE0_TPC0_CFG_KERNEL_SRF_24,
1596 mmDCORE0_TPC0_CFG_KERNEL_SRF_25,
1597 mmDCORE0_TPC0_CFG_KERNEL_SRF_26,
1598 mmDCORE0_TPC0_CFG_KERNEL_SRF_27,
1599 mmDCORE0_TPC0_CFG_KERNEL_SRF_28,
1600 mmDCORE0_TPC0_CFG_KERNEL_SRF_29,
1601 mmDCORE0_TPC0_CFG_KERNEL_SRF_30,
1602 mmDCORE0_TPC0_CFG_KERNEL_SRF_31,
1603 mmDCORE0_TPC0_CFG_TPC_SB_L0CD,
1604 mmDCORE0_TPC0_CFG_TPC_ID,
1605 mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,
1606 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,
1607 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,
1608 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,
1609 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,
1610 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,
1611 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,
1612 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,
1613 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,
1614 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3
1615 };
1616
1617 static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {
1618 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,
1619 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,
1620 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,
1621 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,
1622 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,
1623 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,
1624 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,
1625 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,
1626 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,
1627 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,
1628 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,
1629 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,
1630 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,
1631 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,
1632 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,
1633 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1634 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1635 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1636 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1637 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1638 };
1639
1640 static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = {
1641 mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW,
1642 mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH,
1643 mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE,
1644 mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG,
1645 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE,
1646 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE,
1647 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE,
1648 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE,
1649 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE,
1650 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE,
1651 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE,
1652 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE,
1653 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE,
1654 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE,
1655 mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE,
1656 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1657 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1658 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1659 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1660 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1661 };
1662
1663 static const u32 gaudi2_pb_dcr0_sram0[] = {
1664 mmDCORE0_SRAM0_BANK_BASE,
1665 mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE,
1666 mmDCORE0_SRAM0_RTR_BASE,
1667 };
1668
1669 static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = {
1670 mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE,
1671 };
1672
1673 static const u32 gaudi2_pb_dcr0_sm_glbl[] = {
1674 mmDCORE0_SYNC_MNGR_GLBL_BASE,
1675 };
1676
1677 static const u32 gaudi2_pb_dcr1_sm_glbl[] = {
1678 mmDCORE1_SYNC_MNGR_GLBL_BASE,
1679 };
1680
1681 static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {
1682 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1683 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1684 {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1685 {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
1686 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1687 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1688 {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
1689 {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1690 };
1691
1692 static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {
1693 {mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1694 {mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1695 {mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1696 {mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63},
1697 {mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1698 {mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1699 {mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63},
1700 {mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1701 };
1702
1703 static const u32 gaudi2_pb_arc_sched[] = {
1704 mmARC_FARM_ARC0_AUX_BASE,
1705 mmARC_FARM_ARC0_DUP_ENG_BASE,
1706 mmARC_FARM_ARC0_ACP_ENG_BASE,
1707 };
1708
1709 static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = {
1710 {mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK},
1711 {mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT},
1712 {mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7},
1713 {mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT},
1714 {mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN},
1715 {mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN},
1716 {mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG},
1717 {mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI},
1718 {mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN},
1719 {mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63},
1720 {mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD},
1721 {mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG},
1722 };
1723
1724 static const u32 gaudi2_pb_xbar_mid[] = {
1725 mmXBAR_MID_0_BASE,
1726 };
1727
1728 static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = {
1729 mmXBAR_MID_0_UPSCALE,
1730 mmXBAR_MID_0_DOWN_CONV,
1731 mmXBAR_MID_0_DOWN_CONV_LFSR_EN,
1732 mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD,
1733 mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE,
1734 mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY,
1735 };
1736
1737 static const u32 gaudi2_pb_xbar_edge[] = {
1738 mmXBAR_EDGE_0_BASE,
1739 };
1740
1741 static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = {
1742 mmXBAR_EDGE_0_UPSCALE,
1743 mmXBAR_EDGE_0_DOWN_CONV,
1744 mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN,
1745 mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD,
1746 mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE,
1747 mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY,
1748 };
1749
1750 static const u32 gaudi2_pb_nic0[] = {
1751 mmNIC0_TMR_BASE,
1752 mmNIC0_RXB_CORE_BASE,
1753 mmNIC0_RXE0_BASE,
1754 mmNIC0_RXE1_BASE,
1755 mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE,
1756 mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE,
1757 mmNIC0_TXS0_BASE,
1758 mmNIC0_TXS1_BASE,
1759 mmNIC0_TXE0_BASE,
1760 mmNIC0_TXE1_BASE,
1761 mmNIC0_TXB_BASE,
1762 mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE,
1763 };
1764
1765 static const u32 gaudi2_pb_nic0_qm_qpc[] = {
1766 mmNIC0_QM0_BASE,
1767 mmNIC0_QPC0_BASE,
1768 };
1769
1770 static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = {
1771 mmNIC0_QM_ARC_AUX0_BASE,
1772 };
1773
1774 static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = {
1775 {mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK},
1776 {mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT},
1777 {mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7},
1778 {mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT},
1779 {mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN},
1780 {mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN},
1781 {mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG},
1782 {mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI},
1783 {mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN},
1784 };
1785
1786 static const u32 gaudi2_pb_nic0_umr[] = {
1787 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE,
1788 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1789 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1790 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1791 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1792 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1793 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1794 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1795 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1796 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1797 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1798 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1799 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1800 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1801 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1802 };
1803
1804 static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = {
1805 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32,
1806 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX},
1807 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1808 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1},
1809 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1810 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2},
1811 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1812 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3},
1813 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1814 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4},
1815 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1816 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5},
1817 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1818 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6},
1819 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1820 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7},
1821 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1822 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8},
1823 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1824 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9},
1825 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1826 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10},
1827 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1828 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11},
1829 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1830 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12},
1831 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1832 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13},
1833 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1834 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14},
1835 };
1836
1837 /*
1838 * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit
1839 * registers and since the user writes in bulks of 64 bits we need to un-secure
1840 * also the following 32 bits (that's why we added also the next 4 bytes to the
1841 * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes
1842 * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be
1843 * unsecured as well.
1844 */
1845 #define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4)
1846 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4)
1847 #define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF60
1848
1849 static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = {
1850 mmNIC0_QPC0_LINEAR_WQE_STATIC_0,
1851 mmNIC0_QPC0_LINEAR_WQE_STATIC_1,
1852 mmNIC0_QPC0_LINEAR_WQE_STATIC_2,
1853 mmNIC0_QPC0_LINEAR_WQE_STATIC_3,
1854 mmNIC0_QPC0_LINEAR_WQE_STATIC_4,
1855 mmNIC0_QPC0_LINEAR_WQE_STATIC_5,
1856 mmNIC0_QPC0_LINEAR_WQE_STATIC_6,
1857 mmNIC0_QPC0_LINEAR_WQE_STATIC_7,
1858 mmNIC0_QPC0_LINEAR_WQE_STATIC_8,
1859 mmNIC0_QPC0_LINEAR_WQE_STATIC_9,
1860 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0,
1861 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1,
1862 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2,
1863 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3,
1864 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4,
1865 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5,
1866 mmNIC0_QPC0_LINEAR_WQE_QPN,
1867 mmNIC0_QPC0_LINEAR_WQE_RSV,
1868 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0,
1869 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1,
1870 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2,
1871 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3,
1872 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4,
1873 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5,
1874 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6,
1875 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7,
1876 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8,
1877 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9,
1878 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10,
1879 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11,
1880 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12,
1881 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13,
1882 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14,
1883 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15,
1884 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16,
1885 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17,
1886 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0,
1887 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1,
1888 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2,
1889 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3,
1890 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4,
1891 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5,
1892 mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN,
1893 mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV,
1894 mmNIC0_QPC0_QMAN_DOORBELL,
1895 mmNIC0_QPC0_QMAN_DOORBELL_QPN,
1896 mmNIC0_QPC0_SPECIAL_GLBL_SPARE,
1897 mmNIC0_QM0_CQ_CFG0_0,
1898 mmNIC0_QM0_CQ_CFG0_1,
1899 mmNIC0_QM0_CQ_CFG0_2,
1900 mmNIC0_QM0_CQ_CFG0_3,
1901 mmNIC0_QM0_CQ_CFG0_4,
1902 mmNIC0_QM0_CP_FENCE0_RDATA_0,
1903 mmNIC0_QM0_CP_FENCE0_RDATA_1,
1904 mmNIC0_QM0_CP_FENCE0_RDATA_2,
1905 mmNIC0_QM0_CP_FENCE0_RDATA_3,
1906 mmNIC0_QM0_CP_FENCE0_RDATA_4,
1907 mmNIC0_QM0_CP_FENCE1_RDATA_0,
1908 mmNIC0_QM0_CP_FENCE1_RDATA_1,
1909 mmNIC0_QM0_CP_FENCE1_RDATA_2,
1910 mmNIC0_QM0_CP_FENCE1_RDATA_3,
1911 mmNIC0_QM0_CP_FENCE1_RDATA_4,
1912 mmNIC0_QM0_CP_FENCE2_RDATA_0,
1913 mmNIC0_QM0_CP_FENCE2_RDATA_1,
1914 mmNIC0_QM0_CP_FENCE2_RDATA_2,
1915 mmNIC0_QM0_CP_FENCE2_RDATA_3,
1916 mmNIC0_QM0_CP_FENCE2_RDATA_4,
1917 mmNIC0_QM0_CP_FENCE3_RDATA_0,
1918 mmNIC0_QM0_CP_FENCE3_RDATA_1,
1919 mmNIC0_QM0_CP_FENCE3_RDATA_2,
1920 mmNIC0_QM0_CP_FENCE3_RDATA_3,
1921 mmNIC0_QM0_CP_FENCE3_RDATA_4,
1922 mmNIC0_QM0_CP_FENCE0_CNT_0,
1923 mmNIC0_QM0_CP_FENCE0_CNT_1,
1924 mmNIC0_QM0_CP_FENCE0_CNT_2,
1925 mmNIC0_QM0_CP_FENCE0_CNT_3,
1926 mmNIC0_QM0_CP_FENCE0_CNT_4,
1927 mmNIC0_QM0_CP_FENCE1_CNT_0,
1928 mmNIC0_QM0_CP_FENCE1_CNT_1,
1929 mmNIC0_QM0_CP_FENCE1_CNT_2,
1930 mmNIC0_QM0_CP_FENCE1_CNT_3,
1931 mmNIC0_QM0_CP_FENCE1_CNT_4,
1932 mmNIC0_QM0_CP_FENCE2_CNT_0,
1933 mmNIC0_QM0_CP_FENCE2_CNT_1,
1934 mmNIC0_QM0_CP_FENCE2_CNT_2,
1935 mmNIC0_QM0_CP_FENCE2_CNT_3,
1936 mmNIC0_QM0_CP_FENCE2_CNT_4,
1937 mmNIC0_QM0_CP_FENCE3_CNT_0,
1938 mmNIC0_QM0_CP_FENCE3_CNT_1,
1939 mmNIC0_QM0_CP_FENCE3_CNT_2,
1940 mmNIC0_QM0_CP_FENCE3_CNT_3,
1941 mmNIC0_QM0_CP_FENCE3_CNT_4,
1942 mmNIC0_QM0_CQ_PTR_LO_0,
1943 mmNIC0_QM0_CQ_PTR_HI_0,
1944 mmNIC0_QM0_CQ_TSIZE_0,
1945 mmNIC0_QM0_CQ_CTL_0,
1946 mmNIC0_QM0_CQ_PTR_LO_1,
1947 mmNIC0_QM0_CQ_PTR_HI_1,
1948 mmNIC0_QM0_CQ_TSIZE_1,
1949 mmNIC0_QM0_CQ_CTL_1,
1950 mmNIC0_QM0_CQ_PTR_LO_2,
1951 mmNIC0_QM0_CQ_PTR_HI_2,
1952 mmNIC0_QM0_CQ_TSIZE_2,
1953 mmNIC0_QM0_CQ_CTL_2,
1954 mmNIC0_QM0_CQ_PTR_LO_3,
1955 mmNIC0_QM0_CQ_PTR_HI_3,
1956 mmNIC0_QM0_CQ_TSIZE_3,
1957 mmNIC0_QM0_CQ_CTL_3,
1958 mmNIC0_QM0_CQ_PTR_LO_4,
1959 mmNIC0_QM0_CQ_PTR_HI_4,
1960 mmNIC0_QM0_CQ_TSIZE_4,
1961 mmNIC0_QM0_CQ_CTL_4,
1962 mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE,
1963 mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4,
1964 mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE,
1965 mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4,
1966 mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE,
1967 mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4,
1968 mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE,
1969 mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4,
1970 mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE,
1971 mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4,
1972 mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE,
1973 mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4,
1974 mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE,
1975 mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4,
1976 mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE,
1977 mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4,
1978 mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE,
1979 mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4,
1980 mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE,
1981 mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4,
1982 mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE,
1983 mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4,
1984 mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE,
1985 mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4,
1986 mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE,
1987 mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4,
1988 mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE,
1989 mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4,
1990 mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE,
1991 mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4,
1992 mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE,
1993 mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4,
1994 mmNIC0_QM0_ARC_CQ_PTR_LO,
1995 mmNIC0_QM0_ARC_CQ_PTR_LO_STS,
1996 mmNIC0_QM0_ARC_CQ_PTR_HI,
1997 mmNIC0_QM0_ARC_CQ_PTR_HI_STS,
1998 mmNIC0_QM0_ARB_CFG_0,
1999 mmNIC0_QM0_ARB_MST_QUIET_PER,
2000 mmNIC0_QM0_ARB_CHOICE_Q_PUSH,
2001 mmNIC0_QM0_ARB_WRR_WEIGHT_0,
2002 mmNIC0_QM0_ARB_WRR_WEIGHT_1,
2003 mmNIC0_QM0_ARB_WRR_WEIGHT_2,
2004 mmNIC0_QM0_ARB_WRR_WEIGHT_3,
2005 mmNIC0_QM0_ARB_BASE_LO,
2006 mmNIC0_QM0_ARB_BASE_HI,
2007 mmNIC0_QM0_ARB_MST_SLAVE_EN,
2008 mmNIC0_QM0_ARB_MST_SLAVE_EN_1,
2009 mmNIC0_QM0_ARB_MST_CRED_INC,
2010 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0,
2011 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1,
2012 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2,
2013 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3,
2014 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4,
2015 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5,
2016 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6,
2017 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7,
2018 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8,
2019 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9,
2020 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10,
2021 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11,
2022 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12,
2023 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13,
2024 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14,
2025 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15,
2026 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16,
2027 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17,
2028 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18,
2029 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19,
2030 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20,
2031 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21,
2032 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22,
2033 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23,
2034 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24,
2035 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25,
2036 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26,
2037 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27,
2038 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28,
2039 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29,
2040 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30,
2041 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31,
2042 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32,
2043 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33,
2044 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34,
2045 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35,
2046 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36,
2047 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37,
2048 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38,
2049 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39,
2050 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40,
2051 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41,
2052 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42,
2053 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43,
2054 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44,
2055 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45,
2056 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46,
2057 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47,
2058 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48,
2059 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49,
2060 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50,
2061 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51,
2062 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52,
2063 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53,
2064 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54,
2065 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55,
2066 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56,
2067 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57,
2068 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58,
2069 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59,
2070 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60,
2071 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61,
2072 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62,
2073 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63,
2074 mmNIC0_QM0_ARB_SLV_ID,
2075 mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST,
2076 mmNIC0_QM0_ARC_CQ_CFG0,
2077 mmNIC0_QM0_CQ_IFIFO_CI_0,
2078 mmNIC0_QM0_CQ_IFIFO_CI_1,
2079 mmNIC0_QM0_CQ_IFIFO_CI_2,
2080 mmNIC0_QM0_CQ_IFIFO_CI_3,
2081 mmNIC0_QM0_CQ_IFIFO_CI_4,
2082 mmNIC0_QM0_ARC_CQ_IFIFO_CI,
2083 mmNIC0_QM0_CQ_CTL_CI_0,
2084 mmNIC0_QM0_CQ_CTL_CI_1,
2085 mmNIC0_QM0_CQ_CTL_CI_2,
2086 mmNIC0_QM0_CQ_CTL_CI_3,
2087 mmNIC0_QM0_CQ_CTL_CI_4,
2088 mmNIC0_QM0_ARC_CQ_CTL_CI,
2089 mmNIC0_QM0_ARC_CQ_TSIZE,
2090 mmNIC0_QM0_ARC_CQ_CTL,
2091 mmNIC0_QM0_CP_SWITCH_WD_SET,
2092 mmNIC0_QM0_CP_EXT_SWITCH,
2093 mmNIC0_QM0_CP_PRED_0,
2094 mmNIC0_QM0_CP_PRED_1,
2095 mmNIC0_QM0_CP_PRED_2,
2096 mmNIC0_QM0_CP_PRED_3,
2097 mmNIC0_QM0_CP_PRED_4,
2098 mmNIC0_QM0_CP_PRED_UPEN_0,
2099 mmNIC0_QM0_CP_PRED_UPEN_1,
2100 mmNIC0_QM0_CP_PRED_UPEN_2,
2101 mmNIC0_QM0_CP_PRED_UPEN_3,
2102 mmNIC0_QM0_CP_PRED_UPEN_4,
2103 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0,
2104 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1,
2105 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2,
2106 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3,
2107 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4,
2108 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0,
2109 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1,
2110 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2,
2111 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3,
2112 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4,
2113 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0,
2114 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1,
2115 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2,
2116 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3,
2117 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4,
2118 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0,
2119 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1,
2120 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2,
2121 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3,
2122 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4,
2123 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0,
2124 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1,
2125 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2,
2126 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3,
2127 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4,
2128 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0,
2129 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1,
2130 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2,
2131 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3,
2132 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4,
2133 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0,
2134 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1,
2135 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2,
2136 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3,
2137 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4,
2138 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0,
2139 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1,
2140 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2,
2141 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3,
2142 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4,
2143 mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO,
2144 mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO,
2145 mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO,
2146 mmNIC0_QM0_CQ_CTL_MSG_BASE_LO
2147 };
2148
2149 static const u32 gaudi2_pb_rot0[] = {
2150 mmROT0_BASE,
2151 mmROT0_MSTR_IF_RR_SHRD_HBW_BASE,
2152 mmROT0_QM_BASE,
2153 };
2154
2155 static const u32 gaudi2_pb_rot0_arc[] = {
2156 mmROT0_QM_ARC_AUX_BASE
2157 };
2158
2159 static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = {
2160 {mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK},
2161 {mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT},
2162 {mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7},
2163 {mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
2164 {mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
2165 {mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
2166 {mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
2167 {mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
2168 {mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
2169 };
2170
2171 static const u32 gaudi2_pb_rot0_unsecured_regs[] = {
2172 mmROT0_QM_CQ_CFG0_0,
2173 mmROT0_QM_CQ_CFG0_1,
2174 mmROT0_QM_CQ_CFG0_2,
2175 mmROT0_QM_CQ_CFG0_3,
2176 mmROT0_QM_CQ_CFG0_4,
2177 mmROT0_QM_CP_FENCE0_RDATA_0,
2178 mmROT0_QM_CP_FENCE0_RDATA_1,
2179 mmROT0_QM_CP_FENCE0_RDATA_2,
2180 mmROT0_QM_CP_FENCE0_RDATA_3,
2181 mmROT0_QM_CP_FENCE0_RDATA_4,
2182 mmROT0_QM_CP_FENCE1_RDATA_0,
2183 mmROT0_QM_CP_FENCE1_RDATA_1,
2184 mmROT0_QM_CP_FENCE1_RDATA_2,
2185 mmROT0_QM_CP_FENCE1_RDATA_3,
2186 mmROT0_QM_CP_FENCE1_RDATA_4,
2187 mmROT0_QM_CP_FENCE2_RDATA_0,
2188 mmROT0_QM_CP_FENCE2_RDATA_1,
2189 mmROT0_QM_CP_FENCE2_RDATA_2,
2190 mmROT0_QM_CP_FENCE2_RDATA_3,
2191 mmROT0_QM_CP_FENCE2_RDATA_4,
2192 mmROT0_QM_CP_FENCE3_RDATA_0,
2193 mmROT0_QM_CP_FENCE3_RDATA_1,
2194 mmROT0_QM_CP_FENCE3_RDATA_2,
2195 mmROT0_QM_CP_FENCE3_RDATA_3,
2196 mmROT0_QM_CP_FENCE3_RDATA_4,
2197 mmROT0_QM_CP_FENCE0_CNT_0,
2198 mmROT0_QM_CP_FENCE0_CNT_1,
2199 mmROT0_QM_CP_FENCE0_CNT_2,
2200 mmROT0_QM_CP_FENCE0_CNT_3,
2201 mmROT0_QM_CP_FENCE0_CNT_4,
2202 mmROT0_QM_CP_FENCE1_CNT_0,
2203 mmROT0_QM_CP_FENCE1_CNT_1,
2204 mmROT0_QM_CP_FENCE1_CNT_2,
2205 mmROT0_QM_CP_FENCE1_CNT_3,
2206 mmROT0_QM_CP_FENCE1_CNT_4,
2207 mmROT0_QM_CP_FENCE2_CNT_0,
2208 mmROT0_QM_CP_FENCE2_CNT_1,
2209 mmROT0_QM_CP_FENCE2_CNT_2,
2210 mmROT0_QM_CP_FENCE2_CNT_3,
2211 mmROT0_QM_CP_FENCE2_CNT_4,
2212 mmROT0_QM_CP_FENCE3_CNT_0,
2213 mmROT0_QM_CP_FENCE3_CNT_1,
2214 mmROT0_QM_CP_FENCE3_CNT_2,
2215 mmROT0_QM_CP_FENCE3_CNT_3,
2216 mmROT0_QM_CP_FENCE3_CNT_4,
2217 mmROT0_QM_CQ_PTR_LO_0,
2218 mmROT0_QM_CQ_PTR_HI_0,
2219 mmROT0_QM_CQ_TSIZE_0,
2220 mmROT0_QM_CQ_CTL_0,
2221 mmROT0_QM_CQ_PTR_LO_1,
2222 mmROT0_QM_CQ_PTR_HI_1,
2223 mmROT0_QM_CQ_TSIZE_1,
2224 mmROT0_QM_CQ_CTL_1,
2225 mmROT0_QM_CQ_PTR_LO_2,
2226 mmROT0_QM_CQ_PTR_HI_2,
2227 mmROT0_QM_CQ_TSIZE_2,
2228 mmROT0_QM_CQ_CTL_2,
2229 mmROT0_QM_CQ_PTR_LO_3,
2230 mmROT0_QM_CQ_PTR_HI_3,
2231 mmROT0_QM_CQ_TSIZE_3,
2232 mmROT0_QM_CQ_CTL_3,
2233 mmROT0_QM_CQ_PTR_LO_4,
2234 mmROT0_QM_CQ_PTR_HI_4,
2235 mmROT0_QM_CQ_TSIZE_4,
2236 mmROT0_QM_CQ_CTL_4,
2237 mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE,
2238 mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
2239 mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE,
2240 mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
2241 mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE,
2242 mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
2243 mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE,
2244 mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
2245 mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE,
2246 mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
2247 mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE,
2248 mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
2249 mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE,
2250 mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
2251 mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE,
2252 mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
2253 mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE,
2254 mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
2255 mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE,
2256 mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
2257 mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE,
2258 mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
2259 mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE,
2260 mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
2261 mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE,
2262 mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
2263 mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE,
2264 mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
2265 mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE,
2266 mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
2267 mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE,
2268 mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
2269 mmROT0_QM_ARC_CQ_PTR_LO,
2270 mmROT0_QM_ARC_CQ_PTR_LO_STS,
2271 mmROT0_QM_ARC_CQ_PTR_HI,
2272 mmROT0_QM_ARC_CQ_PTR_HI_STS,
2273 mmROT0_QM_ARB_CFG_0,
2274 mmROT0_QM_ARB_MST_QUIET_PER,
2275 mmROT0_QM_ARB_CHOICE_Q_PUSH,
2276 mmROT0_QM_ARB_WRR_WEIGHT_0,
2277 mmROT0_QM_ARB_WRR_WEIGHT_1,
2278 mmROT0_QM_ARB_WRR_WEIGHT_2,
2279 mmROT0_QM_ARB_WRR_WEIGHT_3,
2280 mmROT0_QM_ARB_BASE_LO,
2281 mmROT0_QM_ARB_BASE_HI,
2282 mmROT0_QM_ARB_MST_SLAVE_EN,
2283 mmROT0_QM_ARB_MST_SLAVE_EN_1,
2284 mmROT0_QM_ARB_MST_CRED_INC,
2285 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
2286 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
2287 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
2288 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
2289 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
2290 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
2291 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
2292 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
2293 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
2294 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
2295 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
2296 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
2297 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
2298 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
2299 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
2300 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
2301 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
2302 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
2303 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
2304 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
2305 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
2306 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
2307 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
2308 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
2309 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
2310 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
2311 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
2312 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
2313 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
2314 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
2315 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
2316 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
2317 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
2318 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
2319 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
2320 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
2321 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
2322 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
2323 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
2324 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
2325 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
2326 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
2327 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
2328 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
2329 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
2330 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
2331 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
2332 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
2333 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
2334 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
2335 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
2336 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
2337 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
2338 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
2339 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
2340 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
2341 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
2342 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
2343 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
2344 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
2345 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
2346 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
2347 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
2348 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
2349 mmROT0_QM_ARB_SLV_ID,
2350 mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
2351 mmROT0_QM_ARC_CQ_CFG0,
2352 mmROT0_QM_CQ_IFIFO_CI_0,
2353 mmROT0_QM_CQ_IFIFO_CI_1,
2354 mmROT0_QM_CQ_IFIFO_CI_2,
2355 mmROT0_QM_CQ_IFIFO_CI_3,
2356 mmROT0_QM_CQ_IFIFO_CI_4,
2357 mmROT0_QM_ARC_CQ_IFIFO_CI,
2358 mmROT0_QM_CQ_CTL_CI_0,
2359 mmROT0_QM_CQ_CTL_CI_1,
2360 mmROT0_QM_CQ_CTL_CI_2,
2361 mmROT0_QM_CQ_CTL_CI_3,
2362 mmROT0_QM_CQ_CTL_CI_4,
2363 mmROT0_QM_ARC_CQ_CTL_CI,
2364 mmROT0_QM_ARC_CQ_TSIZE,
2365 mmROT0_QM_ARC_CQ_CTL,
2366 mmROT0_QM_CP_SWITCH_WD_SET,
2367 mmROT0_QM_CP_EXT_SWITCH,
2368 mmROT0_QM_CP_PRED_0,
2369 mmROT0_QM_CP_PRED_1,
2370 mmROT0_QM_CP_PRED_2,
2371 mmROT0_QM_CP_PRED_3,
2372 mmROT0_QM_CP_PRED_4,
2373 mmROT0_QM_CP_PRED_UPEN_0,
2374 mmROT0_QM_CP_PRED_UPEN_1,
2375 mmROT0_QM_CP_PRED_UPEN_2,
2376 mmROT0_QM_CP_PRED_UPEN_3,
2377 mmROT0_QM_CP_PRED_UPEN_4,
2378 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0,
2379 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1,
2380 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2,
2381 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3,
2382 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4,
2383 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0,
2384 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1,
2385 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2,
2386 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3,
2387 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4,
2388 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0,
2389 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1,
2390 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2,
2391 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3,
2392 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4,
2393 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0,
2394 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1,
2395 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2,
2396 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3,
2397 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4,
2398 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0,
2399 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1,
2400 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2,
2401 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3,
2402 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4,
2403 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0,
2404 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1,
2405 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2,
2406 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3,
2407 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4,
2408 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0,
2409 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1,
2410 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2,
2411 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3,
2412 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4,
2413 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0,
2414 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1,
2415 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2,
2416 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3,
2417 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4,
2418 mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
2419 mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO,
2420 mmROT0_QM_CQ_IFIFO_MSG_BASE_LO,
2421 mmROT0_QM_CQ_CTL_MSG_BASE_LO,
2422 mmROT0_DESC_CONTEXT_ID,
2423 mmROT0_DESC_IN_IMG_START_ADDR_L,
2424 mmROT0_DESC_IN_IMG_START_ADDR_H,
2425 mmROT0_DESC_OUT_IMG_START_ADDR_L,
2426 mmROT0_DESC_OUT_IMG_START_ADDR_H,
2427 mmROT0_DESC_CFG,
2428 mmROT0_DESC_IM_READ_SLOPE,
2429 mmROT0_DESC_SIN_D,
2430 mmROT0_DESC_COS_D,
2431 mmROT0_DESC_IN_IMG,
2432 mmROT0_DESC_IN_STRIDE,
2433 mmROT0_DESC_IN_STRIPE,
2434 mmROT0_DESC_IN_CENTER,
2435 mmROT0_DESC_OUT_IMG,
2436 mmROT0_DESC_OUT_STRIDE,
2437 mmROT0_DESC_OUT_STRIPE,
2438 mmROT0_DESC_OUT_CENTER,
2439 mmROT0_DESC_BACKGROUND,
2440 mmROT0_DESC_CPL_MSG_EN,
2441 mmROT0_DESC_IDLE_STATE,
2442 mmROT0_DESC_CPL_MSG_ADDR,
2443 mmROT0_DESC_CPL_MSG_DATA,
2444 mmROT0_DESC_X_I_START_OFFSET,
2445 mmROT0_DESC_X_I_START_OFFSET_FLIP,
2446 mmROT0_DESC_X_I_FIRST,
2447 mmROT0_DESC_Y_I_FIRST,
2448 mmROT0_DESC_Y_I,
2449 mmROT0_DESC_OUT_STRIPE_SIZE,
2450 mmROT0_DESC_RSB_CFG_0,
2451 mmROT0_DESC_RSB_PAD_VAL,
2452 mmROT0_DESC_OWM_CFG,
2453 mmROT0_DESC_CTRL_CFG,
2454 mmROT0_DESC_PIXEL_PAD,
2455 mmROT0_DESC_PREC_SHIFT,
2456 mmROT0_DESC_MAX_VAL,
2457 mmROT0_DESC_A0_M11,
2458 mmROT0_DESC_A1_M12,
2459 mmROT0_DESC_A2,
2460 mmROT0_DESC_B0_M21,
2461 mmROT0_DESC_B1_M22,
2462 mmROT0_DESC_B2,
2463 mmROT0_DESC_C0,
2464 mmROT0_DESC_C1,
2465 mmROT0_DESC_C2,
2466 mmROT0_DESC_D0,
2467 mmROT0_DESC_D1,
2468 mmROT0_DESC_D2,
2469 mmROT0_DESC_INV_PROC_SIZE_M_1,
2470 mmROT0_DESC_MESH_IMG_START_ADDR_L,
2471 mmROT0_DESC_MESH_IMG_START_ADDR_H,
2472 mmROT0_DESC_MESH_IMG,
2473 mmROT0_DESC_MESH_STRIDE,
2474 mmROT0_DESC_MESH_STRIPE,
2475 mmROT0_DESC_MESH_CTRL,
2476 mmROT0_DESC_MESH_GH,
2477 mmROT0_DESC_MESH_GV,
2478 mmROT0_DESC_MRSB_CFG_0,
2479 mmROT0_DESC_MRSB_PAD_VAL,
2480 mmROT0_DESC_BUF_CFG,
2481 mmROT0_DESC_CID_OFFSET,
2482 mmROT0_DESC_PUSH_DESC
2483 };
2484
2485 static const u32 gaudi2_pb_psoc_global_conf[] = {
2486 mmPSOC_GLOBAL_CONF_BASE
2487 };
2488
2489 static const u32 gaudi2_pb_psoc[] = {
2490 mmPSOC_EFUSE_BASE,
2491 mmPSOC_BTL_BASE,
2492 mmPSOC_CS_TRACE_BASE,
2493 mmPSOC_DFT_EFUSE_BASE,
2494 mmPSOC_PID_BASE,
2495 mmPSOC_ARC0_CFG_BASE,
2496 mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE,
2497 mmPSOC_ARC0_AUX_BASE,
2498 mmPSOC_ARC1_CFG_BASE,
2499 mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE,
2500 mmPSOC_ARC1_AUX_BASE,
2501 mmJT_MSTR_IF_RR_SHRD_HBW_BASE,
2502 mmSMI_MSTR_IF_RR_SHRD_HBW_BASE,
2503 mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE,
2504 mmPSOC_SVID0_BASE,
2505 mmPSOC_SVID1_BASE,
2506 mmPSOC_SVID2_BASE,
2507 mmPSOC_AVS0_BASE,
2508 mmPSOC_AVS1_BASE,
2509 mmPSOC_AVS2_BASE,
2510 mmPSOC_PWM0_BASE,
2511 mmPSOC_PWM1_BASE,
2512 mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE,
2513 };
2514
2515 static const u32 gaudi2_pb_pmmu[] = {
2516 mmPMMU_HBW_MMU_BASE,
2517 mmPMMU_HBW_STLB_BASE,
2518 mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE,
2519 mmPMMU_PIF_BASE,
2520 };
2521
2522 static const u32 gaudi2_pb_psoc_pll[] = {
2523 mmPSOC_MME_PLL_CTRL_BASE,
2524 mmPSOC_CPU_PLL_CTRL_BASE,
2525 mmPSOC_VID_PLL_CTRL_BASE
2526 };
2527
2528 static const u32 gaudi2_pb_pmmu_pll[] = {
2529 mmPMMU_MME_PLL_CTRL_BASE,
2530 mmPMMU_VID_PLL_CTRL_BASE
2531 };
2532
2533 static const u32 gaudi2_pb_xbar_pll[] = {
2534 mmDCORE0_XBAR_DMA_PLL_CTRL_BASE,
2535 mmDCORE0_XBAR_MMU_PLL_CTRL_BASE,
2536 mmDCORE0_XBAR_IF_PLL_CTRL_BASE,
2537 mmDCORE0_XBAR_MESH_PLL_CTRL_BASE,
2538 mmDCORE1_XBAR_DMA_PLL_CTRL_BASE,
2539 mmDCORE1_XBAR_MMU_PLL_CTRL_BASE,
2540 mmDCORE1_XBAR_IF_PLL_CTRL_BASE,
2541 mmDCORE1_XBAR_MESH_PLL_CTRL_BASE,
2542 mmDCORE1_XBAR_HBM_PLL_CTRL_BASE,
2543 mmDCORE2_XBAR_DMA_PLL_CTRL_BASE,
2544 mmDCORE2_XBAR_MMU_PLL_CTRL_BASE,
2545 mmDCORE2_XBAR_IF_PLL_CTRL_BASE,
2546 mmDCORE2_XBAR_BANK_PLL_CTRL_BASE,
2547 mmDCORE2_XBAR_HBM_PLL_CTRL_BASE,
2548 mmDCORE3_XBAR_DMA_PLL_CTRL_BASE,
2549 mmDCORE3_XBAR_MMU_PLL_CTRL_BASE,
2550 mmDCORE3_XBAR_IF_PLL_CTRL_BASE,
2551 mmDCORE3_XBAR_BANK_PLL_CTRL_BASE
2552 };
2553
2554 static const u32 gaudi2_pb_xft_pll[] = {
2555 mmDCORE0_HBM_PLL_CTRL_BASE,
2556 mmDCORE0_TPC_PLL_CTRL_BASE,
2557 mmDCORE0_PCI_PLL_CTRL_BASE,
2558 mmDCORE1_HBM_PLL_CTRL_BASE,
2559 mmDCORE1_TPC_PLL_CTRL_BASE,
2560 mmDCORE1_NIC_PLL_CTRL_BASE,
2561 mmDCORE2_HBM_PLL_CTRL_BASE,
2562 mmDCORE2_TPC_PLL_CTRL_BASE,
2563 mmDCORE3_HBM_PLL_CTRL_BASE,
2564 mmDCORE3_TPC_PLL_CTRL_BASE,
2565 mmDCORE3_NIC_PLL_CTRL_BASE,
2566 };
2567
2568 static const u32 gaudi2_pb_pcie[] = {
2569 mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2570 mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2571 mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2572 mmPCIE_WRAP_BASE,
2573 };
2574
2575 static const u32 gaudi2_pb_pcie_unsecured_regs[] = {
2576 mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0,
2577 };
2578
2579 static const u32 gaudi2_pb_thermal_sensor0[] = {
2580 mmDCORE0_XFT_BASE,
2581 mmDCORE0_TSTDVS_BASE,
2582 };
2583
2584 static const u32 gaudi2_pb_hbm[] = {
2585 mmHBM0_MC0_BASE,
2586 mmHBM0_MC1_BASE,
2587 };
2588
2589 static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = {
2590 mmDCORE0_MME_QM_ARC_ACP_ENG_BASE,
2591 };
2592
2593 static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = {
2594 {mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG},
2595 };
2596
2597 struct gaudi2_tpc_pb_data {
2598 struct hl_block_glbl_sec *glbl_sec;
2599 u32 block_array_size;
2600 };
2601
gaudi2_config_tpcs_glbl_sec(struct hl_device * hdev,int dcore,int inst,u32 offset,struct iterate_module_ctx * ctx)2602 static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
2603 struct iterate_module_ctx *ctx)
2604 {
2605 struct gaudi2_tpc_pb_data *pb_data = ctx->data;
2606
2607 hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,
2608 offset, pb_data->block_array_size);
2609 }
2610
gaudi2_init_pb_tpc(struct hl_device * hdev)2611 static int gaudi2_init_pb_tpc(struct hl_device *hdev)
2612 {
2613 u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size;
2614 struct gaudi2_tpc_pb_data tpc_pb_data;
2615 struct hl_block_glbl_sec *glbl_sec;
2616 struct iterate_module_ctx tpc_iter;
2617 int i;
2618
2619 block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
2620
2621 glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL);
2622 if (!glbl_sec)
2623 return -ENOMEM;
2624
2625 kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE -
2626 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE;
2627 qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE;
2628
2629 hl_secure_block(hdev, glbl_sec, block_array_size);
2630 hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,
2631 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs),
2632 0, gaudi2_pb_dcr0_tpc0, glbl_sec,
2633 block_array_size);
2634
2635 /* Unsecure all TPC kernel tensors */
2636 for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++)
2637 hl_unsecure_registers(hdev,
2638 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs,
2639 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs),
2640 i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0,
2641 glbl_sec, block_array_size);
2642
2643 /* Unsecure all TPC QM tensors */
2644 for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++)
2645 hl_unsecure_registers(hdev,
2646 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs,
2647 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs),
2648 i * qm_tensor_stride,
2649 gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size);
2650
2651 /* unsecure all 32 TPC QM SRF regs */
2652 stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0;
2653 for (i = 0 ; i < 32 ; i++)
2654 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,
2655 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2656 block_array_size);
2657
2658 /* unsecure the 4 TPC LOCK VALUE regs */
2659 stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0;
2660 for (i = 0 ; i < 4 ; i++)
2661 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,
2662 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2663 block_array_size);
2664
2665 /* prepare data for TPC iterator */
2666 tpc_pb_data.glbl_sec = glbl_sec;
2667 tpc_pb_data.block_array_size = block_array_size;
2668 tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec;
2669 tpc_iter.data = &tpc_pb_data;
2670 gaudi2_iterate_tpcs(hdev, &tpc_iter);
2671
2672 kfree(glbl_sec);
2673
2674 return 0;
2675 }
2676
2677 struct gaudi2_tpc_arc_pb_data {
2678 u32 unsecured_regs_arr_size;
2679 u32 arc_regs_arr_size;
2680 };
2681
gaudi2_config_tpcs_pb_ranges(struct hl_device * hdev,int dcore,int inst,u32 offset,struct iterate_module_ctx * ctx)2682 static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
2683 struct iterate_module_ctx *ctx)
2684 {
2685 struct gaudi2_tpc_arc_pb_data *pb_data = ctx->data;
2686
2687 ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,
2688 offset, gaudi2_pb_dcr0_tpc0_arc,
2689 pb_data->arc_regs_arr_size,
2690 gaudi2_pb_dcr0_tpc0_arc_unsecured_regs,
2691 pb_data->unsecured_regs_arr_size);
2692 }
2693
gaudi2_init_pb_tpc_arc(struct hl_device * hdev)2694 static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)
2695 {
2696 struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data;
2697 struct iterate_module_ctx tpc_iter;
2698
2699 tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
2700 tpc_arc_pb_data.unsecured_regs_arr_size =
2701 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs);
2702
2703 tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges;
2704 tpc_iter.data = &tpc_arc_pb_data;
2705 gaudi2_iterate_tpcs(hdev, &tpc_iter);
2706
2707 return tpc_iter.rc;
2708 }
2709
gaudi2_init_pb_sm_objs(struct hl_device * hdev)2710 static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
2711 {
2712 int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length;
2713 u32 sec_entry, *sec_array, array_base, first_sob, first_mon;
2714
2715 array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr +
2716 gaudi2_pb_dcr0_sm_objs.glbl_sec_offset;
2717
2718 sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL);
2719 if (!sec_array)
2720 return -ENOMEM;
2721
2722 first_sob = GAUDI2_RESERVED_SOB_NUMBER;
2723 first_mon = GAUDI2_RESERVED_MON_NUMBER;
2724
2725 /* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */
2726 for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)
2727 UNSET_GLBL_SEC_BIT(sec_array, j);
2728
2729 /* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */
2730 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2731 UNSET_GLBL_SEC_BIT(sec_array, j);
2732
2733 /* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */
2734 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2735 UNSET_GLBL_SEC_BIT(sec_array, j);
2736
2737 /* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */
2738 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2739 UNSET_GLBL_SEC_BIT(sec_array, j);
2740
2741 /* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */
2742 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2743 UNSET_GLBL_SEC_BIT(sec_array, j);
2744
2745 /* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */
2746 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2747 UNSET_GLBL_SEC_BIT(sec_array, j);
2748
2749 /* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */
2750 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2751 UNSET_GLBL_SEC_BIT(sec_array, j);
2752
2753 /* Unsecure selected Dcore0 registers */
2754 for (i = 0 ; i < glbl_sec_array_len ; i++) {
2755 sec_entry = array_base + i * sizeof(u32);
2756 WREG32(sec_entry, sec_array[i]);
2757 }
2758
2759 /* Unsecure Dcore1 - Dcore3 registers */
2760 memset(sec_array, -1, glbl_sec_array_len * sizeof(u32));
2761
2762 for (i = 1 ; i < NUM_OF_DCORES ; i++) {
2763 for (j = 0 ; j < glbl_sec_array_len ; j++) {
2764 sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);
2765 WREG32(sec_entry, sec_array[j]);
2766 }
2767 }
2768
2769 kfree(sec_array);
2770
2771 return 0;
2772 }
2773
gaudi2_write_lbw_range_register(struct hl_device * hdev,u64 base,void * data)2774 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
2775 {
2776 u32 reg_min_offset, reg_max_offset, write_min, write_max;
2777 struct rr_config *rr_cfg = (struct rr_config *) data;
2778
2779 switch (rr_cfg->type) {
2780 case RR_TYPE_SHORT:
2781 reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET;
2782 reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET;
2783 break;
2784
2785 case RR_TYPE_LONG:
2786 reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET;
2787 reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET;
2788 break;
2789
2790 case RR_TYPE_SHORT_PRIV:
2791 reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET;
2792 reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET;
2793 break;
2794
2795 case RR_TYPE_LONG_PRIV:
2796 reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET;
2797 reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET;
2798 break;
2799
2800 default:
2801 dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);
2802 return;
2803 }
2804
2805 reg_min_offset += rr_cfg->index * sizeof(u32);
2806 reg_max_offset += rr_cfg->index * sizeof(u32);
2807
2808 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
2809 write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min));
2810 write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max));
2811
2812 } else {
2813 write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min));
2814 write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max));
2815 }
2816
2817 /* Configure LBW RR:
2818 * Both RR types start blocking from base address 0x1000007FF8000000
2819 * SHORT RRs address bits [26:12]
2820 * LONG RRs address bits [26:0]
2821 */
2822 WREG32(base + reg_min_offset, write_min);
2823 WREG32(base + reg_max_offset, write_max);
2824 }
2825
gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device * hdev,u8 rr_type,u32 rr_index,u64 min_val,u64 max_val)2826 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
2827 u64 max_val)
2828 {
2829 struct dup_block_ctx block_ctx;
2830 struct rr_config rr_cfg;
2831
2832 if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
2833 rr_index >= NUM_SHORT_LBW_RR) {
2834
2835 dev_err(hdev->dev, "invalid short LBW %s range register index: %u",
2836 rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
2837 return;
2838 }
2839
2840 if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
2841 rr_index >= NUM_LONG_LBW_RR) {
2842
2843 dev_err(hdev->dev, "invalid long LBW %s range register index: %u",
2844 rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
2845 return;
2846 }
2847
2848 rr_cfg.type = rr_type;
2849 rr_cfg.index = rr_index;
2850 rr_cfg.min = min_val;
2851 rr_cfg.max = max_val;
2852
2853 block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register;
2854 block_ctx.data = &rr_cfg;
2855
2856 /* SFT */
2857 block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;
2858 block_ctx.blocks = NUM_OF_SFT;
2859 block_ctx.block_off = SFT_OFFSET;
2860 block_ctx.instances = SFT_NUM_OF_LBW_RTR;
2861 block_ctx.instance_off = SFT_LBW_RTR_OFFSET;
2862 gaudi2_init_blocks(hdev, &block_ctx);
2863
2864 /* SIF */
2865 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;
2866 block_ctx.blocks = NUM_OF_DCORES;
2867 block_ctx.block_off = DCORE_OFFSET;
2868 block_ctx.instances = NUM_OF_RTR_PER_DCORE;
2869 block_ctx.instance_off = DCORE_RTR_OFFSET;
2870 gaudi2_init_blocks(hdev, &block_ctx);
2871
2872 block_ctx.blocks = 1;
2873 block_ctx.block_off = 0;
2874 block_ctx.instances = 1;
2875 block_ctx.instance_off = 0;
2876
2877 /* PCIE ELBI */
2878 block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2879 gaudi2_init_blocks(hdev, &block_ctx);
2880
2881 /* PCIE MSTR */
2882 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2883 gaudi2_init_blocks(hdev, &block_ctx);
2884
2885 /* PCIE LBW */
2886 block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2887 gaudi2_init_blocks(hdev, &block_ctx);
2888 }
2889
gaudi2_init_lbw_range_registers_secure(struct hl_device * hdev)2890 static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
2891 {
2892 int i;
2893
2894 /* Up to 14 14bit-address regs.
2895 *
2896 * - range 0: NIC0_CFG
2897 * - range 1: NIC1_CFG
2898 * - range 2: NIC2_CFG
2899 * - range 3: NIC3_CFG
2900 * - range 4: NIC4_CFG
2901 * - range 5: NIC5_CFG
2902 * - range 6: NIC6_CFG
2903 * - range 7: NIC7_CFG
2904 * - range 8: NIC8_CFG
2905 * - range 9: NIC9_CFG
2906 * - range 10: NIC10_CFG
2907 * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)
2908 *
2909 * If F/W security is not enabled:
2910 * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP)
2911 */
2912 u64 lbw_range_min_short[] = {
2913 mmNIC0_TX_AXUSER_BASE,
2914 mmNIC1_TX_AXUSER_BASE,
2915 mmNIC2_TX_AXUSER_BASE,
2916 mmNIC3_TX_AXUSER_BASE,
2917 mmNIC4_TX_AXUSER_BASE,
2918 mmNIC5_TX_AXUSER_BASE,
2919 mmNIC6_TX_AXUSER_BASE,
2920 mmNIC7_TX_AXUSER_BASE,
2921 mmNIC8_TX_AXUSER_BASE,
2922 mmNIC9_TX_AXUSER_BASE,
2923 mmNIC10_TX_AXUSER_BASE,
2924 mmNIC11_TX_AXUSER_BASE,
2925 mmPSOC_I2C_M0_BASE,
2926 mmPSOC_EFUSE_BASE
2927 };
2928 u64 lbw_range_max_short[] = {
2929 mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2930 mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2931 mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2932 mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2933 mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2934 mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2935 mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2936 mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2937 mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2938 mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2939 mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2940 mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE,
2941 mmPSOC_WDOG_BASE + HL_BLOCK_SIZE,
2942 mmSVID2_AC_BASE + HL_BLOCK_SIZE
2943 };
2944
2945 /* Up to 4 26bit-address regs.
2946 *
2947 * - range 0: TPC_DBG
2948 * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF
2949 * - range 2/3: used in soft reset to block access to several blocks and are cleared here
2950 */
2951 u64 lbw_range_min_long[] = {
2952 mmDCORE0_TPC0_ROM_TABLE_BASE,
2953 mmPCIE_DBI_MSIX_DOORBELL_OFF,
2954 0x0,
2955 0x0
2956 };
2957 u64 lbw_range_max_long[] = {
2958 mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE,
2959 mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4,
2960 0x0,
2961 0x0
2962 };
2963
2964 /* write short range registers to all lbw rtrs */
2965 for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) {
2966 if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE ||
2967 lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) &&
2968 hdev->asic_prop.fw_security_enabled)
2969 continue;
2970
2971 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,
2972 lbw_range_min_short[i], lbw_range_max_short[i]);
2973 }
2974
2975 /* write long range registers to all lbw rtrs */
2976 for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) {
2977 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,
2978 lbw_range_min_long[i], lbw_range_max_long[i]);
2979 }
2980 }
2981
gaudi2_init_lbw_range_registers(struct hl_device * hdev)2982 static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)
2983 {
2984 gaudi2_init_lbw_range_registers_secure(hdev);
2985 }
2986
gaudi2_write_hbw_range_register(struct hl_device * hdev,u64 base,void * data)2987 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
2988 {
2989 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
2990 struct rr_config *rr_cfg = (struct rr_config *) data;
2991 u64 val_min, val_max;
2992
2993 switch (rr_cfg->type) {
2994 case RR_TYPE_SHORT:
2995 min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;
2996 min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;
2997 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET;
2998 max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET;
2999 break;
3000
3001 case RR_TYPE_LONG:
3002 min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;
3003 min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;
3004 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET;
3005 max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET;
3006 break;
3007
3008 case RR_TYPE_SHORT_PRIV:
3009 min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;
3010 min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;
3011 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET;
3012 max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET;
3013 break;
3014
3015 case RR_TYPE_LONG_PRIV:
3016 min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;
3017 min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;
3018 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET;
3019 max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET;
3020 break;
3021
3022 default:
3023 dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);
3024 return;
3025 }
3026
3027 min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3028 min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3029 max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3030 max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3031
3032 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
3033 val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) |
3034 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min);
3035 val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) |
3036 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max);
3037 } else {
3038 val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) |
3039 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min);
3040 val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) |
3041 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max);
3042 }
3043
3044 /* Configure HBW RR:
3045 * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12]
3046 * LONG RRs (0x<52bits>000) - HI: address bits [63:44], LO: address bits [43:12]
3047 */
3048 WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));
3049 WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));
3050 WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));
3051 WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));
3052 }
3053
gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device * hdev,u8 rr_type,u32 rr_index,u64 min_val,u64 max_val)3054 static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,
3055 u64 min_val, u64 max_val)
3056 {
3057 struct dup_block_ctx block_ctx;
3058 struct rr_config rr_cfg;
3059
3060 if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
3061 rr_index >= NUM_SHORT_HBW_RR) {
3062
3063 dev_err(hdev->dev, "invalid short HBW %s range register index: %u",
3064 rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
3065 return;
3066 }
3067
3068 if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
3069 rr_index >= NUM_LONG_HBW_RR) {
3070
3071 dev_err(hdev->dev, "invalid long HBW %s range register index: %u",
3072 rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
3073 return;
3074 }
3075
3076 rr_cfg.type = rr_type;
3077 rr_cfg.index = rr_index;
3078 rr_cfg.min = min_val;
3079 rr_cfg.max = max_val;
3080
3081 block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register;
3082 block_ctx.data = &rr_cfg;
3083
3084 /* SFT */
3085 block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;
3086 block_ctx.blocks = NUM_OF_SFT;
3087 block_ctx.block_off = SFT_OFFSET;
3088 block_ctx.instances = SFT_NUM_OF_HBW_RTR;
3089 block_ctx.instance_off = SFT_IF_RTR_OFFSET;
3090 gaudi2_init_blocks(hdev, &block_ctx);
3091
3092 /* SIF */
3093 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;
3094 block_ctx.blocks = NUM_OF_DCORES;
3095 block_ctx.block_off = DCORE_OFFSET;
3096 block_ctx.instances = NUM_OF_RTR_PER_DCORE;
3097 block_ctx.instance_off = DCORE_RTR_OFFSET;
3098 gaudi2_init_blocks(hdev, &block_ctx);
3099
3100 /* PCIE MSTR */
3101 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;
3102 block_ctx.blocks = 1;
3103 block_ctx.block_off = 0;
3104 block_ctx.instances = 1;
3105 block_ctx.instance_off = 0;
3106 gaudi2_init_blocks(hdev, &block_ctx);
3107 }
3108
gaudi2_init_hbw_range_registers(struct hl_device * hdev)3109 static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)
3110 {
3111 int i;
3112
3113 /* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000).
3114 *
3115 * - short range 0:
3116 * SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM
3117 */
3118 u64 hbw_range_min_short[] = {
3119 SPI_FLASH_BASE_ADDR
3120 };
3121 u64 hbw_range_max_short[] = {
3122 PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE
3123 };
3124
3125 for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) {
3126 gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],
3127 hbw_range_max_short[i]);
3128 }
3129 }
3130
gaudi2_write_mmu_range_register(struct hl_device * hdev,u64 base,struct rr_config * rr_cfg)3131 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
3132 struct rr_config *rr_cfg)
3133 {
3134 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
3135
3136 switch (rr_cfg->type) {
3137 case RR_TYPE_LONG:
3138 min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;
3139 min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;
3140 max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET;
3141 max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET;
3142 break;
3143
3144 case RR_TYPE_LONG_PRIV:
3145 min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;
3146 min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;
3147 max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET;
3148 max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET;
3149 break;
3150
3151 default:
3152 dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);
3153 return;
3154 }
3155
3156 min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3157 min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3158 max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3159 max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3160
3161 /* Configure MMU RR (address bits [63:0]) */
3162 WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));
3163 WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));
3164 WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));
3165 WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));
3166 }
3167
gaudi2_init_mmu_range_registers(struct hl_device * hdev)3168 static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)
3169 {
3170 u32 dcore_id, hmmu_id, hmmu_base;
3171 struct rr_config rr_cfg;
3172
3173 /* Up to 8 ranges [63:0].
3174 *
3175 * - range 0: Reserved HBM area for F/W and driver
3176 */
3177
3178 /* The RRs are located after the HMMU so need to use the scrambled addresses */
3179 rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
3180 rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);
3181 rr_cfg.index = 0;
3182 rr_cfg.type = RR_TYPE_LONG;
3183
3184 for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
3185 for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {
3186 if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
3187 continue;
3188
3189 hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +
3190 hmmu_id * DCORE_HMMU_OFFSET;
3191
3192 gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);
3193 }
3194 }
3195 }
3196
3197 /**
3198 * gaudi2_init_range_registers -
3199 * Initialize range registers of all initiators
3200 *
3201 * @hdev: pointer to hl_device structure
3202 */
gaudi2_init_range_registers(struct hl_device * hdev)3203 static void gaudi2_init_range_registers(struct hl_device *hdev)
3204 {
3205 gaudi2_init_lbw_range_registers(hdev);
3206 gaudi2_init_hbw_range_registers(hdev);
3207 gaudi2_init_mmu_range_registers(hdev);
3208 }
3209
3210 /**
3211 * gaudi2_init_protection_bits -
3212 * Initialize protection bits of specific registers
3213 *
3214 * @hdev: pointer to hl_device structure
3215 *
3216 * All protection bits are 1 by default, means not protected. Need to set to 0
3217 * each bit that belongs to a protected register.
3218 *
3219 */
gaudi2_init_protection_bits(struct hl_device * hdev)3220 static int gaudi2_init_protection_bits(struct hl_device *hdev)
3221 {
3222 struct asic_fixed_properties *prop = &hdev->asic_prop;
3223 u32 instance_offset;
3224 int rc = 0;
3225 u8 i;
3226
3227 /* SFT */
3228 instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3229 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3230 gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0),
3231 NULL, HL_PB_NA);
3232
3233 /* HIF */
3234 instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3235 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3236 NUM_OF_HIF_PER_DCORE, instance_offset,
3237 gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3238 NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3239
3240 /* RTR */
3241 instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3242 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3243 gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0),
3244 NULL, HL_PB_NA);
3245
3246 /* HMMU */
3247 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3248 NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3249 gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3250 NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3251
3252 /* CPU.
3253 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3254 * by privileged RR.
3255 */
3256 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3257 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3258 gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if),
3259 NULL, HL_PB_NA);
3260
3261 if (!hdev->asic_prop.fw_security_enabled)
3262 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3263 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3264 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu),
3265 NULL, HL_PB_NA);
3266
3267 /* KDMA */
3268 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3269 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3270 gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma),
3271 NULL, HL_PB_NA);
3272
3273 /* PDMA */
3274 instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3275 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3276 gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0),
3277 gaudi2_pb_pdma0_unsecured_regs,
3278 ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs));
3279
3280 /* ARC PDMA */
3281 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,
3282 instance_offset, gaudi2_pb_pdma0_arc,
3283 ARRAY_SIZE(gaudi2_pb_pdma0_arc),
3284 gaudi2_pb_pdma0_arc_unsecured_regs,
3285 ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs));
3286
3287 /* EDMA */
3288 instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3289 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3290 instance_offset, gaudi2_pb_dcr0_edma0,
3291 ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3292 gaudi2_pb_dcr0_edma0_unsecured_regs,
3293 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs),
3294 prop->edma_enabled_mask);
3295
3296 /* ARC EDMA */
3297 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3298 instance_offset, gaudi2_pb_dcr0_edma0_arc,
3299 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3300 gaudi2_pb_dcr0_edma0_arc_unsecured_regs,
3301 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs),
3302 prop->edma_enabled_mask);
3303
3304 /* MME */
3305 instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3306
3307 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3308 /* MME SBTE */
3309 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3310 instance_offset, gaudi2_pb_dcr0_mme_sbte,
3311 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL,
3312 HL_PB_NA);
3313
3314 /* MME */
3315 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3316 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3317 gaudi2_pb_dcr0_mme_eng,
3318 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng),
3319 gaudi2_pb_dcr0_mme_eng_unsecured_regs,
3320 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs));
3321 }
3322
3323 /*
3324 * we have special iteration for case in which we would like to
3325 * configure stubbed MME's ARC/QMAN
3326 */
3327 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3328 /* MME QM */
3329 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3330 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3331 gaudi2_pb_dcr0_mme_qm,
3332 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm),
3333 gaudi2_pb_dcr0_mme_qm_unsecured_regs,
3334 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs));
3335
3336 /* ARC MME */
3337 rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
3338 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3339 gaudi2_pb_dcr0_mme_arc,
3340 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc),
3341 gaudi2_pb_dcr0_mme_arc_unsecured_regs,
3342 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs));
3343 }
3344
3345 /* MME QM ARC ACP ENG */
3346 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3347 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3348 gaudi2_pb_mme_qm_arc_acp_eng,
3349 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3350 gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs,
3351 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs),
3352 (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3353
3354 /* TPC */
3355 rc |= gaudi2_init_pb_tpc(hdev);
3356 rc |= gaudi2_init_pb_tpc_arc(hdev);
3357
3358 /* SRAM */
3359 instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3360 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3361 gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0),
3362 NULL, HL_PB_NA);
3363
3364 /* Sync Manager MSTR IF */
3365 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3366 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3367 gaudi2_pb_dcr0_sm_mstr_if,
3368 ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if),
3369 NULL, HL_PB_NA);
3370
3371 /* Sync Manager GLBL */
3372
3373 /* Secure Dcore0 CQ0 registers */
3374 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3375 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3376 gaudi2_pb_dcr0_sm_glbl,
3377 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
3378 gaudi2_pb_dcr0_sm_glbl_unsecured_regs,
3379 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));
3380
3381 /* Unsecure all other CQ registers */
3382 rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
3383 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3384 gaudi2_pb_dcr1_sm_glbl,
3385 ARRAY_SIZE(gaudi2_pb_dcr1_sm_glbl),
3386 gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,
3387 ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));
3388
3389 /* PSOC.
3390 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3391 * protected by privileged RR.
3392 */
3393 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3394 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3395 gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),
3396 NULL, HL_PB_NA);
3397
3398 if (!hdev->asic_prop.fw_security_enabled)
3399 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3400 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3401 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc),
3402 NULL, HL_PB_NA);
3403
3404 /* PMMU */
3405 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3406 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3407 gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu),
3408 NULL, HL_PB_NA);
3409
3410 /* PLL.
3411 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3412 * privileged RR.
3413 */
3414 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3415 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3416 gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll),
3417 NULL, HL_PB_NA);
3418 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3419 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3420 gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll),
3421 NULL, HL_PB_NA);
3422
3423 if (!hdev->asic_prop.fw_security_enabled) {
3424 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3425 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3426 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll),
3427 NULL, HL_PB_NA);
3428 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3429 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3430 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll),
3431 NULL, HL_PB_NA);
3432 }
3433
3434 /* PCIE */
3435 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3436 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3437 gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie),
3438 gaudi2_pb_pcie_unsecured_regs,
3439 ARRAY_SIZE(gaudi2_pb_pcie_unsecured_regs));
3440
3441 /* Thermal Sensor.
3442 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3443 */
3444 if (!hdev->asic_prop.fw_security_enabled) {
3445 instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3446 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3447 gaudi2_pb_thermal_sensor0,
3448 ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA);
3449 }
3450
3451 /* Scheduler ARCs */
3452 instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3453 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3454 NUM_OF_ARC_FARMS_ARC,
3455 instance_offset, gaudi2_pb_arc_sched,
3456 ARRAY_SIZE(gaudi2_pb_arc_sched),
3457 gaudi2_pb_arc_sched_unsecured_regs,
3458 ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs));
3459
3460 /* XBAR MIDs */
3461 instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3462 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3463 instance_offset, gaudi2_pb_xbar_mid,
3464 ARRAY_SIZE(gaudi2_pb_xbar_mid),
3465 gaudi2_pb_xbar_mid_unsecured_regs,
3466 ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs));
3467
3468 /* XBAR EDGEs */
3469 instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3470 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3471 instance_offset, gaudi2_pb_xbar_edge,
3472 ARRAY_SIZE(gaudi2_pb_xbar_edge),
3473 gaudi2_pb_xbar_edge_unsecured_regs,
3474 ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs),
3475 prop->xbar_edge_enabled_mask);
3476
3477 /* NIC */
3478 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3479 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3480 gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),
3481 NULL, HL_PB_NA, hdev->nic_ports_mask);
3482
3483 /* NIC QM and QPC */
3484 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3485 NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3486 gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3487 gaudi2_pb_nic0_qm_qpc_unsecured_regs,
3488 ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),
3489 hdev->nic_ports_mask);
3490
3491 /* NIC QM ARC */
3492 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3493 NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3494 gaudi2_pb_nic0_qm_arc_aux0,
3495 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),
3496 gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,
3497 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),
3498 hdev->nic_ports_mask);
3499
3500 /* NIC UMR */
3501 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3502 NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3503 gaudi2_pb_nic0_umr,
3504 ARRAY_SIZE(gaudi2_pb_nic0_umr),
3505 gaudi2_pb_nic0_umr_unsecured_regs,
3506 ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),
3507 hdev->nic_ports_mask);
3508
3509 /* Rotators */
3510 instance_offset = mmROT1_BASE - mmROT0_BASE;
3511 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,
3512 instance_offset, gaudi2_pb_rot0,
3513 ARRAY_SIZE(gaudi2_pb_rot0),
3514 gaudi2_pb_rot0_unsecured_regs,
3515 ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs),
3516 (BIT(NUM_OF_ROT) - 1));
3517
3518 /* Rotators ARCS */
3519 rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,
3520 HL_PB_NA, NUM_OF_ROT, instance_offset,
3521 gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc),
3522 gaudi2_pb_rot0_arc_unsecured_regs,
3523 ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs),
3524 (BIT(NUM_OF_ROT) - 1));
3525
3526 rc |= gaudi2_init_pb_sm_objs(hdev);
3527
3528 return rc;
3529 }
3530
3531 /**
3532 * gaudi2_init_security - Initialize security model
3533 *
3534 * @hdev: pointer to hl_device structure
3535 *
3536 * Initialize the security model of the device
3537 * That includes range registers and protection bit per register.
3538 */
gaudi2_init_security(struct hl_device * hdev)3539 int gaudi2_init_security(struct hl_device *hdev)
3540 {
3541 int rc;
3542
3543 rc = gaudi2_init_protection_bits(hdev);
3544 if (rc)
3545 return rc;
3546
3547 gaudi2_init_range_registers(hdev);
3548
3549 return 0;
3550 }
3551
3552 struct gaudi2_ack_pb_tpc_data {
3553 u32 tpc_regs_array_size;
3554 u32 arc_tpc_regs_array_size;
3555 };
3556
gaudi2_ack_pb_tpc_config(struct hl_device * hdev,int dcore,int inst,u32 offset,struct iterate_module_ctx * ctx)3557 static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
3558 struct iterate_module_ctx *ctx)
3559 {
3560 struct gaudi2_ack_pb_tpc_data *pb_data = ctx->data;
3561
3562 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3563 gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size);
3564
3565 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3566 gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size);
3567 }
3568
gaudi2_ack_pb_tpc(struct hl_device * hdev)3569 static void gaudi2_ack_pb_tpc(struct hl_device *hdev)
3570 {
3571 struct iterate_module_ctx tpc_iter = {
3572 .fn = &gaudi2_ack_pb_tpc_config,
3573 };
3574 struct gaudi2_ack_pb_tpc_data data;
3575
3576 data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
3577 data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
3578 tpc_iter.data = &data;
3579
3580 gaudi2_iterate_tpcs(hdev, &tpc_iter);
3581 }
3582
3583 /**
3584 * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits
3585 * and for every protection error found, display the appropriate error message
3586 * and clear the error.
3587 *
3588 * @hdev: pointer to hl_device structure
3589 *
3590 * All protection bits are 1 by default, means not protected. Need to set to 0
3591 * each bit that belongs to a protected register.
3592 *
3593 */
gaudi2_ack_protection_bits_errors(struct hl_device * hdev)3594 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
3595 {
3596 struct asic_fixed_properties *prop = &hdev->asic_prop;
3597 u32 instance_offset;
3598 u8 i;
3599
3600 /* SFT */
3601 instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3602 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3603 gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0));
3604
3605 /* HIF */
3606 instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3607 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3608 NUM_OF_HIF_PER_DCORE, instance_offset,
3609 gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3610 prop->hmmu_hif_enabled_mask);
3611
3612 /* RTR */
3613 instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3614 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3615 gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0));
3616
3617 /* HMMU */
3618 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3619 NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3620 gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3621 prop->hmmu_hif_enabled_mask);
3622
3623 /* CPU.
3624 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3625 * by privileged RR.
3626 */
3627 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3628 gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if));
3629 if (!hdev->asic_prop.fw_security_enabled)
3630 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3631 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu));
3632
3633 /* KDMA */
3634 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3635 gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma));
3636
3637 /* PDMA */
3638 instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3639 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3640 gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0));
3641
3642 /* ARC PDMA */
3643 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3644 gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc));
3645
3646 /* EDMA */
3647 instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3648 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3649 instance_offset, gaudi2_pb_dcr0_edma0,
3650 ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3651 prop->edma_enabled_mask);
3652
3653 /* ARC EDMA */
3654 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3655 instance_offset, gaudi2_pb_dcr0_edma0_arc,
3656 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3657 prop->edma_enabled_mask);
3658
3659 /* MME */
3660 instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3661
3662 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3663 /* MME SBTE */
3664 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3665 instance_offset, gaudi2_pb_dcr0_mme_sbte,
3666 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte));
3667
3668 /* MME */
3669 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3670 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3671 gaudi2_pb_dcr0_mme_eng,
3672 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng));
3673 }
3674
3675 /*
3676 * we have special iteration for case in which we would like to
3677 * configure stubbed MME's ARC/QMAN
3678 */
3679 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3680 /* MME QM */
3681 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3682 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3683 gaudi2_pb_dcr0_mme_qm,
3684 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm));
3685
3686 /* ARC MME */
3687 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3688 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3689 gaudi2_pb_dcr0_mme_arc,
3690 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc));
3691 }
3692
3693 /* MME QM ARC ACP ENG */
3694 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3695 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3696 gaudi2_pb_mme_qm_arc_acp_eng,
3697 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3698 (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3699
3700 /* TPC */
3701 gaudi2_ack_pb_tpc(hdev);
3702
3703 /* SRAM */
3704 instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3705 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3706 gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0));
3707
3708 /* Sync Manager MSTR IF */
3709 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3710 gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3711
3712 /* Sync Manager */
3713 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3714 gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl));
3715
3716 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3717 gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3718
3719 /* PSOC.
3720 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3721 * protected by privileged RR.
3722 */
3723 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3724 gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf));
3725 if (!hdev->asic_prop.fw_security_enabled)
3726 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3727 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc));
3728
3729 /* PMMU */
3730 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3731 gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu));
3732
3733 /* PLL.
3734 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3735 * privileged RR.
3736 */
3737 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3738 gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll));
3739 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3740 gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll));
3741 if (!hdev->asic_prop.fw_security_enabled) {
3742 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3743 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll));
3744 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3745 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll));
3746 }
3747
3748 /* PCIE */
3749 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3750 gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie));
3751
3752 /* Thermal Sensor.
3753 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3754 */
3755 if (!hdev->asic_prop.fw_security_enabled) {
3756 instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3757 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3758 gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0));
3759 }
3760
3761 /* HBM */
3762 instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;
3763 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3764 instance_offset, gaudi2_pb_hbm,
3765 ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask);
3766
3767 /* Scheduler ARCs */
3768 instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3769 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,
3770 instance_offset, gaudi2_pb_arc_sched,
3771 ARRAY_SIZE(gaudi2_pb_arc_sched));
3772
3773 /* XBAR MIDs */
3774 instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3775 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3776 instance_offset, gaudi2_pb_xbar_mid,
3777 ARRAY_SIZE(gaudi2_pb_xbar_mid));
3778
3779 /* XBAR EDGEs */
3780 instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3781 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3782 instance_offset, gaudi2_pb_xbar_edge,
3783 ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask);
3784
3785 /* NIC */
3786 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3787 gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
3788
3789 /* NIC QM and QPC */
3790 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3791 NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3792 hdev->nic_ports_mask);
3793
3794 /* NIC QM ARC */
3795 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3796 NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,
3797 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
3798
3799 /* NIC UMR */
3800 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3801 NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),
3802 hdev->nic_ports_mask);
3803
3804 /* Rotators */
3805 instance_offset = mmROT1_BASE - mmROT0_BASE;
3806 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3807 gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1));
3808
3809 /* Rotators ARCS */
3810 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3811 gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1));
3812 }
3813
3814 /*
3815 * Print PB security errors
3816 */
3817
gaudi2_pb_print_security_errors(struct hl_device * hdev,u32 block_addr,u32 cause,u32 offended_addr)3818 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
3819 u32 offended_addr)
3820 {
3821 int i = 0;
3822 const char *error_format =
3823 "Security error at block 0x%x, offending address 0x%x\n"
3824 "Cause 0x%x: %s %s %s %s %s %s %s %s\n";
3825 char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" };
3826
3827 if (!cause)
3828 return;
3829
3830 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD)
3831 mcause[i++] = "APB_PRIV_RD";
3832
3833 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD)
3834 mcause[i++] = "APB_SEC_RD";
3835
3836 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD)
3837 mcause[i++] = "APB_UNMAPPED_RD";
3838
3839 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR)
3840 mcause[i++] = "APB_PRIV_WR";
3841
3842 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR)
3843 mcause[i++] = "APB_SEC_WR";
3844
3845 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR)
3846 mcause[i++] = "APB_UNMAPPED_WR";
3847
3848 if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR)
3849 mcause[i++] = "EXT_SEC_WR";
3850
3851 if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR)
3852 mcause[i++] = "APB_EXT_UNMAPPED_WR";
3853
3854 dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,
3855 cause, mcause[0], mcause[1], mcause[2], mcause[3],
3856 mcause[4], mcause[5], mcause[6], mcause[7]);
3857 }
3858