1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/kexec.h>
57 #include <linux/numa.h>
58 #include <linux/pgtable.h>
59 #include <linux/overflow.h>
60 #include <linux/stackprotector.h>
61 #include <linux/cpuhotplug.h>
62 #include <linux/mc146818rtc.h>
63 #include <linux/acpi.h>
64
65 #include <asm/acpi.h>
66 #include <asm/cacheinfo.h>
67 #include <asm/desc.h>
68 #include <asm/nmi.h>
69 #include <asm/irq.h>
70 #include <asm/realmode.h>
71 #include <asm/cpu.h>
72 #include <asm/numa.h>
73 #include <asm/tlbflush.h>
74 #include <asm/mtrr.h>
75 #include <asm/mwait.h>
76 #include <asm/apic.h>
77 #include <asm/io_apic.h>
78 #include <asm/fpu/api.h>
79 #include <asm/setup.h>
80 #include <asm/uv/uv.h>
81 #include <asm/microcode.h>
82 #include <asm/i8259.h>
83 #include <asm/misc.h>
84 #include <asm/qspinlock.h>
85 #include <asm/intel-family.h>
86 #include <asm/cpu_device_id.h>
87 #include <asm/spec-ctrl.h>
88 #include <asm/hw_irq.h>
89 #include <asm/stackprotector.h>
90 #include <asm/sev.h>
91
92 /* representing HT siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
94 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
95
96 /* representing HT and core siblings of each logical CPU */
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
98 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
99
100 /* representing HT, core, and die siblings of each logical CPU */
101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
102 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
103
104 /* Per CPU bogomips and other parameters */
105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
106 EXPORT_PER_CPU_SYMBOL(cpu_info);
107
108 /* CPUs which are the primary SMT threads */
109 struct cpumask __cpu_primary_thread_mask __read_mostly;
110
111 /* Representing CPUs for which sibling maps can be computed */
112 static cpumask_var_t cpu_sibling_setup_mask;
113
114 struct mwait_cpu_dead {
115 unsigned int control;
116 unsigned int status;
117 };
118
119 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
120 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
121
122 /*
123 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
124 * that it's unlikely to be touched by other CPUs.
125 */
126 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
127
128 /* Logical package management. We might want to allocate that dynamically */
129 unsigned int __max_logical_packages __read_mostly;
130 EXPORT_SYMBOL(__max_logical_packages);
131 static unsigned int logical_packages __read_mostly;
132 static unsigned int logical_die __read_mostly;
133
134 /* Maximum number of SMT threads on any online core */
135 int __read_mostly __max_smt_threads = 1;
136
137 /* Flag to indicate if a complete sched domain rebuild is required */
138 bool x86_topology_update;
139
arch_update_cpu_topology(void)140 int arch_update_cpu_topology(void)
141 {
142 int retval = x86_topology_update;
143
144 x86_topology_update = false;
145 return retval;
146 }
147
148 static unsigned int smpboot_warm_reset_vector_count;
149
smpboot_setup_warm_reset_vector(unsigned long start_eip)150 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
151 {
152 unsigned long flags;
153
154 spin_lock_irqsave(&rtc_lock, flags);
155 if (!smpboot_warm_reset_vector_count++) {
156 CMOS_WRITE(0xa, 0xf);
157 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
158 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
159 }
160 spin_unlock_irqrestore(&rtc_lock, flags);
161 }
162
smpboot_restore_warm_reset_vector(void)163 static inline void smpboot_restore_warm_reset_vector(void)
164 {
165 unsigned long flags;
166
167 /*
168 * Paranoid: Set warm reset code and vector here back
169 * to default values.
170 */
171 spin_lock_irqsave(&rtc_lock, flags);
172 if (!--smpboot_warm_reset_vector_count) {
173 CMOS_WRITE(0, 0xf);
174 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
175 }
176 spin_unlock_irqrestore(&rtc_lock, flags);
177
178 }
179
180 /* Run the next set of setup steps for the upcoming CPU */
ap_starting(void)181 static void ap_starting(void)
182 {
183 int cpuid = smp_processor_id();
184
185 /* Mop up eventual mwait_play_dead() wreckage */
186 this_cpu_write(mwait_cpu_dead.status, 0);
187 this_cpu_write(mwait_cpu_dead.control, 0);
188
189 /*
190 * If woken up by an INIT in an 82489DX configuration the alive
191 * synchronization guarantees that the CPU does not reach this
192 * point before an INIT_deassert IPI reaches the local APIC, so it
193 * is now safe to touch the local APIC.
194 *
195 * Set up this CPU, first the APIC, which is probably redundant on
196 * most boards.
197 */
198 apic_ap_setup();
199
200 /* Save the processor parameters. */
201 smp_store_cpu_info(cpuid);
202
203 /*
204 * The topology information must be up to date before
205 * notify_cpu_starting().
206 */
207 set_cpu_sibling_map(cpuid);
208
209 ap_init_aperfmperf();
210
211 pr_debug("Stack at about %p\n", &cpuid);
212
213 wmb();
214
215 /*
216 * This runs the AP through all the cpuhp states to its target
217 * state CPUHP_ONLINE.
218 */
219 notify_cpu_starting(cpuid);
220 }
221
ap_calibrate_delay(void)222 static void ap_calibrate_delay(void)
223 {
224 /*
225 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
226 * smp_store_cpu_info() stored a value that is close but not as
227 * accurate as the value just calculated.
228 *
229 * As this is invoked after the TSC synchronization check,
230 * calibrate_delay_is_known() will skip the calibration routine
231 * when TSC is synchronized across sockets.
232 */
233 calibrate_delay();
234 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
235 }
236
237 /*
238 * Activate a secondary processor.
239 */
start_secondary(void * unused)240 static void notrace start_secondary(void *unused)
241 {
242 /*
243 * Don't put *anything* except direct CPU state initialization
244 * before cpu_init(), SMP booting is too fragile that we want to
245 * limit the things done here to the most necessary things.
246 */
247 cr4_init();
248
249 /*
250 * 32-bit specific. 64-bit reaches this code with the correct page
251 * table established. Yet another historical divergence.
252 */
253 if (IS_ENABLED(CONFIG_X86_32)) {
254 /* switch away from the initial page table */
255 load_cr3(swapper_pg_dir);
256 __flush_tlb_all();
257 }
258
259 cpu_init_exception_handling();
260
261 /*
262 * Load the microcode before reaching the AP alive synchronization
263 * point below so it is not part of the full per CPU serialized
264 * bringup part when "parallel" bringup is enabled.
265 *
266 * That's even safe when hyperthreading is enabled in the CPU as
267 * the core code starts the primary threads first and leaves the
268 * secondary threads waiting for SIPI. Loading microcode on
269 * physical cores concurrently is a safe operation.
270 *
271 * This covers both the Intel specific issue that concurrent
272 * microcode loading on SMT siblings must be prohibited and the
273 * vendor independent issue`that microcode loading which changes
274 * CPUID, MSRs etc. must be strictly serialized to maintain
275 * software state correctness.
276 */
277 load_ucode_ap();
278
279 /*
280 * Synchronization point with the hotplug core. Sets this CPUs
281 * synchronization state to ALIVE and spin-waits for the control CPU to
282 * release this CPU for further bringup.
283 */
284 cpuhp_ap_sync_alive();
285
286 cpu_init();
287 fpu__init_cpu();
288 rcu_cpu_starting(raw_smp_processor_id());
289 x86_cpuinit.early_percpu_clock_init();
290
291 ap_starting();
292
293 /* Check TSC synchronization with the control CPU. */
294 check_tsc_sync_target();
295
296 /*
297 * Calibrate the delay loop after the TSC synchronization check.
298 * This allows to skip the calibration when TSC is synchronized
299 * across sockets.
300 */
301 ap_calibrate_delay();
302
303 speculative_store_bypass_ht_init();
304
305 /*
306 * Lock vector_lock, set CPU online and bring the vector
307 * allocator online. Online must be set with vector_lock held
308 * to prevent a concurrent irq setup/teardown from seeing a
309 * half valid vector space.
310 */
311 lock_vector_lock();
312 set_cpu_online(smp_processor_id(), true);
313 lapic_online();
314 unlock_vector_lock();
315 x86_platform.nmi_init();
316
317 /* enable local interrupts */
318 local_irq_enable();
319
320 x86_cpuinit.setup_percpu_clockev();
321
322 wmb();
323 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
324 }
325
326 /**
327 * topology_phys_to_logical_pkg - Map a physical package id to a logical
328 * @phys_pkg: The physical package id to map
329 *
330 * Returns logical package id or -1 if not found
331 */
topology_phys_to_logical_pkg(unsigned int phys_pkg)332 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
333 {
334 int cpu;
335
336 for_each_possible_cpu(cpu) {
337 struct cpuinfo_x86 *c = &cpu_data(cpu);
338
339 if (c->initialized && c->phys_proc_id == phys_pkg)
340 return c->logical_proc_id;
341 }
342 return -1;
343 }
344 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
345
346 /**
347 * topology_phys_to_logical_die - Map a physical die id to logical
348 * @die_id: The physical die id to map
349 * @cur_cpu: The CPU for which the mapping is done
350 *
351 * Returns logical die id or -1 if not found
352 */
topology_phys_to_logical_die(unsigned int die_id,unsigned int cur_cpu)353 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
354 {
355 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id;
356
357 for_each_possible_cpu(cpu) {
358 struct cpuinfo_x86 *c = &cpu_data(cpu);
359
360 if (c->initialized && c->cpu_die_id == die_id &&
361 c->phys_proc_id == proc_id)
362 return c->logical_die_id;
363 }
364 return -1;
365 }
366
367 /**
368 * topology_update_package_map - Update the physical to logical package map
369 * @pkg: The physical package id as retrieved via CPUID
370 * @cpu: The cpu for which this is updated
371 */
topology_update_package_map(unsigned int pkg,unsigned int cpu)372 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
373 {
374 int new;
375
376 /* Already available somewhere? */
377 new = topology_phys_to_logical_pkg(pkg);
378 if (new >= 0)
379 goto found;
380
381 new = logical_packages++;
382 if (new != pkg) {
383 pr_info("CPU %u Converting physical %u to logical package %u\n",
384 cpu, pkg, new);
385 }
386 found:
387 cpu_data(cpu).logical_proc_id = new;
388 return 0;
389 }
390 /**
391 * topology_update_die_map - Update the physical to logical die map
392 * @die: The die id as retrieved via CPUID
393 * @cpu: The cpu for which this is updated
394 */
topology_update_die_map(unsigned int die,unsigned int cpu)395 int topology_update_die_map(unsigned int die, unsigned int cpu)
396 {
397 int new;
398
399 /* Already available somewhere? */
400 new = topology_phys_to_logical_die(die, cpu);
401 if (new >= 0)
402 goto found;
403
404 new = logical_die++;
405 if (new != die) {
406 pr_info("CPU %u Converting physical %u to logical die %u\n",
407 cpu, die, new);
408 }
409 found:
410 cpu_data(cpu).logical_die_id = new;
411 return 0;
412 }
413
smp_store_boot_cpu_info(void)414 static void __init smp_store_boot_cpu_info(void)
415 {
416 int id = 0; /* CPU 0 */
417 struct cpuinfo_x86 *c = &cpu_data(id);
418
419 *c = boot_cpu_data;
420 c->cpu_index = id;
421 topology_update_package_map(c->phys_proc_id, id);
422 topology_update_die_map(c->cpu_die_id, id);
423 c->initialized = true;
424 }
425
426 /*
427 * The bootstrap kernel entry code has set these up. Save them for
428 * a given CPU
429 */
smp_store_cpu_info(int id)430 void smp_store_cpu_info(int id)
431 {
432 struct cpuinfo_x86 *c = &cpu_data(id);
433
434 /* Copy boot_cpu_data only on the first bringup */
435 if (!c->initialized)
436 *c = boot_cpu_data;
437 c->cpu_index = id;
438 /*
439 * During boot time, CPU0 has this setup already. Save the info when
440 * bringing up an AP.
441 */
442 identify_secondary_cpu(c);
443 c->initialized = true;
444 }
445
446 static bool
topology_same_node(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)447 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
448 {
449 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
450
451 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
452 }
453
454 static bool
topology_sane(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o,const char * name)455 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
456 {
457 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
458
459 return !WARN_ONCE(!topology_same_node(c, o),
460 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
461 "[node: %d != %d]. Ignoring dependency.\n",
462 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
463 }
464
465 #define link_mask(mfunc, c1, c2) \
466 do { \
467 cpumask_set_cpu((c1), mfunc(c2)); \
468 cpumask_set_cpu((c2), mfunc(c1)); \
469 } while (0)
470
match_smt(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)471 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
472 {
473 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
474 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
475
476 if (c->phys_proc_id == o->phys_proc_id &&
477 c->cpu_die_id == o->cpu_die_id &&
478 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
479 if (c->cpu_core_id == o->cpu_core_id)
480 return topology_sane(c, o, "smt");
481
482 if ((c->cu_id != 0xff) &&
483 (o->cu_id != 0xff) &&
484 (c->cu_id == o->cu_id))
485 return topology_sane(c, o, "smt");
486 }
487
488 } else if (c->phys_proc_id == o->phys_proc_id &&
489 c->cpu_die_id == o->cpu_die_id &&
490 c->cpu_core_id == o->cpu_core_id) {
491 return topology_sane(c, o, "smt");
492 }
493
494 return false;
495 }
496
match_die(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)497 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
498 {
499 if (c->phys_proc_id == o->phys_proc_id &&
500 c->cpu_die_id == o->cpu_die_id)
501 return true;
502 return false;
503 }
504
match_l2c(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)505 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
506 {
507 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
508
509 /* If the arch didn't set up l2c_id, fall back to SMT */
510 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID)
511 return match_smt(c, o);
512
513 /* Do not match if L2 cache id does not match: */
514 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2))
515 return false;
516
517 return topology_sane(c, o, "l2c");
518 }
519
520 /*
521 * Unlike the other levels, we do not enforce keeping a
522 * multicore group inside a NUMA node. If this happens, we will
523 * discard the MC level of the topology later.
524 */
match_pkg(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)525 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
526 {
527 if (c->phys_proc_id == o->phys_proc_id)
528 return true;
529 return false;
530 }
531
532 /*
533 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
534 *
535 * Any Intel CPU that has multiple nodes per package and does not
536 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
537 *
538 * When in SNC mode, these CPUs enumerate an LLC that is shared
539 * by multiple NUMA nodes. The LLC is shared for off-package data
540 * access but private to the NUMA node (half of the package) for
541 * on-package access. CPUID (the source of the information about
542 * the LLC) can only enumerate the cache as shared or unshared,
543 * but not this particular configuration.
544 */
545
546 static const struct x86_cpu_id intel_cod_cpu[] = {
547 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
548 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
549 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
550 {}
551 };
552
match_llc(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)553 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
554 {
555 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
556 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
557 bool intel_snc = id && id->driver_data;
558
559 /* Do not match if we do not have a valid APICID for cpu: */
560 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
561 return false;
562
563 /* Do not match if LLC id does not match: */
564 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
565 return false;
566
567 /*
568 * Allow the SNC topology without warning. Return of false
569 * means 'c' does not share the LLC of 'o'. This will be
570 * reflected to userspace.
571 */
572 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
573 return false;
574
575 return topology_sane(c, o, "llc");
576 }
577
578
x86_sched_itmt_flags(void)579 static inline int x86_sched_itmt_flags(void)
580 {
581 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
582 }
583
584 #ifdef CONFIG_SCHED_MC
x86_core_flags(void)585 static int x86_core_flags(void)
586 {
587 return cpu_core_flags() | x86_sched_itmt_flags();
588 }
589 #endif
590 #ifdef CONFIG_SCHED_SMT
x86_smt_flags(void)591 static int x86_smt_flags(void)
592 {
593 return cpu_smt_flags();
594 }
595 #endif
596 #ifdef CONFIG_SCHED_CLUSTER
x86_cluster_flags(void)597 static int x86_cluster_flags(void)
598 {
599 return cpu_cluster_flags() | x86_sched_itmt_flags();
600 }
601 #endif
602
603 /*
604 * Set if a package/die has multiple NUMA nodes inside.
605 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
606 * Sub-NUMA Clustering have this.
607 */
608 static bool x86_has_numa_in_package;
609
610 static struct sched_domain_topology_level x86_topology[6];
611
build_sched_topology(void)612 static void __init build_sched_topology(void)
613 {
614 int i = 0;
615
616 #ifdef CONFIG_SCHED_SMT
617 x86_topology[i++] = (struct sched_domain_topology_level){
618 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
619 };
620 #endif
621 #ifdef CONFIG_SCHED_CLUSTER
622 x86_topology[i++] = (struct sched_domain_topology_level){
623 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
624 };
625 #endif
626 #ifdef CONFIG_SCHED_MC
627 x86_topology[i++] = (struct sched_domain_topology_level){
628 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
629 };
630 #endif
631 /*
632 * When there is NUMA topology inside the package skip the PKG domain
633 * since the NUMA domains will auto-magically create the right spanning
634 * domains based on the SLIT.
635 */
636 if (!x86_has_numa_in_package) {
637 x86_topology[i++] = (struct sched_domain_topology_level){
638 cpu_cpu_mask, x86_sched_itmt_flags, SD_INIT_NAME(PKG)
639 };
640 }
641
642 /*
643 * There must be one trailing NULL entry left.
644 */
645 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
646
647 set_sched_topology(x86_topology);
648 }
649
set_cpu_sibling_map(int cpu)650 void set_cpu_sibling_map(int cpu)
651 {
652 bool has_smt = smp_num_siblings > 1;
653 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
654 struct cpuinfo_x86 *c = &cpu_data(cpu);
655 struct cpuinfo_x86 *o;
656 int i, threads;
657
658 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
659
660 if (!has_mp) {
661 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
662 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
663 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
664 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
665 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
666 c->booted_cores = 1;
667 return;
668 }
669
670 for_each_cpu(i, cpu_sibling_setup_mask) {
671 o = &cpu_data(i);
672
673 if (match_pkg(c, o) && !topology_same_node(c, o))
674 x86_has_numa_in_package = true;
675
676 if ((i == cpu) || (has_smt && match_smt(c, o)))
677 link_mask(topology_sibling_cpumask, cpu, i);
678
679 if ((i == cpu) || (has_mp && match_llc(c, o)))
680 link_mask(cpu_llc_shared_mask, cpu, i);
681
682 if ((i == cpu) || (has_mp && match_l2c(c, o)))
683 link_mask(cpu_l2c_shared_mask, cpu, i);
684
685 if ((i == cpu) || (has_mp && match_die(c, o)))
686 link_mask(topology_die_cpumask, cpu, i);
687 }
688
689 threads = cpumask_weight(topology_sibling_cpumask(cpu));
690 if (threads > __max_smt_threads)
691 __max_smt_threads = threads;
692
693 for_each_cpu(i, topology_sibling_cpumask(cpu))
694 cpu_data(i).smt_active = threads > 1;
695
696 /*
697 * This needs a separate iteration over the cpus because we rely on all
698 * topology_sibling_cpumask links to be set-up.
699 */
700 for_each_cpu(i, cpu_sibling_setup_mask) {
701 o = &cpu_data(i);
702
703 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
704 link_mask(topology_core_cpumask, cpu, i);
705
706 /*
707 * Does this new cpu bringup a new core?
708 */
709 if (threads == 1) {
710 /*
711 * for each core in package, increment
712 * the booted_cores for this new cpu
713 */
714 if (cpumask_first(
715 topology_sibling_cpumask(i)) == i)
716 c->booted_cores++;
717 /*
718 * increment the core count for all
719 * the other cpus in this package
720 */
721 if (i != cpu)
722 cpu_data(i).booted_cores++;
723 } else if (i != cpu && !c->booted_cores)
724 c->booted_cores = cpu_data(i).booted_cores;
725 }
726 }
727 }
728
729 /* maps the cpu to the sched domain representing multi-core */
cpu_coregroup_mask(int cpu)730 const struct cpumask *cpu_coregroup_mask(int cpu)
731 {
732 return cpu_llc_shared_mask(cpu);
733 }
734
cpu_clustergroup_mask(int cpu)735 const struct cpumask *cpu_clustergroup_mask(int cpu)
736 {
737 return cpu_l2c_shared_mask(cpu);
738 }
739
impress_friends(void)740 static void impress_friends(void)
741 {
742 int cpu;
743 unsigned long bogosum = 0;
744 /*
745 * Allow the user to impress friends.
746 */
747 pr_debug("Before bogomips\n");
748 for_each_online_cpu(cpu)
749 bogosum += cpu_data(cpu).loops_per_jiffy;
750
751 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
752 num_online_cpus(),
753 bogosum/(500000/HZ),
754 (bogosum/(5000/HZ))%100);
755
756 pr_debug("Before bogocount - setting activated=1\n");
757 }
758
759 /*
760 * The Multiprocessor Specification 1.4 (1997) example code suggests
761 * that there should be a 10ms delay between the BSP asserting INIT
762 * and de-asserting INIT, when starting a remote processor.
763 * But that slows boot and resume on modern processors, which include
764 * many cores and don't require that delay.
765 *
766 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
767 * Modern processor families are quirked to remove the delay entirely.
768 */
769 #define UDELAY_10MS_DEFAULT 10000
770
771 static unsigned int init_udelay = UINT_MAX;
772
cpu_init_udelay(char * str)773 static int __init cpu_init_udelay(char *str)
774 {
775 get_option(&str, &init_udelay);
776
777 return 0;
778 }
779 early_param("cpu_init_udelay", cpu_init_udelay);
780
smp_quirk_init_udelay(void)781 static void __init smp_quirk_init_udelay(void)
782 {
783 /* if cmdline changed it from default, leave it alone */
784 if (init_udelay != UINT_MAX)
785 return;
786
787 /* if modern processor, use no delay */
788 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
789 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
790 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
791 init_udelay = 0;
792 return;
793 }
794 /* else, use legacy delay */
795 init_udelay = UDELAY_10MS_DEFAULT;
796 }
797
798 /*
799 * Wake up AP by INIT, INIT, STARTUP sequence.
800 */
send_init_sequence(int phys_apicid)801 static void send_init_sequence(int phys_apicid)
802 {
803 int maxlvt = lapic_get_maxlvt();
804
805 /* Be paranoid about clearing APIC errors. */
806 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
807 /* Due to the Pentium erratum 3AP. */
808 if (maxlvt > 3)
809 apic_write(APIC_ESR, 0);
810 apic_read(APIC_ESR);
811 }
812
813 /* Assert INIT on the target CPU */
814 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
815 safe_apic_wait_icr_idle();
816
817 udelay(init_udelay);
818
819 /* Deassert INIT on the target CPU */
820 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
821 safe_apic_wait_icr_idle();
822 }
823
824 /*
825 * Wake up AP by INIT, INIT, STARTUP sequence.
826 */
wakeup_secondary_cpu_via_init(int phys_apicid,unsigned long start_eip)827 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
828 {
829 unsigned long send_status = 0, accept_status = 0;
830 int num_starts, j, maxlvt;
831
832 preempt_disable();
833 maxlvt = lapic_get_maxlvt();
834 send_init_sequence(phys_apicid);
835
836 mb();
837
838 /*
839 * Should we send STARTUP IPIs ?
840 *
841 * Determine this based on the APIC version.
842 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
843 */
844 if (APIC_INTEGRATED(boot_cpu_apic_version))
845 num_starts = 2;
846 else
847 num_starts = 0;
848
849 /*
850 * Run STARTUP IPI loop.
851 */
852 pr_debug("#startup loops: %d\n", num_starts);
853
854 for (j = 1; j <= num_starts; j++) {
855 pr_debug("Sending STARTUP #%d\n", j);
856 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
857 apic_write(APIC_ESR, 0);
858 apic_read(APIC_ESR);
859 pr_debug("After apic_write\n");
860
861 /*
862 * STARTUP IPI
863 */
864
865 /* Target chip */
866 /* Boot on the stack */
867 /* Kick the second */
868 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
869 phys_apicid);
870
871 /*
872 * Give the other CPU some time to accept the IPI.
873 */
874 if (init_udelay == 0)
875 udelay(10);
876 else
877 udelay(300);
878
879 pr_debug("Startup point 1\n");
880
881 pr_debug("Waiting for send to finish...\n");
882 send_status = safe_apic_wait_icr_idle();
883
884 /*
885 * Give the other CPU some time to accept the IPI.
886 */
887 if (init_udelay == 0)
888 udelay(10);
889 else
890 udelay(200);
891
892 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
893 apic_write(APIC_ESR, 0);
894 accept_status = (apic_read(APIC_ESR) & 0xEF);
895 if (send_status || accept_status)
896 break;
897 }
898 pr_debug("After Startup\n");
899
900 if (send_status)
901 pr_err("APIC never delivered???\n");
902 if (accept_status)
903 pr_err("APIC delivery error (%lx)\n", accept_status);
904
905 preempt_enable();
906 return (send_status | accept_status);
907 }
908
909 /* reduce the number of lines printed when booting a large cpu count system */
announce_cpu(int cpu,int apicid)910 static void announce_cpu(int cpu, int apicid)
911 {
912 static int width, node_width, first = 1;
913 static int current_node = NUMA_NO_NODE;
914 int node = early_cpu_to_node(cpu);
915
916 if (!width)
917 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
918
919 if (!node_width)
920 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
921
922 if (system_state < SYSTEM_RUNNING) {
923 if (first)
924 pr_info("x86: Booting SMP configuration:\n");
925
926 if (node != current_node) {
927 if (current_node > (-1))
928 pr_cont("\n");
929 current_node = node;
930
931 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
932 node_width - num_digits(node), " ", node);
933 }
934
935 /* Add padding for the BSP */
936 if (first)
937 pr_cont("%*s", width + 1, " ");
938 first = 0;
939
940 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
941 } else
942 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
943 node, cpu, apicid);
944 }
945
common_cpu_up(unsigned int cpu,struct task_struct * idle)946 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
947 {
948 int ret;
949
950 /* Just in case we booted with a single CPU. */
951 alternatives_enable_smp();
952
953 per_cpu(pcpu_hot.current_task, cpu) = idle;
954 cpu_init_stack_canary(cpu, idle);
955
956 /* Initialize the interrupt stack(s) */
957 ret = irq_init_percpu_irqstack(cpu);
958 if (ret)
959 return ret;
960
961 #ifdef CONFIG_X86_32
962 /* Stack for startup_32 can be just as for start_secondary onwards */
963 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
964 #endif
965 return 0;
966 }
967
968 /*
969 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
970 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
971 * Returns zero if startup was successfully sent, else error code from
972 * ->wakeup_secondary_cpu.
973 */
do_boot_cpu(int apicid,int cpu,struct task_struct * idle)974 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
975 {
976 unsigned long start_ip = real_mode_header->trampoline_start;
977 int ret;
978
979 #ifdef CONFIG_X86_64
980 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
981 if (apic->wakeup_secondary_cpu_64)
982 start_ip = real_mode_header->trampoline_start64;
983 #endif
984 idle->thread.sp = (unsigned long)task_pt_regs(idle);
985 initial_code = (unsigned long)start_secondary;
986
987 if (IS_ENABLED(CONFIG_X86_32)) {
988 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
989 initial_stack = idle->thread.sp;
990 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
991 smpboot_control = cpu;
992 }
993
994 /* Enable the espfix hack for this CPU */
995 init_espfix_ap(cpu);
996
997 /* So we see what's up */
998 announce_cpu(cpu, apicid);
999
1000 /*
1001 * This grunge runs the startup process for
1002 * the targeted processor.
1003 */
1004 if (x86_platform.legacy.warm_reset) {
1005
1006 pr_debug("Setting warm reset code and vector.\n");
1007
1008 smpboot_setup_warm_reset_vector(start_ip);
1009 /*
1010 * Be paranoid about clearing APIC errors.
1011 */
1012 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1013 apic_write(APIC_ESR, 0);
1014 apic_read(APIC_ESR);
1015 }
1016 }
1017
1018 smp_mb();
1019
1020 /*
1021 * Wake up a CPU in difference cases:
1022 * - Use a method from the APIC driver if one defined, with wakeup
1023 * straight to 64-bit mode preferred over wakeup to RM.
1024 * Otherwise,
1025 * - Use an INIT boot APIC message
1026 */
1027 if (apic->wakeup_secondary_cpu_64)
1028 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
1029 else if (apic->wakeup_secondary_cpu)
1030 ret = apic->wakeup_secondary_cpu(apicid, start_ip);
1031 else
1032 ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
1033
1034 /* If the wakeup mechanism failed, cleanup the warm reset vector */
1035 if (ret)
1036 arch_cpuhp_cleanup_kick_cpu(cpu);
1037 return ret;
1038 }
1039
native_kick_ap(unsigned int cpu,struct task_struct * tidle)1040 int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
1041 {
1042 int apicid = apic->cpu_present_to_apicid(cpu);
1043 int err;
1044
1045 lockdep_assert_irqs_enabled();
1046
1047 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1048
1049 if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) ||
1050 !apic_id_valid(apicid)) {
1051 pr_err("%s: bad cpu %d\n", __func__, cpu);
1052 return -EINVAL;
1053 }
1054
1055 /*
1056 * Save current MTRR state in case it was changed since early boot
1057 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1058 */
1059 mtrr_save_state();
1060
1061 /* the FPU context is blank, nobody can own it */
1062 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1063
1064 err = common_cpu_up(cpu, tidle);
1065 if (err)
1066 return err;
1067
1068 err = do_boot_cpu(apicid, cpu, tidle);
1069 if (err)
1070 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1071
1072 return err;
1073 }
1074
arch_cpuhp_kick_ap_alive(unsigned int cpu,struct task_struct * tidle)1075 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
1076 {
1077 return smp_ops.kick_ap_alive(cpu, tidle);
1078 }
1079
arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)1080 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
1081 {
1082 /* Cleanup possible dangling ends... */
1083 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
1084 smpboot_restore_warm_reset_vector();
1085 }
1086
arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)1087 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
1088 {
1089 if (smp_ops.cleanup_dead_cpu)
1090 smp_ops.cleanup_dead_cpu(cpu);
1091
1092 if (system_state == SYSTEM_RUNNING)
1093 pr_info("CPU %u is now offline\n", cpu);
1094 }
1095
arch_cpuhp_sync_state_poll(void)1096 void arch_cpuhp_sync_state_poll(void)
1097 {
1098 if (smp_ops.poll_sync_state)
1099 smp_ops.poll_sync_state();
1100 }
1101
1102 /**
1103 * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1104 */
arch_disable_smp_support(void)1105 void __init arch_disable_smp_support(void)
1106 {
1107 disable_ioapic_support();
1108 }
1109
1110 /*
1111 * Fall back to non SMP mode after errors.
1112 *
1113 * RED-PEN audit/test this more. I bet there is more state messed up here.
1114 */
disable_smp(void)1115 static __init void disable_smp(void)
1116 {
1117 pr_info("SMP disabled\n");
1118
1119 disable_ioapic_support();
1120
1121 init_cpu_present(cpumask_of(0));
1122 init_cpu_possible(cpumask_of(0));
1123
1124 if (smp_found_config)
1125 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1126 else
1127 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1128 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1129 cpumask_set_cpu(0, topology_core_cpumask(0));
1130 cpumask_set_cpu(0, topology_die_cpumask(0));
1131 }
1132
smp_cpu_index_default(void)1133 static void __init smp_cpu_index_default(void)
1134 {
1135 int i;
1136 struct cpuinfo_x86 *c;
1137
1138 for_each_possible_cpu(i) {
1139 c = &cpu_data(i);
1140 /* mark all to hotplug */
1141 c->cpu_index = nr_cpu_ids;
1142 }
1143 }
1144
smp_prepare_cpus_common(void)1145 void __init smp_prepare_cpus_common(void)
1146 {
1147 unsigned int i;
1148
1149 smp_cpu_index_default();
1150
1151 /*
1152 * Setup boot CPU information
1153 */
1154 smp_store_boot_cpu_info(); /* Final full version of the data */
1155 mb();
1156
1157 for_each_possible_cpu(i) {
1158 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1159 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1160 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1161 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1162 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1163 }
1164
1165 set_cpu_sibling_map(0);
1166 }
1167
1168 #ifdef CONFIG_X86_64
1169 /* Establish whether parallel bringup can be supported. */
arch_cpuhp_init_parallel_bringup(void)1170 bool __init arch_cpuhp_init_parallel_bringup(void)
1171 {
1172 if (!x86_cpuinit.parallel_bringup) {
1173 pr_info("Parallel CPU startup disabled by the platform\n");
1174 return false;
1175 }
1176
1177 smpboot_control = STARTUP_READ_APICID;
1178 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1179 return true;
1180 }
1181 #endif
1182
1183 /*
1184 * Prepare for SMP bootup.
1185 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1186 * for common interface support.
1187 */
native_smp_prepare_cpus(unsigned int max_cpus)1188 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1189 {
1190 smp_prepare_cpus_common();
1191
1192 switch (apic_intr_mode) {
1193 case APIC_PIC:
1194 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1195 disable_smp();
1196 return;
1197 case APIC_SYMMETRIC_IO_NO_ROUTING:
1198 disable_smp();
1199 /* Setup local timer */
1200 x86_init.timers.setup_percpu_clockev();
1201 return;
1202 case APIC_VIRTUAL_WIRE:
1203 case APIC_SYMMETRIC_IO:
1204 break;
1205 }
1206
1207 /* Setup local timer */
1208 x86_init.timers.setup_percpu_clockev();
1209
1210 pr_info("CPU0: ");
1211 print_cpu_info(&cpu_data(0));
1212
1213 uv_system_init();
1214
1215 smp_quirk_init_udelay();
1216
1217 speculative_store_bypass_ht_init();
1218
1219 snp_set_wakeup_secondary_cpu();
1220 }
1221
arch_thaw_secondary_cpus_begin(void)1222 void arch_thaw_secondary_cpus_begin(void)
1223 {
1224 set_cache_aps_delayed_init(true);
1225 }
1226
arch_thaw_secondary_cpus_end(void)1227 void arch_thaw_secondary_cpus_end(void)
1228 {
1229 cache_aps_init();
1230 }
1231
1232 /*
1233 * Early setup to make printk work.
1234 */
native_smp_prepare_boot_cpu(void)1235 void __init native_smp_prepare_boot_cpu(void)
1236 {
1237 int me = smp_processor_id();
1238
1239 /* SMP handles this from setup_per_cpu_areas() */
1240 if (!IS_ENABLED(CONFIG_SMP))
1241 switch_gdt_and_percpu_base(me);
1242
1243 native_pv_lock_init();
1244 }
1245
calculate_max_logical_packages(void)1246 void __init calculate_max_logical_packages(void)
1247 {
1248 int ncpus;
1249
1250 /*
1251 * Today neither Intel nor AMD support heterogeneous systems so
1252 * extrapolate the boot cpu's data to all packages.
1253 */
1254 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1255 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1256 pr_info("Max logical packages: %u\n", __max_logical_packages);
1257 }
1258
native_smp_cpus_done(unsigned int max_cpus)1259 void __init native_smp_cpus_done(unsigned int max_cpus)
1260 {
1261 pr_debug("Boot done\n");
1262
1263 calculate_max_logical_packages();
1264 build_sched_topology();
1265 nmi_selftest();
1266 impress_friends();
1267 cache_aps_init();
1268 }
1269
1270 static int __initdata setup_possible_cpus = -1;
_setup_possible_cpus(char * str)1271 static int __init _setup_possible_cpus(char *str)
1272 {
1273 get_option(&str, &setup_possible_cpus);
1274 return 0;
1275 }
1276 early_param("possible_cpus", _setup_possible_cpus);
1277
1278
1279 /*
1280 * cpu_possible_mask should be static, it cannot change as cpu's
1281 * are onlined, or offlined. The reason is per-cpu data-structures
1282 * are allocated by some modules at init time, and don't expect to
1283 * do this dynamically on cpu arrival/departure.
1284 * cpu_present_mask on the other hand can change dynamically.
1285 * In case when cpu_hotplug is not compiled, then we resort to current
1286 * behaviour, which is cpu_possible == cpu_present.
1287 * - Ashok Raj
1288 *
1289 * Three ways to find out the number of additional hotplug CPUs:
1290 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1291 * - The user can overwrite it with possible_cpus=NUM
1292 * - Otherwise don't reserve additional CPUs.
1293 * We do this because additional CPUs waste a lot of memory.
1294 * -AK
1295 */
prefill_possible_map(void)1296 __init void prefill_possible_map(void)
1297 {
1298 int i, possible;
1299
1300 i = setup_max_cpus ?: 1;
1301 if (setup_possible_cpus == -1) {
1302 possible = num_processors;
1303 #ifdef CONFIG_HOTPLUG_CPU
1304 if (setup_max_cpus)
1305 possible += disabled_cpus;
1306 #else
1307 if (possible > i)
1308 possible = i;
1309 #endif
1310 } else
1311 possible = setup_possible_cpus;
1312
1313 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1314
1315 /* nr_cpu_ids could be reduced via nr_cpus= */
1316 if (possible > nr_cpu_ids) {
1317 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1318 possible, nr_cpu_ids);
1319 possible = nr_cpu_ids;
1320 }
1321
1322 #ifdef CONFIG_HOTPLUG_CPU
1323 if (!setup_max_cpus)
1324 #endif
1325 if (possible > i) {
1326 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1327 possible, setup_max_cpus);
1328 possible = i;
1329 }
1330
1331 set_nr_cpu_ids(possible);
1332
1333 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1334 possible, max_t(int, possible - num_processors, 0));
1335
1336 reset_cpu_possible_mask();
1337
1338 for (i = 0; i < possible; i++)
1339 set_cpu_possible(i, true);
1340 }
1341
1342 /* correctly size the local cpu masks */
setup_cpu_local_masks(void)1343 void __init setup_cpu_local_masks(void)
1344 {
1345 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1346 }
1347
1348 #ifdef CONFIG_HOTPLUG_CPU
1349
1350 /* Recompute SMT state for all CPUs on offline */
recompute_smt_state(void)1351 static void recompute_smt_state(void)
1352 {
1353 int max_threads, cpu;
1354
1355 max_threads = 0;
1356 for_each_online_cpu (cpu) {
1357 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1358
1359 if (threads > max_threads)
1360 max_threads = threads;
1361 }
1362 __max_smt_threads = max_threads;
1363 }
1364
remove_siblinginfo(int cpu)1365 static void remove_siblinginfo(int cpu)
1366 {
1367 int sibling;
1368 struct cpuinfo_x86 *c = &cpu_data(cpu);
1369
1370 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1371 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1372 /*/
1373 * last thread sibling in this cpu core going down
1374 */
1375 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1376 cpu_data(sibling).booted_cores--;
1377 }
1378
1379 for_each_cpu(sibling, topology_die_cpumask(cpu))
1380 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1381
1382 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1383 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1384 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1385 cpu_data(sibling).smt_active = false;
1386 }
1387
1388 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1389 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1390 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1391 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1392 cpumask_clear(cpu_llc_shared_mask(cpu));
1393 cpumask_clear(cpu_l2c_shared_mask(cpu));
1394 cpumask_clear(topology_sibling_cpumask(cpu));
1395 cpumask_clear(topology_core_cpumask(cpu));
1396 cpumask_clear(topology_die_cpumask(cpu));
1397 c->cpu_core_id = 0;
1398 c->booted_cores = 0;
1399 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1400 recompute_smt_state();
1401 }
1402
remove_cpu_from_maps(int cpu)1403 static void remove_cpu_from_maps(int cpu)
1404 {
1405 set_cpu_online(cpu, false);
1406 numa_remove_cpu(cpu);
1407 }
1408
cpu_disable_common(void)1409 void cpu_disable_common(void)
1410 {
1411 int cpu = smp_processor_id();
1412
1413 remove_siblinginfo(cpu);
1414
1415 /* It's now safe to remove this processor from the online map */
1416 lock_vector_lock();
1417 remove_cpu_from_maps(cpu);
1418 unlock_vector_lock();
1419 fixup_irqs();
1420 lapic_offline();
1421 }
1422
native_cpu_disable(void)1423 int native_cpu_disable(void)
1424 {
1425 int ret;
1426
1427 ret = lapic_can_unplug_cpu();
1428 if (ret)
1429 return ret;
1430
1431 cpu_disable_common();
1432
1433 /*
1434 * Disable the local APIC. Otherwise IPI broadcasts will reach
1435 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1436 * messages.
1437 *
1438 * Disabling the APIC must happen after cpu_disable_common()
1439 * which invokes fixup_irqs().
1440 *
1441 * Disabling the APIC preserves already set bits in IRR, but
1442 * an interrupt arriving after disabling the local APIC does not
1443 * set the corresponding IRR bit.
1444 *
1445 * fixup_irqs() scans IRR for set bits so it can raise a not
1446 * yet handled interrupt on the new destination CPU via an IPI
1447 * but obviously it can't do so for IRR bits which are not set.
1448 * IOW, interrupts arriving after disabling the local APIC will
1449 * be lost.
1450 */
1451 apic_soft_disable();
1452
1453 return 0;
1454 }
1455
play_dead_common(void)1456 void play_dead_common(void)
1457 {
1458 idle_task_exit();
1459
1460 cpuhp_ap_report_dead();
1461
1462 local_irq_disable();
1463 }
1464
1465 /*
1466 * We need to flush the caches before going to sleep, lest we have
1467 * dirty data in our caches when we come back up.
1468 */
mwait_play_dead(void)1469 static inline void mwait_play_dead(void)
1470 {
1471 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1472 unsigned int eax, ebx, ecx, edx;
1473 unsigned int highest_cstate = 0;
1474 unsigned int highest_subcstate = 0;
1475 int i;
1476
1477 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1478 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1479 return;
1480 if (!this_cpu_has(X86_FEATURE_MWAIT))
1481 return;
1482 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1483 return;
1484 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1485 return;
1486
1487 eax = CPUID_MWAIT_LEAF;
1488 ecx = 0;
1489 native_cpuid(&eax, &ebx, &ecx, &edx);
1490
1491 /*
1492 * eax will be 0 if EDX enumeration is not valid.
1493 * Initialized below to cstate, sub_cstate value when EDX is valid.
1494 */
1495 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1496 eax = 0;
1497 } else {
1498 edx >>= MWAIT_SUBSTATE_SIZE;
1499 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1500 if (edx & MWAIT_SUBSTATE_MASK) {
1501 highest_cstate = i;
1502 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1503 }
1504 }
1505 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1506 (highest_subcstate - 1);
1507 }
1508
1509 /* Set up state for the kexec() hack below */
1510 md->status = CPUDEAD_MWAIT_WAIT;
1511 md->control = CPUDEAD_MWAIT_WAIT;
1512
1513 wbinvd();
1514
1515 while (1) {
1516 /*
1517 * The CLFLUSH is a workaround for erratum AAI65 for
1518 * the Xeon 7400 series. It's not clear it is actually
1519 * needed, but it should be harmless in either case.
1520 * The WBINVD is insufficient due to the spurious-wakeup
1521 * case where we return around the loop.
1522 */
1523 mb();
1524 clflush(md);
1525 mb();
1526 __monitor(md, 0, 0);
1527 mb();
1528 __mwait(eax, 0);
1529
1530 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1531 /*
1532 * Kexec is about to happen. Don't go back into mwait() as
1533 * the kexec kernel might overwrite text and data including
1534 * page tables and stack. So mwait() would resume when the
1535 * monitor cache line is written to and then the CPU goes
1536 * south due to overwritten text, page tables and stack.
1537 *
1538 * Note: This does _NOT_ protect against a stray MCE, NMI,
1539 * SMI. They will resume execution at the instruction
1540 * following the HLT instruction and run into the problem
1541 * which this is trying to prevent.
1542 */
1543 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1544 while(1)
1545 native_halt();
1546 }
1547 }
1548 }
1549
1550 /*
1551 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1552 * mwait_play_dead().
1553 */
smp_kick_mwait_play_dead(void)1554 void smp_kick_mwait_play_dead(void)
1555 {
1556 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1557 struct mwait_cpu_dead *md;
1558 unsigned int cpu, i;
1559
1560 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1561 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1562
1563 /* Does it sit in mwait_play_dead() ? */
1564 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1565 continue;
1566
1567 /* Wait up to 5ms */
1568 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1569 /* Bring it out of mwait */
1570 WRITE_ONCE(md->control, newstate);
1571 udelay(5);
1572 }
1573
1574 if (READ_ONCE(md->status) != newstate)
1575 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1576 }
1577 }
1578
hlt_play_dead(void)1579 void __noreturn hlt_play_dead(void)
1580 {
1581 if (__this_cpu_read(cpu_info.x86) >= 4)
1582 wbinvd();
1583
1584 while (1)
1585 native_halt();
1586 }
1587
native_play_dead(void)1588 void native_play_dead(void)
1589 {
1590 play_dead_common();
1591 tboot_shutdown(TB_SHUTDOWN_WFS);
1592
1593 mwait_play_dead();
1594 if (cpuidle_play_dead())
1595 hlt_play_dead();
1596 }
1597
1598 #else /* ... !CONFIG_HOTPLUG_CPU */
native_cpu_disable(void)1599 int native_cpu_disable(void)
1600 {
1601 return -ENOSYS;
1602 }
1603
native_play_dead(void)1604 void native_play_dead(void)
1605 {
1606 BUG();
1607 }
1608
1609 #endif
1610