1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "hdp_v4_0.h"
26 #include "amdgpu_ras.h"
27
28 #include "hdp/hdp_4_0_offset.h"
29 #include "hdp/hdp_4_0_sh_mask.h"
30 #include <uapi/linux/kfd_ioctl.h>
31
32 /* for Vega20 register name change */
33 #define mmHDP_MEM_POWER_CTRL 0x00d4
34 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
35 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
36 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
37 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
38 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
39
hdp_v4_0_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)40 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
41 struct amdgpu_ring *ring)
42 {
43 if (!ring || !ring->funcs->emit_wreg) {
44 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
45 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
46 } else {
47 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
48 }
49 }
50
hdp_v4_0_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)51 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
52 struct amdgpu_ring *ring)
53 {
54 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0) ||
55 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 2))
56 return;
57
58 if (!ring || !ring->funcs->emit_wreg) {
59 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
60 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
61 } else {
62 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
63 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
64 }
65 }
66
hdp_v4_0_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)67 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
68 void *ras_error_status)
69 {
70 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
71
72 err_data->ue_count = 0;
73 err_data->ce_count = 0;
74
75 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
76 return;
77
78 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
79 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
80 };
81
hdp_v4_0_reset_ras_error_count(struct amdgpu_device * adev)82 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
83 {
84 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
85 return;
86
87 if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
88 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
89 else
90 /*read back hdp ras counter to reset it to 0 */
91 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
92 }
93
hdp_v4_0_update_clock_gating(struct amdgpu_device * adev,bool enable)94 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
95 bool enable)
96 {
97 uint32_t def, data;
98
99 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
100 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
101 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
102 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
103 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
104
105 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
106 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
107 else
108 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
109
110 if (def != data)
111 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
112 } else {
113 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
114
115 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
116 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
117 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
118 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
119 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
120 else
121 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
122 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
123 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
124 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
125
126 if (def != data)
127 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
128 }
129 }
130
hdp_v4_0_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)131 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
132 u64 *flags)
133 {
134 int data;
135
136 /* AMD_CG_SUPPORT_HDP_LS */
137 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
138 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
139 *flags |= AMD_CG_SUPPORT_HDP_LS;
140 }
141
hdp_v4_0_init_registers(struct amdgpu_device * adev)142 static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
143 {
144 switch (adev->ip_versions[HDP_HWIP][0]) {
145 case IP_VERSION(4, 2, 1):
146 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
147 break;
148 default:
149 break;
150 }
151
152 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
153
154 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
155 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
156
157 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
158 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
159 }
160
161 struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
162 .query_ras_error_count = hdp_v4_0_query_ras_error_count,
163 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
164 };
165
166 struct amdgpu_hdp_ras hdp_v4_0_ras = {
167 .ras_block = {
168 .hw_ops = &hdp_v4_0_ras_hw_ops,
169 },
170 };
171
172 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
173 .flush_hdp = hdp_v4_0_flush_hdp,
174 .invalidate_hdp = hdp_v4_0_invalidate_hdp,
175 .update_clock_gating = hdp_v4_0_update_clock_gating,
176 .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
177 .init_registers = hdp_v4_0_init_registers,
178 };
179