1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * OMAP5 HDMI CORE IP driver library
4  *
5  * Copyright (C) 2014 Texas Instruments Incorporated
6  *
7  * Authors:
8  *	Yong Zhi
9  *	Mythri pk
10  *	Archit Taneja <archit@ti.com>
11  *	Tomi Valkeinen <tomi.valkeinen@ti.com>
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/seq_file.h>
21 #include <drm/drm_edid.h>
22 #include <sound/asound.h>
23 #include <sound/asoundef.h>
24 
25 #include "hdmi5_core.h"
26 
27 /* only 24 bit color depth used for now */
28 static const struct csc_table csc_table_deepcolor[] = {
29 	/* HDMI_DEEP_COLOR_24BIT */
30 	[0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
31 	/* HDMI_DEEP_COLOR_30BIT */
32 	[1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
33 	/* HDMI_DEEP_COLOR_36BIT */
34 	[2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
35 	/* FULL RANGE */
36 	[3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
37 };
38 
hdmi_core_ddc_init(struct hdmi_core_data * core)39 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
40 {
41 	void __iomem *base = core->base;
42 	const unsigned long long iclk = 266000000;	/* DSS L3 ICLK */
43 	const unsigned ss_scl_high = 4600;		/* ns */
44 	const unsigned ss_scl_low = 5400;		/* ns */
45 	const unsigned fs_scl_high = 600;		/* ns */
46 	const unsigned fs_scl_low = 1300;		/* ns */
47 	const unsigned sda_hold = 1000;			/* ns */
48 	const unsigned sfr_div = 10;
49 	unsigned long long sfr;
50 	unsigned v;
51 
52 	sfr = iclk / sfr_div;	/* SFR_DIV */
53 	sfr /= 1000;		/* SFR clock in kHz */
54 
55 	/* Reset */
56 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
57 	if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
58 				0, 0, 1) != 1)
59 		DSSERR("HDMI I2CM reset failed\n");
60 
61 	/* Standard (0) or Fast (1) Mode */
62 	REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
63 
64 	/* Standard Mode SCL High counter */
65 	v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
66 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
67 			(v >> 8) & 0xff, 7, 0);
68 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
69 			v & 0xff, 7, 0);
70 
71 	/* Standard Mode SCL Low counter */
72 	v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
73 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
74 			(v >> 8) & 0xff, 7, 0);
75 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
76 			v & 0xff, 7, 0);
77 
78 	/* Fast Mode SCL High Counter */
79 	v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
80 	REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
81 			(v >> 8) & 0xff, 7, 0);
82 	REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
83 			v & 0xff, 7, 0);
84 
85 	/* Fast Mode SCL Low Counter */
86 	v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
87 	REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
88 			(v >> 8) & 0xff, 7, 0);
89 	REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
90 			v & 0xff, 7, 0);
91 
92 	/* SDA Hold Time */
93 	v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
94 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
95 
96 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
97 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
98 
99 	/* NACK_POL to high */
100 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
101 
102 	/* NACK_MASK to unmasked */
103 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
104 
105 	/* ARBITRATION_POL to high */
106 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
107 
108 	/* ARBITRATION_MASK to unmasked */
109 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
110 
111 	/* DONE_POL to high */
112 	REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
113 
114 	/* DONE_MASK to unmasked */
115 	REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
116 }
117 
hdmi_core_ddc_uninit(struct hdmi_core_data * core)118 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
119 {
120 	void __iomem *base = core->base;
121 
122 	/* Mask I2C interrupts */
123 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
124 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
125 	REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
126 }
127 
hdmi_core_ddc_edid(struct hdmi_core_data * core,u8 * pedid,u8 ext)128 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
129 {
130 	void __iomem *base = core->base;
131 	u8 cur_addr;
132 	const int retries = 1000;
133 	u8 seg_ptr = ext / 2;
134 	u8 edidbase = ((ext % 2) * 0x80);
135 
136 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
137 
138 	/*
139 	 * TODO: We use polling here, although we probably should use proper
140 	 * interrupts.
141 	 */
142 	for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
143 		int i;
144 
145 		/* clear ERROR and DONE */
146 		REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
147 
148 		REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
149 				edidbase + cur_addr, 7, 0);
150 
151 		if (seg_ptr)
152 			REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
153 		else
154 			REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
155 
156 		for (i = 0; i < retries; ++i) {
157 			u32 stat;
158 
159 			stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
160 
161 			/* I2CM_ERROR */
162 			if (stat & 1) {
163 				DSSERR("HDMI I2C Master Error\n");
164 				return -EIO;
165 			}
166 
167 			/* I2CM_DONE */
168 			if (stat & (1 << 1))
169 				break;
170 
171 			usleep_range(250, 1000);
172 		}
173 
174 		if (i == retries) {
175 			DSSERR("HDMI I2C timeout reading EDID\n");
176 			return -EIO;
177 		}
178 
179 		pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
180 	}
181 
182 	return 0;
183 
184 }
185 
hdmi5_read_edid(struct hdmi_core_data * core,u8 * edid,int len)186 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
187 {
188 	int r, n, i;
189 	int max_ext_blocks = (len / 128) - 1;
190 
191 	if (len < 128)
192 		return -EINVAL;
193 
194 	hdmi_core_ddc_init(core);
195 
196 	r = hdmi_core_ddc_edid(core, edid, 0);
197 	if (r)
198 		goto out;
199 
200 	n = edid[0x7e];
201 
202 	if (n > max_ext_blocks)
203 		n = max_ext_blocks;
204 
205 	for (i = 1; i <= n; i++) {
206 		r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
207 		if (r)
208 			goto out;
209 	}
210 
211 out:
212 	hdmi_core_ddc_uninit(core);
213 
214 	return r ? r : len;
215 }
216 
hdmi5_core_dump(struct hdmi_core_data * core,struct seq_file * s)217 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
218 {
219 
220 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
221 		hdmi_read_reg(core->base, r))
222 
223 	DUMPCORE(HDMI_CORE_FC_INVIDCONF);
224 	DUMPCORE(HDMI_CORE_FC_INHACTIV0);
225 	DUMPCORE(HDMI_CORE_FC_INHACTIV1);
226 	DUMPCORE(HDMI_CORE_FC_INHBLANK0);
227 	DUMPCORE(HDMI_CORE_FC_INHBLANK1);
228 	DUMPCORE(HDMI_CORE_FC_INVACTIV0);
229 	DUMPCORE(HDMI_CORE_FC_INVACTIV1);
230 	DUMPCORE(HDMI_CORE_FC_INVBLANK);
231 	DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
232 	DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
233 	DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
234 	DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
235 	DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
236 	DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
237 	DUMPCORE(HDMI_CORE_FC_CTRLDUR);
238 	DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
239 	DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
240 	DUMPCORE(HDMI_CORE_FC_CH0PREAM);
241 	DUMPCORE(HDMI_CORE_FC_CH1PREAM);
242 	DUMPCORE(HDMI_CORE_FC_CH2PREAM);
243 	DUMPCORE(HDMI_CORE_FC_AVICONF0);
244 	DUMPCORE(HDMI_CORE_FC_AVICONF1);
245 	DUMPCORE(HDMI_CORE_FC_AVICONF2);
246 	DUMPCORE(HDMI_CORE_FC_AVIVID);
247 	DUMPCORE(HDMI_CORE_FC_PRCONF);
248 
249 	DUMPCORE(HDMI_CORE_MC_CLKDIS);
250 	DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
251 	DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
252 	DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
253 	DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
254 
255 	DUMPCORE(HDMI_CORE_I2CM_SLAVE);
256 	DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
257 	DUMPCORE(HDMI_CORE_I2CM_DATAO);
258 	DUMPCORE(HDMI_CORE_I2CM_DATAI);
259 	DUMPCORE(HDMI_CORE_I2CM_OPERATION);
260 	DUMPCORE(HDMI_CORE_I2CM_INT);
261 	DUMPCORE(HDMI_CORE_I2CM_CTLINT);
262 	DUMPCORE(HDMI_CORE_I2CM_DIV);
263 	DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
264 	DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
265 	DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
266 	DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
267 	DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
268 	DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
269 	DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
270 	DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
271 	DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
272 	DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
273 	DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
274 	DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
275 }
276 
hdmi_core_init(struct hdmi_core_vid_config * video_cfg,struct hdmi_config * cfg)277 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
278 			struct hdmi_config *cfg)
279 {
280 	DSSDBG("hdmi_core_init\n");
281 
282 	/* video core */
283 	video_cfg->data_enable_pol = 1; /* It is always 1*/
284 	video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level;
285 	video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res;
286 	video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1;
287 	video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp;
288 	video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp;
289 	video_cfg->hblank = cfg->timings.hfp +
290 				cfg->timings.hbp + cfg->timings.hsw - 1;
291 	video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level;
292 	video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res;
293 	video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw;
294 	video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp;
295 	video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp;
296 	video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
297 	video_cfg->vblank = cfg->timings.vsw +
298 				cfg->timings.vfp + cfg->timings.vbp;
299 	video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
300 	video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace;
301 }
302 
303 /* DSS_HDMI_CORE_VIDEO_CONFIG */
hdmi_core_video_config(struct hdmi_core_data * core,struct hdmi_core_vid_config * cfg)304 static void hdmi_core_video_config(struct hdmi_core_data *core,
305 			struct hdmi_core_vid_config *cfg)
306 {
307 	void __iomem *base = core->base;
308 	unsigned char r = 0;
309 	bool vsync_pol, hsync_pol;
310 
311 	vsync_pol =
312 		cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
313 	hsync_pol =
314 		cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
315 
316 	/* Set hsync, vsync and data-enable polarity  */
317 	r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
318 	r = FLD_MOD(r, vsync_pol, 6, 6);
319 	r = FLD_MOD(r, hsync_pol, 5, 5);
320 	r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
321 	r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
322 	r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0);
323 	hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
324 
325 	/* set x resolution */
326 	REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
327 			cfg->v_fc_config.timings.x_res >> 8, 4, 0);
328 	REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
329 			cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
330 
331 	/* set y resolution */
332 	REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
333 			cfg->v_fc_config.timings.y_res >> 8, 4, 0);
334 	REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
335 			cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
336 
337 	/* set horizontal blanking pixels */
338 	REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
339 	REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
340 
341 	/* set vertial blanking pixels */
342 	REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
343 
344 	/* set horizontal sync offset */
345 	REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
346 			cfg->v_fc_config.timings.hfp >> 8, 4, 0);
347 	REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
348 			cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
349 
350 	/* set vertical sync offset */
351 	REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
352 			cfg->v_fc_config.timings.vfp, 7, 0);
353 
354 	/* set horizontal sync pulse width */
355 	REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
356 			(cfg->v_fc_config.timings.hsw >> 8), 1, 0);
357 	REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
358 			cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
359 
360 	/*  set vertical sync pulse width */
361 	REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
362 			cfg->v_fc_config.timings.vsw, 5, 0);
363 
364 	/* select DVI mode */
365 	REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
366 			cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
367 }
368 
hdmi_core_config_video_packetizer(struct hdmi_core_data * core)369 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
370 {
371 	void __iomem *base = core->base;
372 	int clr_depth = 0;	/* 24 bit color depth */
373 
374 	/* COLOR_DEPTH */
375 	REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
376 	/* BYPASS_EN */
377 	REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
378 	/* PP_EN */
379 	REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
380 	/* YCC422_EN */
381 	REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
382 	/* PP_STUFFING */
383 	REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
384 	/* YCC422_STUFFING */
385 	REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
386 	/* OUTPUT_SELECTOR */
387 	REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
388 }
389 
hdmi_core_config_csc(struct hdmi_core_data * core)390 static void hdmi_core_config_csc(struct hdmi_core_data *core)
391 {
392 	int clr_depth = 0;	/* 24 bit color depth */
393 
394 	/* CSC_COLORDEPTH */
395 	REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
396 }
397 
hdmi_core_config_video_sampler(struct hdmi_core_data * core)398 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
399 {
400 	int video_mapping = 1;	/* for 24 bit color depth */
401 
402 	/* VIDEO_MAPPING */
403 	REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
404 }
405 
hdmi_core_write_avi_infoframe(struct hdmi_core_data * core,struct hdmi_avi_infoframe * frame)406 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
407 	struct hdmi_avi_infoframe *frame)
408 {
409 	void __iomem *base = core->base;
410 	u8 data[HDMI_INFOFRAME_SIZE(AVI)];
411 	u8 *ptr;
412 	unsigned y, a, b, s;
413 	unsigned c, m, r;
414 	unsigned itc, ec, q, sc;
415 	unsigned vic;
416 	unsigned yq, cn, pr;
417 
418 	hdmi_avi_infoframe_pack(frame, data, sizeof(data));
419 
420 	print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
421 		HDMI_INFOFRAME_SIZE(AVI), false);
422 
423 	ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
424 
425 	y = (ptr[0] >> 5) & 0x3;
426 	a = (ptr[0] >> 4) & 0x1;
427 	b = (ptr[0] >> 2) & 0x3;
428 	s = (ptr[0] >> 0) & 0x3;
429 
430 	c = (ptr[1] >> 6) & 0x3;
431 	m = (ptr[1] >> 4) & 0x3;
432 	r = (ptr[1] >> 0) & 0xf;
433 
434 	itc = (ptr[2] >> 7) & 0x1;
435 	ec = (ptr[2] >> 4) & 0x7;
436 	q = (ptr[2] >> 2) & 0x3;
437 	sc = (ptr[2] >> 0) & 0x3;
438 
439 	vic = ptr[3];
440 
441 	yq = (ptr[4] >> 6) & 0x3;
442 	cn = (ptr[4] >> 4) & 0x3;
443 	pr = (ptr[4] >> 0) & 0xf;
444 
445 	hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
446 		(a << 6) | (s << 4) | (b << 2) | (y << 0));
447 
448 	hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
449 		(c << 6) | (m << 4) | (r << 0));
450 
451 	hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
452 		(itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
453 
454 	hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
455 
456 	hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
457 		(yq << 2) | (cn << 0));
458 
459 	REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
460 }
461 
hdmi_core_csc_config(struct hdmi_core_data * core,struct csc_table csc_coeff)462 static void hdmi_core_csc_config(struct hdmi_core_data *core,
463 		struct csc_table csc_coeff)
464 {
465 	void __iomem *base = core->base;
466 
467 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
468 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
469 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
470 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
471 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
472 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
473 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
474 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
475 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
476 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
477 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
478 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
479 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
480 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
481 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
482 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
483 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
484 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
485 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
486 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
487 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
488 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
489 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
490 	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
491 
492 	REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
493 }
494 
hdmi_core_configure_range(struct hdmi_core_data * core)495 static void hdmi_core_configure_range(struct hdmi_core_data *core)
496 {
497 	struct csc_table csc_coeff = { 0 };
498 
499 	/* support limited range with 24 bit color depth for now */
500 	csc_coeff = csc_table_deepcolor[0];
501 
502 	hdmi_core_csc_config(core, csc_coeff);
503 }
504 
hdmi_core_enable_video_path(struct hdmi_core_data * core)505 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
506 {
507 	void __iomem *base = core->base;
508 
509 	DSSDBG("hdmi_core_enable_video_path\n");
510 
511 	REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
512 	REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
513 	REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
514 	REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
515 	REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
516 	REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
517 	REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
518 	REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
519 }
520 
hdmi_core_mask_interrupts(struct hdmi_core_data * core)521 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
522 {
523 	void __iomem *base = core->base;
524 
525 	/* Master IRQ mask */
526 	REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
527 
528 	/* Mask all the interrupts in HDMI core */
529 
530 	REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
531 	REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
532 	REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
533 	REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
534 
535 	REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
536 	REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
537 
538 	REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
539 
540 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
541 	REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
542 	REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
543 
544 	REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
545 
546 	REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
547 
548 	/* Clear all the current interrupt bits */
549 
550 	REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
551 	REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
552 	REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
553 	REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
554 
555 	REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
556 
557 	REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
558 
559 	REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
560 
561 	REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
562 }
563 
hdmi_core_enable_interrupts(struct hdmi_core_data * core)564 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
565 {
566 	/* Unmute interrupts */
567 	REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
568 }
569 
hdmi5_core_handle_irqs(struct hdmi_core_data * core)570 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
571 {
572 	void __iomem *base = core->base;
573 
574 	REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
575 	REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
576 	REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
577 	REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
578 	REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
579 	REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
580 	REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
581 	REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
582 	REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
583 
584 	return 0;
585 }
586 
hdmi5_configure(struct hdmi_core_data * core,struct hdmi_wp_data * wp,struct hdmi_config * cfg)587 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
588 		struct hdmi_config *cfg)
589 {
590 	struct omap_video_timings video_timing;
591 	struct hdmi_video_format video_format;
592 	struct hdmi_core_vid_config v_core_cfg;
593 
594 	hdmi_core_mask_interrupts(core);
595 
596 	hdmi_core_init(&v_core_cfg, cfg);
597 
598 	hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
599 
600 	hdmi_wp_video_config_timing(wp, &video_timing);
601 
602 	/* video config */
603 	video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
604 
605 	hdmi_wp_video_config_format(wp, &video_format);
606 
607 	hdmi_wp_video_config_interface(wp, &video_timing);
608 
609 	/* support limited range with 24 bit color depth for now */
610 	hdmi_core_configure_range(core);
611 	cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
612 
613 	/*
614 	 * configure core video part, set software reset in the core
615 	 */
616 	v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
617 
618 	hdmi_core_video_config(core, &v_core_cfg);
619 
620 	hdmi_core_config_video_packetizer(core);
621 	hdmi_core_config_csc(core);
622 	hdmi_core_config_video_sampler(core);
623 
624 	if (cfg->hdmi_dvi_mode == HDMI_HDMI)
625 		hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
626 
627 	hdmi_core_enable_video_path(core);
628 
629 	hdmi_core_enable_interrupts(core);
630 }
631 
hdmi5_core_audio_config(struct hdmi_core_data * core,struct hdmi_core_audio_config * cfg)632 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
633 			struct hdmi_core_audio_config *cfg)
634 {
635 	void __iomem *base = core->base;
636 	u8 val;
637 
638 	/* Mute audio before configuring */
639 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
640 
641 	/* Set the N parameter */
642 	REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
643 	REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
644 	REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
645 
646 	/*
647 	 * CTS manual mode. Automatic mode is not supported when using audio
648 	 * parallel interface.
649 	 */
650 	REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
651 	REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
652 	REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
653 	REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
654 
655 	/* Layout of Audio Sample Packets: 2-channel or multichannels */
656 	if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
657 		REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
658 	else
659 		REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
660 
661 	/* Configure IEC-609580 Validity bits */
662 	/* Channel 0 is valid */
663 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
664 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
665 
666 	if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
667 		val = 1;
668 	else
669 		val = 0;
670 
671 	/* Channels 1, 2 setting */
672 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
673 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
674 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
675 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
676 	/* Channel 3 setting */
677 	if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
678 		val = 1;
679 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
680 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
681 
682 	/* Configure IEC-60958 User bits */
683 	/* TODO: should be set by user. */
684 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
685 
686 	/* Configure IEC-60958 Channel Status word */
687 	/* CGMSA */
688 	val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
689 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
690 
691 	/* Copyright */
692 	val = (cfg->iec60958_cfg->status[0] &
693 			IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
694 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
695 
696 	/* Category */
697 	hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
698 		cfg->iec60958_cfg->status[1]);
699 
700 	/* PCM audio mode */
701 	val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
702 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
703 
704 	/* Source number */
705 	val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
706 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
707 
708 	/* Channel number right 0  */
709 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
710 	/* Channel number right 1*/
711 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
712 	/* Channel number right 2  */
713 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
714 	/* Channel number right 3*/
715 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
716 	/* Channel number left 0  */
717 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
718 	/* Channel number left 1*/
719 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
720 	/* Channel number left 2  */
721 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
722 	/* Channel number left 3*/
723 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
724 
725 	/* Clock accuracy and sample rate */
726 	hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
727 		cfg->iec60958_cfg->status[3]);
728 
729 	/* Original sample rate and word length */
730 	hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
731 		cfg->iec60958_cfg->status[4]);
732 
733 	/* Enable FIFO empty and full interrupts */
734 	REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
735 
736 	/* Configure GPA */
737 	/* select HBR/SPDIF interfaces */
738 	if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
739 		/* select HBR/SPDIF interfaces */
740 		REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
741 		/* enable two channels in GPA */
742 		REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
743 	} else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
744 		/* select HBR/SPDIF interfaces */
745 		REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
746 		/* enable six channels in GPA */
747 		REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
748 	} else {
749 		/* select HBR/SPDIF interfaces */
750 		REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
751 		/* enable eight channels in GPA */
752 		REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
753 	}
754 
755 	/* disable HBR */
756 	REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
757 	/* enable PCUV */
758 	REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
759 	/* enable GPA FIFO full and empty mask */
760 	REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
761 	/* set polarity of GPA FIFO empty interrupts */
762 	REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
763 
764 	/* unmute audio */
765 	REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
766 }
767 
hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data * core,struct snd_cea_861_aud_if * info_aud)768 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
769 	 struct snd_cea_861_aud_if *info_aud)
770 {
771 	void __iomem *base = core->base;
772 
773 	/* channel count and coding type fields in AUDICONF0 are swapped */
774 	hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
775 		(info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
776 		(info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
777 
778 	hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
779 	hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
780 	hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
781 	  (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
782 	  (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
783 }
784 
hdmi5_audio_config(struct hdmi_core_data * core,struct hdmi_wp_data * wp,struct omap_dss_audio * audio,u32 pclk)785 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
786 			struct omap_dss_audio *audio, u32 pclk)
787 {
788 	struct hdmi_audio_format audio_format;
789 	struct hdmi_audio_dma audio_dma;
790 	struct hdmi_core_audio_config core_cfg;
791 	int n, cts, channel_count;
792 	unsigned int fs_nr;
793 	bool word_length_16b = false;
794 
795 	if (!audio || !audio->iec || !audio->cea || !core)
796 		return -EINVAL;
797 
798 	core_cfg.iec60958_cfg = audio->iec;
799 
800 	if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
801 		(audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
802 			word_length_16b = true;
803 
804 	/* only 16-bit word length supported atm */
805 	if (!word_length_16b)
806 		return -EINVAL;
807 
808 	switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
809 	case IEC958_AES3_CON_FS_32000:
810 		fs_nr = 32000;
811 		break;
812 	case IEC958_AES3_CON_FS_44100:
813 		fs_nr = 44100;
814 		break;
815 	case IEC958_AES3_CON_FS_48000:
816 		fs_nr = 48000;
817 		break;
818 	case IEC958_AES3_CON_FS_88200:
819 		fs_nr = 88200;
820 		break;
821 	case IEC958_AES3_CON_FS_96000:
822 		fs_nr = 96000;
823 		break;
824 	case IEC958_AES3_CON_FS_176400:
825 		fs_nr = 176400;
826 		break;
827 	case IEC958_AES3_CON_FS_192000:
828 		fs_nr = 192000;
829 		break;
830 	default:
831 		return -EINVAL;
832 	}
833 
834 	hdmi_compute_acr(pclk, fs_nr, &n, &cts);
835 	core_cfg.n = n;
836 	core_cfg.cts = cts;
837 
838 	/* Audio channels settings */
839 	channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
840 				+ 1;
841 
842 	if (channel_count == 2)
843 		core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
844 	else if (channel_count == 6)
845 		core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
846 	else
847 		core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
848 
849 	/* DMA settings */
850 	if (word_length_16b)
851 		audio_dma.transfer_size = 0x10;
852 	else
853 		audio_dma.transfer_size = 0x20;
854 	audio_dma.block_size = 0xC0;
855 	audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
856 	audio_dma.fifo_threshold = 0x20; /* in number of samples */
857 
858 	/* audio FIFO format settings for 16-bit samples*/
859 	audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
860 	audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
861 	audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
862 	audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
863 
864 	/* only LPCM atm */
865 	audio_format.type = HDMI_AUDIO_TYPE_LPCM;
866 
867 	/* only allowed option */
868 	audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
869 
870 	/* disable start/stop signals of IEC 60958 blocks */
871 	audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
872 
873 	/* configure DMA and audio FIFO format*/
874 	hdmi_wp_audio_config_dma(wp, &audio_dma);
875 	hdmi_wp_audio_config_format(wp, &audio_format);
876 
877 	/* configure the core */
878 	hdmi5_core_audio_config(core, &core_cfg);
879 
880 	/* configure CEA 861 audio infoframe */
881 	hdmi5_core_audio_infoframe_cfg(core, audio->cea);
882 
883 	return 0;
884 }
885 
hdmi5_core_init(struct platform_device * pdev,struct hdmi_core_data * core)886 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
887 {
888 	core->base = devm_platform_ioremap_resource_byname(pdev, "core");
889 	if (IS_ERR(core->base)) {
890 		DSSERR("can't ioremap HDMI core\n");
891 		return PTR_ERR(core->base);
892 	}
893 
894 	return 0;
895 }
896