1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "system/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 #include "hw/ppc/spapr_nested.h" /* For SpaprMachineStateNested */ 16 #include "hw/ppc/spapr_fadump.h" /* For FadumpMemStruct */ 17 18 struct SpaprVioBus; 19 struct SpaprPhbState; 20 struct SpaprNvram; 21 22 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 23 typedef struct SpaprEventSource SpaprEventSource; 24 typedef struct SpaprPendingHpt SpaprPendingHpt; 25 26 typedef struct Vof Vof; 27 28 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 29 #define SPAPR_ENTRY_POINT 0x100 30 31 #define SPAPR_TIMEBASE_FREQ 512000000ULL 32 33 #define TYPE_SPAPR_RTC "spapr-rtc" 34 35 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 36 37 struct SpaprRtcState { 38 /*< private >*/ 39 DeviceState parent_obj; 40 int64_t ns_offset; 41 }; 42 43 typedef struct SpaprDimmState SpaprDimmState; 44 45 #define TYPE_SPAPR_MACHINE "spapr-machine" 46 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 47 48 typedef enum { 49 SPAPR_RESIZE_HPT_DEFAULT = 0, 50 SPAPR_RESIZE_HPT_DISABLED, 51 SPAPR_RESIZE_HPT_ENABLED, 52 SPAPR_RESIZE_HPT_REQUIRED, 53 } SpaprResizeHpt; 54 55 /** 56 * Capabilities 57 */ 58 59 /* Hardware Transactional Memory */ 60 #define SPAPR_CAP_HTM 0x00 61 /* Vector Scalar Extensions */ 62 #define SPAPR_CAP_VSX 0x01 63 /* Decimal Floating Point */ 64 #define SPAPR_CAP_DFP 0x02 65 /* Cache Flush on Privilege Change */ 66 #define SPAPR_CAP_CFPC 0x03 67 /* Speculation Barrier Bounds Checking */ 68 #define SPAPR_CAP_SBBC 0x04 69 /* Indirect Branch Serialisation */ 70 #define SPAPR_CAP_IBS 0x05 71 /* HPT Maximum Page Size (encoded as a shift) */ 72 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 73 /* Nested KVM-HV */ 74 #define SPAPR_CAP_NESTED_KVM_HV 0x07 75 /* Large Decrementer */ 76 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 77 /* Count Cache Flush Assist HW Instruction */ 78 #define SPAPR_CAP_CCF_ASSIST 0x09 79 /* Implements PAPR FWNMI option */ 80 #define SPAPR_CAP_FWNMI 0x0A 81 /* Support H_RPT_INVALIDATE */ 82 #define SPAPR_CAP_RPT_INVALIDATE 0x0B 83 /* Support for AIL modes */ 84 #define SPAPR_CAP_AIL_MODE_3 0x0C 85 /* Nested PAPR */ 86 #define SPAPR_CAP_NESTED_PAPR 0x0D 87 /* DAWR1 */ 88 #define SPAPR_CAP_DAWR1 0x0E 89 /* Num Caps */ 90 #define SPAPR_CAP_NUM (SPAPR_CAP_DAWR1 + 1) 91 92 /* 93 * Capability Values 94 */ 95 /* Bool Caps */ 96 #define SPAPR_CAP_OFF 0x00 97 #define SPAPR_CAP_ON 0x01 98 99 /* Custom Caps */ 100 101 /* Generic */ 102 #define SPAPR_CAP_BROKEN 0x00 103 #define SPAPR_CAP_WORKAROUND 0x01 104 #define SPAPR_CAP_FIXED 0x02 105 /* SPAPR_CAP_IBS (cap-ibs) */ 106 #define SPAPR_CAP_FIXED_IBS 0x02 107 #define SPAPR_CAP_FIXED_CCD 0x03 108 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 109 110 #define FDT_MAX_SIZE 0x200000 111 112 /* Max number of NUMA nodes */ 113 #define NUMA_NODES_MAX_NUM (MAX_NODES) 114 115 /* 116 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 117 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 118 * kernel source. It represents the amount of associativity domains 119 * for non-CPU resources. 120 * 121 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 122 * array for any non-CPU resource. 123 */ 124 #define FORM1_DIST_REF_POINTS 4 125 #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 126 127 /* 128 * FORM2 NUMA affinity has a single associativity domain, giving 129 * us a assoc size of 2. 130 */ 131 #define FORM2_DIST_REF_POINTS 1 132 #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 133 134 typedef struct SpaprCapabilities SpaprCapabilities; 135 struct SpaprCapabilities { 136 uint8_t caps[SPAPR_CAP_NUM]; 137 }; 138 139 /** 140 * SpaprMachineClass: 141 */ 142 struct SpaprMachineClass { 143 MachineClass parent_class; 144 145 bool pre_5_1_assoc_refpoints; 146 bool pre_5_2_numa_associativity; 147 bool pre_6_2_numa_affinity; 148 SpaprResizeHpt resize_hpt_default; 149 SpaprCapabilities default_caps; 150 SpaprIrq *irq; 151 }; 152 153 #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 154 155 #define TYPE_SPAPR_WDT "spapr-wdt" 156 OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 157 158 typedef struct SpaprWatchdog { 159 /*< private >*/ 160 DeviceState parent_obj; 161 /*< public >*/ 162 163 QEMUTimer timer; 164 uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 165 uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 166 } SpaprWatchdog; 167 168 /** 169 * SpaprMachineState: 170 */ 171 struct SpaprMachineState { 172 /*< private >*/ 173 MachineState parent_obj; 174 175 struct SpaprVioBus *vio_bus; 176 QLIST_HEAD(, SpaprPhbState) phbs; 177 struct SpaprNvram *nvram; 178 SpaprRtcState rtc; 179 180 SpaprResizeHpt resize_hpt; 181 void *htab; 182 uint32_t htab_shift; 183 uint64_t patb_entry; /* Process tbl registered in H_REGISTER_PROC_TBL */ 184 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 185 186 hwaddr rma_size; 187 uint32_t fdt_size; 188 uint32_t fdt_initial_size; 189 void *fdt_blob; 190 uint8_t fdt_rng_seed[32]; 191 uint64_t hashpkey_val; 192 long kernel_size; 193 bool kernel_le; 194 uint64_t kernel_addr; 195 uint32_t initrd_base; 196 long initrd_size; 197 Vof *vof; 198 uint64_t rtc_offset; /* Now used only during incoming migration */ 199 struct PPCTimebase tb; 200 bool want_stdout_path; 201 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 202 203 /* Nested HV support (TCG only) */ 204 SpaprMachineStateNested nested; 205 206 Notifier epow_notifier; 207 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 208 bool use_hotplug_event_source; 209 SpaprEventSource *event_sources; 210 211 /* ibm,client-architecture-support option negotiation */ 212 bool cas_pre_isa3_guest; 213 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 214 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 215 uint32_t max_compat_pvr; 216 217 /* Migration state */ 218 int htab_save_index; 219 bool htab_first_pass; 220 int htab_fd; 221 222 /* Pending DIMM unplug cache. It is populated when a LMB 223 * unplug starts. It can be regenerated if a migration 224 * occurs during the unplug process. */ 225 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 226 227 /* State related to FWNMI option */ 228 229 /* System Reset and Machine Check Notification Routine addresses 230 * registered by "ibm,nmi-register" RTAS call. 231 */ 232 target_ulong fwnmi_system_reset_addr; 233 target_ulong fwnmi_machine_check_addr; 234 235 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 236 * set to -1 if a FWNMI machine check is not in progress, else is set to 237 * the CPU that was delivered the machine check, and is set back to -1 238 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 239 * to synchronize other CPUs. 240 */ 241 int fwnmi_machine_check_interlock; 242 QemuCond fwnmi_machine_check_interlock_cond; 243 244 /* Set by -boot */ 245 char *boot_device; 246 247 /*< public >*/ 248 char *kvm_type; 249 char *host_model; 250 char *host_serial; 251 252 int32_t irq_map_nr; 253 unsigned long *irq_map; 254 SpaprIrq *irq; 255 qemu_irq *qirqs; 256 SpaprInterruptController *active_intc; 257 ICSState *ics; 258 SpaprXive *xive; 259 260 bool cmd_line_caps[SPAPR_CAP_NUM]; 261 SpaprCapabilities def, eff, mig; 262 263 SpaprTpmProxy *tpm_proxy; 264 265 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 266 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 267 268 Error *fwnmi_migration_blocker; 269 270 SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 271 272 /* Fadump State */ 273 bool fadump_registered; 274 bool fadump_dump_active; 275 FadumpMemStruct registered_fdm; 276 }; 277 278 #define H_SUCCESS 0 279 #define H_BUSY 1 /* Hardware busy -- retry later */ 280 #define H_CLOSED 2 /* Resource closed */ 281 #define H_NOT_AVAILABLE 3 282 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 283 #define H_PARTIAL 5 284 #define H_IN_PROGRESS 14 /* Kind of like busy */ 285 #define H_PAGE_REGISTERED 15 286 #define H_PARTIAL_STORE 16 287 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 288 #define H_CONTINUE 18 /* Returned from H_Join on success */ 289 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 290 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 291 is a good time to retry */ 292 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 293 is a good time to retry */ 294 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 295 is a good time to retry */ 296 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 297 is a good time to retry */ 298 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 299 is a good time to retry */ 300 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 301 is a good time to retry */ 302 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 303 #define H_HARDWARE -1 /* Hardware error */ 304 #define H_FUNCTION -2 /* Function not supported */ 305 #define H_PRIVILEGE -3 /* Caller not privileged */ 306 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 307 #define H_BAD_MODE -5 /* Illegal msr value */ 308 #define H_PTEG_FULL -6 /* PTEG is full */ 309 #define H_NOT_FOUND -7 /* PTE was not found" */ 310 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 311 #define H_NO_MEM -9 312 #define H_AUTHORITY -10 313 #define H_PERMISSION -11 314 #define H_DROPPED -12 315 #define H_SOURCE_PARM -13 316 #define H_DEST_PARM -14 317 #define H_REMOTE_PARM -15 318 #define H_RESOURCE -16 319 #define H_ADAPTER_PARM -17 320 #define H_RH_PARM -18 321 #define H_RCQ_PARM -19 322 #define H_SCQ_PARM -20 323 #define H_EQ_PARM -21 324 #define H_RT_PARM -22 325 #define H_ST_PARM -23 326 #define H_SIGT_PARM -24 327 #define H_TOKEN_PARM -25 328 #define H_MLENGTH_PARM -27 329 #define H_MEM_PARM -28 330 #define H_MEM_ACCESS_PARM -29 331 #define H_ATTR_PARM -30 332 #define H_PORT_PARM -31 333 #define H_MCG_PARM -32 334 #define H_VL_PARM -33 335 #define H_TSIZE_PARM -34 336 #define H_TRACE_PARM -35 337 338 #define H_MASK_PARM -37 339 #define H_MCG_FULL -38 340 #define H_ALIAS_EXIST -39 341 #define H_P_COUNTER -40 342 #define H_TABLE_FULL -41 343 #define H_ALT_TABLE -42 344 #define H_MR_CONDITION -43 345 #define H_NOT_ENOUGH_RESOURCES -44 346 #define H_R_STATE -45 347 #define H_RESCINDEND -46 348 #define H_P2 -55 349 #define H_P3 -56 350 #define H_P4 -57 351 #define H_P5 -58 352 #define H_P6 -59 353 #define H_P7 -60 354 #define H_P8 -61 355 #define H_P9 -62 356 #define H_NOOP -63 357 #define H_UNSUPPORTED -67 358 #define H_OVERLAP -68 359 #define H_STATE -75 360 #define H_IN_USE -77 361 #define H_INVALID_ELEMENT_VALUE -81 362 #define H_UNSUPPORTED_FLAG -256 363 #define H_MULTI_THREADS_ACTIVE -9005 364 365 366 /* Long Busy is a condition that can be returned by the firmware 367 * when a call cannot be completed now, but the identical call 368 * should be retried later. This prevents calls blocking in the 369 * firmware for long periods of time. Annoyingly the firmware can return 370 * a range of return codes, hinting at how long we should wait before 371 * retrying. If you don't care for the hint, the macro below is a good 372 * way to check for the long_busy return codes 373 */ 374 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 375 && (x <= H_LONG_BUSY_END_RANGE)) 376 377 /* Flags */ 378 #define H_LARGE_PAGE (1ULL<<(63-16)) 379 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 380 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 381 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 382 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 383 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 384 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 385 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 386 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 387 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 388 #define H_ANDCOND (1ULL<<(63-33)) 389 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 390 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 391 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 392 #define H_COPY_PAGE (1ULL<<(63-49)) 393 #define H_N (1ULL<<(63-61)) 394 #define H_PP1 (1ULL<<(63-62)) 395 #define H_PP2 (1ULL<<(63-63)) 396 397 /* Values for 2nd argument to H_SET_MODE */ 398 #define H_SET_MODE_RESOURCE_SET_CIABR 1 399 #define H_SET_MODE_RESOURCE_SET_DAWR0 2 400 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 401 #define H_SET_MODE_RESOURCE_LE 4 402 #define H_SET_MODE_RESOURCE_SET_DAWR1 5 403 404 /* Flags for H_SET_MODE_RESOURCE_LE */ 405 #define H_SET_MODE_ENDIAN_BIG 0 406 #define H_SET_MODE_ENDIAN_LITTLE 1 407 408 /* VASI States */ 409 #define H_VASI_INVALID 0 410 #define H_VASI_ENABLED 1 411 #define H_VASI_ABORTED 2 412 #define H_VASI_SUSPENDING 3 413 #define H_VASI_SUSPENDED 4 414 #define H_VASI_RESUMED 5 415 #define H_VASI_COMPLETED 6 416 417 /* DABRX flags */ 418 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 419 #define H_DABRX_KERNEL (1ULL<<(63-62)) 420 #define H_DABRX_USER (1ULL<<(63-63)) 421 422 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 423 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 424 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 425 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 426 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 427 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 428 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 429 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 430 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 431 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 432 433 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 434 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 435 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 436 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 437 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 438 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 439 440 /* Each control block has to be on a 4K boundary */ 441 #define H_CB_ALIGNMENT 4096 442 443 /* pSeries hypervisor opcodes */ 444 #define H_REMOVE 0x04 445 #define H_ENTER 0x08 446 #define H_READ 0x0c 447 #define H_CLEAR_MOD 0x10 448 #define H_CLEAR_REF 0x14 449 #define H_PROTECT 0x18 450 #define H_GET_TCE 0x1c 451 #define H_PUT_TCE 0x20 452 #define H_SET_SPRG0 0x24 453 #define H_SET_DABR 0x28 454 #define H_PAGE_INIT 0x2c 455 #define H_SET_ASR 0x30 456 #define H_ASR_ON 0x34 457 #define H_ASR_OFF 0x38 458 #define H_LOGICAL_CI_LOAD 0x3c 459 #define H_LOGICAL_CI_STORE 0x40 460 #define H_LOGICAL_CACHE_LOAD 0x44 461 #define H_LOGICAL_CACHE_STORE 0x48 462 #define H_LOGICAL_ICBI 0x4c 463 #define H_LOGICAL_DCBF 0x50 464 #define H_GET_TERM_CHAR 0x54 465 #define H_PUT_TERM_CHAR 0x58 466 #define H_REAL_TO_LOGICAL 0x5c 467 #define H_HYPERVISOR_DATA 0x60 468 #define H_EOI 0x64 469 #define H_CPPR 0x68 470 #define H_IPI 0x6c 471 #define H_IPOLL 0x70 472 #define H_XIRR 0x74 473 #define H_PERFMON 0x7c 474 #define H_MIGRATE_DMA 0x78 475 #define H_REGISTER_VPA 0xDC 476 #define H_CEDE 0xE0 477 #define H_CONFER 0xE4 478 #define H_PROD 0xE8 479 #define H_GET_PPP 0xEC 480 #define H_SET_PPP 0xF0 481 #define H_PURR 0xF4 482 #define H_PIC 0xF8 483 #define H_REG_CRQ 0xFC 484 #define H_FREE_CRQ 0x100 485 #define H_VIO_SIGNAL 0x104 486 #define H_SEND_CRQ 0x108 487 #define H_COPY_RDMA 0x110 488 #define H_REGISTER_LOGICAL_LAN 0x114 489 #define H_FREE_LOGICAL_LAN 0x118 490 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 491 #define H_SEND_LOGICAL_LAN 0x120 492 #define H_BULK_REMOVE 0x124 493 #define H_MULTICAST_CTRL 0x130 494 #define H_SET_XDABR 0x134 495 #define H_STUFF_TCE 0x138 496 #define H_PUT_TCE_INDIRECT 0x13C 497 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 498 #define H_VTERM_PARTNER_INFO 0x150 499 #define H_REGISTER_VTERM 0x154 500 #define H_FREE_VTERM 0x158 501 #define H_RESET_EVENTS 0x15C 502 #define H_ALLOC_RESOURCE 0x160 503 #define H_FREE_RESOURCE 0x164 504 #define H_MODIFY_QP 0x168 505 #define H_QUERY_QP 0x16C 506 #define H_REREGISTER_PMR 0x170 507 #define H_REGISTER_SMR 0x174 508 #define H_QUERY_MR 0x178 509 #define H_QUERY_MW 0x17C 510 #define H_QUERY_HCA 0x180 511 #define H_QUERY_PORT 0x184 512 #define H_MODIFY_PORT 0x188 513 #define H_DEFINE_AQP1 0x18C 514 #define H_GET_TRACE_BUFFER 0x190 515 #define H_DEFINE_AQP0 0x194 516 #define H_RESIZE_MR 0x198 517 #define H_ATTACH_MCQP 0x19C 518 #define H_DETACH_MCQP 0x1A0 519 #define H_CREATE_RPT 0x1A4 520 #define H_REMOVE_RPT 0x1A8 521 #define H_REGISTER_RPAGES 0x1AC 522 #define H_DISABLE_AND_GETC 0x1B0 523 #define H_ERROR_DATA 0x1B4 524 #define H_GET_HCA_INFO 0x1B8 525 #define H_GET_PERF_COUNT 0x1BC 526 #define H_MANAGE_TRACE 0x1C0 527 #define H_GET_CPU_CHARACTERISTICS 0x1C8 528 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 529 #define H_QUERY_INT_STATE 0x1E4 530 #define H_POLL_PENDING 0x1D8 531 #define H_ILLAN_ATTRIBUTES 0x244 532 #define H_MODIFY_HEA_QP 0x250 533 #define H_QUERY_HEA_QP 0x254 534 #define H_QUERY_HEA 0x258 535 #define H_QUERY_HEA_PORT 0x25C 536 #define H_MODIFY_HEA_PORT 0x260 537 #define H_REG_BCMC 0x264 538 #define H_DEREG_BCMC 0x268 539 #define H_REGISTER_HEA_RPAGES 0x26C 540 #define H_DISABLE_AND_GET_HEA 0x270 541 #define H_GET_HEA_INFO 0x274 542 #define H_ALLOC_HEA_RESOURCE 0x278 543 #define H_ADD_CONN 0x284 544 #define H_DEL_CONN 0x288 545 #define H_JOIN 0x298 546 #define H_VASI_STATE 0x2A4 547 #define H_ENABLE_CRQ 0x2B0 548 #define H_GET_EM_PARMS 0x2B8 549 #define H_SET_MPP 0x2D0 550 #define H_GET_MPP 0x2D4 551 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 552 #define H_XIRR_X 0x2FC 553 #define H_RANDOM 0x300 554 #define H_SET_MODE 0x31C 555 #define H_RESIZE_HPT_PREPARE 0x36C 556 #define H_RESIZE_HPT_COMMIT 0x370 557 #define H_CLEAN_SLB 0x374 558 #define H_INVALIDATE_PID 0x378 559 #define H_REGISTER_PROC_TBL 0x37C 560 #define H_SIGNAL_SYS_RESET 0x380 561 562 #define H_INT_GET_SOURCE_INFO 0x3A8 563 #define H_INT_SET_SOURCE_CONFIG 0x3AC 564 #define H_INT_GET_SOURCE_CONFIG 0x3B0 565 #define H_INT_GET_QUEUE_INFO 0x3B4 566 #define H_INT_SET_QUEUE_CONFIG 0x3B8 567 #define H_INT_GET_QUEUE_CONFIG 0x3BC 568 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 569 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 570 #define H_INT_ESB 0x3C8 571 #define H_INT_SYNC 0x3CC 572 #define H_INT_RESET 0x3D0 573 #define H_SCM_READ_METADATA 0x3E4 574 #define H_SCM_WRITE_METADATA 0x3E8 575 #define H_SCM_BIND_MEM 0x3EC 576 #define H_SCM_UNBIND_MEM 0x3F0 577 #define H_SCM_UNBIND_ALL 0x3FC 578 #define H_SCM_HEALTH 0x400 579 #define H_RPT_INVALIDATE 0x448 580 #define H_SCM_FLUSH 0x44C 581 #define H_WATCHDOG 0x45C 582 #define H_GUEST_GET_CAPABILITIES 0x460 583 #define H_GUEST_SET_CAPABILITIES 0x464 584 #define H_GUEST_CREATE 0x470 585 #define H_GUEST_CREATE_VCPU 0x474 586 #define H_GUEST_GET_STATE 0x478 587 #define H_GUEST_SET_STATE 0x47C 588 #define H_GUEST_RUN_VCPU 0x480 589 #define H_GUEST_DELETE 0x488 590 591 #define MAX_HCALL_OPCODE H_GUEST_DELETE 592 593 /* The hcalls above are standardized in PAPR and implemented by pHyp 594 * as well. 595 * 596 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 597 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 598 * for "platform-specific" hcalls. 599 */ 600 #define KVMPPC_HCALL_BASE 0xf000 601 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 602 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 603 /* Client Architecture support */ 604 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 605 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 606 /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 607 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 608 609 /* Platform-specific hcalls used for nested HV KVM */ 610 #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 611 #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 612 #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 613 #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 614 615 #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 616 617 /* 618 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 619 * Secure VM mode via an Ultravisor / Protected Execution Facility 620 */ 621 #define SVM_HCALL_BASE 0xEF00 622 #define SVM_H_TPM_COMM 0xEF10 623 #define SVM_HCALL_MAX SVM_H_TPM_COMM 624 625 typedef struct SpaprDeviceTreeUpdateHeader { 626 uint32_t version_id; 627 } SpaprDeviceTreeUpdateHeader; 628 629 #define hcall_dprintf(fmt, ...) \ 630 do { \ 631 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 632 } while (0) 633 634 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 635 target_ulong opcode, 636 target_ulong *args); 637 638 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 639 void spapr_unregister_hypercall(target_ulong opcode); 640 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 641 target_ulong *args); 642 643 target_ulong vhyp_mmu_resize_hpt_prepare(PowerPCCPU *cpu, 644 SpaprMachineState *spapr, 645 target_ulong shift); 646 target_ulong vhyp_mmu_resize_hpt_commit(PowerPCCPU *cpu, 647 SpaprMachineState *spapr, 648 target_ulong flags, 649 target_ulong shift); 650 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 651 void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 652 653 /* Virtual Processor Area structure constants */ 654 #define VPA_MIN_SIZE 640 655 #define VPA_SIZE_OFFSET 0x4 656 #define VPA_SHARED_PROC_OFFSET 0x9 657 #define VPA_SHARED_PROC_VAL 0x2 658 #define VPA_DISPATCH_COUNTER 0x100 659 660 /* ibm,set-eeh-option */ 661 #define RTAS_EEH_DISABLE 0 662 #define RTAS_EEH_ENABLE 1 663 #define RTAS_EEH_THAW_IO 2 664 #define RTAS_EEH_THAW_DMA 3 665 666 /* ibm,get-config-addr-info2 */ 667 #define RTAS_GET_PE_ADDR 0 668 #define RTAS_GET_PE_MODE 1 669 #define RTAS_PE_MODE_NONE 0 670 #define RTAS_PE_MODE_NOT_SHARED 1 671 #define RTAS_PE_MODE_SHARED 2 672 673 /* ibm,read-slot-reset-state2 */ 674 #define RTAS_EEH_PE_STATE_NORMAL 0 675 #define RTAS_EEH_PE_STATE_RESET 1 676 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 677 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 678 #define RTAS_EEH_PE_STATE_UNAVAIL 5 679 #define RTAS_EEH_NOT_SUPPORT 0 680 #define RTAS_EEH_SUPPORT 1 681 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 682 #define RTAS_EEH_PE_RECOVER_INFO 0 683 684 /* ibm,set-slot-reset */ 685 #define RTAS_SLOT_RESET_DEACTIVATE 0 686 #define RTAS_SLOT_RESET_HOT 1 687 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 688 689 /* ibm,slot-error-detail */ 690 #define RTAS_SLOT_TEMP_ERR_LOG 1 691 #define RTAS_SLOT_PERM_ERR_LOG 2 692 693 /* RTAS return codes */ 694 #define RTAS_OUT_SUCCESS 0 695 #define RTAS_OUT_NO_ERRORS_FOUND 1 696 #define RTAS_OUT_HW_ERROR -1 697 #define RTAS_OUT_BUSY -2 698 #define RTAS_OUT_PARAM_ERROR -3 699 #define RTAS_OUT_NOT_SUPPORTED -3 700 #define RTAS_OUT_NO_SUCH_INDICATOR -3 701 #define RTAS_OUT_DUMP_ALREADY_REGISTERED -9 702 #define RTAS_OUT_DUMP_ACTIVE -10 703 #define RTAS_OUT_NOT_AUTHORIZED -9002 704 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 705 706 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 707 #define RTAS_DDW_PGSIZE_4K 0x01 708 #define RTAS_DDW_PGSIZE_64K 0x02 709 #define RTAS_DDW_PGSIZE_16M 0x04 710 #define RTAS_DDW_PGSIZE_32M 0x08 711 #define RTAS_DDW_PGSIZE_64M 0x10 712 #define RTAS_DDW_PGSIZE_128M 0x20 713 #define RTAS_DDW_PGSIZE_256M 0x40 714 #define RTAS_DDW_PGSIZE_16G 0x80 715 #define RTAS_DDW_PGSIZE_2M 0x100 716 717 /* RTAS tokens */ 718 #define RTAS_TOKEN_BASE 0x2000 719 720 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 721 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 722 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 723 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 724 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 725 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 726 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 727 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 728 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 729 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 730 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 731 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 732 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 733 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 734 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 735 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 736 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 737 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 738 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 739 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 740 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 741 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 742 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 743 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 744 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 745 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 746 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 747 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 748 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 749 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 750 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 751 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 752 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 753 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 754 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 755 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 756 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 757 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 758 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 759 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 760 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 761 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 762 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 763 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 764 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 765 #define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D) 766 767 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2E) 768 769 /* RTAS ibm,get-system-parameter token values */ 770 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 771 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 772 #define RTAS_SYSPARM_UUID 48 773 774 /* RTAS indicator/sensor types 775 * 776 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 777 * 778 * NOTE: currently only DR-related sensors are implemented here 779 */ 780 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 781 #define RTAS_SENSOR_TYPE_DR 9002 782 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 783 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 784 785 /* Possible values for the platform-processor-diagnostics-run-mode parameter 786 * of the RTAS ibm,get-system-parameter call. 787 */ 788 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 789 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 790 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 791 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 792 793 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 794 { 795 return addr & ~0xF000000000000000ULL; 796 } 797 798 static inline uint32_t rtas_ld(target_ulong phys, int n) 799 { 800 return ldl_be_phys(&address_space_memory, 801 ppc64_phys_to_real(phys + 4 * n)); 802 } 803 804 static inline uint64_t rtas_ldq(target_ulong phys, int n) 805 { 806 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 807 } 808 809 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 810 { 811 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 812 } 813 814 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 815 uint32_t token, 816 uint32_t nargs, target_ulong args, 817 uint32_t nret, target_ulong rets); 818 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 819 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 820 uint32_t token, uint32_t nargs, target_ulong args, 821 uint32_t nret, target_ulong rets); 822 void spapr_dt_rtas_tokens(void *fdt, int rtas); 823 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 824 825 #define SPAPR_TCE_PAGE_SHIFT 12 826 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 827 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 828 829 #define SPAPR_VIO_BASE_LIOBN 0x00000000 830 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 831 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 832 (0x80000000 | ((phb_index) << 8) | (window_num)) 833 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 834 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 835 836 #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 837 #define RTAS_ERROR_LOG_MAX 2048 838 839 /* Offset from rtas-base where error log is placed */ 840 #define RTAS_ERROR_LOG_OFFSET 0x30 841 842 #define RTAS_EVENT_SCAN_RATE 1 843 844 /* This helper should be used to encode interrupt specifiers when the related 845 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 846 * VIO devices, RTAS event sources and PHBs). 847 */ 848 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 849 { 850 intspec[0] = cpu_to_be32(irq); 851 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 852 } 853 854 855 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 856 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 857 858 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 859 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 860 TYPE_SPAPR_IOMMU_MEMORY_REGION) 861 862 struct SpaprTceTable { 863 DeviceState parent; 864 uint32_t liobn; 865 uint32_t nb_table; 866 uint64_t bus_offset; 867 uint32_t page_shift; 868 uint64_t *table; 869 uint32_t mig_nb_table; 870 uint64_t *mig_table; 871 bool bypass; 872 bool need_vfio; 873 bool skipping_replay; 874 bool def_win; 875 int fd; 876 MemoryRegion root; 877 IOMMUMemoryRegion iommu; 878 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 879 QLIST_ENTRY(SpaprTceTable) list; 880 }; 881 882 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 883 884 struct SpaprEventLogEntry { 885 uint32_t summary; 886 uint32_t extended_length; 887 void *extended_log; 888 QTAILQ_ENTRY(SpaprEventLogEntry) next; 889 }; 890 891 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 892 void spapr_events_init(SpaprMachineState *sm); 893 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 894 void close_htab_fd(SpaprMachineState *spapr); 895 void spapr_setup_hpt(SpaprMachineState *spapr); 896 void spapr_free_hpt(SpaprMachineState *spapr); 897 void spapr_check_mmu_mode(bool guest_radix); 898 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 899 void spapr_tce_table_enable(SpaprTceTable *tcet, 900 uint32_t page_shift, uint64_t bus_offset, 901 uint32_t nb_table); 902 void spapr_tce_table_disable(SpaprTceTable *tcet); 903 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 904 905 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 906 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 907 uint32_t liobn, uint64_t window, uint32_t size); 908 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 909 SpaprTceTable *tcet); 910 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 911 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 912 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 913 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 914 uint32_t count); 915 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 916 uint32_t count); 917 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 918 uint32_t count, uint32_t index); 919 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 920 uint32_t count, uint32_t index); 921 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 922 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 923 void spapr_clear_pending_events(SpaprMachineState *spapr); 924 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 925 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 926 int spapr_max_server_number(SpaprMachineState *spapr); 927 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 928 uint64_t pte0, uint64_t pte1); 929 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 930 931 /* DRC callbacks. */ 932 void spapr_core_release(DeviceState *dev); 933 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 934 void *fdt, int *fdt_start_offset, Error **errp); 935 void spapr_lmb_release(DeviceState *dev); 936 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 937 void *fdt, int *fdt_start_offset, Error **errp); 938 void spapr_phb_release(DeviceState *dev); 939 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 940 void *fdt, int *fdt_start_offset, Error **errp); 941 942 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 943 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 944 945 #define TYPE_SPAPR_RNG "spapr-rng" 946 947 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 948 949 /* 950 * This defines the maximum number of DIMM slots we can have for sPAPR 951 * guest. This is not defined by sPAPR but we are defining it to 32 slots 952 * based on default number of slots provided by PowerPC kernel. 953 */ 954 #define SPAPR_MAX_RAM_SLOTS 32 955 956 /* 1GB alignment for hotplug memory region */ 957 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 958 959 /* 960 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 961 * property under ibm,dynamic-reconfiguration-memory node. 962 */ 963 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 964 965 /* 966 * Defines for flag value in ibm,dynamic-memory property under 967 * ibm,dynamic-reconfiguration-memory node. 968 */ 969 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 970 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 971 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 972 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 973 974 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 975 976 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 977 978 int spapr_get_vcpu_id(PowerPCCPU *cpu); 979 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 980 PowerPCCPU *spapr_find_cpu(int vcpu_id); 981 982 int spapr_caps_pre_load(void *opaque); 983 int spapr_caps_pre_save(void *opaque); 984 985 /* 986 * Handling of optional capabilities 987 */ 988 extern const VMStateDescription vmstate_spapr_cap_htm; 989 extern const VMStateDescription vmstate_spapr_cap_vsx; 990 extern const VMStateDescription vmstate_spapr_cap_dfp; 991 extern const VMStateDescription vmstate_spapr_cap_cfpc; 992 extern const VMStateDescription vmstate_spapr_cap_sbbc; 993 extern const VMStateDescription vmstate_spapr_cap_ibs; 994 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 995 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 996 extern const VMStateDescription vmstate_spapr_cap_nested_papr; 997 extern const VMStateDescription vmstate_spapr_cap_large_decr; 998 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 999 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 1000 extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 1001 extern const VMStateDescription vmstate_spapr_cap_ail_mode_3; 1002 extern const VMStateDescription vmstate_spapr_wdt; 1003 extern const VMStateDescription vmstate_spapr_cap_dawr1; 1004 1005 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 1006 { 1007 return spapr->eff.caps[cap]; 1008 } 1009 1010 void spapr_caps_init(SpaprMachineState *spapr); 1011 void spapr_caps_apply(SpaprMachineState *spapr); 1012 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 1013 void spapr_caps_add_properties(SpaprMachineClass *smc); 1014 int spapr_caps_post_migration(SpaprMachineState *spapr); 1015 1016 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1017 Error **errp); 1018 /* 1019 * XIVE definitions 1020 */ 1021 #define SPAPR_OV5_XIVE_LEGACY 0x0 1022 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1023 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1024 1025 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 1026 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask); 1027 hwaddr spapr_get_rtas_addr(void); 1028 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1029 1030 void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1031 void spapr_vof_quiesce(MachineState *ms); 1032 bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1033 void *val, int vallen); 1034 target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1035 target_ulong opcode, target_ulong *args); 1036 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1037 CPUState *cs, 1038 target_ulong ovec_addr); 1039 void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1040 1041 /* H_WATCHDOG */ 1042 void spapr_watchdog_init(SpaprMachineState *spapr); 1043 void spapr_register_nested_hv(void); 1044 void spapr_unregister_nested_hv(void); 1045 void spapr_nested_reset(SpaprMachineState *spapr); 1046 void spapr_register_nested_papr(void); 1047 void spapr_unregister_nested_papr(void); 1048 1049 #endif /* HW_SPAPR_H */ 1050