1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include "qapi/visitor.h"
19 #include <math.h>
20 #include <sys/ioctl.h>
21 #include <sys/utsname.h>
22 #include <sys/syscall.h>
23 #include <sys/resource.h>
24 #include <sys/time.h>
25
26 #include <linux/kvm.h>
27 #include <linux/kvm_para.h>
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
30
31 #include "cpu.h"
32 #include "host-cpu.h"
33 #include "vmsr_energy.h"
34 #include "system/system.h"
35 #include "system/hw_accel.h"
36 #include "system/kvm_int.h"
37 #include "system/runstate.h"
38 #include "kvm_i386.h"
39 #include "../confidential-guest.h"
40 #include "sev.h"
41 #include "tdx.h"
42 #include "xen-emu.h"
43 #include "hyperv.h"
44 #include "hyperv-proto.h"
45
46 #include "gdbstub/enums.h"
47 #include "qemu/host-utils.h"
48 #include "qemu/main-loop.h"
49 #include "qemu/ratelimit.h"
50 #include "qemu/config-file.h"
51 #include "qemu/error-report.h"
52 #include "qemu/memalign.h"
53 #include "hw/i386/x86.h"
54 #include "hw/i386/kvm/xen_evtchn.h"
55 #include "hw/i386/pc.h"
56 #include "hw/i386/apic.h"
57 #include "hw/i386/apic_internal.h"
58 #include "hw/i386/apic-msidef.h"
59 #include "hw/i386/intel_iommu.h"
60 #include "hw/i386/topology.h"
61 #include "hw/i386/x86-iommu.h"
62 #include "hw/i386/e820_memory_layout.h"
63
64 #include "hw/xen/xen.h"
65
66 #include "hw/pci/pci.h"
67 #include "hw/pci/msi.h"
68 #include "hw/pci/msix.h"
69 #include "migration/blocker.h"
70 #include "exec/memattrs.h"
71 #include "exec/target_page.h"
72 #include "trace.h"
73
74 #include CONFIG_DEVICES
75
76 //#define DEBUG_KVM
77
78 #ifdef DEBUG_KVM
79 #define DPRINTF(fmt, ...) \
80 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define DPRINTF(fmt, ...) \
83 do { } while (0)
84 #endif
85
86 /*
87 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
88 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
89 * Since these must be part of guest physical memory, we need to allocate
90 * them, both by setting their start addresses in the kernel and by
91 * creating a corresponding e820 entry. We need 4 pages before the BIOS,
92 * so this value allows up to 16M BIOSes.
93 */
94 #define KVM_IDENTITY_BASE 0xfeffc000
95
96 /* From arch/x86/kvm/lapic.h */
97 #define KVM_APIC_BUS_CYCLE_NS 1
98 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
99
100 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
101 * 255 kvm_msr_entry structs */
102 #define MSR_BUF_SIZE 4096
103
104 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
105 typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
106 typedef struct {
107 uint32_t msr;
108 QEMURDMSRHandler *rdmsr;
109 QEMUWRMSRHandler *wrmsr;
110 } KVMMSRHandlers;
111
112 static void kvm_init_msrs(X86CPU *cpu);
113 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
114 QEMUWRMSRHandler *wrmsr);
115
116 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
117 KVM_CAP_INFO(SET_TSS_ADDR),
118 KVM_CAP_INFO(EXT_CPUID),
119 KVM_CAP_INFO(MP_STATE),
120 KVM_CAP_INFO(SIGNAL_MSI),
121 KVM_CAP_INFO(IRQ_ROUTING),
122 KVM_CAP_INFO(DEBUGREGS),
123 KVM_CAP_INFO(XSAVE),
124 KVM_CAP_INFO(VCPU_EVENTS),
125 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP),
126 KVM_CAP_INFO(MCE),
127 KVM_CAP_INFO(ADJUST_CLOCK),
128 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR),
129 KVM_CAP_LAST_INFO
130 };
131
132 static bool has_msr_star;
133 static bool has_msr_hsave_pa;
134 static bool has_msr_tsc_aux;
135 static bool has_msr_tsc_adjust;
136 static bool has_msr_tsc_deadline;
137 static bool has_msr_feature_control;
138 static bool has_msr_misc_enable;
139 static bool has_msr_smbase;
140 static bool has_msr_bndcfgs;
141 static int lm_capable_kernel;
142 static bool has_msr_hv_hypercall;
143 static bool has_msr_hv_crash;
144 static bool has_msr_hv_reset;
145 static bool has_msr_hv_vpindex;
146 static bool hv_vpindex_settable;
147 static bool has_msr_hv_runtime;
148 static bool has_msr_hv_synic;
149 static bool has_msr_hv_stimer;
150 static bool has_msr_hv_frequencies;
151 static bool has_msr_hv_reenlightenment;
152 static bool has_msr_hv_syndbg_options;
153 static bool has_msr_xss;
154 static bool has_msr_umwait;
155 static bool has_msr_spec_ctrl;
156 static bool has_tsc_scale_msr;
157 static bool has_msr_tsx_ctrl;
158 static bool has_msr_virt_ssbd;
159 static bool has_msr_smi_count;
160 static bool has_msr_arch_capabs;
161 static bool has_msr_core_capabs;
162 static bool has_msr_vmx_vmfunc;
163 static bool has_msr_ucode_rev;
164 static bool has_msr_vmx_procbased_ctls2;
165 static bool has_msr_perf_capabs;
166 static bool has_msr_pkrs;
167 static bool has_msr_hwcr;
168
169 static uint32_t has_architectural_pmu_version;
170 static uint32_t num_architectural_pmu_gp_counters;
171 static uint32_t num_architectural_pmu_fixed_counters;
172
173 static int has_xsave2;
174 static int has_xcrs;
175 static int has_sregs2;
176 static int has_exception_payload;
177 static int has_triple_fault_event;
178
179 static bool has_msr_mcg_ext_ctl;
180
181 static struct kvm_cpuid2 *cpuid_cache;
182 static struct kvm_cpuid2 *hv_cpuid_cache;
183 static struct kvm_msr_list *kvm_feature_msrs;
184
185 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES];
186
187 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
188 static RateLimit bus_lock_ratelimit_ctrl;
189 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
190
191 static const char *vm_type_name[] = {
192 [KVM_X86_DEFAULT_VM] = "default",
193 [KVM_X86_SEV_VM] = "SEV",
194 [KVM_X86_SEV_ES_VM] = "SEV-ES",
195 [KVM_X86_SNP_VM] = "SEV-SNP",
196 [KVM_X86_TDX_VM] = "TDX",
197 };
198
kvm_is_vm_type_supported(int type)199 bool kvm_is_vm_type_supported(int type)
200 {
201 uint32_t machine_types;
202
203 /*
204 * old KVM doesn't support KVM_CAP_VM_TYPES but KVM_X86_DEFAULT_VM
205 * is always supported
206 */
207 if (type == KVM_X86_DEFAULT_VM) {
208 return true;
209 }
210
211 machine_types = kvm_check_extension(KVM_STATE(current_machine->accelerator),
212 KVM_CAP_VM_TYPES);
213 return !!(machine_types & BIT(type));
214 }
215
kvm_get_vm_type(MachineState * ms)216 int kvm_get_vm_type(MachineState *ms)
217 {
218 int kvm_type = KVM_X86_DEFAULT_VM;
219
220 if (ms->cgs) {
221 if (!object_dynamic_cast(OBJECT(ms->cgs), TYPE_X86_CONFIDENTIAL_GUEST)) {
222 error_report("configuration type %s not supported for x86 guests",
223 object_get_typename(OBJECT(ms->cgs)));
224 exit(1);
225 }
226 kvm_type = x86_confidential_guest_kvm_type(
227 X86_CONFIDENTIAL_GUEST(ms->cgs));
228 }
229
230 if (!kvm_is_vm_type_supported(kvm_type)) {
231 error_report("vm-type %s not supported by KVM", vm_type_name[kvm_type]);
232 exit(1);
233 }
234
235 return kvm_type;
236 }
237
kvm_enable_hypercall(uint64_t enable_mask)238 bool kvm_enable_hypercall(uint64_t enable_mask)
239 {
240 KVMState *s = KVM_STATE(current_accel());
241
242 return !kvm_vm_enable_cap(s, KVM_CAP_EXIT_HYPERCALL, 0, enable_mask);
243 }
244
kvm_has_smm(void)245 bool kvm_has_smm(void)
246 {
247 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
248 }
249
kvm_has_adjust_clock_stable(void)250 bool kvm_has_adjust_clock_stable(void)
251 {
252 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
253
254 return (ret & KVM_CLOCK_TSC_STABLE);
255 }
256
kvm_has_exception_payload(void)257 bool kvm_has_exception_payload(void)
258 {
259 return has_exception_payload;
260 }
261
kvm_x2apic_api_set_flags(uint64_t flags)262 static bool kvm_x2apic_api_set_flags(uint64_t flags)
263 {
264 KVMState *s = KVM_STATE(current_accel());
265
266 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
267 }
268
269 #define MEMORIZE(fn, _result) \
270 ({ \
271 static bool _memorized; \
272 \
273 if (_memorized) { \
274 return _result; \
275 } \
276 _memorized = true; \
277 _result = fn; \
278 })
279
280 static bool has_x2apic_api;
281
kvm_has_x2apic_api(void)282 bool kvm_has_x2apic_api(void)
283 {
284 return has_x2apic_api;
285 }
286
kvm_enable_x2apic(void)287 bool kvm_enable_x2apic(void)
288 {
289 return MEMORIZE(
290 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
291 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
292 has_x2apic_api);
293 }
294
kvm_hv_vpindex_settable(void)295 bool kvm_hv_vpindex_settable(void)
296 {
297 return hv_vpindex_settable;
298 }
299
kvm_get_tsc(CPUState * cs)300 static int kvm_get_tsc(CPUState *cs)
301 {
302 X86CPU *cpu = X86_CPU(cs);
303 CPUX86State *env = &cpu->env;
304 uint64_t value;
305 int ret;
306
307 if (env->tsc_valid) {
308 return 0;
309 }
310
311 env->tsc_valid = !runstate_is_running();
312
313 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
314 if (ret < 0) {
315 return ret;
316 }
317
318 env->tsc = value;
319 return 0;
320 }
321
do_kvm_synchronize_tsc(CPUState * cpu,run_on_cpu_data arg)322 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
323 {
324 kvm_get_tsc(cpu);
325 }
326
kvm_synchronize_all_tsc(void)327 void kvm_synchronize_all_tsc(void)
328 {
329 CPUState *cpu;
330
331 if (kvm_enabled() && !is_tdx_vm()) {
332 CPU_FOREACH(cpu) {
333 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
334 }
335 }
336 }
337
try_get_cpuid(KVMState * s,int max)338 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
339 {
340 struct kvm_cpuid2 *cpuid;
341 int r, size;
342
343 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
344 cpuid = g_malloc0(size);
345 cpuid->nent = max;
346 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
347 if (r == 0 && cpuid->nent >= max) {
348 r = -E2BIG;
349 }
350 if (r < 0) {
351 if (r == -E2BIG) {
352 g_free(cpuid);
353 return NULL;
354 } else {
355 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
356 strerror(-r));
357 exit(1);
358 }
359 }
360 return cpuid;
361 }
362
363 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
364 * for all entries.
365 */
get_supported_cpuid(KVMState * s)366 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
367 {
368 struct kvm_cpuid2 *cpuid;
369 int max = 1;
370
371 if (cpuid_cache != NULL) {
372 return cpuid_cache;
373 }
374 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
375 max *= 2;
376 }
377 cpuid_cache = cpuid;
378 return cpuid;
379 }
380
host_tsx_broken(void)381 static bool host_tsx_broken(void)
382 {
383 int family, model, stepping;\
384 char vendor[CPUID_VENDOR_SZ + 1];
385
386 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
387
388 /* Check if we are running on a Haswell host known to have broken TSX */
389 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
390 (family == 6) &&
391 ((model == 63 && stepping < 4) ||
392 model == 60 || model == 69 || model == 70);
393 }
394
395 /* Returns the value for a specific register on the cpuid entry
396 */
cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,int reg)397 uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
398 {
399 uint32_t ret = 0;
400 switch (reg) {
401 case R_EAX:
402 ret = entry->eax;
403 break;
404 case R_EBX:
405 ret = entry->ebx;
406 break;
407 case R_ECX:
408 ret = entry->ecx;
409 break;
410 case R_EDX:
411 ret = entry->edx;
412 break;
413 }
414 return ret;
415 }
416
417 /* Find matching entry for function/index on kvm_cpuid2 struct
418 */
cpuid_find_entry(struct kvm_cpuid2 * cpuid,uint32_t function,uint32_t index)419 struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
420 uint32_t function,
421 uint32_t index)
422 {
423 int i;
424 for (i = 0; i < cpuid->nent; ++i) {
425 if (cpuid->entries[i].function == function &&
426 cpuid->entries[i].index == index) {
427 return &cpuid->entries[i];
428 }
429 }
430 /* not found: */
431 return NULL;
432 }
433
kvm_arch_get_supported_cpuid(KVMState * s,uint32_t function,uint32_t index,int reg)434 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
435 uint32_t index, int reg)
436 {
437 struct kvm_cpuid2 *cpuid;
438 uint32_t ret = 0;
439 uint32_t cpuid_1_edx, unused;
440 uint64_t bitmask;
441
442 cpuid = get_supported_cpuid(s);
443
444 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
445 if (entry) {
446 ret = cpuid_entry_get_reg(entry, reg);
447 }
448
449 /* Fixups for the data returned by KVM, below */
450
451 if (function == 1 && reg == R_EDX) {
452 /* KVM before 2.6.30 misreports the following features */
453 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
454 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */
455 ret |= CPUID_HT;
456 } else if (function == 1 && reg == R_ECX) {
457 /* We can set the hypervisor flag, even if KVM does not return it on
458 * GET_SUPPORTED_CPUID
459 */
460 ret |= CPUID_EXT_HYPERVISOR;
461 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
462 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
463 * and the irqchip is in the kernel.
464 */
465 if (kvm_irqchip_in_kernel() &&
466 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
467 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
468 }
469
470 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
471 * without the in-kernel irqchip
472 */
473 if (!kvm_irqchip_in_kernel()) {
474 ret &= ~CPUID_EXT_X2APIC;
475 }
476
477 if (enable_cpu_pm) {
478 int disable_exits = kvm_check_extension(s,
479 KVM_CAP_X86_DISABLE_EXITS);
480
481 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
482 ret |= CPUID_EXT_MONITOR;
483 }
484 }
485 } else if (function == 6 && reg == R_EAX) {
486 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
487 } else if (function == 7 && index == 0 && reg == R_EBX) {
488 /* Not new instructions, just an optimization. */
489 uint32_t ebx;
490 host_cpuid(7, 0, &unused, &ebx, &unused, &unused);
491 ret |= ebx & CPUID_7_0_EBX_ERMS;
492
493 if (host_tsx_broken()) {
494 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
495 }
496 } else if (function == 7 && index == 0 && reg == R_EDX) {
497 /* Not new instructions, just an optimization. */
498 uint32_t edx;
499 host_cpuid(7, 0, &unused, &unused, &unused, &edx);
500 ret |= edx & CPUID_7_0_EDX_FSRM;
501
502 /*
503 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
504 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
505 * returned by KVM_GET_MSR_INDEX_LIST.
506 */
507 if (!has_msr_arch_capabs) {
508 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
509 }
510 } else if (function == 7 && index == 1 && reg == R_EAX) {
511 /* Not new instructions, just an optimization. */
512 uint32_t eax;
513 host_cpuid(7, 1, &eax, &unused, &unused, &unused);
514 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
515 } else if (function == 7 && index == 2 && reg == R_EDX) {
516 uint32_t edx;
517 host_cpuid(7, 2, &unused, &unused, &unused, &edx);
518 ret |= edx & CPUID_7_2_EDX_MCDT_NO;
519 } else if (function == 0xd && index == 0 &&
520 (reg == R_EAX || reg == R_EDX)) {
521 /*
522 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
523 * features that still have to be enabled with the arch_prctl
524 * system call. QEMU needs the full value, which is retrieved
525 * with KVM_GET_DEVICE_ATTR.
526 */
527 struct kvm_device_attr attr = {
528 .group = 0,
529 .attr = KVM_X86_XCOMP_GUEST_SUPP,
530 .addr = (unsigned long) &bitmask
531 };
532
533 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
534 if (!sys_attr) {
535 return ret;
536 }
537
538 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
539 if (rc < 0) {
540 if (rc != -ENXIO) {
541 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
542 "error: %d", rc);
543 }
544 return ret;
545 }
546 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
547 } else if (function == 0x80000001 && reg == R_ECX) {
548 /*
549 * It's safe to enable TOPOEXT even if it's not returned by
550 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
551 * us to keep CPU models including TOPOEXT runnable on older kernels.
552 */
553 ret |= CPUID_EXT3_TOPOEXT;
554 } else if (function == 0x80000001 && reg == R_EDX) {
555 /* On Intel, kvm returns cpuid according to the Intel spec,
556 * so add missing bits according to the AMD spec:
557 */
558 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
559 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
560 } else if (function == 0x80000007 && reg == R_EBX) {
561 ret |= CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR;
562 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
563 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
564 * be enabled without the in-kernel irqchip
565 */
566 if (!kvm_irqchip_in_kernel()) {
567 ret &= ~CPUID_KVM_PV_UNHALT;
568 }
569 if (kvm_irqchip_is_split()) {
570 ret |= CPUID_KVM_MSI_EXT_DEST_ID;
571 }
572 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
573 ret |= CPUID_KVM_HINTS_REALTIME;
574 }
575
576 if (current_machine->cgs) {
577 ret = x86_confidential_guest_adjust_cpuid_features(
578 X86_CONFIDENTIAL_GUEST(current_machine->cgs),
579 function, index, reg, ret);
580 }
581 return ret;
582 }
583
kvm_arch_get_supported_msr_feature(KVMState * s,uint32_t index)584 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
585 {
586 struct {
587 struct kvm_msrs info;
588 struct kvm_msr_entry entries[1];
589 } msr_data = {};
590 uint64_t value;
591 uint32_t ret, can_be_one, must_be_one;
592
593 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
594 return 0;
595 }
596
597 /* Check if requested MSR is supported feature MSR */
598 int i;
599 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
600 if (kvm_feature_msrs->indices[i] == index) {
601 break;
602 }
603 if (i == kvm_feature_msrs->nmsrs) {
604 return 0; /* if the feature MSR is not supported, simply return 0 */
605 }
606
607 msr_data.info.nmsrs = 1;
608 msr_data.entries[0].index = index;
609
610 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
611 if (ret != 1) {
612 error_report("KVM get MSR (index=0x%x) feature failed, %s",
613 index, strerror(-ret));
614 exit(1);
615 }
616
617 value = msr_data.entries[0].data;
618 switch (index) {
619 case MSR_IA32_VMX_PROCBASED_CTLS2:
620 if (!has_msr_vmx_procbased_ctls2) {
621 /* KVM forgot to add these bits for some time, do this ourselves. */
622 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
623 CPUID_XSAVE_XSAVES) {
624 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
625 }
626 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
627 CPUID_EXT_RDRAND) {
628 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
629 }
630 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
631 CPUID_7_0_EBX_INVPCID) {
632 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
633 }
634 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
635 CPUID_7_0_EBX_RDSEED) {
636 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
637 }
638 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
639 CPUID_EXT2_RDTSCP) {
640 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
641 }
642 }
643 /* fall through */
644 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
645 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
646 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
647 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
648 /*
649 * Return true for bits that can be one, but do not have to be one.
650 * The SDM tells us which bits could have a "must be one" setting,
651 * so we can do the opposite transformation in make_vmx_msr_value.
652 */
653 must_be_one = (uint32_t)value;
654 can_be_one = (uint32_t)(value >> 32);
655 return can_be_one & ~must_be_one;
656 case MSR_IA32_ARCH_CAPABILITIES:
657 /*
658 * Special handling for fb-clear bit in ARCH_CAPABILITIES MSR.
659 * KVM will only report the bit if it is enabled in the host,
660 * but, for live migration capability purposes, we want to
661 * expose the bit to the guest even if it is disabled in the
662 * host, as long as the host itself is not vulnerable to
663 * the issue that the fb-clear bit is meant to mitigate.
664 */
665 if ((value & MSR_ARCH_CAP_MDS_NO) &&
666 (value & MSR_ARCH_CAP_TAA_NO) &&
667 (value & MSR_ARCH_CAP_SBDR_SSDP_NO) &&
668 (value & MSR_ARCH_CAP_FBSDP_NO) &&
669 (value & MSR_ARCH_CAP_PSDP_NO)) {
670 value |= MSR_ARCH_CAP_FB_CLEAR;
671 }
672 return value;
673
674 default:
675 return value;
676 }
677 }
678
kvm_get_mce_cap_supported(KVMState * s,uint64_t * mce_cap,int * max_banks)679 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
680 int *max_banks)
681 {
682 *max_banks = kvm_check_extension(s, KVM_CAP_MCE);
683 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
684 }
685
kvm_mce_inject(X86CPU * cpu,hwaddr paddr,int code)686 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
687 {
688 CPUState *cs = CPU(cpu);
689 CPUX86State *env = &cpu->env;
690 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_MISCV |
691 MCI_STATUS_ADDRV;
692 uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
693 int flags = 0;
694
695 if (!IS_AMD_CPU(env)) {
696 status |= MCI_STATUS_S | MCI_STATUS_UC;
697 if (code == BUS_MCEERR_AR) {
698 status |= MCI_STATUS_AR | 0x134;
699 mcg_status |= MCG_STATUS_EIPV;
700 } else {
701 status |= 0xc0;
702 }
703 } else {
704 if (code == BUS_MCEERR_AR) {
705 status |= MCI_STATUS_UC | MCI_STATUS_POISON;
706 mcg_status |= MCG_STATUS_EIPV;
707 } else {
708 /* Setting the POISON bit for deferred errors indicates to the
709 * guest kernel that the address provided by the MCE is valid
710 * and usable which will ensure that the guest kernel will send
711 * a SIGBUS_AO signal to the guest process. This allows for
712 * more desirable behavior in the case that the guest process
713 * with poisoned memory has set the MCE_KILL_EARLY prctl flag
714 * which indicates that the process would prefer to handle or
715 * shutdown due to the poisoned memory condition before the
716 * memory has been accessed.
717 *
718 * While the POISON bit would not be set in a deferred error
719 * sent from hardware, the bit is not meaningful for deferred
720 * errors and can be reused in this scenario.
721 */
722 status |= MCI_STATUS_DEFERRED | MCI_STATUS_POISON;
723 }
724 }
725
726 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
727 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
728 * guest kernel back into env->mcg_ext_ctl.
729 */
730 cpu_synchronize_state(cs);
731 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
732 mcg_status |= MCG_STATUS_LMCE;
733 flags = 0;
734 }
735
736 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
737 (MCM_ADDR_PHYS << 6) | 0xc, flags);
738 }
739
emit_hypervisor_memory_failure(MemoryFailureAction action,bool ar)740 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
741 {
742 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
743
744 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
745 &mff);
746 }
747
hardware_memory_error(void * host_addr)748 static void hardware_memory_error(void *host_addr)
749 {
750 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
751 error_report("QEMU got Hardware memory error at addr %p", host_addr);
752 exit(1);
753 }
754
kvm_arch_on_sigbus_vcpu(CPUState * c,int code,void * addr)755 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
756 {
757 X86CPU *cpu = X86_CPU(c);
758 CPUX86State *env = &cpu->env;
759 ram_addr_t ram_addr;
760 hwaddr paddr;
761
762 /* If we get an action required MCE, it has been injected by KVM
763 * while the VM was running. An action optional MCE instead should
764 * be coming from the main thread, which qemu_init_sigbus identifies
765 * as the "early kill" thread.
766 */
767 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
768
769 if ((env->mcg_cap & MCG_SER_P) && addr) {
770 ram_addr = qemu_ram_addr_from_host(addr);
771 if (ram_addr != RAM_ADDR_INVALID &&
772 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
773 kvm_hwpoison_page_add(ram_addr);
774 kvm_mce_inject(cpu, paddr, code);
775
776 /*
777 * Use different logging severity based on error type.
778 * If there is additional MCE reporting on the hypervisor, QEMU VA
779 * could be another source to identify the PA and MCE details.
780 */
781 if (code == BUS_MCEERR_AR) {
782 error_report("Guest MCE Memory Error at QEMU addr %p and "
783 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
784 addr, paddr, "BUS_MCEERR_AR");
785 } else {
786 warn_report("Guest MCE Memory Error at QEMU addr %p and "
787 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
788 addr, paddr, "BUS_MCEERR_AO");
789 }
790
791 return;
792 }
793
794 if (code == BUS_MCEERR_AO) {
795 warn_report("Hardware memory error at addr %p of type %s "
796 "for memory used by QEMU itself instead of guest system!",
797 addr, "BUS_MCEERR_AO");
798 }
799 }
800
801 if (code == BUS_MCEERR_AR) {
802 hardware_memory_error(addr);
803 }
804
805 /* Hope we are lucky for AO MCE, just notify a event */
806 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
807 }
808
kvm_queue_exception(CPUX86State * env,int32_t exception_nr,uint8_t exception_has_payload,uint64_t exception_payload)809 static void kvm_queue_exception(CPUX86State *env,
810 int32_t exception_nr,
811 uint8_t exception_has_payload,
812 uint64_t exception_payload)
813 {
814 assert(env->exception_nr == -1);
815 assert(!env->exception_pending);
816 assert(!env->exception_injected);
817 assert(!env->exception_has_payload);
818
819 env->exception_nr = exception_nr;
820
821 if (has_exception_payload) {
822 env->exception_pending = 1;
823
824 env->exception_has_payload = exception_has_payload;
825 env->exception_payload = exception_payload;
826 } else {
827 env->exception_injected = 1;
828
829 if (exception_nr == EXCP01_DB) {
830 assert(exception_has_payload);
831 env->dr[6] = exception_payload;
832 } else if (exception_nr == EXCP0E_PAGE) {
833 assert(exception_has_payload);
834 env->cr[2] = exception_payload;
835 } else {
836 assert(!exception_has_payload);
837 }
838 }
839 }
840
cpu_update_state(void * opaque,bool running,RunState state)841 static void cpu_update_state(void *opaque, bool running, RunState state)
842 {
843 CPUX86State *env = opaque;
844
845 if (running) {
846 env->tsc_valid = false;
847 }
848 }
849
kvm_arch_vcpu_id(CPUState * cs)850 unsigned long kvm_arch_vcpu_id(CPUState *cs)
851 {
852 X86CPU *cpu = X86_CPU(cs);
853 return cpu->apic_id;
854 }
855
856 #ifndef KVM_CPUID_SIGNATURE_NEXT
857 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
858 #endif
859
hyperv_enabled(X86CPU * cpu)860 static bool hyperv_enabled(X86CPU *cpu)
861 {
862 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
863 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
864 cpu->hyperv_features || cpu->hyperv_passthrough);
865 }
866
867 /*
868 * Check whether target_freq is within conservative
869 * ntp correctable bounds (250ppm) of freq
870 */
freq_within_bounds(int freq,int target_freq)871 static inline bool freq_within_bounds(int freq, int target_freq)
872 {
873 int max_freq = freq + (freq * 250 / 1000000);
874 int min_freq = freq - (freq * 250 / 1000000);
875
876 if (target_freq >= min_freq && target_freq <= max_freq) {
877 return true;
878 }
879
880 return false;
881 }
882
kvm_arch_set_tsc_khz(CPUState * cs)883 static int kvm_arch_set_tsc_khz(CPUState *cs)
884 {
885 X86CPU *cpu = X86_CPU(cs);
886 CPUX86State *env = &cpu->env;
887 int r, cur_freq;
888 bool set_ioctl = false;
889
890 /*
891 * TSC of TD vcpu is immutable, it cannot be set/changed via vcpu scope
892 * VM_SET_TSC_KHZ, but only be initialized via VM scope VM_SET_TSC_KHZ
893 * before ioctl KVM_TDX_INIT_VM in tdx_pre_create_vcpu()
894 */
895 if (is_tdx_vm()) {
896 return 0;
897 }
898
899 if (!env->tsc_khz) {
900 return 0;
901 }
902
903 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
904 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
905
906 /*
907 * If TSC scaling is supported, attempt to set TSC frequency.
908 */
909 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
910 set_ioctl = true;
911 }
912
913 /*
914 * If desired TSC frequency is within bounds of NTP correction,
915 * attempt to set TSC frequency.
916 */
917 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
918 set_ioctl = true;
919 }
920
921 r = set_ioctl ?
922 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
923 -ENOTSUP;
924
925 if (r < 0) {
926 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
927 * TSC frequency doesn't match the one we want.
928 */
929 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
930 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
931 -ENOTSUP;
932 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
933 warn_report("TSC frequency mismatch between "
934 "VM (%" PRId64 " kHz) and host (%d kHz), "
935 "and TSC scaling unavailable",
936 env->tsc_khz, cur_freq);
937 return r;
938 }
939 }
940
941 return 0;
942 }
943
tsc_is_stable_and_known(CPUX86State * env)944 static bool tsc_is_stable_and_known(CPUX86State *env)
945 {
946 if (!env->tsc_khz) {
947 return false;
948 }
949 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
950 || env->user_tsc_khz;
951 }
952
953 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
954
955 static struct {
956 const char *desc;
957 struct {
958 uint32_t func;
959 int reg;
960 uint32_t bits;
961 } flags[2];
962 uint64_t dependencies;
963 bool skip_passthrough;
964 } kvm_hyperv_properties[] = {
965 [HYPERV_FEAT_RELAXED] = {
966 .desc = "relaxed timing (hv-relaxed)",
967 .flags = {
968 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
969 .bits = HV_RELAXED_TIMING_RECOMMENDED}
970 }
971 },
972 [HYPERV_FEAT_VAPIC] = {
973 .desc = "virtual APIC (hv-vapic)",
974 .flags = {
975 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
976 .bits = HV_APIC_ACCESS_AVAILABLE}
977 }
978 },
979 [HYPERV_FEAT_TIME] = {
980 .desc = "clocksources (hv-time)",
981 .flags = {
982 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
983 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
984 }
985 },
986 [HYPERV_FEAT_CRASH] = {
987 .desc = "crash MSRs (hv-crash)",
988 .flags = {
989 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
990 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
991 }
992 },
993 [HYPERV_FEAT_RESET] = {
994 .desc = "reset MSR (hv-reset)",
995 .flags = {
996 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
997 .bits = HV_RESET_AVAILABLE}
998 }
999 },
1000 [HYPERV_FEAT_VPINDEX] = {
1001 .desc = "VP_INDEX MSR (hv-vpindex)",
1002 .flags = {
1003 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1004 .bits = HV_VP_INDEX_AVAILABLE}
1005 }
1006 },
1007 [HYPERV_FEAT_RUNTIME] = {
1008 .desc = "VP_RUNTIME MSR (hv-runtime)",
1009 .flags = {
1010 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1011 .bits = HV_VP_RUNTIME_AVAILABLE}
1012 }
1013 },
1014 [HYPERV_FEAT_SYNIC] = {
1015 .desc = "synthetic interrupt controller (hv-synic)",
1016 .flags = {
1017 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1018 .bits = HV_SYNIC_AVAILABLE}
1019 }
1020 },
1021 [HYPERV_FEAT_STIMER] = {
1022 .desc = "synthetic timers (hv-stimer)",
1023 .flags = {
1024 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1025 .bits = HV_SYNTIMERS_AVAILABLE}
1026 },
1027 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
1028 },
1029 [HYPERV_FEAT_FREQUENCIES] = {
1030 .desc = "frequency MSRs (hv-frequencies)",
1031 .flags = {
1032 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1033 .bits = HV_ACCESS_FREQUENCY_MSRS},
1034 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1035 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
1036 }
1037 },
1038 [HYPERV_FEAT_REENLIGHTENMENT] = {
1039 .desc = "reenlightenment MSRs (hv-reenlightenment)",
1040 .flags = {
1041 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1042 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
1043 }
1044 },
1045 [HYPERV_FEAT_TLBFLUSH] = {
1046 .desc = "paravirtualized TLB flush (hv-tlbflush)",
1047 .flags = {
1048 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1049 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
1050 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1051 },
1052 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1053 },
1054 [HYPERV_FEAT_EVMCS] = {
1055 .desc = "enlightened VMCS (hv-evmcs)",
1056 .flags = {
1057 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1058 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
1059 },
1060 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1061 },
1062 [HYPERV_FEAT_IPI] = {
1063 .desc = "paravirtualized IPI (hv-ipi)",
1064 .flags = {
1065 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1066 .bits = HV_CLUSTER_IPI_RECOMMENDED |
1067 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1068 },
1069 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1070 },
1071 [HYPERV_FEAT_STIMER_DIRECT] = {
1072 .desc = "direct mode synthetic timers (hv-stimer-direct)",
1073 .flags = {
1074 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1075 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
1076 },
1077 .dependencies = BIT(HYPERV_FEAT_STIMER)
1078 },
1079 [HYPERV_FEAT_AVIC] = {
1080 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
1081 .flags = {
1082 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1083 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
1084 }
1085 },
1086 [HYPERV_FEAT_SYNDBG] = {
1087 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
1088 .flags = {
1089 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1090 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
1091 },
1092 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED),
1093 .skip_passthrough = true,
1094 },
1095 [HYPERV_FEAT_MSR_BITMAP] = {
1096 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
1097 .flags = {
1098 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1099 .bits = HV_NESTED_MSR_BITMAP}
1100 }
1101 },
1102 [HYPERV_FEAT_XMM_INPUT] = {
1103 .desc = "XMM fast hypercall input (hv-xmm-input)",
1104 .flags = {
1105 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1106 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
1107 }
1108 },
1109 [HYPERV_FEAT_TLBFLUSH_EXT] = {
1110 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
1111 .flags = {
1112 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1113 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
1114 },
1115 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
1116 },
1117 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1118 .desc = "direct TLB flush (hv-tlbflush-direct)",
1119 .flags = {
1120 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1121 .bits = HV_NESTED_DIRECT_FLUSH}
1122 },
1123 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1124 },
1125 };
1126
try_get_hv_cpuid(CPUState * cs,int max,bool do_sys_ioctl)1127 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1128 bool do_sys_ioctl)
1129 {
1130 struct kvm_cpuid2 *cpuid;
1131 int r, size;
1132
1133 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1134 cpuid = g_malloc0(size);
1135 cpuid->nent = max;
1136
1137 if (do_sys_ioctl) {
1138 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1139 } else {
1140 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1141 }
1142 if (r == 0 && cpuid->nent >= max) {
1143 r = -E2BIG;
1144 }
1145 if (r < 0) {
1146 if (r == -E2BIG) {
1147 g_free(cpuid);
1148 return NULL;
1149 } else {
1150 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1151 strerror(-r));
1152 exit(1);
1153 }
1154 }
1155 return cpuid;
1156 }
1157
1158 /*
1159 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1160 * for all entries.
1161 */
get_supported_hv_cpuid(CPUState * cs)1162 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1163 {
1164 struct kvm_cpuid2 *cpuid;
1165 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1166 int max = 11;
1167 int i;
1168 bool do_sys_ioctl;
1169
1170 do_sys_ioctl =
1171 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
1172
1173 /*
1174 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1175 * unsupported, kvm_hyperv_expand_features() checks for that.
1176 */
1177 assert(do_sys_ioctl || cs->kvm_state);
1178
1179 /*
1180 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1181 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1182 * it and re-trying until we succeed.
1183 */
1184 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
1185 max++;
1186 }
1187
1188 /*
1189 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1190 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1191 * information early, just check for the capability and set the bit
1192 * manually.
1193 */
1194 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
1195 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1196 for (i = 0; i < cpuid->nent; i++) {
1197 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1198 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1199 }
1200 }
1201 }
1202
1203 return cpuid;
1204 }
1205
1206 /*
1207 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1208 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1209 */
get_supported_hv_cpuid_legacy(CPUState * cs)1210 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1211 {
1212 X86CPU *cpu = X86_CPU(cs);
1213 struct kvm_cpuid2 *cpuid;
1214 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1215
1216 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1217 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1218 cpuid->nent = 2;
1219
1220 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1221 entry_feat = &cpuid->entries[0];
1222 entry_feat->function = HV_CPUID_FEATURES;
1223
1224 entry_recomm = &cpuid->entries[1];
1225 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1226 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1227
1228 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1229 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1230 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1231 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1232 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1233 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1234 }
1235
1236 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1237 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1238 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1239 }
1240
1241 if (has_msr_hv_frequencies) {
1242 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1243 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1244 }
1245
1246 if (has_msr_hv_crash) {
1247 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1248 }
1249
1250 if (has_msr_hv_reenlightenment) {
1251 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1252 }
1253
1254 if (has_msr_hv_reset) {
1255 entry_feat->eax |= HV_RESET_AVAILABLE;
1256 }
1257
1258 if (has_msr_hv_vpindex) {
1259 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1260 }
1261
1262 if (has_msr_hv_runtime) {
1263 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1264 }
1265
1266 if (has_msr_hv_synic) {
1267 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1268 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1269
1270 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1271 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1272 }
1273 }
1274
1275 if (has_msr_hv_stimer) {
1276 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1277 }
1278
1279 if (has_msr_hv_syndbg_options) {
1280 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1281 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1282 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1283 }
1284
1285 if (kvm_check_extension(cs->kvm_state,
1286 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1287 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1288 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1289 }
1290
1291 if (kvm_check_extension(cs->kvm_state,
1292 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1293 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1294 }
1295
1296 if (kvm_check_extension(cs->kvm_state,
1297 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1298 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1299 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1300 }
1301
1302 return cpuid;
1303 }
1304
hv_cpuid_get_host(CPUState * cs,uint32_t func,int reg)1305 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1306 {
1307 struct kvm_cpuid_entry2 *entry;
1308 struct kvm_cpuid2 *cpuid;
1309
1310 if (hv_cpuid_cache) {
1311 cpuid = hv_cpuid_cache;
1312 } else {
1313 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1314 cpuid = get_supported_hv_cpuid(cs);
1315 } else {
1316 /*
1317 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1318 * before KVM context is created but this is only done when
1319 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1320 * KVM_CAP_HYPERV_CPUID.
1321 */
1322 assert(cs->kvm_state);
1323
1324 cpuid = get_supported_hv_cpuid_legacy(cs);
1325 }
1326 hv_cpuid_cache = cpuid;
1327 }
1328
1329 if (!cpuid) {
1330 return 0;
1331 }
1332
1333 entry = cpuid_find_entry(cpuid, func, 0);
1334 if (!entry) {
1335 return 0;
1336 }
1337
1338 return cpuid_entry_get_reg(entry, reg);
1339 }
1340
hyperv_feature_supported(CPUState * cs,int feature)1341 static bool hyperv_feature_supported(CPUState *cs, int feature)
1342 {
1343 uint32_t func, bits;
1344 int i, reg;
1345
1346 /*
1347 * kvm_hyperv_properties needs to define at least one CPUID flag which
1348 * must be used to detect the feature, it's hard to say whether it is
1349 * supported or not otherwise.
1350 */
1351 assert(kvm_hyperv_properties[feature].flags[0].func);
1352
1353 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1354
1355 func = kvm_hyperv_properties[feature].flags[i].func;
1356 reg = kvm_hyperv_properties[feature].flags[i].reg;
1357 bits = kvm_hyperv_properties[feature].flags[i].bits;
1358
1359 if (!func) {
1360 continue;
1361 }
1362
1363 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1364 return false;
1365 }
1366 }
1367
1368 return true;
1369 }
1370
1371 /* Checks that all feature dependencies are enabled */
hv_feature_check_deps(X86CPU * cpu,int feature,Error ** errp)1372 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
1373 {
1374 uint64_t deps;
1375 int dep_feat;
1376
1377 deps = kvm_hyperv_properties[feature].dependencies;
1378 while (deps) {
1379 dep_feat = ctz64(deps);
1380 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1381 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1382 kvm_hyperv_properties[feature].desc,
1383 kvm_hyperv_properties[dep_feat].desc);
1384 return false;
1385 }
1386 deps &= ~(1ull << dep_feat);
1387 }
1388
1389 return true;
1390 }
1391
hv_build_cpuid_leaf(CPUState * cs,uint32_t func,int reg)1392 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1393 {
1394 X86CPU *cpu = X86_CPU(cs);
1395 uint32_t r = 0;
1396 int i, j;
1397
1398 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1399 if (!hyperv_feat_enabled(cpu, i)) {
1400 continue;
1401 }
1402
1403 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1404 if (kvm_hyperv_properties[i].flags[j].func != func) {
1405 continue;
1406 }
1407 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1408 continue;
1409 }
1410
1411 r |= kvm_hyperv_properties[i].flags[j].bits;
1412 }
1413 }
1414
1415 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1416 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1417 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1418 r |= DEFAULT_EVMCS_VERSION;
1419 }
1420 }
1421
1422 return r;
1423 }
1424
1425 /*
1426 * Expand Hyper-V CPU features. In partucular, check that all the requested
1427 * features are supported by the host and the sanity of the configuration
1428 * (that all the required dependencies are included). Also, this takes care
1429 * of 'hv_passthrough' mode and fills the environment with all supported
1430 * Hyper-V features.
1431 */
kvm_hyperv_expand_features(X86CPU * cpu,Error ** errp)1432 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
1433 {
1434 CPUState *cs = CPU(cpu);
1435 Error *local_err = NULL;
1436 int feat;
1437
1438 if (!hyperv_enabled(cpu))
1439 return true;
1440
1441 /*
1442 * When kvm_hyperv_expand_features is called at CPU feature expansion
1443 * time per-CPU kvm_state is not available yet so we can only proceed
1444 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1445 */
1446 if (!cs->kvm_state &&
1447 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1448 return true;
1449
1450 if (cpu->hyperv_passthrough) {
1451 cpu->hyperv_vendor_id[0] =
1452 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1453 cpu->hyperv_vendor_id[1] =
1454 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1455 cpu->hyperv_vendor_id[2] =
1456 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1457 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1458 sizeof(cpu->hyperv_vendor_id) + 1);
1459 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1460 sizeof(cpu->hyperv_vendor_id));
1461 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1462
1463 cpu->hyperv_interface_id[0] =
1464 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1465 cpu->hyperv_interface_id[1] =
1466 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1467 cpu->hyperv_interface_id[2] =
1468 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1469 cpu->hyperv_interface_id[3] =
1470 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1471
1472 cpu->hyperv_ver_id_build =
1473 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1474 cpu->hyperv_ver_id_major =
1475 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1476 cpu->hyperv_ver_id_minor =
1477 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1478 cpu->hyperv_ver_id_sp =
1479 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1480 cpu->hyperv_ver_id_sb =
1481 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1482 cpu->hyperv_ver_id_sn =
1483 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
1484
1485 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1486 R_EAX);
1487 cpu->hyperv_limits[0] =
1488 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1489 cpu->hyperv_limits[1] =
1490 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1491 cpu->hyperv_limits[2] =
1492 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1493
1494 cpu->hyperv_spinlock_attempts =
1495 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1496
1497 /*
1498 * Mark feature as enabled in 'cpu->hyperv_features' as
1499 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1500 */
1501 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1502 if (hyperv_feature_supported(cs, feat) &&
1503 !kvm_hyperv_properties[feat].skip_passthrough) {
1504 cpu->hyperv_features |= BIT(feat);
1505 }
1506 }
1507 } else {
1508 /* Check features availability and dependencies */
1509 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1510 /* If the feature was not requested skip it. */
1511 if (!hyperv_feat_enabled(cpu, feat)) {
1512 continue;
1513 }
1514
1515 /* Check if the feature is supported by KVM */
1516 if (!hyperv_feature_supported(cs, feat)) {
1517 error_setg(errp, "Hyper-V %s is not supported by kernel",
1518 kvm_hyperv_properties[feat].desc);
1519 return false;
1520 }
1521
1522 /* Check dependencies */
1523 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1524 error_propagate(errp, local_err);
1525 return false;
1526 }
1527 }
1528 }
1529
1530 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1531 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1532 !cpu->hyperv_synic_kvm_only &&
1533 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1534 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1535 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1536 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1537 return false;
1538 }
1539
1540 return true;
1541 }
1542
1543 /*
1544 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1545 */
hyperv_fill_cpuids(CPUState * cs,struct kvm_cpuid_entry2 * cpuid_ent)1546 static int hyperv_fill_cpuids(CPUState *cs,
1547 struct kvm_cpuid_entry2 *cpuid_ent)
1548 {
1549 X86CPU *cpu = X86_CPU(cs);
1550 struct kvm_cpuid_entry2 *c;
1551 uint32_t signature[3];
1552 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
1553 uint32_t nested_eax =
1554 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
1555
1556 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1557 HV_CPUID_IMPLEMENT_LIMITS;
1558
1559 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1560 max_cpuid_leaf =
1561 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1562 }
1563
1564 c = &cpuid_ent[cpuid_i++];
1565 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1566 c->eax = max_cpuid_leaf;
1567 c->ebx = cpu->hyperv_vendor_id[0];
1568 c->ecx = cpu->hyperv_vendor_id[1];
1569 c->edx = cpu->hyperv_vendor_id[2];
1570
1571 c = &cpuid_ent[cpuid_i++];
1572 c->function = HV_CPUID_INTERFACE;
1573 c->eax = cpu->hyperv_interface_id[0];
1574 c->ebx = cpu->hyperv_interface_id[1];
1575 c->ecx = cpu->hyperv_interface_id[2];
1576 c->edx = cpu->hyperv_interface_id[3];
1577
1578 c = &cpuid_ent[cpuid_i++];
1579 c->function = HV_CPUID_VERSION;
1580 c->eax = cpu->hyperv_ver_id_build;
1581 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1582 cpu->hyperv_ver_id_minor;
1583 c->ecx = cpu->hyperv_ver_id_sp;
1584 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1585 (cpu->hyperv_ver_id_sn & 0xffffff);
1586
1587 c = &cpuid_ent[cpuid_i++];
1588 c->function = HV_CPUID_FEATURES;
1589 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1590 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1591 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1592
1593 /* Unconditionally required with any Hyper-V enlightenment */
1594 c->eax |= HV_HYPERCALL_AVAILABLE;
1595
1596 /* SynIC and Vmbus devices require messages/signals hypercalls */
1597 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1598 !cpu->hyperv_synic_kvm_only) {
1599 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1600 }
1601
1602
1603 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1604 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1605
1606 c = &cpuid_ent[cpuid_i++];
1607 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1608 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1609 c->ebx = cpu->hyperv_spinlock_attempts;
1610
1611 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1612 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
1613 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1614 }
1615
1616 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1617 c->eax |= HV_NO_NONARCH_CORESHARING;
1618 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1619 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1620 HV_NO_NONARCH_CORESHARING;
1621 }
1622
1623 c = &cpuid_ent[cpuid_i++];
1624 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1625 c->eax = cpu->hv_max_vps;
1626 c->ebx = cpu->hyperv_limits[0];
1627 c->ecx = cpu->hyperv_limits[1];
1628 c->edx = cpu->hyperv_limits[2];
1629
1630 if (nested_eax) {
1631 uint32_t function;
1632
1633 /* Create zeroed 0x40000006..0x40000009 leaves */
1634 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1635 function < HV_CPUID_NESTED_FEATURES; function++) {
1636 c = &cpuid_ent[cpuid_i++];
1637 c->function = function;
1638 }
1639
1640 c = &cpuid_ent[cpuid_i++];
1641 c->function = HV_CPUID_NESTED_FEATURES;
1642 c->eax = nested_eax;
1643 }
1644
1645 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1646 c = &cpuid_ent[cpuid_i++];
1647 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1648 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1649 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1650 memcpy(signature, "Microsoft VS", 12);
1651 c->eax = 0;
1652 c->ebx = signature[0];
1653 c->ecx = signature[1];
1654 c->edx = signature[2];
1655
1656 c = &cpuid_ent[cpuid_i++];
1657 c->function = HV_CPUID_SYNDBG_INTERFACE;
1658 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1659 c->eax = signature[0];
1660 c->ebx = 0;
1661 c->ecx = 0;
1662 c->edx = 0;
1663
1664 c = &cpuid_ent[cpuid_i++];
1665 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1666 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1667 c->ebx = 0;
1668 c->ecx = 0;
1669 c->edx = 0;
1670 }
1671
1672 return cpuid_i;
1673 }
1674
1675 static Error *hv_passthrough_mig_blocker;
1676 static Error *hv_no_nonarch_cs_mig_blocker;
1677
1678 /* Checks that the exposed eVMCS version range is supported by KVM */
evmcs_version_supported(uint16_t evmcs_version,uint16_t supported_evmcs_version)1679 static bool evmcs_version_supported(uint16_t evmcs_version,
1680 uint16_t supported_evmcs_version)
1681 {
1682 uint8_t min_version = evmcs_version & 0xff;
1683 uint8_t max_version = evmcs_version >> 8;
1684 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1685 uint8_t max_supported_version = supported_evmcs_version >> 8;
1686
1687 return (min_version >= min_supported_version) &&
1688 (max_version <= max_supported_version);
1689 }
1690
hyperv_init_vcpu(X86CPU * cpu)1691 static int hyperv_init_vcpu(X86CPU *cpu)
1692 {
1693 CPUState *cs = CPU(cpu);
1694 Error *local_err = NULL;
1695 int ret;
1696
1697 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1698 error_setg(&hv_passthrough_mig_blocker,
1699 "'hv-passthrough' CPU flag prevents migration, use explicit"
1700 " set of hv-* flags instead");
1701 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err);
1702 if (ret < 0) {
1703 error_report_err(local_err);
1704 return ret;
1705 }
1706 }
1707
1708 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1709 hv_no_nonarch_cs_mig_blocker == NULL) {
1710 error_setg(&hv_no_nonarch_cs_mig_blocker,
1711 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1712 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1713 " make sure SMT is disabled and/or that vCPUs are properly"
1714 " pinned)");
1715 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err);
1716 if (ret < 0) {
1717 error_report_err(local_err);
1718 return ret;
1719 }
1720 }
1721
1722 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1723 /*
1724 * the kernel doesn't support setting vp_index; assert that its value
1725 * is in sync
1726 */
1727 uint64_t value;
1728
1729 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
1730 if (ret < 0) {
1731 return ret;
1732 }
1733
1734 if (value != hyperv_vp_index(CPU(cpu))) {
1735 error_report("kernel's vp_index != QEMU's vp_index");
1736 return -ENXIO;
1737 }
1738 }
1739
1740 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1741 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1742 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1743 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1744 if (ret < 0) {
1745 error_report("failed to turn on HyperV SynIC in KVM: %s",
1746 strerror(-ret));
1747 return ret;
1748 }
1749
1750 if (!cpu->hyperv_synic_kvm_only) {
1751 ret = hyperv_x86_synic_add(cpu);
1752 if (ret < 0) {
1753 error_report("failed to create HyperV SynIC: %s",
1754 strerror(-ret));
1755 return ret;
1756 }
1757 }
1758 }
1759
1760 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1761 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1762 uint16_t supported_evmcs_version;
1763
1764 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1765 (uintptr_t)&supported_evmcs_version);
1766
1767 /*
1768 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1769 * option sets. Note: we hardcode the maximum supported eVMCS version
1770 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1771 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1772 * to be added.
1773 */
1774 if (ret < 0) {
1775 error_report("Hyper-V %s is not supported by kernel",
1776 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1777 return ret;
1778 }
1779
1780 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1781 error_report("eVMCS version range [%d..%d] is not supported by "
1782 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1783 evmcs_version >> 8, supported_evmcs_version & 0xff,
1784 supported_evmcs_version >> 8);
1785 return -ENOTSUP;
1786 }
1787 }
1788
1789 if (cpu->hyperv_enforce_cpuid) {
1790 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1791 if (ret < 0) {
1792 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1793 strerror(-ret));
1794 return ret;
1795 }
1796 }
1797
1798 /* Skip SynIC and VP_INDEX since they are hard deps already */
1799 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) &&
1800 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1801 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
1802 hyperv_x86_set_vmbus_recommended_features_enabled();
1803 }
1804
1805 return 0;
1806 }
1807
1808 static Error *invtsc_mig_blocker;
1809
kvm_init_xsave(CPUX86State * env)1810 static void kvm_init_xsave(CPUX86State *env)
1811 {
1812 if (has_xsave2) {
1813 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1814 } else {
1815 env->xsave_buf_len = sizeof(struct kvm_xsave);
1816 }
1817
1818 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1819 memset(env->xsave_buf, 0, env->xsave_buf_len);
1820 /*
1821 * The allocated storage must be large enough for all of the
1822 * possible XSAVE state components.
1823 */
1824 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1825 env->xsave_buf_len);
1826 }
1827
kvm_init_nested_state(CPUX86State * env)1828 static void kvm_init_nested_state(CPUX86State *env)
1829 {
1830 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1831 uint32_t size;
1832
1833 if (!env->nested_state) {
1834 return;
1835 }
1836
1837 size = env->nested_state->size;
1838
1839 memset(env->nested_state, 0, size);
1840 env->nested_state->size = size;
1841
1842 if (cpu_has_vmx(env)) {
1843 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1844 vmx_hdr = &env->nested_state->hdr.vmx;
1845 vmx_hdr->vmxon_pa = -1ull;
1846 vmx_hdr->vmcs12_pa = -1ull;
1847 } else if (cpu_has_svm(env)) {
1848 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1849 }
1850 }
1851
kvm_x86_build_cpuid(CPUX86State * env,struct kvm_cpuid_entry2 * entries,uint32_t cpuid_i)1852 uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries,
1853 uint32_t cpuid_i)
1854 {
1855 uint32_t limit, i, j;
1856 uint32_t unused;
1857 struct kvm_cpuid_entry2 *c;
1858
1859 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1860
1861 for (i = 0; i <= limit; i++) {
1862 j = 0;
1863 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1864 goto full;
1865 }
1866 c = &entries[cpuid_i++];
1867 switch (i) {
1868 case 2: {
1869 /* Keep reading function 2 till all the input is received */
1870 int times;
1871
1872 c->function = i;
1873 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1874 times = c->eax & 0xff;
1875 if (times > 1) {
1876 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1877 KVM_CPUID_FLAG_STATE_READ_NEXT;
1878 }
1879
1880 for (j = 1; j < times; ++j) {
1881 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1882 goto full;
1883 }
1884 c = &entries[cpuid_i++];
1885 c->function = i;
1886 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1887 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1888 }
1889 break;
1890 }
1891 case 0x1f:
1892 if (!x86_has_cpuid_0x1f(env_archcpu(env))) {
1893 cpuid_i--;
1894 break;
1895 }
1896 /* fallthrough */
1897 case 4:
1898 case 0xb:
1899 case 0xd:
1900 for (j = 0; ; j++) {
1901 c->function = i;
1902 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1903 c->index = j;
1904 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1905
1906 if (i == 4 && c->eax == 0) {
1907 break;
1908 }
1909 if (i == 0xb && !(c->ecx & 0xff00)) {
1910 break;
1911 }
1912 if (i == 0x1f && !(c->ecx & 0xff00)) {
1913 break;
1914 }
1915 if (i == 0xd && c->eax == 0) {
1916 if (j < 63) {
1917 continue;
1918 } else {
1919 cpuid_i--;
1920 break;
1921 }
1922 }
1923 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1924 goto full;
1925 }
1926 c = &entries[cpuid_i++];
1927 }
1928 break;
1929 case 0x12:
1930 for (j = 0; ; j++) {
1931 c->function = i;
1932 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1933 c->index = j;
1934 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1935
1936 if (j > 1 && (c->eax & 0xf) != 1) {
1937 break;
1938 }
1939
1940 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1941 goto full;
1942 }
1943 c = &entries[cpuid_i++];
1944 }
1945 break;
1946 case 0x7:
1947 case 0x14:
1948 case 0x1d:
1949 case 0x1e:
1950 case 0x24: {
1951 uint32_t times;
1952
1953 c->function = i;
1954 c->index = 0;
1955 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1956 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1957 times = c->eax;
1958
1959 for (j = 1; j <= times; ++j) {
1960 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1961 goto full;
1962 }
1963 c = &entries[cpuid_i++];
1964 c->function = i;
1965 c->index = j;
1966 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1967 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1968 }
1969 break;
1970 }
1971 default:
1972 c->function = i;
1973 c->flags = 0;
1974 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1975 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1976 /*
1977 * KVM already returns all zeroes if a CPUID entry is missing,
1978 * so we can omit it and avoid hitting KVM's 80-entry limit.
1979 */
1980 cpuid_i--;
1981 }
1982 break;
1983 }
1984 }
1985
1986 if (limit >= 0x0a) {
1987 uint32_t eax, edx;
1988
1989 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1990
1991 has_architectural_pmu_version = eax & 0xff;
1992 if (has_architectural_pmu_version > 0) {
1993 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1994
1995 /* Shouldn't be more than 32, since that's the number of bits
1996 * available in EBX to tell us _which_ counters are available.
1997 * Play it safe.
1998 */
1999 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
2000 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
2001 }
2002
2003 if (has_architectural_pmu_version > 1) {
2004 num_architectural_pmu_fixed_counters = edx & 0x1f;
2005
2006 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
2007 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
2008 }
2009 }
2010 }
2011 }
2012
2013 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
2014
2015 for (i = 0x80000000; i <= limit; i++) {
2016 j = 0;
2017 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2018 goto full;
2019 }
2020 c = &entries[cpuid_i++];
2021
2022 switch (i) {
2023 case 0x8000001d:
2024 /* Query for all AMD cache information leaves */
2025 for (j = 0; ; j++) {
2026 c->function = i;
2027 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2028 c->index = j;
2029 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2030
2031 if (c->eax == 0) {
2032 break;
2033 }
2034 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2035 goto full;
2036 }
2037 c = &entries[cpuid_i++];
2038 }
2039 break;
2040 default:
2041 c->function = i;
2042 c->flags = 0;
2043 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2044 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2045 /*
2046 * KVM already returns all zeroes if a CPUID entry is missing,
2047 * so we can omit it and avoid hitting KVM's 80-entry limit.
2048 */
2049 cpuid_i--;
2050 }
2051 break;
2052 }
2053 }
2054
2055 /* Call Centaur's CPUID instructions they are supported. */
2056 if (env->cpuid_xlevel2 > 0) {
2057 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2058
2059 for (i = 0xC0000000; i <= limit; i++) {
2060 j = 0;
2061 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2062 goto full;
2063 }
2064 c = &entries[cpuid_i++];
2065
2066 c->function = i;
2067 c->flags = 0;
2068 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2069 }
2070 }
2071
2072 return cpuid_i;
2073
2074 full:
2075 fprintf(stderr, "cpuid_data is full, no space for "
2076 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2077 abort();
2078 }
2079
kvm_arch_pre_create_vcpu(CPUState * cpu,Error ** errp)2080 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp)
2081 {
2082 if (is_tdx_vm()) {
2083 return tdx_pre_create_vcpu(cpu, errp);
2084 }
2085
2086 return 0;
2087 }
2088
kvm_arch_init_vcpu(CPUState * cs)2089 int kvm_arch_init_vcpu(CPUState *cs)
2090 {
2091 struct {
2092 struct kvm_cpuid2 cpuid;
2093 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
2094 } cpuid_data;
2095 /*
2096 * The kernel defines these structs with padding fields so there
2097 * should be no extra padding in our cpuid_data struct.
2098 */
2099 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
2100 sizeof(struct kvm_cpuid2) +
2101 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
2102
2103 X86CPU *cpu = X86_CPU(cs);
2104 CPUX86State *env = &cpu->env;
2105 uint32_t cpuid_i;
2106 struct kvm_cpuid_entry2 *c;
2107 uint32_t signature[3];
2108 int kvm_base = KVM_CPUID_SIGNATURE;
2109 int max_nested_state_len;
2110 int r;
2111 Error *local_err = NULL;
2112
2113 if (current_machine->cgs) {
2114 r = x86_confidential_guest_check_features(
2115 X86_CONFIDENTIAL_GUEST(current_machine->cgs), cs);
2116 if (r < 0) {
2117 return r;
2118 }
2119 }
2120
2121 memset(&cpuid_data, 0, sizeof(cpuid_data));
2122
2123 cpuid_i = 0;
2124
2125 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
2126
2127 r = kvm_arch_set_tsc_khz(cs);
2128 if (r < 0) {
2129 return r;
2130 }
2131
2132 /* vcpu's TSC frequency is either specified by user, or following
2133 * the value used by KVM if the former is not present. In the
2134 * latter case, we query it from KVM and record in env->tsc_khz,
2135 * so that vcpu's TSC frequency can be migrated later via this field.
2136 */
2137 if (!env->tsc_khz) {
2138 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
2139 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
2140 -ENOTSUP;
2141 if (r > 0) {
2142 env->tsc_khz = r;
2143 }
2144 }
2145
2146 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
2147
2148 /*
2149 * kvm_hyperv_expand_features() is called here for the second time in case
2150 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
2151 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
2152 * check which Hyper-V enlightenments are supported and which are not, we
2153 * can still proceed and check/expand Hyper-V enlightenments here so legacy
2154 * behavior is preserved.
2155 */
2156 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
2157 error_report_err(local_err);
2158 return -ENOSYS;
2159 }
2160
2161 if (hyperv_enabled(cpu)) {
2162 r = hyperv_init_vcpu(cpu);
2163 if (r) {
2164 return r;
2165 }
2166
2167 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
2168 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
2169 has_msr_hv_hypercall = true;
2170 }
2171
2172 if (cs->kvm_state->xen_version) {
2173 #ifdef CONFIG_XEN_EMU
2174 struct kvm_cpuid_entry2 *xen_max_leaf;
2175
2176 memcpy(signature, "XenVMMXenVMM", 12);
2177
2178 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
2179 c->function = kvm_base + XEN_CPUID_SIGNATURE;
2180 c->eax = kvm_base + XEN_CPUID_TIME;
2181 c->ebx = signature[0];
2182 c->ecx = signature[1];
2183 c->edx = signature[2];
2184
2185 c = &cpuid_data.entries[cpuid_i++];
2186 c->function = kvm_base + XEN_CPUID_VENDOR;
2187 c->eax = cs->kvm_state->xen_version;
2188 c->ebx = 0;
2189 c->ecx = 0;
2190 c->edx = 0;
2191
2192 c = &cpuid_data.entries[cpuid_i++];
2193 c->function = kvm_base + XEN_CPUID_HVM_MSR;
2194 /* Number of hypercall-transfer pages */
2195 c->eax = 1;
2196 /* Hypercall MSR base address */
2197 if (hyperv_enabled(cpu)) {
2198 c->ebx = XEN_HYPERCALL_MSR_HYPERV;
2199 kvm_xen_init(cs->kvm_state, c->ebx);
2200 } else {
2201 c->ebx = XEN_HYPERCALL_MSR;
2202 }
2203 c->ecx = 0;
2204 c->edx = 0;
2205
2206 c = &cpuid_data.entries[cpuid_i++];
2207 c->function = kvm_base + XEN_CPUID_TIME;
2208 c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
2209 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
2210 /* default=0 (emulate if necessary) */
2211 c->ebx = 0;
2212 /* guest tsc frequency */
2213 c->ecx = env->user_tsc_khz;
2214 /* guest tsc incarnation (migration count) */
2215 c->edx = 0;
2216
2217 c = &cpuid_data.entries[cpuid_i++];
2218 c->function = kvm_base + XEN_CPUID_HVM;
2219 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
2220 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
2221 c->function = kvm_base + XEN_CPUID_HVM;
2222
2223 if (cpu->xen_vapic) {
2224 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
2225 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
2226 }
2227
2228 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
2229
2230 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
2231 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
2232 c->ebx = cs->cpu_index;
2233 }
2234
2235 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) {
2236 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR;
2237 }
2238 }
2239
2240 r = kvm_xen_init_vcpu(cs);
2241 if (r) {
2242 return r;
2243 }
2244
2245 kvm_base += 0x100;
2246 #else /* CONFIG_XEN_EMU */
2247 /* This should never happen as kvm_arch_init() would have died first. */
2248 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
2249 abort();
2250 #endif
2251 } else if (cpu->expose_kvm) {
2252 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
2253 c = &cpuid_data.entries[cpuid_i++];
2254 c->function = KVM_CPUID_SIGNATURE | kvm_base;
2255 c->eax = KVM_CPUID_FEATURES | kvm_base;
2256 c->ebx = signature[0];
2257 c->ecx = signature[1];
2258 c->edx = signature[2];
2259
2260 c = &cpuid_data.entries[cpuid_i++];
2261 c->function = KVM_CPUID_FEATURES | kvm_base;
2262 c->eax = env->features[FEAT_KVM];
2263 c->edx = env->features[FEAT_KVM_HINTS];
2264 }
2265
2266 if (cpu->kvm_pv_enforce_cpuid) {
2267 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
2268 if (r < 0) {
2269 fprintf(stderr,
2270 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
2271 strerror(-r));
2272 abort();
2273 }
2274 }
2275
2276 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i);
2277 cpuid_data.cpuid.nent = cpuid_i;
2278
2279 if (x86_cpu_family(env->cpuid_version) >= 6
2280 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2281 (CPUID_MCE | CPUID_MCA)) {
2282 uint64_t mcg_cap, unsupported_caps;
2283 int banks;
2284 int ret;
2285
2286 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
2287 if (ret < 0) {
2288 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2289 return ret;
2290 }
2291
2292 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
2293 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2294 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
2295 return -ENOTSUP;
2296 }
2297
2298 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2299 if (unsupported_caps) {
2300 if (unsupported_caps & MCG_LMCE_P) {
2301 error_report("kvm: LMCE not supported");
2302 return -ENOTSUP;
2303 }
2304 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2305 unsupported_caps);
2306 }
2307
2308 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2309 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
2310 if (ret < 0) {
2311 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2312 return ret;
2313 }
2314 }
2315
2316 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
2317
2318 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2319 if (c) {
2320 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2321 !!(c->ecx & CPUID_EXT_SMX);
2322 }
2323
2324 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2325 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2326 has_msr_feature_control = true;
2327 }
2328
2329 if (env->mcg_cap & MCG_LMCE_P) {
2330 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2331 }
2332
2333 if (!env->user_tsc_khz) {
2334 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2335 invtsc_mig_blocker == NULL) {
2336 error_setg(&invtsc_mig_blocker,
2337 "State blocked by non-migratable CPU device"
2338 " (invtsc flag)");
2339 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err);
2340 if (r < 0) {
2341 error_report_err(local_err);
2342 return r;
2343 }
2344 }
2345 }
2346
2347 if (cpu->vmware_cpuid_freq
2348 /* Guests depend on 0x40000000 to detect this feature, so only expose
2349 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2350 && cpu->expose_kvm
2351 && kvm_base == KVM_CPUID_SIGNATURE
2352 /* TSC clock must be stable and known for this feature. */
2353 && tsc_is_stable_and_known(env)) {
2354
2355 c = &cpuid_data.entries[cpuid_i++];
2356 c->function = KVM_CPUID_SIGNATURE | 0x10;
2357 c->eax = env->tsc_khz;
2358 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
2359 c->ecx = c->edx = 0;
2360
2361 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2362 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2363 }
2364
2365 cpuid_data.cpuid.nent = cpuid_i;
2366
2367 cpuid_data.cpuid.padding = 0;
2368 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2369 if (r) {
2370 goto fail;
2371 }
2372 kvm_init_xsave(env);
2373
2374 max_nested_state_len = kvm_max_nested_state_length();
2375 if (max_nested_state_len > 0) {
2376 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
2377
2378 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
2379 env->nested_state = g_malloc0(max_nested_state_len);
2380 env->nested_state->size = max_nested_state_len;
2381
2382 kvm_init_nested_state(env);
2383 }
2384 }
2385
2386 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
2387
2388 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2389 has_msr_tsc_aux = false;
2390 }
2391
2392 kvm_init_msrs(cpu);
2393
2394 return 0;
2395
2396 fail:
2397 migrate_del_blocker(&invtsc_mig_blocker);
2398
2399 return r;
2400 }
2401
kvm_arch_destroy_vcpu(CPUState * cs)2402 int kvm_arch_destroy_vcpu(CPUState *cs)
2403 {
2404 X86CPU *cpu = X86_CPU(cs);
2405 CPUX86State *env = &cpu->env;
2406
2407 g_free(env->xsave_buf);
2408
2409 g_free(cpu->kvm_msr_buf);
2410 cpu->kvm_msr_buf = NULL;
2411
2412 g_free(env->nested_state);
2413 env->nested_state = NULL;
2414
2415 qemu_del_vm_change_state_handler(cpu->vmsentry);
2416
2417 return 0;
2418 }
2419
kvm_arch_reset_vcpu(X86CPU * cpu)2420 void kvm_arch_reset_vcpu(X86CPU *cpu)
2421 {
2422 CPUX86State *env = &cpu->env;
2423
2424 env->xcr0 = 1;
2425 if (kvm_irqchip_in_kernel()) {
2426 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
2427 KVM_MP_STATE_UNINITIALIZED;
2428 } else {
2429 env->mp_state = KVM_MP_STATE_RUNNABLE;
2430 }
2431
2432 /* enabled by default */
2433 env->poll_control_msr = 1;
2434
2435 kvm_init_nested_state(env);
2436
2437 sev_es_set_reset_vector(CPU(cpu));
2438 }
2439
kvm_arch_after_reset_vcpu(X86CPU * cpu)2440 void kvm_arch_after_reset_vcpu(X86CPU *cpu)
2441 {
2442 CPUX86State *env = &cpu->env;
2443 int i;
2444
2445 /*
2446 * Reset SynIC after all other devices have been reset to let them remove
2447 * their SINT routes first.
2448 */
2449 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2450 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2451 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2452 }
2453
2454 hyperv_x86_synic_reset(cpu);
2455 }
2456 }
2457
kvm_arch_reset_parked_vcpu(unsigned long vcpu_id,int kvm_fd)2458 void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd)
2459 {
2460 g_autofree struct kvm_msrs *msrs = NULL;
2461
2462 msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0]));
2463 msrs->entries[0].index = MSR_IA32_TSC;
2464 msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */
2465 msrs->nmsrs++;
2466
2467 if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) {
2468 warn_report("parked vCPU %lu TSC reset failed: %d",
2469 vcpu_id, errno);
2470 }
2471 }
2472
kvm_arch_do_init_vcpu(X86CPU * cpu)2473 void kvm_arch_do_init_vcpu(X86CPU *cpu)
2474 {
2475 CPUX86State *env = &cpu->env;
2476
2477 /* APs get directly into wait-for-SIPI state. */
2478 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2479 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2480 }
2481 }
2482
kvm_get_supported_feature_msrs(KVMState * s)2483 static int kvm_get_supported_feature_msrs(KVMState *s)
2484 {
2485 int ret = 0;
2486
2487 if (kvm_feature_msrs != NULL) {
2488 return 0;
2489 }
2490
2491 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2492 return 0;
2493 }
2494
2495 struct kvm_msr_list msr_list;
2496
2497 msr_list.nmsrs = 0;
2498 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2499 if (ret < 0 && ret != -E2BIG) {
2500 error_report("Fetch KVM feature MSR list failed: %s",
2501 strerror(-ret));
2502 return ret;
2503 }
2504
2505 assert(msr_list.nmsrs > 0);
2506 kvm_feature_msrs = g_malloc0(sizeof(msr_list) +
2507 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2508
2509 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2510 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2511
2512 if (ret < 0) {
2513 error_report("Fetch KVM feature MSR list failed: %s",
2514 strerror(-ret));
2515 g_free(kvm_feature_msrs);
2516 kvm_feature_msrs = NULL;
2517 return ret;
2518 }
2519
2520 return 0;
2521 }
2522
kvm_get_supported_msrs(KVMState * s)2523 static int kvm_get_supported_msrs(KVMState *s)
2524 {
2525 int ret = 0;
2526 struct kvm_msr_list msr_list, *kvm_msr_list;
2527
2528 /*
2529 * Obtain MSR list from KVM. These are the MSRs that we must
2530 * save/restore.
2531 */
2532 msr_list.nmsrs = 0;
2533 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2534 if (ret < 0 && ret != -E2BIG) {
2535 return ret;
2536 }
2537 /*
2538 * Old kernel modules had a bug and could write beyond the provided
2539 * memory. Allocate at least a safe amount of 1K.
2540 */
2541 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2542 msr_list.nmsrs *
2543 sizeof(msr_list.indices[0])));
2544
2545 kvm_msr_list->nmsrs = msr_list.nmsrs;
2546 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2547 if (ret >= 0) {
2548 int i;
2549
2550 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2551 switch (kvm_msr_list->indices[i]) {
2552 case MSR_STAR:
2553 has_msr_star = true;
2554 break;
2555 case MSR_VM_HSAVE_PA:
2556 has_msr_hsave_pa = true;
2557 break;
2558 case MSR_TSC_AUX:
2559 has_msr_tsc_aux = true;
2560 break;
2561 case MSR_TSC_ADJUST:
2562 has_msr_tsc_adjust = true;
2563 break;
2564 case MSR_IA32_TSCDEADLINE:
2565 has_msr_tsc_deadline = true;
2566 break;
2567 case MSR_IA32_SMBASE:
2568 has_msr_smbase = true;
2569 break;
2570 case MSR_SMI_COUNT:
2571 has_msr_smi_count = true;
2572 break;
2573 case MSR_IA32_MISC_ENABLE:
2574 has_msr_misc_enable = true;
2575 break;
2576 case MSR_IA32_BNDCFGS:
2577 has_msr_bndcfgs = true;
2578 break;
2579 case MSR_IA32_XSS:
2580 has_msr_xss = true;
2581 break;
2582 case MSR_IA32_UMWAIT_CONTROL:
2583 has_msr_umwait = true;
2584 break;
2585 case HV_X64_MSR_CRASH_CTL:
2586 has_msr_hv_crash = true;
2587 break;
2588 case HV_X64_MSR_RESET:
2589 has_msr_hv_reset = true;
2590 break;
2591 case HV_X64_MSR_VP_INDEX:
2592 has_msr_hv_vpindex = true;
2593 break;
2594 case HV_X64_MSR_VP_RUNTIME:
2595 has_msr_hv_runtime = true;
2596 break;
2597 case HV_X64_MSR_SCONTROL:
2598 has_msr_hv_synic = true;
2599 break;
2600 case HV_X64_MSR_STIMER0_CONFIG:
2601 has_msr_hv_stimer = true;
2602 break;
2603 case HV_X64_MSR_TSC_FREQUENCY:
2604 has_msr_hv_frequencies = true;
2605 break;
2606 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2607 has_msr_hv_reenlightenment = true;
2608 break;
2609 case HV_X64_MSR_SYNDBG_OPTIONS:
2610 has_msr_hv_syndbg_options = true;
2611 break;
2612 case MSR_IA32_SPEC_CTRL:
2613 has_msr_spec_ctrl = true;
2614 break;
2615 case MSR_AMD64_TSC_RATIO:
2616 has_tsc_scale_msr = true;
2617 break;
2618 case MSR_IA32_TSX_CTRL:
2619 has_msr_tsx_ctrl = true;
2620 break;
2621 case MSR_VIRT_SSBD:
2622 has_msr_virt_ssbd = true;
2623 break;
2624 case MSR_IA32_ARCH_CAPABILITIES:
2625 has_msr_arch_capabs = true;
2626 break;
2627 case MSR_IA32_CORE_CAPABILITY:
2628 has_msr_core_capabs = true;
2629 break;
2630 case MSR_IA32_PERF_CAPABILITIES:
2631 has_msr_perf_capabs = true;
2632 break;
2633 case MSR_IA32_VMX_VMFUNC:
2634 has_msr_vmx_vmfunc = true;
2635 break;
2636 case MSR_IA32_UCODE_REV:
2637 has_msr_ucode_rev = true;
2638 break;
2639 case MSR_IA32_VMX_PROCBASED_CTLS2:
2640 has_msr_vmx_procbased_ctls2 = true;
2641 break;
2642 case MSR_IA32_PKRS:
2643 has_msr_pkrs = true;
2644 break;
2645 case MSR_K7_HWCR:
2646 has_msr_hwcr = true;
2647 }
2648 }
2649 }
2650
2651 g_free(kvm_msr_list);
2652
2653 return ret;
2654 }
2655
kvm_rdmsr_core_thread_count(X86CPU * cpu,uint32_t msr,uint64_t * val)2656 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu,
2657 uint32_t msr,
2658 uint64_t *val)
2659 {
2660 *val = cpu_x86_get_msr_core_thread_count(cpu);
2661
2662 return true;
2663 }
2664
kvm_rdmsr_rapl_power_unit(X86CPU * cpu,uint32_t msr,uint64_t * val)2665 static bool kvm_rdmsr_rapl_power_unit(X86CPU *cpu,
2666 uint32_t msr,
2667 uint64_t *val)
2668 {
2669
2670 CPUState *cs = CPU(cpu);
2671
2672 *val = cs->kvm_state->msr_energy.msr_unit;
2673
2674 return true;
2675 }
2676
kvm_rdmsr_pkg_power_limit(X86CPU * cpu,uint32_t msr,uint64_t * val)2677 static bool kvm_rdmsr_pkg_power_limit(X86CPU *cpu,
2678 uint32_t msr,
2679 uint64_t *val)
2680 {
2681
2682 CPUState *cs = CPU(cpu);
2683
2684 *val = cs->kvm_state->msr_energy.msr_limit;
2685
2686 return true;
2687 }
2688
kvm_rdmsr_pkg_power_info(X86CPU * cpu,uint32_t msr,uint64_t * val)2689 static bool kvm_rdmsr_pkg_power_info(X86CPU *cpu,
2690 uint32_t msr,
2691 uint64_t *val)
2692 {
2693
2694 CPUState *cs = CPU(cpu);
2695
2696 *val = cs->kvm_state->msr_energy.msr_info;
2697
2698 return true;
2699 }
2700
kvm_rdmsr_pkg_energy_status(X86CPU * cpu,uint32_t msr,uint64_t * val)2701 static bool kvm_rdmsr_pkg_energy_status(X86CPU *cpu,
2702 uint32_t msr,
2703 uint64_t *val)
2704 {
2705
2706 CPUState *cs = CPU(cpu);
2707 *val = cs->kvm_state->msr_energy.msr_value[cs->cpu_index];
2708
2709 return true;
2710 }
2711
2712 static Notifier smram_machine_done;
2713 static KVMMemoryListener smram_listener;
2714 static AddressSpace smram_address_space;
2715 static MemoryRegion smram_as_root;
2716 static MemoryRegion smram_as_mem;
2717
register_smram_listener(Notifier * n,void * unused)2718 static void register_smram_listener(Notifier *n, void *unused)
2719 {
2720 CPUState *cpu;
2721 MemoryRegion *smram =
2722 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2723
2724 /* Outer container... */
2725 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2726 memory_region_set_enabled(&smram_as_root, true);
2727
2728 /* ... with two regions inside: normal system memory with low
2729 * priority, and...
2730 */
2731 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2732 get_system_memory(), 0, ~0ull);
2733 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2734 memory_region_set_enabled(&smram_as_mem, true);
2735
2736 if (smram) {
2737 /* ... SMRAM with higher priority */
2738 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2739 memory_region_set_enabled(smram, true);
2740 }
2741
2742 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2743 kvm_memory_listener_register(kvm_state, &smram_listener,
2744 &smram_address_space, X86ASIdx_SMM, "kvm-smram");
2745
2746 CPU_FOREACH(cpu) {
2747 cpu_address_space_init(cpu, X86ASIdx_SMM, "cpu-smm", &smram_as_root);
2748 }
2749 }
2750
kvm_msr_energy_thread(void * data)2751 static void *kvm_msr_energy_thread(void *data)
2752 {
2753 KVMState *s = data;
2754 struct KVMMsrEnergy *vmsr = &s->msr_energy;
2755
2756 g_autofree vmsr_package_energy_stat *pkg_stat = NULL;
2757 g_autofree vmsr_thread_stat *thd_stat = NULL;
2758 g_autofree CPUState *cpu = NULL;
2759 g_autofree unsigned int *vpkgs_energy_stat = NULL;
2760 unsigned int num_threads = 0;
2761
2762 X86CPUTopoIDs topo_ids;
2763
2764 rcu_register_thread();
2765
2766 /* Allocate memory for each package energy status */
2767 pkg_stat = g_new0(vmsr_package_energy_stat, vmsr->host_topo.maxpkgs);
2768
2769 /* Allocate memory for thread stats */
2770 thd_stat = g_new0(vmsr_thread_stat, 1);
2771
2772 /* Allocate memory for holding virtual package energy counter */
2773 vpkgs_energy_stat = g_new0(unsigned int, vmsr->guest_vsockets);
2774
2775 /* Populate the max tick of each packages */
2776 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2777 /*
2778 * Max numbers of ticks per package
2779 * Time in second * Number of ticks/second * Number of cores/package
2780 * ex: 100 ticks/second/CPU, 12 CPUs per Package gives 1200 ticks max
2781 */
2782 vmsr->host_topo.maxticks[i] = (MSR_ENERGY_THREAD_SLEEP_US / 1000000)
2783 * sysconf(_SC_CLK_TCK)
2784 * vmsr->host_topo.pkg_cpu_count[i];
2785 }
2786
2787 while (true) {
2788 /* Get all qemu threads id */
2789 g_autofree pid_t *thread_ids
2790 = vmsr_get_thread_ids(vmsr->pid, &num_threads);
2791
2792 if (thread_ids == NULL) {
2793 goto clean;
2794 }
2795
2796 thd_stat = g_renew(vmsr_thread_stat, thd_stat, num_threads);
2797 /* Unlike g_new0, g_renew0 function doesn't exist yet... */
2798 memset(thd_stat, 0, num_threads * sizeof(vmsr_thread_stat));
2799
2800 /* Populate all the thread stats */
2801 for (int i = 0; i < num_threads; i++) {
2802 thd_stat[i].utime = g_new0(unsigned long long, 2);
2803 thd_stat[i].stime = g_new0(unsigned long long, 2);
2804 thd_stat[i].thread_id = thread_ids[i];
2805 vmsr_read_thread_stat(vmsr->pid,
2806 thd_stat[i].thread_id,
2807 &thd_stat[i].utime[0],
2808 &thd_stat[i].stime[0],
2809 &thd_stat[i].cpu_id);
2810 thd_stat[i].pkg_id =
2811 vmsr_get_physical_package_id(thd_stat[i].cpu_id);
2812 }
2813
2814 /* Retrieve all packages power plane energy counter */
2815 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2816 for (int j = 0; j < num_threads; j++) {
2817 /*
2818 * Use the first thread we found that ran on the CPU
2819 * of the package to read the packages energy counter
2820 */
2821 if (thd_stat[j].pkg_id == i) {
2822 pkg_stat[i].e_start =
2823 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2824 thd_stat[j].cpu_id,
2825 thd_stat[j].thread_id,
2826 s->msr_energy.sioc);
2827 break;
2828 }
2829 }
2830 }
2831
2832 /* Sleep a short period while the other threads are working */
2833 usleep(MSR_ENERGY_THREAD_SLEEP_US);
2834
2835 /*
2836 * Retrieve all packages power plane energy counter
2837 * Calculate the delta of all packages
2838 */
2839 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2840 for (int j = 0; j < num_threads; j++) {
2841 /*
2842 * Use the first thread we found that ran on the CPU
2843 * of the package to read the packages energy counter
2844 */
2845 if (thd_stat[j].pkg_id == i) {
2846 pkg_stat[i].e_end =
2847 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2848 thd_stat[j].cpu_id,
2849 thd_stat[j].thread_id,
2850 s->msr_energy.sioc);
2851 /*
2852 * Prevent the case we have migrate the VM
2853 * during the sleep period or any other cases
2854 * were energy counter might be lower after
2855 * the sleep period.
2856 */
2857 if (pkg_stat[i].e_end > pkg_stat[i].e_start) {
2858 pkg_stat[i].e_delta =
2859 pkg_stat[i].e_end - pkg_stat[i].e_start;
2860 } else {
2861 pkg_stat[i].e_delta = 0;
2862 }
2863 break;
2864 }
2865 }
2866 }
2867
2868 /* Delta of ticks spend by each thread between the sample */
2869 for (int i = 0; i < num_threads; i++) {
2870 vmsr_read_thread_stat(vmsr->pid,
2871 thd_stat[i].thread_id,
2872 &thd_stat[i].utime[1],
2873 &thd_stat[i].stime[1],
2874 &thd_stat[i].cpu_id);
2875
2876 if (vmsr->pid < 0) {
2877 /*
2878 * We don't count the dead thread
2879 * i.e threads that existed before the sleep
2880 * and not anymore
2881 */
2882 thd_stat[i].delta_ticks = 0;
2883 } else {
2884 vmsr_delta_ticks(thd_stat, i);
2885 }
2886 }
2887
2888 /*
2889 * Identify the vcpu threads
2890 * Calculate the number of vcpu per package
2891 */
2892 CPU_FOREACH(cpu) {
2893 for (int i = 0; i < num_threads; i++) {
2894 if (cpu->thread_id == thd_stat[i].thread_id) {
2895 thd_stat[i].is_vcpu = true;
2896 thd_stat[i].vcpu_id = cpu->cpu_index;
2897 pkg_stat[thd_stat[i].pkg_id].nb_vcpu++;
2898 thd_stat[i].acpi_id = kvm_arch_vcpu_id(cpu);
2899 break;
2900 }
2901 }
2902 }
2903
2904 /* Retrieve the virtual package number of each vCPU */
2905 for (int i = 0; i < vmsr->guest_cpu_list->len; i++) {
2906 for (int j = 0; j < num_threads; j++) {
2907 if ((thd_stat[j].acpi_id ==
2908 vmsr->guest_cpu_list->cpus[i].arch_id)
2909 && (thd_stat[j].is_vcpu == true)) {
2910 x86_topo_ids_from_apicid(thd_stat[j].acpi_id,
2911 &vmsr->guest_topo_info, &topo_ids);
2912 thd_stat[j].vpkg_id = topo_ids.pkg_id;
2913 }
2914 }
2915 }
2916
2917 /* Calculate the total energy of all non-vCPU thread */
2918 for (int i = 0; i < num_threads; i++) {
2919 if ((thd_stat[i].is_vcpu != true) &&
2920 (thd_stat[i].delta_ticks > 0)) {
2921 double temp;
2922 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2923 thd_stat[i].delta_ticks,
2924 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2925 pkg_stat[thd_stat[i].pkg_id].e_ratio
2926 += (uint64_t)lround(temp);
2927 }
2928 }
2929
2930 /* Calculate the ratio per non-vCPU thread of each package */
2931 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2932 if (pkg_stat[i].nb_vcpu > 0) {
2933 pkg_stat[i].e_ratio = pkg_stat[i].e_ratio / pkg_stat[i].nb_vcpu;
2934 }
2935 }
2936
2937 /*
2938 * Calculate the energy for each Package:
2939 * Energy Package = sum of each vCPU energy that belongs to the package
2940 */
2941 for (int i = 0; i < num_threads; i++) {
2942 if ((thd_stat[i].is_vcpu == true) && \
2943 (thd_stat[i].delta_ticks > 0)) {
2944 double temp;
2945 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2946 thd_stat[i].delta_ticks,
2947 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2948 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2949 (uint64_t)lround(temp);
2950 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2951 pkg_stat[thd_stat[i].pkg_id].e_ratio;
2952 }
2953 }
2954
2955 /*
2956 * Finally populate the vmsr register of each vCPU with the total
2957 * package value to emulate the real hardware where each CPU return the
2958 * value of the package it belongs.
2959 */
2960 for (int i = 0; i < num_threads; i++) {
2961 if ((thd_stat[i].is_vcpu == true) && \
2962 (thd_stat[i].delta_ticks > 0)) {
2963 vmsr->msr_value[thd_stat[i].vcpu_id] = \
2964 vpkgs_energy_stat[thd_stat[i].vpkg_id];
2965 }
2966 }
2967
2968 /* Freeing memory before zeroing the pointer */
2969 for (int i = 0; i < num_threads; i++) {
2970 g_free(thd_stat[i].utime);
2971 g_free(thd_stat[i].stime);
2972 }
2973 }
2974
2975 clean:
2976 rcu_unregister_thread();
2977 return NULL;
2978 }
2979
kvm_msr_energy_thread_init(KVMState * s,MachineState * ms)2980 static int kvm_msr_energy_thread_init(KVMState *s, MachineState *ms)
2981 {
2982 MachineClass *mc = MACHINE_GET_CLASS(ms);
2983 struct KVMMsrEnergy *r = &s->msr_energy;
2984
2985 /*
2986 * Sanity check
2987 * 1. Host cpu must be Intel cpu
2988 * 2. RAPL must be enabled on the Host
2989 */
2990 if (!is_host_cpu_intel()) {
2991 error_report("The RAPL feature can only be enabled on hosts "
2992 "with Intel CPU models");
2993 return -1;
2994 }
2995
2996 if (!is_rapl_enabled()) {
2997 return -1;
2998 }
2999
3000 /* Retrieve the virtual topology */
3001 vmsr_init_topo_info(&r->guest_topo_info, ms);
3002
3003 /* Retrieve the number of vcpu */
3004 r->guest_vcpus = ms->smp.cpus;
3005
3006 /* Retrieve the number of virtual sockets */
3007 r->guest_vsockets = ms->smp.sockets;
3008
3009 /* Allocate register memory (MSR_PKG_STATUS) for each vcpu */
3010 r->msr_value = g_new0(uint64_t, r->guest_vcpus);
3011
3012 /* Retrieve the CPUArchIDlist */
3013 r->guest_cpu_list = mc->possible_cpu_arch_ids(ms);
3014
3015 /* Max number of cpus on the Host */
3016 r->host_topo.maxcpus = vmsr_get_maxcpus();
3017 if (r->host_topo.maxcpus == 0) {
3018 error_report("host max cpus = 0");
3019 return -1;
3020 }
3021
3022 /* Max number of packages on the host */
3023 r->host_topo.maxpkgs = vmsr_get_max_physical_package(r->host_topo.maxcpus);
3024 if (r->host_topo.maxpkgs == 0) {
3025 error_report("host max pkgs = 0");
3026 return -1;
3027 }
3028
3029 /* Allocate memory for each package on the host */
3030 r->host_topo.pkg_cpu_count = g_new0(unsigned int, r->host_topo.maxpkgs);
3031 r->host_topo.maxticks = g_new0(unsigned int, r->host_topo.maxpkgs);
3032
3033 vmsr_count_cpus_per_package(r->host_topo.pkg_cpu_count,
3034 r->host_topo.maxpkgs);
3035 for (int i = 0; i < r->host_topo.maxpkgs; i++) {
3036 if (r->host_topo.pkg_cpu_count[i] == 0) {
3037 error_report("cpu per packages = 0 on package_%d", i);
3038 return -1;
3039 }
3040 }
3041
3042 /* Get QEMU PID*/
3043 r->pid = getpid();
3044
3045 /* Compute the socket path if necessary */
3046 if (s->msr_energy.socket_path == NULL) {
3047 s->msr_energy.socket_path = vmsr_compute_default_paths();
3048 }
3049
3050 /* Open socket with vmsr helper */
3051 s->msr_energy.sioc = vmsr_open_socket(s->msr_energy.socket_path);
3052
3053 if (s->msr_energy.sioc == NULL) {
3054 error_report("vmsr socket opening failed");
3055 return -1;
3056 }
3057
3058 /* Those MSR values should not change */
3059 r->msr_unit = vmsr_read_msr(MSR_RAPL_POWER_UNIT, 0, r->pid,
3060 s->msr_energy.sioc);
3061 r->msr_limit = vmsr_read_msr(MSR_PKG_POWER_LIMIT, 0, r->pid,
3062 s->msr_energy.sioc);
3063 r->msr_info = vmsr_read_msr(MSR_PKG_POWER_INFO, 0, r->pid,
3064 s->msr_energy.sioc);
3065 if (r->msr_unit == 0 || r->msr_limit == 0 || r->msr_info == 0) {
3066 error_report("can't read any virtual msr");
3067 return -1;
3068 }
3069
3070 qemu_thread_create(&r->msr_thr, "kvm-msr",
3071 kvm_msr_energy_thread,
3072 s, QEMU_THREAD_JOINABLE);
3073 return 0;
3074 }
3075
kvm_arch_get_default_type(MachineState * ms)3076 int kvm_arch_get_default_type(MachineState *ms)
3077 {
3078 return 0;
3079 }
3080
kvm_vm_enable_exception_payload(KVMState * s)3081 static int kvm_vm_enable_exception_payload(KVMState *s)
3082 {
3083 int ret = 0;
3084 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
3085 if (has_exception_payload) {
3086 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
3087 if (ret < 0) {
3088 error_report("kvm: Failed to enable exception payload cap: %s",
3089 strerror(-ret));
3090 }
3091 }
3092
3093 return ret;
3094 }
3095
kvm_vm_enable_triple_fault_event(KVMState * s)3096 static int kvm_vm_enable_triple_fault_event(KVMState *s)
3097 {
3098 int ret = 0;
3099 has_triple_fault_event = \
3100 kvm_check_extension(s,
3101 KVM_CAP_X86_TRIPLE_FAULT_EVENT);
3102 if (has_triple_fault_event) {
3103 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
3104 if (ret < 0) {
3105 error_report("kvm: Failed to enable triple fault event cap: %s",
3106 strerror(-ret));
3107 }
3108 }
3109 return ret;
3110 }
3111
kvm_vm_set_identity_map_addr(KVMState * s,uint64_t identity_base)3112 static int kvm_vm_set_identity_map_addr(KVMState *s, uint64_t identity_base)
3113 {
3114 return kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
3115 }
3116
kvm_vm_set_nr_mmu_pages(KVMState * s)3117 static int kvm_vm_set_nr_mmu_pages(KVMState *s)
3118 {
3119 uint64_t shadow_mem;
3120 int ret = 0;
3121 shadow_mem = object_property_get_int(OBJECT(s),
3122 "kvm-shadow-mem",
3123 &error_abort);
3124 if (shadow_mem != -1) {
3125 shadow_mem /= 4096;
3126 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
3127 }
3128 return ret;
3129 }
3130
kvm_vm_set_tss_addr(KVMState * s,uint64_t tss_base)3131 static int kvm_vm_set_tss_addr(KVMState *s, uint64_t tss_base)
3132 {
3133 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, tss_base);
3134 }
3135
kvm_vm_enable_disable_exits(KVMState * s)3136 static int kvm_vm_enable_disable_exits(KVMState *s)
3137 {
3138 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
3139
3140 if (disable_exits) {
3141 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
3142 KVM_X86_DISABLE_EXITS_HLT |
3143 KVM_X86_DISABLE_EXITS_PAUSE |
3144 KVM_X86_DISABLE_EXITS_CSTATE);
3145 }
3146
3147 return kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
3148 disable_exits);
3149 }
3150
kvm_vm_enable_bus_lock_exit(KVMState * s)3151 static int kvm_vm_enable_bus_lock_exit(KVMState *s)
3152 {
3153 int ret = 0;
3154 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
3155 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
3156 error_report("kvm: bus lock detection unsupported");
3157 return -ENOTSUP;
3158 }
3159 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
3160 KVM_BUS_LOCK_DETECTION_EXIT);
3161 if (ret < 0) {
3162 error_report("kvm: Failed to enable bus lock detection cap: %s",
3163 strerror(-ret));
3164 }
3165
3166 return ret;
3167 }
3168
kvm_vm_enable_notify_vmexit(KVMState * s)3169 static int kvm_vm_enable_notify_vmexit(KVMState *s)
3170 {
3171 int ret = 0;
3172 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE) {
3173 uint64_t notify_window_flags =
3174 ((uint64_t)s->notify_window << 32) |
3175 KVM_X86_NOTIFY_VMEXIT_ENABLED |
3176 KVM_X86_NOTIFY_VMEXIT_USER;
3177 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
3178 notify_window_flags);
3179 if (ret < 0) {
3180 error_report("kvm: Failed to enable notify vmexit cap: %s",
3181 strerror(-ret));
3182 }
3183 }
3184 return ret;
3185 }
3186
kvm_vm_enable_userspace_msr(KVMState * s)3187 static int kvm_vm_enable_userspace_msr(KVMState *s)
3188 {
3189 int ret;
3190
3191 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0,
3192 KVM_MSR_EXIT_REASON_FILTER);
3193 if (ret < 0) {
3194 error_report("Could not enable user space MSRs: %s",
3195 strerror(-ret));
3196 exit(1);
3197 }
3198
3199 ret = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT,
3200 kvm_rdmsr_core_thread_count, NULL);
3201 if (ret < 0) {
3202 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s",
3203 strerror(-ret));
3204 exit(1);
3205 }
3206
3207 return 0;
3208 }
3209
kvm_vm_enable_energy_msrs(KVMState * s)3210 static int kvm_vm_enable_energy_msrs(KVMState *s)
3211 {
3212 int ret;
3213
3214 if (s->msr_energy.enable == true) {
3215 ret = kvm_filter_msr(s, MSR_RAPL_POWER_UNIT,
3216 kvm_rdmsr_rapl_power_unit, NULL);
3217 if (ret < 0) {
3218 error_report("Could not install MSR_RAPL_POWER_UNIT handler: %s",
3219 strerror(-ret));
3220 return ret;
3221 }
3222
3223 ret = kvm_filter_msr(s, MSR_PKG_POWER_LIMIT,
3224 kvm_rdmsr_pkg_power_limit, NULL);
3225 if (ret < 0) {
3226 error_report("Could not install MSR_PKG_POWER_LIMIT handler: %s",
3227 strerror(-ret));
3228 return ret;
3229 }
3230
3231 ret = kvm_filter_msr(s, MSR_PKG_POWER_INFO,
3232 kvm_rdmsr_pkg_power_info, NULL);
3233 if (ret < 0) {
3234 error_report("Could not install MSR_PKG_POWER_INFO handler: %s",
3235 strerror(-ret));
3236 return ret;
3237 }
3238 ret = kvm_filter_msr(s, MSR_PKG_ENERGY_STATUS,
3239 kvm_rdmsr_pkg_energy_status, NULL);
3240 if (ret < 0) {
3241 error_report("Could not install MSR_PKG_ENERGY_STATUS handler: %s",
3242 strerror(-ret));
3243 return ret;
3244 }
3245 }
3246 return 0;
3247 }
3248
kvm_arch_init(MachineState * ms,KVMState * s)3249 int kvm_arch_init(MachineState *ms, KVMState *s)
3250 {
3251 int ret;
3252 struct utsname utsname;
3253 Error *local_err = NULL;
3254
3255 /*
3256 * Initialize confidential guest (SEV/TDX) context, if required
3257 */
3258 if (ms->cgs) {
3259 ret = confidential_guest_kvm_init(ms->cgs, &local_err);
3260 if (ret < 0) {
3261 error_report_err(local_err);
3262 return ret;
3263 }
3264 }
3265
3266 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
3267 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
3268
3269 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
3270
3271 ret = kvm_vm_enable_exception_payload(s);
3272 if (ret < 0) {
3273 return ret;
3274 }
3275
3276 ret = kvm_vm_enable_triple_fault_event(s);
3277 if (ret < 0) {
3278 return ret;
3279 }
3280
3281 if (s->xen_version) {
3282 #ifdef CONFIG_XEN_EMU
3283 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) {
3284 error_report("kvm: Xen support only available in PC machine");
3285 return -ENOTSUP;
3286 }
3287 /* hyperv_enabled() doesn't work yet. */
3288 uint32_t msr = XEN_HYPERCALL_MSR;
3289 ret = kvm_xen_init(s, msr);
3290 if (ret < 0) {
3291 return ret;
3292 }
3293 #else
3294 error_report("kvm: Xen support not enabled in qemu");
3295 return -ENOTSUP;
3296 #endif
3297 }
3298
3299 ret = kvm_get_supported_msrs(s);
3300 if (ret < 0) {
3301 return ret;
3302 }
3303
3304 ret = kvm_get_supported_feature_msrs(s);
3305 if (ret < 0) {
3306 return ret;
3307 }
3308
3309 uname(&utsname);
3310 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
3311
3312 ret = kvm_vm_set_identity_map_addr(s, KVM_IDENTITY_BASE);
3313 if (ret < 0) {
3314 return ret;
3315 }
3316
3317 /* Set TSS base one page after EPT identity map. */
3318 ret = kvm_vm_set_tss_addr(s, KVM_IDENTITY_BASE + 0x1000);
3319 if (ret < 0) {
3320 return ret;
3321 }
3322
3323 /* Tell fw_cfg to notify the BIOS to reserve the range. */
3324 e820_add_entry(KVM_IDENTITY_BASE, 0x4000, E820_RESERVED);
3325
3326 ret = kvm_vm_set_nr_mmu_pages(s);
3327 if (ret < 0) {
3328 return ret;
3329 }
3330
3331 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
3332 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
3333 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
3334 smram_machine_done.notify = register_smram_listener;
3335 qemu_add_machine_init_done_notifier(&smram_machine_done);
3336 }
3337
3338 if (enable_cpu_pm) {
3339 ret = kvm_vm_enable_disable_exits(s);
3340 if (ret < 0) {
3341 error_report("kvm: guest stopping CPU not supported: %s",
3342 strerror(-ret));
3343 return ret;
3344 }
3345 }
3346
3347 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
3348 X86MachineState *x86ms = X86_MACHINE(ms);
3349
3350 if (x86ms->bus_lock_ratelimit > 0) {
3351 ret = kvm_vm_enable_bus_lock_exit(s);
3352 if (ret < 0) {
3353 return ret;
3354 }
3355 ratelimit_init(&bus_lock_ratelimit_ctrl);
3356 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
3357 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
3358 }
3359 }
3360
3361 if (kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
3362 ret = kvm_vm_enable_notify_vmexit(s);
3363 if (ret < 0) {
3364 return ret;
3365 }
3366 }
3367
3368 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) {
3369 ret = kvm_vm_enable_userspace_msr(s);
3370 if (ret < 0) {
3371 return ret;
3372 }
3373
3374 if (s->msr_energy.enable == true) {
3375 ret = kvm_vm_enable_energy_msrs(s);
3376 if (ret < 0) {
3377 return ret;
3378 }
3379
3380 ret = kvm_msr_energy_thread_init(s, ms);
3381 if (ret < 0) {
3382 error_report("kvm : error RAPL feature requirement not met");
3383 return ret;
3384 }
3385 }
3386 }
3387
3388 return 0;
3389 }
3390
set_v8086_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3391 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3392 {
3393 lhs->selector = rhs->selector;
3394 lhs->base = rhs->base;
3395 lhs->limit = rhs->limit;
3396 lhs->type = 3;
3397 lhs->present = 1;
3398 lhs->dpl = 3;
3399 lhs->db = 0;
3400 lhs->s = 1;
3401 lhs->l = 0;
3402 lhs->g = 0;
3403 lhs->avl = 0;
3404 lhs->unusable = 0;
3405 }
3406
set_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3407 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3408 {
3409 unsigned flags = rhs->flags;
3410 lhs->selector = rhs->selector;
3411 lhs->base = rhs->base;
3412 lhs->limit = rhs->limit;
3413 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
3414 lhs->present = (flags & DESC_P_MASK) != 0;
3415 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
3416 lhs->db = (flags >> DESC_B_SHIFT) & 1;
3417 lhs->s = (flags & DESC_S_MASK) != 0;
3418 lhs->l = (flags >> DESC_L_SHIFT) & 1;
3419 lhs->g = (flags & DESC_G_MASK) != 0;
3420 lhs->avl = (flags & DESC_AVL_MASK) != 0;
3421 lhs->unusable = !lhs->present;
3422 lhs->padding = 0;
3423 }
3424
get_seg(SegmentCache * lhs,const struct kvm_segment * rhs)3425 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
3426 {
3427 lhs->selector = rhs->selector;
3428 lhs->base = rhs->base;
3429 lhs->limit = rhs->limit;
3430 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
3431 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
3432 (rhs->dpl << DESC_DPL_SHIFT) |
3433 (rhs->db << DESC_B_SHIFT) |
3434 (rhs->s * DESC_S_MASK) |
3435 (rhs->l << DESC_L_SHIFT) |
3436 (rhs->g * DESC_G_MASK) |
3437 (rhs->avl * DESC_AVL_MASK);
3438 }
3439
kvm_getput_reg(__u64 * kvm_reg,target_ulong * qemu_reg,int set)3440 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
3441 {
3442 if (set) {
3443 *kvm_reg = *qemu_reg;
3444 } else {
3445 *qemu_reg = *kvm_reg;
3446 }
3447 }
3448
kvm_getput_regs(X86CPU * cpu,int set)3449 static int kvm_getput_regs(X86CPU *cpu, int set)
3450 {
3451 CPUX86State *env = &cpu->env;
3452 struct kvm_regs regs;
3453 int ret = 0;
3454
3455 if (!set) {
3456 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s);
3457 if (ret < 0) {
3458 return ret;
3459 }
3460 }
3461
3462 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
3463 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
3464 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
3465 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
3466 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
3467 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
3468 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
3469 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
3470 #ifdef TARGET_X86_64
3471 kvm_getput_reg(®s.r8, &env->regs[8], set);
3472 kvm_getput_reg(®s.r9, &env->regs[9], set);
3473 kvm_getput_reg(®s.r10, &env->regs[10], set);
3474 kvm_getput_reg(®s.r11, &env->regs[11], set);
3475 kvm_getput_reg(®s.r12, &env->regs[12], set);
3476 kvm_getput_reg(®s.r13, &env->regs[13], set);
3477 kvm_getput_reg(®s.r14, &env->regs[14], set);
3478 kvm_getput_reg(®s.r15, &env->regs[15], set);
3479 #endif
3480
3481 kvm_getput_reg(®s.rflags, &env->eflags, set);
3482 kvm_getput_reg(®s.rip, &env->eip, set);
3483
3484 if (set) {
3485 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s);
3486 }
3487
3488 return ret;
3489 }
3490
kvm_put_xsave(X86CPU * cpu)3491 static int kvm_put_xsave(X86CPU *cpu)
3492 {
3493 CPUX86State *env = &cpu->env;
3494 void *xsave = env->xsave_buf;
3495
3496 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
3497
3498 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
3499 }
3500
kvm_put_xcrs(X86CPU * cpu)3501 static int kvm_put_xcrs(X86CPU *cpu)
3502 {
3503 CPUX86State *env = &cpu->env;
3504 struct kvm_xcrs xcrs = {};
3505
3506 if (!has_xcrs) {
3507 return 0;
3508 }
3509
3510 xcrs.nr_xcrs = 1;
3511 xcrs.flags = 0;
3512 xcrs.xcrs[0].xcr = 0;
3513 xcrs.xcrs[0].value = env->xcr0;
3514 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
3515 }
3516
kvm_put_sregs(X86CPU * cpu)3517 static int kvm_put_sregs(X86CPU *cpu)
3518 {
3519 CPUX86State *env = &cpu->env;
3520 struct kvm_sregs sregs;
3521
3522 /*
3523 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
3524 * always followed by KVM_SET_VCPU_EVENTS.
3525 */
3526 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
3527
3528 if ((env->eflags & VM_MASK)) {
3529 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3530 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3531 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3532 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3533 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3534 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3535 } else {
3536 set_seg(&sregs.cs, &env->segs[R_CS]);
3537 set_seg(&sregs.ds, &env->segs[R_DS]);
3538 set_seg(&sregs.es, &env->segs[R_ES]);
3539 set_seg(&sregs.fs, &env->segs[R_FS]);
3540 set_seg(&sregs.gs, &env->segs[R_GS]);
3541 set_seg(&sregs.ss, &env->segs[R_SS]);
3542 }
3543
3544 set_seg(&sregs.tr, &env->tr);
3545 set_seg(&sregs.ldt, &env->ldt);
3546
3547 sregs.idt.limit = env->idt.limit;
3548 sregs.idt.base = env->idt.base;
3549 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3550 sregs.gdt.limit = env->gdt.limit;
3551 sregs.gdt.base = env->gdt.base;
3552 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3553
3554 sregs.cr0 = env->cr[0];
3555 sregs.cr2 = env->cr[2];
3556 sregs.cr3 = env->cr[3];
3557 sregs.cr4 = env->cr[4];
3558
3559 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3560 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3561
3562 sregs.efer = env->efer;
3563
3564 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
3565 }
3566
kvm_put_sregs2(X86CPU * cpu)3567 static int kvm_put_sregs2(X86CPU *cpu)
3568 {
3569 CPUX86State *env = &cpu->env;
3570 struct kvm_sregs2 sregs;
3571 int i;
3572
3573 sregs.flags = 0;
3574
3575 if ((env->eflags & VM_MASK)) {
3576 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3577 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3578 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3579 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3580 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3581 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3582 } else {
3583 set_seg(&sregs.cs, &env->segs[R_CS]);
3584 set_seg(&sregs.ds, &env->segs[R_DS]);
3585 set_seg(&sregs.es, &env->segs[R_ES]);
3586 set_seg(&sregs.fs, &env->segs[R_FS]);
3587 set_seg(&sregs.gs, &env->segs[R_GS]);
3588 set_seg(&sregs.ss, &env->segs[R_SS]);
3589 }
3590
3591 set_seg(&sregs.tr, &env->tr);
3592 set_seg(&sregs.ldt, &env->ldt);
3593
3594 sregs.idt.limit = env->idt.limit;
3595 sregs.idt.base = env->idt.base;
3596 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3597 sregs.gdt.limit = env->gdt.limit;
3598 sregs.gdt.base = env->gdt.base;
3599 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3600
3601 sregs.cr0 = env->cr[0];
3602 sregs.cr2 = env->cr[2];
3603 sregs.cr3 = env->cr[3];
3604 sregs.cr4 = env->cr[4];
3605
3606 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3607 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3608
3609 sregs.efer = env->efer;
3610
3611 if (env->pdptrs_valid) {
3612 for (i = 0; i < 4; i++) {
3613 sregs.pdptrs[i] = env->pdptrs[i];
3614 }
3615 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
3616 }
3617
3618 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
3619 }
3620
3621
kvm_msr_buf_reset(X86CPU * cpu)3622 static void kvm_msr_buf_reset(X86CPU *cpu)
3623 {
3624 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
3625 }
3626
kvm_msr_entry_add(X86CPU * cpu,uint32_t index,uint64_t value)3627 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
3628 {
3629 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
3630 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
3631 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
3632
3633 assert((void *)(entry + 1) <= limit);
3634
3635 entry->index = index;
3636 entry->reserved = 0;
3637 entry->data = value;
3638 msrs->nmsrs++;
3639 }
3640
kvm_put_one_msr(X86CPU * cpu,int index,uint64_t value)3641 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
3642 {
3643 kvm_msr_buf_reset(cpu);
3644 kvm_msr_entry_add(cpu, index, value);
3645
3646 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3647 }
3648
kvm_get_one_msr(X86CPU * cpu,int index,uint64_t * value)3649 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
3650 {
3651 int ret;
3652 struct {
3653 struct kvm_msrs info;
3654 struct kvm_msr_entry entries[1];
3655 } msr_data = {
3656 .info.nmsrs = 1,
3657 .entries[0].index = index,
3658 };
3659
3660 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
3661 if (ret < 0) {
3662 return ret;
3663 }
3664 assert(ret == 1);
3665 *value = msr_data.entries[0].data;
3666 return ret;
3667 }
kvm_put_apicbase(X86CPU * cpu,uint64_t value)3668 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
3669 {
3670 int ret;
3671
3672 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
3673 assert(ret == 1);
3674 }
3675
kvm_put_tscdeadline_msr(X86CPU * cpu)3676 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
3677 {
3678 CPUX86State *env = &cpu->env;
3679 int ret;
3680
3681 if (!has_msr_tsc_deadline) {
3682 return 0;
3683 }
3684
3685 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
3686 if (ret < 0) {
3687 return ret;
3688 }
3689
3690 assert(ret == 1);
3691 return 0;
3692 }
3693
3694 /*
3695 * Provide a separate write service for the feature control MSR in order to
3696 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
3697 * before writing any other state because forcibly leaving nested mode
3698 * invalidates the VCPU state.
3699 */
kvm_put_msr_feature_control(X86CPU * cpu)3700 static int kvm_put_msr_feature_control(X86CPU *cpu)
3701 {
3702 int ret;
3703
3704 if (!has_msr_feature_control) {
3705 return 0;
3706 }
3707
3708 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
3709 cpu->env.msr_ia32_feature_control);
3710 if (ret < 0) {
3711 return ret;
3712 }
3713
3714 assert(ret == 1);
3715 return 0;
3716 }
3717
make_vmx_msr_value(uint32_t index,uint32_t features)3718 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
3719 {
3720 uint32_t default1, can_be_one, can_be_zero;
3721 uint32_t must_be_one;
3722
3723 switch (index) {
3724 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3725 default1 = 0x00000016;
3726 break;
3727 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3728 default1 = 0x0401e172;
3729 break;
3730 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3731 default1 = 0x000011ff;
3732 break;
3733 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3734 default1 = 0x00036dff;
3735 break;
3736 case MSR_IA32_VMX_PROCBASED_CTLS2:
3737 default1 = 0;
3738 break;
3739 default:
3740 abort();
3741 }
3742
3743 /* If a feature bit is set, the control can be either set or clear.
3744 * Otherwise the value is limited to either 0 or 1 by default1.
3745 */
3746 can_be_one = features | default1;
3747 can_be_zero = features | ~default1;
3748 must_be_one = ~can_be_zero;
3749
3750 /*
3751 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3752 * Bit 32:63 -> 1 if the control bit can be one.
3753 */
3754 return must_be_one | (((uint64_t)can_be_one) << 32);
3755 }
3756
kvm_msr_entry_add_vmx(X86CPU * cpu,FeatureWordArray f)3757 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3758 {
3759 uint64_t kvm_vmx_basic =
3760 kvm_arch_get_supported_msr_feature(kvm_state,
3761 MSR_IA32_VMX_BASIC);
3762
3763 if (!kvm_vmx_basic) {
3764 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3765 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3766 */
3767 return;
3768 }
3769
3770 uint64_t kvm_vmx_misc =
3771 kvm_arch_get_supported_msr_feature(kvm_state,
3772 MSR_IA32_VMX_MISC);
3773 uint64_t kvm_vmx_ept_vpid =
3774 kvm_arch_get_supported_msr_feature(kvm_state,
3775 MSR_IA32_VMX_EPT_VPID_CAP);
3776
3777 /*
3778 * If the guest is 64-bit, a value of 1 is allowed for the host address
3779 * space size vmexit control.
3780 */
3781 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3782 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3783
3784 /*
3785 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3786 * not change them for backwards compatibility.
3787 */
3788 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3789 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3790 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3791 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3792
3793 /*
3794 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3795 * change in the future but are always zero for now, clear them to be
3796 * future proof. Bits 32-63 in theory could change, though KVM does
3797 * not support dual-monitor treatment and probably never will; mask
3798 * them out as well.
3799 */
3800 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3801 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3802 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3803
3804 /*
3805 * EPT memory types should not change either, so we do not bother
3806 * adding features for them.
3807 */
3808 uint64_t fixed_vmx_ept_mask =
3809 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3810 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3811 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3812
3813 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3814 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3815 f[FEAT_VMX_PROCBASED_CTLS]));
3816 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3817 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3818 f[FEAT_VMX_PINBASED_CTLS]));
3819 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3820 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3821 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3822 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3823 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3824 f[FEAT_VMX_ENTRY_CTLS]));
3825 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3826 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3827 f[FEAT_VMX_SECONDARY_CTLS]));
3828 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3829 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3830 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3831 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3832 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3833 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3834 if (has_msr_vmx_vmfunc) {
3835 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3836 }
3837
3838 /*
3839 * Just to be safe, write these with constant values. The CRn_FIXED1
3840 * MSRs are generated by KVM based on the vCPU's CPUID.
3841 */
3842 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3843 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3844 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3845 CR4_VMXE_MASK);
3846
3847 if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3848 /* FRED injected-event data (0x2052). */
3849 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52);
3850 } else if (f[FEAT_VMX_EXIT_CTLS] &
3851 VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) {
3852 /* Secondary VM-exit controls (0x2044). */
3853 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x44);
3854 } else if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3855 /* TSC multiplier (0x2032). */
3856 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3857 } else {
3858 /* Preemption timer (0x482E). */
3859 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3860 }
3861 }
3862
kvm_msr_entry_add_perf(X86CPU * cpu,FeatureWordArray f)3863 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3864 {
3865 uint64_t kvm_perf_cap =
3866 kvm_arch_get_supported_msr_feature(kvm_state,
3867 MSR_IA32_PERF_CAPABILITIES);
3868
3869 if (kvm_perf_cap) {
3870 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3871 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3872 }
3873 }
3874
kvm_buf_set_msrs(X86CPU * cpu)3875 static int kvm_buf_set_msrs(X86CPU *cpu)
3876 {
3877 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3878 if (ret < 0) {
3879 return ret;
3880 }
3881
3882 if (ret < cpu->kvm_msr_buf->nmsrs) {
3883 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3884 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3885 (uint32_t)e->index, (uint64_t)e->data);
3886 }
3887
3888 assert(ret == cpu->kvm_msr_buf->nmsrs);
3889 return 0;
3890 }
3891
kvm_init_msrs(X86CPU * cpu)3892 static void kvm_init_msrs(X86CPU *cpu)
3893 {
3894 CPUX86State *env = &cpu->env;
3895
3896 kvm_msr_buf_reset(cpu);
3897
3898 if (!is_tdx_vm()) {
3899 if (has_msr_arch_capabs) {
3900 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3901 env->features[FEAT_ARCH_CAPABILITIES]);
3902 }
3903
3904 if (has_msr_core_capabs) {
3905 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3906 env->features[FEAT_CORE_CAPABILITY]);
3907 }
3908
3909 if (has_msr_perf_capabs && cpu->enable_pmu) {
3910 kvm_msr_entry_add_perf(cpu, env->features);
3911 }
3912
3913 /*
3914 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3915 * all kernels with MSR features should have them.
3916 */
3917 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3918 kvm_msr_entry_add_vmx(cpu, env->features);
3919 }
3920 }
3921
3922 if (has_msr_ucode_rev) {
3923 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3924 }
3925 assert(kvm_buf_set_msrs(cpu) == 0);
3926 }
3927
kvm_put_msrs(X86CPU * cpu,int level)3928 static int kvm_put_msrs(X86CPU *cpu, int level)
3929 {
3930 CPUX86State *env = &cpu->env;
3931 int i;
3932
3933 kvm_msr_buf_reset(cpu);
3934
3935 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3936 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3937 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3938 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
3939 if (has_msr_star) {
3940 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
3941 }
3942 if (has_msr_hsave_pa) {
3943 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
3944 }
3945 if (has_msr_tsc_aux) {
3946 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
3947 }
3948 if (has_msr_tsc_adjust) {
3949 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
3950 }
3951 if (has_msr_misc_enable) {
3952 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
3953 env->msr_ia32_misc_enable);
3954 }
3955 if (has_msr_smbase) {
3956 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
3957 }
3958 if (has_msr_smi_count) {
3959 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3960 }
3961 if (has_msr_pkrs) {
3962 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3963 }
3964 if (has_msr_bndcfgs) {
3965 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
3966 }
3967 if (has_msr_xss) {
3968 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
3969 }
3970 if (has_msr_umwait) {
3971 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3972 }
3973 if (has_msr_spec_ctrl) {
3974 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3975 }
3976 if (has_tsc_scale_msr) {
3977 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3978 }
3979
3980 if (has_msr_tsx_ctrl) {
3981 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3982 }
3983 if (has_msr_virt_ssbd) {
3984 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3985 }
3986 if (has_msr_hwcr) {
3987 kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->msr_hwcr);
3988 }
3989
3990 #ifdef TARGET_X86_64
3991 if (lm_capable_kernel) {
3992 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3993 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3994 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3995 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
3996 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3997 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0);
3998 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1);
3999 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2);
4000 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3);
4001 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvls);
4002 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1);
4003 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2);
4004 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3);
4005 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config);
4006 }
4007 }
4008 #endif
4009
4010 /*
4011 * The following MSRs have side effects on the guest or are too heavy
4012 * for normal writeback. Limit them to reset or full state updates.
4013 */
4014 if (level >= KVM_PUT_RESET_STATE) {
4015 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
4016 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
4017 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
4018 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
4019 }
4020 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4021 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
4022 }
4023 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4024 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
4025 }
4026 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4027 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
4028 }
4029 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4030 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
4031 }
4032
4033 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4034 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
4035 }
4036
4037 if (has_architectural_pmu_version > 0) {
4038 if (has_architectural_pmu_version > 1) {
4039 /* Stop the counter. */
4040 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4041 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4042 }
4043
4044 /* Set the counter values. */
4045 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4046 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
4047 env->msr_fixed_counters[i]);
4048 }
4049 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4050 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
4051 env->msr_gp_counters[i]);
4052 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
4053 env->msr_gp_evtsel[i]);
4054 }
4055 if (has_architectural_pmu_version > 1) {
4056 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
4057 env->msr_global_status);
4058 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
4059 env->msr_global_ovf_ctrl);
4060
4061 /* Now start the PMU. */
4062 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
4063 env->msr_fixed_ctr_ctrl);
4064 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
4065 env->msr_global_ctrl);
4066 }
4067 }
4068 /*
4069 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
4070 * only sync them to KVM on the first cpu
4071 */
4072 if (current_cpu == first_cpu) {
4073 if (has_msr_hv_hypercall) {
4074 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
4075 env->msr_hv_guest_os_id);
4076 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
4077 env->msr_hv_hypercall);
4078 }
4079 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4080 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
4081 env->msr_hv_tsc);
4082 }
4083 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4084 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
4085 env->msr_hv_reenlightenment_control);
4086 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
4087 env->msr_hv_tsc_emulation_control);
4088 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
4089 env->msr_hv_tsc_emulation_status);
4090 }
4091 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
4092 has_msr_hv_syndbg_options) {
4093 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
4094 hyperv_syndbg_query_options());
4095 }
4096 }
4097 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4098 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
4099 env->msr_hv_vapic);
4100 }
4101 if (has_msr_hv_crash) {
4102 int j;
4103
4104 for (j = 0; j < HV_CRASH_PARAMS; j++)
4105 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
4106 env->msr_hv_crash_params[j]);
4107
4108 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
4109 }
4110 if (has_msr_hv_runtime) {
4111 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
4112 }
4113 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
4114 && hv_vpindex_settable) {
4115 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
4116 hyperv_vp_index(CPU(cpu)));
4117 }
4118 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4119 int j;
4120
4121 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
4122
4123 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
4124 env->msr_hv_synic_control);
4125 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
4126 env->msr_hv_synic_evt_page);
4127 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
4128 env->msr_hv_synic_msg_page);
4129
4130 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
4131 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
4132 env->msr_hv_synic_sint[j]);
4133 }
4134 }
4135 if (has_msr_hv_stimer) {
4136 int j;
4137
4138 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
4139 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
4140 env->msr_hv_stimer_config[j]);
4141 }
4142
4143 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
4144 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
4145 env->msr_hv_stimer_count[j]);
4146 }
4147 }
4148 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4149 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
4150
4151 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
4152 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
4153 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
4154 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
4155 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
4156 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
4157 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
4158 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
4159 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
4160 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
4161 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
4162 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
4163 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4164 /* The CPU GPs if we write to a bit above the physical limit of
4165 * the host CPU (and KVM emulates that)
4166 */
4167 uint64_t mask = env->mtrr_var[i].mask;
4168 mask &= phys_mask;
4169
4170 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
4171 env->mtrr_var[i].base);
4172 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
4173 }
4174 }
4175 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4176 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
4177 0x14, 1, R_EAX) & 0x7;
4178
4179 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
4180 env->msr_rtit_ctrl);
4181 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
4182 env->msr_rtit_status);
4183 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
4184 env->msr_rtit_output_base);
4185 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
4186 env->msr_rtit_output_mask);
4187 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
4188 env->msr_rtit_cr3_match);
4189 for (i = 0; i < addr_num; i++) {
4190 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
4191 env->msr_rtit_addrs[i]);
4192 }
4193 }
4194
4195 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4196 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
4197 env->msr_ia32_sgxlepubkeyhash[0]);
4198 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
4199 env->msr_ia32_sgxlepubkeyhash[1]);
4200 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
4201 env->msr_ia32_sgxlepubkeyhash[2]);
4202 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
4203 env->msr_ia32_sgxlepubkeyhash[3]);
4204 }
4205
4206 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4207 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
4208 env->msr_xfd);
4209 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
4210 env->msr_xfd_err);
4211 }
4212
4213 if (kvm_enabled() && cpu->enable_pmu &&
4214 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4215 uint64_t depth;
4216 int ret;
4217
4218 /*
4219 * Only migrate Arch LBR states when the host Arch LBR depth
4220 * equals that of source guest's, this is to avoid mismatch
4221 * of guest/host config for the msr hence avoid unexpected
4222 * misbehavior.
4223 */
4224 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4225
4226 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
4227 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
4228 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
4229
4230 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4231 if (!env->lbr_records[i].from) {
4232 continue;
4233 }
4234 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
4235 env->lbr_records[i].from);
4236 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
4237 env->lbr_records[i].to);
4238 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
4239 env->lbr_records[i].info);
4240 }
4241 }
4242 }
4243
4244 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
4245 * kvm_put_msr_feature_control. */
4246 }
4247
4248 if (env->mcg_cap) {
4249 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
4250 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
4251 if (has_msr_mcg_ext_ctl) {
4252 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
4253 }
4254 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4255 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
4256 }
4257 }
4258
4259 return kvm_buf_set_msrs(cpu);
4260 }
4261
4262
kvm_get_xsave(X86CPU * cpu)4263 static int kvm_get_xsave(X86CPU *cpu)
4264 {
4265 CPUX86State *env = &cpu->env;
4266 void *xsave = env->xsave_buf;
4267 unsigned long type;
4268 int ret;
4269
4270 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
4271 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
4272 if (ret < 0) {
4273 return ret;
4274 }
4275 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
4276
4277 return 0;
4278 }
4279
kvm_get_xcrs(X86CPU * cpu)4280 static int kvm_get_xcrs(X86CPU *cpu)
4281 {
4282 CPUX86State *env = &cpu->env;
4283 int i, ret;
4284 struct kvm_xcrs xcrs;
4285
4286 if (!has_xcrs) {
4287 return 0;
4288 }
4289
4290 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
4291 if (ret < 0) {
4292 return ret;
4293 }
4294
4295 for (i = 0; i < xcrs.nr_xcrs; i++) {
4296 /* Only support xcr0 now */
4297 if (xcrs.xcrs[i].xcr == 0) {
4298 env->xcr0 = xcrs.xcrs[i].value;
4299 break;
4300 }
4301 }
4302 return 0;
4303 }
4304
kvm_get_sregs(X86CPU * cpu)4305 static int kvm_get_sregs(X86CPU *cpu)
4306 {
4307 CPUX86State *env = &cpu->env;
4308 struct kvm_sregs sregs;
4309 int ret;
4310
4311 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
4312 if (ret < 0) {
4313 return ret;
4314 }
4315
4316 /*
4317 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
4318 * always preceded by KVM_GET_VCPU_EVENTS.
4319 */
4320
4321 get_seg(&env->segs[R_CS], &sregs.cs);
4322 get_seg(&env->segs[R_DS], &sregs.ds);
4323 get_seg(&env->segs[R_ES], &sregs.es);
4324 get_seg(&env->segs[R_FS], &sregs.fs);
4325 get_seg(&env->segs[R_GS], &sregs.gs);
4326 get_seg(&env->segs[R_SS], &sregs.ss);
4327
4328 get_seg(&env->tr, &sregs.tr);
4329 get_seg(&env->ldt, &sregs.ldt);
4330
4331 env->idt.limit = sregs.idt.limit;
4332 env->idt.base = sregs.idt.base;
4333 env->gdt.limit = sregs.gdt.limit;
4334 env->gdt.base = sregs.gdt.base;
4335
4336 env->cr[0] = sregs.cr0;
4337 env->cr[2] = sregs.cr2;
4338 env->cr[3] = sregs.cr3;
4339 env->cr[4] = sregs.cr4;
4340
4341 env->efer = sregs.efer;
4342 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4343 env->cr[0] & CR0_PG_MASK) {
4344 env->efer |= MSR_EFER_LMA;
4345 }
4346
4347 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4348 x86_update_hflags(env);
4349
4350 return 0;
4351 }
4352
kvm_get_sregs2(X86CPU * cpu)4353 static int kvm_get_sregs2(X86CPU *cpu)
4354 {
4355 CPUX86State *env = &cpu->env;
4356 struct kvm_sregs2 sregs;
4357 int i, ret;
4358
4359 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
4360 if (ret < 0) {
4361 return ret;
4362 }
4363
4364 get_seg(&env->segs[R_CS], &sregs.cs);
4365 get_seg(&env->segs[R_DS], &sregs.ds);
4366 get_seg(&env->segs[R_ES], &sregs.es);
4367 get_seg(&env->segs[R_FS], &sregs.fs);
4368 get_seg(&env->segs[R_GS], &sregs.gs);
4369 get_seg(&env->segs[R_SS], &sregs.ss);
4370
4371 get_seg(&env->tr, &sregs.tr);
4372 get_seg(&env->ldt, &sregs.ldt);
4373
4374 env->idt.limit = sregs.idt.limit;
4375 env->idt.base = sregs.idt.base;
4376 env->gdt.limit = sregs.gdt.limit;
4377 env->gdt.base = sregs.gdt.base;
4378
4379 env->cr[0] = sregs.cr0;
4380 env->cr[2] = sregs.cr2;
4381 env->cr[3] = sregs.cr3;
4382 env->cr[4] = sregs.cr4;
4383
4384 env->efer = sregs.efer;
4385 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4386 env->cr[0] & CR0_PG_MASK) {
4387 env->efer |= MSR_EFER_LMA;
4388 }
4389
4390 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
4391
4392 if (env->pdptrs_valid) {
4393 for (i = 0; i < 4; i++) {
4394 env->pdptrs[i] = sregs.pdptrs[i];
4395 }
4396 }
4397
4398 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4399 x86_update_hflags(env);
4400
4401 return 0;
4402 }
4403
kvm_get_msrs(X86CPU * cpu)4404 static int kvm_get_msrs(X86CPU *cpu)
4405 {
4406 CPUX86State *env = &cpu->env;
4407 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
4408 int ret, i;
4409 uint64_t mtrr_top_bits;
4410
4411 kvm_msr_buf_reset(cpu);
4412
4413 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
4414 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
4415 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
4416 kvm_msr_entry_add(cpu, MSR_PAT, 0);
4417 if (has_msr_star) {
4418 kvm_msr_entry_add(cpu, MSR_STAR, 0);
4419 }
4420 if (has_msr_hsave_pa) {
4421 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
4422 }
4423 if (has_msr_tsc_aux) {
4424 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
4425 }
4426 if (has_msr_tsc_adjust) {
4427 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
4428 }
4429 if (has_msr_tsc_deadline) {
4430 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
4431 }
4432 if (has_msr_misc_enable) {
4433 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
4434 }
4435 if (has_msr_smbase) {
4436 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
4437 }
4438 if (has_msr_smi_count) {
4439 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
4440 }
4441 if (has_msr_feature_control) {
4442 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
4443 }
4444 if (has_msr_pkrs) {
4445 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
4446 }
4447 if (has_msr_bndcfgs) {
4448 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
4449 }
4450 if (has_msr_xss) {
4451 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
4452 }
4453 if (has_msr_umwait) {
4454 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
4455 }
4456 if (has_msr_spec_ctrl) {
4457 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
4458 }
4459 if (has_tsc_scale_msr) {
4460 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
4461 }
4462
4463 if (has_msr_tsx_ctrl) {
4464 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
4465 }
4466 if (has_msr_virt_ssbd) {
4467 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
4468 }
4469 if (!env->tsc_valid) {
4470 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
4471 env->tsc_valid = !runstate_is_running();
4472 }
4473 if (has_msr_hwcr) {
4474 kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
4475 }
4476
4477 #ifdef TARGET_X86_64
4478 if (lm_capable_kernel) {
4479 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
4480 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
4481 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
4482 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
4483 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
4484 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0);
4485 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0);
4486 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0);
4487 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0);
4488 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0);
4489 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0);
4490 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0);
4491 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0);
4492 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0);
4493 }
4494 }
4495 #endif
4496 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
4497 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
4498 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
4499 }
4500 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4501 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
4502 }
4503 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4504 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
4505 }
4506 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4507 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
4508 }
4509 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4510 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
4511 }
4512 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4513 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
4514 }
4515 if (has_architectural_pmu_version > 0) {
4516 if (has_architectural_pmu_version > 1) {
4517 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4518 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4519 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
4520 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
4521 }
4522 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4523 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
4524 }
4525 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4526 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
4527 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
4528 }
4529 }
4530
4531 if (env->mcg_cap) {
4532 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
4533 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
4534 if (has_msr_mcg_ext_ctl) {
4535 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
4536 }
4537 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4538 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
4539 }
4540 }
4541
4542 if (has_msr_hv_hypercall) {
4543 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
4544 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
4545 }
4546 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4547 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
4548 }
4549 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4550 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
4551 }
4552 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4553 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
4554 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
4555 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
4556 }
4557 if (has_msr_hv_syndbg_options) {
4558 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
4559 }
4560 if (has_msr_hv_crash) {
4561 int j;
4562
4563 for (j = 0; j < HV_CRASH_PARAMS; j++) {
4564 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
4565 }
4566 }
4567 if (has_msr_hv_runtime) {
4568 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
4569 }
4570 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4571 uint32_t msr;
4572
4573 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
4574 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
4575 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
4576 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
4577 kvm_msr_entry_add(cpu, msr, 0);
4578 }
4579 }
4580 if (has_msr_hv_stimer) {
4581 uint32_t msr;
4582
4583 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
4584 msr++) {
4585 kvm_msr_entry_add(cpu, msr, 0);
4586 }
4587 }
4588 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4589 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
4590 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
4591 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
4592 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
4593 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
4594 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
4595 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
4596 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
4597 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
4598 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
4599 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
4600 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
4601 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4602 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
4603 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
4604 }
4605 }
4606
4607 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4608 int addr_num =
4609 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
4610
4611 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
4612 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
4613 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
4614 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
4615 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
4616 for (i = 0; i < addr_num; i++) {
4617 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
4618 }
4619 }
4620
4621 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4622 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
4623 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
4624 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
4625 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
4626 }
4627
4628 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4629 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
4630 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
4631 }
4632
4633 if (kvm_enabled() && cpu->enable_pmu &&
4634 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4635 uint64_t depth;
4636
4637 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4638 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
4639 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
4640 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
4641
4642 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4643 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
4644 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
4645 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
4646 }
4647 }
4648 }
4649
4650 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
4651 if (ret < 0) {
4652 return ret;
4653 }
4654
4655 if (ret < cpu->kvm_msr_buf->nmsrs) {
4656 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
4657 error_report("error: failed to get MSR 0x%" PRIx32,
4658 (uint32_t)e->index);
4659 }
4660
4661 assert(ret == cpu->kvm_msr_buf->nmsrs);
4662 /*
4663 * MTRR masks: Each mask consists of 5 parts
4664 * a 10..0: must be zero
4665 * b 11 : valid bit
4666 * c n-1.12: actual mask bits
4667 * d 51..n: reserved must be zero
4668 * e 63.52: reserved must be zero
4669 *
4670 * 'n' is the number of physical bits supported by the CPU and is
4671 * apparently always <= 52. We know our 'n' but don't know what
4672 * the destinations 'n' is; it might be smaller, in which case
4673 * it masks (c) on loading. It might be larger, in which case
4674 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
4675 * we're migrating to.
4676 */
4677
4678 if (cpu->fill_mtrr_mask) {
4679 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
4680 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
4681 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
4682 } else {
4683 mtrr_top_bits = 0;
4684 }
4685
4686 for (i = 0; i < ret; i++) {
4687 uint32_t index = msrs[i].index;
4688 switch (index) {
4689 case MSR_IA32_SYSENTER_CS:
4690 env->sysenter_cs = msrs[i].data;
4691 break;
4692 case MSR_IA32_SYSENTER_ESP:
4693 env->sysenter_esp = msrs[i].data;
4694 break;
4695 case MSR_IA32_SYSENTER_EIP:
4696 env->sysenter_eip = msrs[i].data;
4697 break;
4698 case MSR_PAT:
4699 env->pat = msrs[i].data;
4700 break;
4701 case MSR_STAR:
4702 env->star = msrs[i].data;
4703 break;
4704 #ifdef TARGET_X86_64
4705 case MSR_CSTAR:
4706 env->cstar = msrs[i].data;
4707 break;
4708 case MSR_KERNELGSBASE:
4709 env->kernelgsbase = msrs[i].data;
4710 break;
4711 case MSR_FMASK:
4712 env->fmask = msrs[i].data;
4713 break;
4714 case MSR_LSTAR:
4715 env->lstar = msrs[i].data;
4716 break;
4717 case MSR_IA32_FRED_RSP0:
4718 env->fred_rsp0 = msrs[i].data;
4719 break;
4720 case MSR_IA32_FRED_RSP1:
4721 env->fred_rsp1 = msrs[i].data;
4722 break;
4723 case MSR_IA32_FRED_RSP2:
4724 env->fred_rsp2 = msrs[i].data;
4725 break;
4726 case MSR_IA32_FRED_RSP3:
4727 env->fred_rsp3 = msrs[i].data;
4728 break;
4729 case MSR_IA32_FRED_STKLVLS:
4730 env->fred_stklvls = msrs[i].data;
4731 break;
4732 case MSR_IA32_FRED_SSP1:
4733 env->fred_ssp1 = msrs[i].data;
4734 break;
4735 case MSR_IA32_FRED_SSP2:
4736 env->fred_ssp2 = msrs[i].data;
4737 break;
4738 case MSR_IA32_FRED_SSP3:
4739 env->fred_ssp3 = msrs[i].data;
4740 break;
4741 case MSR_IA32_FRED_CONFIG:
4742 env->fred_config = msrs[i].data;
4743 break;
4744 #endif
4745 case MSR_IA32_TSC:
4746 env->tsc = msrs[i].data;
4747 break;
4748 case MSR_TSC_AUX:
4749 env->tsc_aux = msrs[i].data;
4750 break;
4751 case MSR_TSC_ADJUST:
4752 env->tsc_adjust = msrs[i].data;
4753 break;
4754 case MSR_IA32_TSCDEADLINE:
4755 env->tsc_deadline = msrs[i].data;
4756 break;
4757 case MSR_VM_HSAVE_PA:
4758 env->vm_hsave = msrs[i].data;
4759 break;
4760 case MSR_KVM_SYSTEM_TIME:
4761 env->system_time_msr = msrs[i].data;
4762 break;
4763 case MSR_KVM_WALL_CLOCK:
4764 env->wall_clock_msr = msrs[i].data;
4765 break;
4766 case MSR_MCG_STATUS:
4767 env->mcg_status = msrs[i].data;
4768 break;
4769 case MSR_MCG_CTL:
4770 env->mcg_ctl = msrs[i].data;
4771 break;
4772 case MSR_MCG_EXT_CTL:
4773 env->mcg_ext_ctl = msrs[i].data;
4774 break;
4775 case MSR_IA32_MISC_ENABLE:
4776 env->msr_ia32_misc_enable = msrs[i].data;
4777 break;
4778 case MSR_IA32_SMBASE:
4779 env->smbase = msrs[i].data;
4780 break;
4781 case MSR_SMI_COUNT:
4782 env->msr_smi_count = msrs[i].data;
4783 break;
4784 case MSR_IA32_FEATURE_CONTROL:
4785 env->msr_ia32_feature_control = msrs[i].data;
4786 break;
4787 case MSR_IA32_BNDCFGS:
4788 env->msr_bndcfgs = msrs[i].data;
4789 break;
4790 case MSR_IA32_XSS:
4791 env->xss = msrs[i].data;
4792 break;
4793 case MSR_IA32_UMWAIT_CONTROL:
4794 env->umwait = msrs[i].data;
4795 break;
4796 case MSR_IA32_PKRS:
4797 env->pkrs = msrs[i].data;
4798 break;
4799 default:
4800 if (msrs[i].index >= MSR_MC0_CTL &&
4801 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4802 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
4803 }
4804 break;
4805 case MSR_KVM_ASYNC_PF_EN:
4806 env->async_pf_en_msr = msrs[i].data;
4807 break;
4808 case MSR_KVM_ASYNC_PF_INT:
4809 env->async_pf_int_msr = msrs[i].data;
4810 break;
4811 case MSR_KVM_PV_EOI_EN:
4812 env->pv_eoi_en_msr = msrs[i].data;
4813 break;
4814 case MSR_KVM_STEAL_TIME:
4815 env->steal_time_msr = msrs[i].data;
4816 break;
4817 case MSR_KVM_POLL_CONTROL: {
4818 env->poll_control_msr = msrs[i].data;
4819 break;
4820 }
4821 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4822 env->msr_fixed_ctr_ctrl = msrs[i].data;
4823 break;
4824 case MSR_CORE_PERF_GLOBAL_CTRL:
4825 env->msr_global_ctrl = msrs[i].data;
4826 break;
4827 case MSR_CORE_PERF_GLOBAL_STATUS:
4828 env->msr_global_status = msrs[i].data;
4829 break;
4830 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4831 env->msr_global_ovf_ctrl = msrs[i].data;
4832 break;
4833 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4834 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4835 break;
4836 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4837 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4838 break;
4839 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4840 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4841 break;
4842 case HV_X64_MSR_HYPERCALL:
4843 env->msr_hv_hypercall = msrs[i].data;
4844 break;
4845 case HV_X64_MSR_GUEST_OS_ID:
4846 env->msr_hv_guest_os_id = msrs[i].data;
4847 break;
4848 case HV_X64_MSR_APIC_ASSIST_PAGE:
4849 env->msr_hv_vapic = msrs[i].data;
4850 break;
4851 case HV_X64_MSR_REFERENCE_TSC:
4852 env->msr_hv_tsc = msrs[i].data;
4853 break;
4854 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4855 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4856 break;
4857 case HV_X64_MSR_VP_RUNTIME:
4858 env->msr_hv_runtime = msrs[i].data;
4859 break;
4860 case HV_X64_MSR_SCONTROL:
4861 env->msr_hv_synic_control = msrs[i].data;
4862 break;
4863 case HV_X64_MSR_SIEFP:
4864 env->msr_hv_synic_evt_page = msrs[i].data;
4865 break;
4866 case HV_X64_MSR_SIMP:
4867 env->msr_hv_synic_msg_page = msrs[i].data;
4868 break;
4869 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4870 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
4871 break;
4872 case HV_X64_MSR_STIMER0_CONFIG:
4873 case HV_X64_MSR_STIMER1_CONFIG:
4874 case HV_X64_MSR_STIMER2_CONFIG:
4875 case HV_X64_MSR_STIMER3_CONFIG:
4876 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4877 msrs[i].data;
4878 break;
4879 case HV_X64_MSR_STIMER0_COUNT:
4880 case HV_X64_MSR_STIMER1_COUNT:
4881 case HV_X64_MSR_STIMER2_COUNT:
4882 case HV_X64_MSR_STIMER3_COUNT:
4883 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4884 msrs[i].data;
4885 break;
4886 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4887 env->msr_hv_reenlightenment_control = msrs[i].data;
4888 break;
4889 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4890 env->msr_hv_tsc_emulation_control = msrs[i].data;
4891 break;
4892 case HV_X64_MSR_TSC_EMULATION_STATUS:
4893 env->msr_hv_tsc_emulation_status = msrs[i].data;
4894 break;
4895 case HV_X64_MSR_SYNDBG_OPTIONS:
4896 env->msr_hv_syndbg_options = msrs[i].data;
4897 break;
4898 case MSR_MTRRdefType:
4899 env->mtrr_deftype = msrs[i].data;
4900 break;
4901 case MSR_MTRRfix64K_00000:
4902 env->mtrr_fixed[0] = msrs[i].data;
4903 break;
4904 case MSR_MTRRfix16K_80000:
4905 env->mtrr_fixed[1] = msrs[i].data;
4906 break;
4907 case MSR_MTRRfix16K_A0000:
4908 env->mtrr_fixed[2] = msrs[i].data;
4909 break;
4910 case MSR_MTRRfix4K_C0000:
4911 env->mtrr_fixed[3] = msrs[i].data;
4912 break;
4913 case MSR_MTRRfix4K_C8000:
4914 env->mtrr_fixed[4] = msrs[i].data;
4915 break;
4916 case MSR_MTRRfix4K_D0000:
4917 env->mtrr_fixed[5] = msrs[i].data;
4918 break;
4919 case MSR_MTRRfix4K_D8000:
4920 env->mtrr_fixed[6] = msrs[i].data;
4921 break;
4922 case MSR_MTRRfix4K_E0000:
4923 env->mtrr_fixed[7] = msrs[i].data;
4924 break;
4925 case MSR_MTRRfix4K_E8000:
4926 env->mtrr_fixed[8] = msrs[i].data;
4927 break;
4928 case MSR_MTRRfix4K_F0000:
4929 env->mtrr_fixed[9] = msrs[i].data;
4930 break;
4931 case MSR_MTRRfix4K_F8000:
4932 env->mtrr_fixed[10] = msrs[i].data;
4933 break;
4934 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4935 if (index & 1) {
4936 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4937 mtrr_top_bits;
4938 } else {
4939 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4940 }
4941 break;
4942 case MSR_IA32_SPEC_CTRL:
4943 env->spec_ctrl = msrs[i].data;
4944 break;
4945 case MSR_AMD64_TSC_RATIO:
4946 env->amd_tsc_scale_msr = msrs[i].data;
4947 break;
4948 case MSR_IA32_TSX_CTRL:
4949 env->tsx_ctrl = msrs[i].data;
4950 break;
4951 case MSR_VIRT_SSBD:
4952 env->virt_ssbd = msrs[i].data;
4953 break;
4954 case MSR_IA32_RTIT_CTL:
4955 env->msr_rtit_ctrl = msrs[i].data;
4956 break;
4957 case MSR_IA32_RTIT_STATUS:
4958 env->msr_rtit_status = msrs[i].data;
4959 break;
4960 case MSR_IA32_RTIT_OUTPUT_BASE:
4961 env->msr_rtit_output_base = msrs[i].data;
4962 break;
4963 case MSR_IA32_RTIT_OUTPUT_MASK:
4964 env->msr_rtit_output_mask = msrs[i].data;
4965 break;
4966 case MSR_IA32_RTIT_CR3_MATCH:
4967 env->msr_rtit_cr3_match = msrs[i].data;
4968 break;
4969 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4970 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4971 break;
4972 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4973 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4974 msrs[i].data;
4975 break;
4976 case MSR_IA32_XFD:
4977 env->msr_xfd = msrs[i].data;
4978 break;
4979 case MSR_IA32_XFD_ERR:
4980 env->msr_xfd_err = msrs[i].data;
4981 break;
4982 case MSR_ARCH_LBR_CTL:
4983 env->msr_lbr_ctl = msrs[i].data;
4984 break;
4985 case MSR_ARCH_LBR_DEPTH:
4986 env->msr_lbr_depth = msrs[i].data;
4987 break;
4988 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4989 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4990 break;
4991 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4992 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4993 break;
4994 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4995 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4996 break;
4997 case MSR_K7_HWCR:
4998 env->msr_hwcr = msrs[i].data;
4999 break;
5000 }
5001 }
5002
5003 return 0;
5004 }
5005
kvm_put_mp_state(X86CPU * cpu)5006 static int kvm_put_mp_state(X86CPU *cpu)
5007 {
5008 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
5009
5010 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
5011 }
5012
kvm_get_mp_state(X86CPU * cpu)5013 static int kvm_get_mp_state(X86CPU *cpu)
5014 {
5015 CPUState *cs = CPU(cpu);
5016 CPUX86State *env = &cpu->env;
5017 struct kvm_mp_state mp_state;
5018 int ret;
5019
5020 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
5021 if (ret < 0) {
5022 return ret;
5023 }
5024 env->mp_state = mp_state.mp_state;
5025 if (kvm_irqchip_in_kernel()) {
5026 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
5027 }
5028 return 0;
5029 }
5030
kvm_get_apic(X86CPU * cpu)5031 static int kvm_get_apic(X86CPU *cpu)
5032 {
5033 DeviceState *apic = cpu->apic_state;
5034 struct kvm_lapic_state kapic;
5035 int ret;
5036
5037 if (apic && kvm_irqchip_in_kernel()) {
5038 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
5039 if (ret < 0) {
5040 return ret;
5041 }
5042
5043 kvm_get_apic_state(apic, &kapic);
5044 }
5045 return 0;
5046 }
5047
kvm_put_vcpu_events(X86CPU * cpu,int level)5048 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
5049 {
5050 CPUState *cs = CPU(cpu);
5051 CPUX86State *env = &cpu->env;
5052 struct kvm_vcpu_events events = {};
5053
5054 events.flags = 0;
5055
5056 if (has_exception_payload) {
5057 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5058 events.exception.pending = env->exception_pending;
5059 events.exception_has_payload = env->exception_has_payload;
5060 events.exception_payload = env->exception_payload;
5061 }
5062 events.exception.nr = env->exception_nr;
5063 events.exception.injected = env->exception_injected;
5064 events.exception.has_error_code = env->has_error_code;
5065 events.exception.error_code = env->error_code;
5066
5067 events.interrupt.injected = (env->interrupt_injected >= 0);
5068 events.interrupt.nr = env->interrupt_injected;
5069 events.interrupt.soft = env->soft_interrupt;
5070
5071 events.nmi.injected = env->nmi_injected;
5072 events.nmi.pending = env->nmi_pending;
5073 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
5074
5075 events.sipi_vector = env->sipi_vector;
5076
5077 if (has_msr_smbase) {
5078 events.flags |= KVM_VCPUEVENT_VALID_SMM;
5079 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
5080 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
5081 if (kvm_irqchip_in_kernel()) {
5082 /* As soon as these are moved to the kernel, remove them
5083 * from cs->interrupt_request.
5084 */
5085 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
5086 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
5087 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
5088 } else {
5089 /* Keep these in cs->interrupt_request. */
5090 events.smi.pending = 0;
5091 events.smi.latched_init = 0;
5092 }
5093 }
5094
5095 if (level >= KVM_PUT_RESET_STATE) {
5096 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
5097 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
5098 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
5099 }
5100 }
5101
5102 if (has_triple_fault_event) {
5103 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5104 events.triple_fault.pending = env->triple_fault_pending;
5105 }
5106
5107 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
5108 }
5109
kvm_get_vcpu_events(X86CPU * cpu)5110 static int kvm_get_vcpu_events(X86CPU *cpu)
5111 {
5112 CPUX86State *env = &cpu->env;
5113 struct kvm_vcpu_events events;
5114 int ret;
5115
5116 memset(&events, 0, sizeof(events));
5117 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
5118 if (ret < 0) {
5119 return ret;
5120 }
5121
5122 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5123 env->exception_pending = events.exception.pending;
5124 env->exception_has_payload = events.exception_has_payload;
5125 env->exception_payload = events.exception_payload;
5126 } else {
5127 env->exception_pending = 0;
5128 env->exception_has_payload = false;
5129 }
5130 env->exception_injected = events.exception.injected;
5131 env->exception_nr =
5132 (env->exception_pending || env->exception_injected) ?
5133 events.exception.nr : -1;
5134 env->has_error_code = events.exception.has_error_code;
5135 env->error_code = events.exception.error_code;
5136
5137 env->interrupt_injected =
5138 events.interrupt.injected ? events.interrupt.nr : -1;
5139 env->soft_interrupt = events.interrupt.soft;
5140
5141 env->nmi_injected = events.nmi.injected;
5142 env->nmi_pending = events.nmi.pending;
5143 if (events.nmi.masked) {
5144 env->hflags2 |= HF2_NMI_MASK;
5145 } else {
5146 env->hflags2 &= ~HF2_NMI_MASK;
5147 }
5148
5149 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
5150 if (events.smi.smm) {
5151 env->hflags |= HF_SMM_MASK;
5152 } else {
5153 env->hflags &= ~HF_SMM_MASK;
5154 }
5155 if (events.smi.pending) {
5156 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5157 } else {
5158 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5159 }
5160 if (events.smi.smm_inside_nmi) {
5161 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
5162 } else {
5163 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
5164 }
5165 if (events.smi.latched_init) {
5166 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5167 } else {
5168 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5169 }
5170 }
5171
5172 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5173 env->triple_fault_pending = events.triple_fault.pending;
5174 }
5175
5176 env->sipi_vector = events.sipi_vector;
5177
5178 return 0;
5179 }
5180
kvm_put_debugregs(X86CPU * cpu)5181 static int kvm_put_debugregs(X86CPU *cpu)
5182 {
5183 CPUX86State *env = &cpu->env;
5184 struct kvm_debugregs dbgregs;
5185 int i;
5186
5187 memset(&dbgregs, 0, sizeof(dbgregs));
5188 for (i = 0; i < 4; i++) {
5189 dbgregs.db[i] = env->dr[i];
5190 }
5191 dbgregs.dr6 = env->dr[6];
5192 dbgregs.dr7 = env->dr[7];
5193 dbgregs.flags = 0;
5194
5195 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
5196 }
5197
kvm_get_debugregs(X86CPU * cpu)5198 static int kvm_get_debugregs(X86CPU *cpu)
5199 {
5200 CPUX86State *env = &cpu->env;
5201 struct kvm_debugregs dbgregs;
5202 int i, ret;
5203
5204 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
5205 if (ret < 0) {
5206 return ret;
5207 }
5208 for (i = 0; i < 4; i++) {
5209 env->dr[i] = dbgregs.db[i];
5210 }
5211 env->dr[4] = env->dr[6] = dbgregs.dr6;
5212 env->dr[5] = env->dr[7] = dbgregs.dr7;
5213
5214 return 0;
5215 }
5216
kvm_put_nested_state(X86CPU * cpu)5217 static int kvm_put_nested_state(X86CPU *cpu)
5218 {
5219 CPUX86State *env = &cpu->env;
5220 int max_nested_state_len = kvm_max_nested_state_length();
5221
5222 if (!env->nested_state) {
5223 return 0;
5224 }
5225
5226 /*
5227 * Copy flags that are affected by reset from env->hflags and env->hflags2.
5228 */
5229 if (env->hflags & HF_GUEST_MASK) {
5230 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
5231 } else {
5232 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
5233 }
5234
5235 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
5236 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
5237 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
5238 } else {
5239 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
5240 }
5241
5242 assert(env->nested_state->size <= max_nested_state_len);
5243 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
5244 }
5245
kvm_get_nested_state(X86CPU * cpu)5246 static int kvm_get_nested_state(X86CPU *cpu)
5247 {
5248 CPUX86State *env = &cpu->env;
5249 int max_nested_state_len = kvm_max_nested_state_length();
5250 int ret;
5251
5252 if (!env->nested_state) {
5253 return 0;
5254 }
5255
5256 /*
5257 * It is possible that migration restored a smaller size into
5258 * nested_state->hdr.size than what our kernel support.
5259 * We preserve migration origin nested_state->hdr.size for
5260 * call to KVM_SET_NESTED_STATE but wish that our next call
5261 * to KVM_GET_NESTED_STATE will use max size our kernel support.
5262 */
5263 env->nested_state->size = max_nested_state_len;
5264
5265 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
5266 if (ret < 0) {
5267 return ret;
5268 }
5269
5270 /*
5271 * Copy flags that are affected by reset to env->hflags and env->hflags2.
5272 */
5273 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
5274 env->hflags |= HF_GUEST_MASK;
5275 } else {
5276 env->hflags &= ~HF_GUEST_MASK;
5277 }
5278
5279 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
5280 if (cpu_has_svm(env)) {
5281 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
5282 env->hflags2 |= HF2_GIF_MASK;
5283 } else {
5284 env->hflags2 &= ~HF2_GIF_MASK;
5285 }
5286 }
5287
5288 return ret;
5289 }
5290
kvm_arch_put_registers(CPUState * cpu,int level,Error ** errp)5291 int kvm_arch_put_registers(CPUState *cpu, int level, Error **errp)
5292 {
5293 X86CPU *x86_cpu = X86_CPU(cpu);
5294 int ret;
5295
5296 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
5297
5298 /*
5299 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
5300 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
5301 * precede kvm_put_nested_state() when 'real' nested state is set.
5302 */
5303 if (level >= KVM_PUT_RESET_STATE) {
5304 ret = kvm_put_msr_feature_control(x86_cpu);
5305 if (ret < 0) {
5306 error_setg_errno(errp, -ret, "Failed to set feature control MSR");
5307 return ret;
5308 }
5309 }
5310
5311 /* must be before kvm_put_nested_state so that EFER.SVME is set */
5312 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
5313 if (ret < 0) {
5314 error_setg_errno(errp, -ret, "Failed to set special registers");
5315 return ret;
5316 }
5317
5318 if (level >= KVM_PUT_RESET_STATE) {
5319 ret = kvm_put_nested_state(x86_cpu);
5320 if (ret < 0) {
5321 error_setg_errno(errp, -ret, "Failed to set nested state");
5322 return ret;
5323 }
5324 }
5325
5326 if (level == KVM_PUT_FULL_STATE) {
5327 /* We don't check for kvm_arch_set_tsc_khz() errors here,
5328 * because TSC frequency mismatch shouldn't abort migration,
5329 * unless the user explicitly asked for a more strict TSC
5330 * setting (e.g. using an explicit "tsc-freq" option).
5331 */
5332 kvm_arch_set_tsc_khz(cpu);
5333 }
5334
5335 #ifdef CONFIG_XEN_EMU
5336 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) {
5337 ret = kvm_put_xen_state(cpu);
5338 if (ret < 0) {
5339 error_setg_errno(errp, -ret, "Failed to set Xen state");
5340 return ret;
5341 }
5342 }
5343 #endif
5344
5345 ret = kvm_getput_regs(x86_cpu, 1);
5346 if (ret < 0) {
5347 error_setg_errno(errp, -ret, "Failed to set general purpose registers");
5348 return ret;
5349 }
5350 ret = kvm_put_xsave(x86_cpu);
5351 if (ret < 0) {
5352 error_setg_errno(errp, -ret, "Failed to set XSAVE");
5353 return ret;
5354 }
5355 ret = kvm_put_xcrs(x86_cpu);
5356 if (ret < 0) {
5357 error_setg_errno(errp, -ret, "Failed to set XCRs");
5358 return ret;
5359 }
5360 ret = kvm_put_msrs(x86_cpu, level);
5361 if (ret < 0) {
5362 error_setg_errno(errp, -ret, "Failed to set MSRs");
5363 return ret;
5364 }
5365 ret = kvm_put_vcpu_events(x86_cpu, level);
5366 if (ret < 0) {
5367 error_setg_errno(errp, -ret, "Failed to set vCPU events");
5368 return ret;
5369 }
5370 if (level >= KVM_PUT_RESET_STATE) {
5371 ret = kvm_put_mp_state(x86_cpu);
5372 if (ret < 0) {
5373 error_setg_errno(errp, -ret, "Failed to set MP state");
5374 return ret;
5375 }
5376 }
5377
5378 ret = kvm_put_tscdeadline_msr(x86_cpu);
5379 if (ret < 0) {
5380 error_setg_errno(errp, -ret, "Failed to set TSC deadline MSR");
5381 return ret;
5382 }
5383 ret = kvm_put_debugregs(x86_cpu);
5384 if (ret < 0) {
5385 error_setg_errno(errp, -ret, "Failed to set debug registers");
5386 return ret;
5387 }
5388 return 0;
5389 }
5390
kvm_arch_get_registers(CPUState * cs,Error ** errp)5391 int kvm_arch_get_registers(CPUState *cs, Error **errp)
5392 {
5393 X86CPU *cpu = X86_CPU(cs);
5394 int ret;
5395
5396 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
5397
5398 ret = kvm_get_vcpu_events(cpu);
5399 if (ret < 0) {
5400 error_setg_errno(errp, -ret, "Failed to get vCPU events");
5401 goto out;
5402 }
5403 /*
5404 * KVM_GET_MPSTATE can modify CS and RIP, call it before
5405 * KVM_GET_REGS and KVM_GET_SREGS.
5406 */
5407 ret = kvm_get_mp_state(cpu);
5408 if (ret < 0) {
5409 error_setg_errno(errp, -ret, "Failed to get MP state");
5410 goto out;
5411 }
5412 ret = kvm_getput_regs(cpu, 0);
5413 if (ret < 0) {
5414 error_setg_errno(errp, -ret, "Failed to get general purpose registers");
5415 goto out;
5416 }
5417 ret = kvm_get_xsave(cpu);
5418 if (ret < 0) {
5419 error_setg_errno(errp, -ret, "Failed to get XSAVE");
5420 goto out;
5421 }
5422 ret = kvm_get_xcrs(cpu);
5423 if (ret < 0) {
5424 error_setg_errno(errp, -ret, "Failed to get XCRs");
5425 goto out;
5426 }
5427 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
5428 if (ret < 0) {
5429 error_setg_errno(errp, -ret, "Failed to get special registers");
5430 goto out;
5431 }
5432 ret = kvm_get_msrs(cpu);
5433 if (ret < 0) {
5434 error_setg_errno(errp, -ret, "Failed to get MSRs");
5435 goto out;
5436 }
5437 ret = kvm_get_apic(cpu);
5438 if (ret < 0) {
5439 error_setg_errno(errp, -ret, "Failed to get APIC");
5440 goto out;
5441 }
5442 ret = kvm_get_debugregs(cpu);
5443 if (ret < 0) {
5444 error_setg_errno(errp, -ret, "Failed to get debug registers");
5445 goto out;
5446 }
5447 ret = kvm_get_nested_state(cpu);
5448 if (ret < 0) {
5449 error_setg_errno(errp, -ret, "Failed to get nested state");
5450 goto out;
5451 }
5452 #ifdef CONFIG_XEN_EMU
5453 if (xen_mode == XEN_EMULATE) {
5454 ret = kvm_get_xen_state(cs);
5455 if (ret < 0) {
5456 error_setg_errno(errp, -ret, "Failed to get Xen state");
5457 goto out;
5458 }
5459 }
5460 #endif
5461 ret = 0;
5462 out:
5463 cpu_sync_bndcs_hflags(&cpu->env);
5464 return ret;
5465 }
5466
kvm_arch_pre_run(CPUState * cpu,struct kvm_run * run)5467 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
5468 {
5469 X86CPU *x86_cpu = X86_CPU(cpu);
5470 CPUX86State *env = &x86_cpu->env;
5471 int ret;
5472
5473 /* Inject NMI */
5474 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
5475 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
5476 bql_lock();
5477 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
5478 bql_unlock();
5479 DPRINTF("injected NMI\n");
5480 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
5481 if (ret < 0) {
5482 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
5483 strerror(-ret));
5484 }
5485 }
5486 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
5487 bql_lock();
5488 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
5489 bql_unlock();
5490 DPRINTF("injected SMI\n");
5491 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
5492 if (ret < 0) {
5493 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
5494 strerror(-ret));
5495 }
5496 }
5497 }
5498
5499 if (!kvm_pic_in_kernel()) {
5500 bql_lock();
5501 }
5502
5503 /* Force the VCPU out of its inner loop to process any INIT requests
5504 * or (for userspace APIC, but it is cheap to combine the checks here)
5505 * pending TPR access reports.
5506 */
5507 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
5508 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
5509 !(env->hflags & HF_SMM_MASK)) {
5510 cpu->exit_request = 1;
5511 }
5512 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
5513 cpu->exit_request = 1;
5514 }
5515 }
5516
5517 if (!kvm_pic_in_kernel()) {
5518 /* Try to inject an interrupt if the guest can accept it */
5519 if (run->ready_for_interrupt_injection &&
5520 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
5521 (env->eflags & IF_MASK)) {
5522 int irq;
5523
5524 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
5525 irq = cpu_get_pic_interrupt(env);
5526 if (irq >= 0) {
5527 struct kvm_interrupt intr;
5528
5529 intr.irq = irq;
5530 DPRINTF("injected interrupt %d\n", irq);
5531 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
5532 if (ret < 0) {
5533 fprintf(stderr,
5534 "KVM: injection failed, interrupt lost (%s)\n",
5535 strerror(-ret));
5536 }
5537 }
5538 }
5539
5540 /* If we have an interrupt but the guest is not ready to receive an
5541 * interrupt, request an interrupt window exit. This will
5542 * cause a return to userspace as soon as the guest is ready to
5543 * receive interrupts. */
5544 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
5545 run->request_interrupt_window = 1;
5546 } else {
5547 run->request_interrupt_window = 0;
5548 }
5549
5550 DPRINTF("setting tpr\n");
5551 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
5552
5553 bql_unlock();
5554 }
5555 }
5556
kvm_rate_limit_on_bus_lock(void)5557 static void kvm_rate_limit_on_bus_lock(void)
5558 {
5559 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
5560
5561 if (delay_ns) {
5562 g_usleep(delay_ns / SCALE_US);
5563 }
5564 }
5565
kvm_arch_post_run(CPUState * cpu,struct kvm_run * run)5566 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
5567 {
5568 X86CPU *x86_cpu = X86_CPU(cpu);
5569 CPUX86State *env = &x86_cpu->env;
5570
5571 if (run->flags & KVM_RUN_X86_SMM) {
5572 env->hflags |= HF_SMM_MASK;
5573 } else {
5574 env->hflags &= ~HF_SMM_MASK;
5575 }
5576 if (run->if_flag) {
5577 env->eflags |= IF_MASK;
5578 } else {
5579 env->eflags &= ~IF_MASK;
5580 }
5581 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
5582 kvm_rate_limit_on_bus_lock();
5583 }
5584
5585 #ifdef CONFIG_XEN_EMU
5586 /*
5587 * If the callback is asserted as a GSI (or PCI INTx) then check if
5588 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert
5589 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC
5590 * EOI and only resample then, exactly how the VFIO eventfd pairs
5591 * are designed to work for level triggered interrupts.
5592 */
5593 if (x86_cpu->env.xen_callback_asserted) {
5594 kvm_xen_maybe_deassert_callback(cpu);
5595 }
5596 #endif
5597
5598 /* We need to protect the apic state against concurrent accesses from
5599 * different threads in case the userspace irqchip is used. */
5600 if (!kvm_irqchip_in_kernel()) {
5601 bql_lock();
5602 }
5603 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
5604 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
5605 if (!kvm_irqchip_in_kernel()) {
5606 bql_unlock();
5607 }
5608 return cpu_get_mem_attrs(env);
5609 }
5610
kvm_arch_process_async_events(CPUState * cs)5611 int kvm_arch_process_async_events(CPUState *cs)
5612 {
5613 X86CPU *cpu = X86_CPU(cs);
5614 CPUX86State *env = &cpu->env;
5615
5616 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
5617 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
5618 assert(env->mcg_cap);
5619
5620 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
5621
5622 kvm_cpu_synchronize_state(cs);
5623
5624 if (env->exception_nr == EXCP08_DBLE) {
5625 /* this means triple fault */
5626 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
5627 cs->exit_request = 1;
5628 return 0;
5629 }
5630 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
5631 env->has_error_code = 0;
5632
5633 cs->halted = 0;
5634 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
5635 env->mp_state = KVM_MP_STATE_RUNNABLE;
5636 }
5637 }
5638
5639 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
5640 !(env->hflags & HF_SMM_MASK)) {
5641 kvm_cpu_synchronize_state(cs);
5642 do_cpu_init(cpu);
5643 }
5644
5645 if (kvm_irqchip_in_kernel()) {
5646 return 0;
5647 }
5648
5649 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
5650 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
5651 apic_poll_irq(cpu->apic_state);
5652 }
5653 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5654 (env->eflags & IF_MASK)) ||
5655 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5656 cs->halted = 0;
5657 }
5658 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
5659 kvm_cpu_synchronize_state(cs);
5660 do_cpu_sipi(cpu);
5661 }
5662 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
5663 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
5664 kvm_cpu_synchronize_state(cs);
5665 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
5666 env->tpr_access_type);
5667 }
5668
5669 return cs->halted;
5670 }
5671
kvm_handle_halt(X86CPU * cpu)5672 static int kvm_handle_halt(X86CPU *cpu)
5673 {
5674 CPUState *cs = CPU(cpu);
5675 CPUX86State *env = &cpu->env;
5676
5677 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5678 (env->eflags & IF_MASK)) &&
5679 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5680 cs->halted = 1;
5681 return EXCP_HLT;
5682 }
5683
5684 return 0;
5685 }
5686
kvm_handle_tpr_access(X86CPU * cpu)5687 static int kvm_handle_tpr_access(X86CPU *cpu)
5688 {
5689 CPUState *cs = CPU(cpu);
5690 struct kvm_run *run = cs->kvm_run;
5691
5692 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
5693 run->tpr_access.is_write ? TPR_ACCESS_WRITE
5694 : TPR_ACCESS_READ);
5695 return 1;
5696 }
5697
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5698 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5699 {
5700 static const uint8_t int3 = 0xcc;
5701
5702 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
5703 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
5704 return -EINVAL;
5705 }
5706 return 0;
5707 }
5708
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5709 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5710 {
5711 uint8_t int3;
5712
5713 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
5714 return -EINVAL;
5715 }
5716 if (int3 != 0xcc) {
5717 return 0;
5718 }
5719 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
5720 return -EINVAL;
5721 }
5722 return 0;
5723 }
5724
5725 static struct {
5726 target_ulong addr;
5727 int len;
5728 int type;
5729 } hw_breakpoint[4];
5730
5731 static int nb_hw_breakpoint;
5732
find_hw_breakpoint(target_ulong addr,int len,int type)5733 static int find_hw_breakpoint(target_ulong addr, int len, int type)
5734 {
5735 int n;
5736
5737 for (n = 0; n < nb_hw_breakpoint; n++) {
5738 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
5739 (hw_breakpoint[n].len == len || len == -1)) {
5740 return n;
5741 }
5742 }
5743 return -1;
5744 }
5745
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)5746 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
5747 {
5748 switch (type) {
5749 case GDB_BREAKPOINT_HW:
5750 len = 1;
5751 break;
5752 case GDB_WATCHPOINT_WRITE:
5753 case GDB_WATCHPOINT_ACCESS:
5754 switch (len) {
5755 case 1:
5756 break;
5757 case 2:
5758 case 4:
5759 case 8:
5760 if (addr & (len - 1)) {
5761 return -EINVAL;
5762 }
5763 break;
5764 default:
5765 return -EINVAL;
5766 }
5767 break;
5768 default:
5769 return -ENOSYS;
5770 }
5771
5772 if (nb_hw_breakpoint == 4) {
5773 return -ENOBUFS;
5774 }
5775 if (find_hw_breakpoint(addr, len, type) >= 0) {
5776 return -EEXIST;
5777 }
5778 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5779 hw_breakpoint[nb_hw_breakpoint].len = len;
5780 hw_breakpoint[nb_hw_breakpoint].type = type;
5781 nb_hw_breakpoint++;
5782
5783 return 0;
5784 }
5785
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)5786 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
5787 {
5788 int n;
5789
5790 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
5791 if (n < 0) {
5792 return -ENOENT;
5793 }
5794 nb_hw_breakpoint--;
5795 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5796
5797 return 0;
5798 }
5799
kvm_arch_remove_all_hw_breakpoints(void)5800 void kvm_arch_remove_all_hw_breakpoints(void)
5801 {
5802 nb_hw_breakpoint = 0;
5803 }
5804
5805 static CPUWatchpoint hw_watchpoint;
5806
kvm_handle_debug(X86CPU * cpu,struct kvm_debug_exit_arch * arch_info)5807 static int kvm_handle_debug(X86CPU *cpu,
5808 struct kvm_debug_exit_arch *arch_info)
5809 {
5810 CPUState *cs = CPU(cpu);
5811 CPUX86State *env = &cpu->env;
5812 int ret = 0;
5813 int n;
5814
5815 if (arch_info->exception == EXCP01_DB) {
5816 if (arch_info->dr6 & DR6_BS) {
5817 if (cs->singlestep_enabled) {
5818 ret = EXCP_DEBUG;
5819 }
5820 } else {
5821 for (n = 0; n < 4; n++) {
5822 if (arch_info->dr6 & (1 << n)) {
5823 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5824 case 0x0:
5825 ret = EXCP_DEBUG;
5826 break;
5827 case 0x1:
5828 ret = EXCP_DEBUG;
5829 cs->watchpoint_hit = &hw_watchpoint;
5830 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5831 hw_watchpoint.flags = BP_MEM_WRITE;
5832 break;
5833 case 0x3:
5834 ret = EXCP_DEBUG;
5835 cs->watchpoint_hit = &hw_watchpoint;
5836 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5837 hw_watchpoint.flags = BP_MEM_ACCESS;
5838 break;
5839 }
5840 }
5841 }
5842 }
5843 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
5844 ret = EXCP_DEBUG;
5845 }
5846 if (ret == 0) {
5847 cpu_synchronize_state(cs);
5848 assert(env->exception_nr == -1);
5849
5850 /* pass to guest */
5851 kvm_queue_exception(env, arch_info->exception,
5852 arch_info->exception == EXCP01_DB,
5853 arch_info->dr6);
5854 env->has_error_code = 0;
5855 }
5856
5857 return ret;
5858 }
5859
kvm_arch_update_guest_debug(CPUState * cpu,struct kvm_guest_debug * dbg)5860 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
5861 {
5862 const uint8_t type_code[] = {
5863 [GDB_BREAKPOINT_HW] = 0x0,
5864 [GDB_WATCHPOINT_WRITE] = 0x1,
5865 [GDB_WATCHPOINT_ACCESS] = 0x3
5866 };
5867 const uint8_t len_code[] = {
5868 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5869 };
5870 int n;
5871
5872 if (kvm_sw_breakpoints_active(cpu)) {
5873 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
5874 }
5875 if (nb_hw_breakpoint > 0) {
5876 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5877 dbg->arch.debugreg[7] = 0x0600;
5878 for (n = 0; n < nb_hw_breakpoint; n++) {
5879 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5880 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5881 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
5882 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
5883 }
5884 }
5885 }
5886
kvm_install_msr_filters(KVMState * s)5887 static int kvm_install_msr_filters(KVMState *s)
5888 {
5889 uint64_t zero = 0;
5890 struct kvm_msr_filter filter = {
5891 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW,
5892 };
5893 int i, j = 0;
5894
5895 QEMU_BUILD_BUG_ON(ARRAY_SIZE(msr_handlers) != ARRAY_SIZE(filter.ranges));
5896 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5897 KVMMSRHandlers *handler = &msr_handlers[i];
5898 if (handler->msr) {
5899 struct kvm_msr_filter_range *range = &filter.ranges[j++];
5900
5901 *range = (struct kvm_msr_filter_range) {
5902 .flags = 0,
5903 .nmsrs = 1,
5904 .base = handler->msr,
5905 .bitmap = (__u8 *)&zero,
5906 };
5907
5908 if (handler->rdmsr) {
5909 range->flags |= KVM_MSR_FILTER_READ;
5910 }
5911
5912 if (handler->wrmsr) {
5913 range->flags |= KVM_MSR_FILTER_WRITE;
5914 }
5915 }
5916 }
5917
5918 return kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter);
5919 }
5920
kvm_filter_msr(KVMState * s,uint32_t msr,QEMURDMSRHandler * rdmsr,QEMUWRMSRHandler * wrmsr)5921 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
5922 QEMUWRMSRHandler *wrmsr)
5923 {
5924 int i, ret;
5925
5926 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5927 if (!msr_handlers[i].msr) {
5928 msr_handlers[i] = (KVMMSRHandlers) {
5929 .msr = msr,
5930 .rdmsr = rdmsr,
5931 .wrmsr = wrmsr,
5932 };
5933
5934 ret = kvm_install_msr_filters(s);
5935 if (ret) {
5936 msr_handlers[i] = (KVMMSRHandlers) { };
5937 return ret;
5938 }
5939
5940 return 0;
5941 }
5942 }
5943
5944 return -EINVAL;
5945 }
5946
kvm_handle_rdmsr(X86CPU * cpu,struct kvm_run * run)5947 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run)
5948 {
5949 int i;
5950 bool r;
5951
5952 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5953 KVMMSRHandlers *handler = &msr_handlers[i];
5954 if (run->msr.index == handler->msr) {
5955 if (handler->rdmsr) {
5956 r = handler->rdmsr(cpu, handler->msr,
5957 (uint64_t *)&run->msr.data);
5958 run->msr.error = r ? 0 : 1;
5959 return 0;
5960 }
5961 }
5962 }
5963
5964 g_assert_not_reached();
5965 }
5966
kvm_handle_wrmsr(X86CPU * cpu,struct kvm_run * run)5967 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run)
5968 {
5969 int i;
5970 bool r;
5971
5972 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5973 KVMMSRHandlers *handler = &msr_handlers[i];
5974 if (run->msr.index == handler->msr) {
5975 if (handler->wrmsr) {
5976 r = handler->wrmsr(cpu, handler->msr, run->msr.data);
5977 run->msr.error = r ? 0 : 1;
5978 return 0;
5979 }
5980 }
5981 }
5982
5983 g_assert_not_reached();
5984 }
5985
5986 static bool has_sgx_provisioning;
5987
__kvm_enable_sgx_provisioning(KVMState * s)5988 static bool __kvm_enable_sgx_provisioning(KVMState *s)
5989 {
5990 int fd, ret;
5991
5992 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5993 return false;
5994 }
5995
5996 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5997 if (fd < 0) {
5998 return false;
5999 }
6000
6001 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
6002 if (ret) {
6003 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
6004 exit(1);
6005 }
6006 close(fd);
6007 return true;
6008 }
6009
kvm_enable_sgx_provisioning(KVMState * s)6010 bool kvm_enable_sgx_provisioning(KVMState *s)
6011 {
6012 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
6013 }
6014
host_supports_vmx(void)6015 static bool host_supports_vmx(void)
6016 {
6017 uint32_t ecx, unused;
6018
6019 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
6020 return ecx & CPUID_EXT_VMX;
6021 }
6022
6023 /*
6024 * Currently the handling here only supports use of KVM_HC_MAP_GPA_RANGE
6025 * to service guest-initiated memory attribute update requests so that
6026 * KVM_SET_MEMORY_ATTRIBUTES can update whether or not a page should be
6027 * backed by the private memory pool provided by guest_memfd, and as such
6028 * is only applicable to guest_memfd-backed guests (e.g. SNP/TDX).
6029 *
6030 * Other other use-cases for KVM_HC_MAP_GPA_RANGE, such as for SEV live
6031 * migration, are not implemented here currently.
6032 *
6033 * For the guest_memfd use-case, these exits will generally be synthesized
6034 * by KVM based on platform-specific hypercalls, like GHCB requests in the
6035 * case of SEV-SNP, and not issued directly within the guest though the
6036 * KVM_HC_MAP_GPA_RANGE hypercall. So in this case, KVM_HC_MAP_GPA_RANGE is
6037 * not actually advertised to guests via the KVM CPUID feature bit, as
6038 * opposed to SEV live migration where it would be. Since it is unlikely the
6039 * SEV live migration use-case would be useful for guest-memfd backed guests,
6040 * because private/shared page tracking is already provided through other
6041 * means, these 2 use-cases should be treated as being mutually-exclusive.
6042 */
kvm_handle_hc_map_gpa_range(X86CPU * cpu,struct kvm_run * run)6043 static int kvm_handle_hc_map_gpa_range(X86CPU *cpu, struct kvm_run *run)
6044 {
6045 struct kvm_pre_fault_memory mem;
6046 uint64_t gpa, size, attributes;
6047 int ret;
6048
6049 if (!machine_require_guest_memfd(current_machine))
6050 return -EINVAL;
6051
6052 gpa = run->hypercall.args[0];
6053 size = run->hypercall.args[1] * TARGET_PAGE_SIZE;
6054 attributes = run->hypercall.args[2];
6055
6056 trace_kvm_hc_map_gpa_range(gpa, size, attributes, run->hypercall.flags);
6057
6058 ret = kvm_convert_memory(gpa, size, attributes & KVM_MAP_GPA_RANGE_ENCRYPTED);
6059 if (ret || !kvm_pre_fault_memory_supported) {
6060 return ret;
6061 }
6062
6063 /*
6064 * Opportunistically pre-fault memory in. Failures are ignored so that any
6065 * errors in faulting in the memory will get captured in KVM page fault
6066 * path when the guest first accesses the page.
6067 */
6068 memset(&mem, 0, sizeof(mem));
6069 mem.gpa = gpa;
6070 mem.size = size;
6071 while (mem.size) {
6072 if (kvm_vcpu_ioctl(CPU(cpu), KVM_PRE_FAULT_MEMORY, &mem)) {
6073 break;
6074 }
6075 }
6076
6077 return 0;
6078 }
6079
kvm_handle_hypercall(X86CPU * cpu,struct kvm_run * run)6080 static int kvm_handle_hypercall(X86CPU *cpu, struct kvm_run *run)
6081 {
6082 if (run->hypercall.nr == KVM_HC_MAP_GPA_RANGE)
6083 return kvm_handle_hc_map_gpa_range(cpu, run);
6084
6085 return -EINVAL;
6086 }
6087
6088 #define VMX_INVALID_GUEST_STATE 0x80000021
6089
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)6090 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
6091 {
6092 X86CPU *cpu = X86_CPU(cs);
6093 uint64_t code;
6094 int ret;
6095 bool ctx_invalid;
6096 KVMState *state;
6097
6098 switch (run->exit_reason) {
6099 case KVM_EXIT_HLT:
6100 DPRINTF("handle_hlt\n");
6101 bql_lock();
6102 ret = kvm_handle_halt(cpu);
6103 bql_unlock();
6104 break;
6105 case KVM_EXIT_SET_TPR:
6106 ret = 0;
6107 break;
6108 case KVM_EXIT_TPR_ACCESS:
6109 bql_lock();
6110 ret = kvm_handle_tpr_access(cpu);
6111 bql_unlock();
6112 break;
6113 case KVM_EXIT_FAIL_ENTRY:
6114 code = run->fail_entry.hardware_entry_failure_reason;
6115 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
6116 code);
6117 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
6118 fprintf(stderr,
6119 "\nIf you're running a guest on an Intel machine without "
6120 "unrestricted mode\n"
6121 "support, the failure can be most likely due to the guest "
6122 "entering an invalid\n"
6123 "state for Intel VT. For example, the guest maybe running "
6124 "in big real mode\n"
6125 "which is not supported on less recent Intel processors."
6126 "\n\n");
6127 }
6128 ret = -1;
6129 break;
6130 case KVM_EXIT_EXCEPTION:
6131 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
6132 run->ex.exception, run->ex.error_code);
6133 ret = -1;
6134 break;
6135 case KVM_EXIT_DEBUG:
6136 DPRINTF("kvm_exit_debug\n");
6137 bql_lock();
6138 ret = kvm_handle_debug(cpu, &run->debug.arch);
6139 bql_unlock();
6140 break;
6141 case KVM_EXIT_HYPERV:
6142 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
6143 break;
6144 case KVM_EXIT_IOAPIC_EOI:
6145 ioapic_eoi_broadcast(run->eoi.vector);
6146 ret = 0;
6147 break;
6148 case KVM_EXIT_X86_BUS_LOCK:
6149 /* already handled in kvm_arch_post_run */
6150 ret = 0;
6151 break;
6152 case KVM_EXIT_NOTIFY:
6153 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
6154 state = KVM_STATE(current_accel());
6155 if (ctx_invalid ||
6156 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
6157 warn_report("KVM internal error: Encountered a notify exit "
6158 "with invalid context in guest.");
6159 ret = -1;
6160 } else {
6161 warn_report_once("KVM: Encountered a notify exit with valid "
6162 "context in guest. "
6163 "The guest could be misbehaving.");
6164 ret = 0;
6165 }
6166 break;
6167 case KVM_EXIT_X86_RDMSR:
6168 /* We only enable MSR filtering, any other exit is bogus */
6169 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6170 ret = kvm_handle_rdmsr(cpu, run);
6171 break;
6172 case KVM_EXIT_X86_WRMSR:
6173 /* We only enable MSR filtering, any other exit is bogus */
6174 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6175 ret = kvm_handle_wrmsr(cpu, run);
6176 break;
6177 #ifdef CONFIG_XEN_EMU
6178 case KVM_EXIT_XEN:
6179 ret = kvm_xen_handle_exit(cpu, &run->xen);
6180 break;
6181 #endif
6182 case KVM_EXIT_HYPERCALL:
6183 ret = kvm_handle_hypercall(cpu, run);
6184 break;
6185 case KVM_EXIT_SYSTEM_EVENT:
6186 switch (run->system_event.type) {
6187 case KVM_SYSTEM_EVENT_TDX_FATAL:
6188 ret = tdx_handle_report_fatal_error(cpu, run);
6189 break;
6190 default:
6191 ret = -1;
6192 break;
6193 }
6194 break;
6195 case KVM_EXIT_TDX:
6196 /*
6197 * run->tdx is already set up for the case where userspace
6198 * does not handle the TDVMCALL.
6199 */
6200 switch (run->tdx.nr) {
6201 case TDVMCALL_GET_QUOTE:
6202 tdx_handle_get_quote(cpu, run);
6203 break;
6204 case TDVMCALL_GET_TD_VM_CALL_INFO:
6205 tdx_handle_get_tdvmcall_info(cpu, run);
6206 break;
6207 case TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT:
6208 tdx_handle_setup_event_notify_interrupt(cpu, run);
6209 break;
6210 }
6211 ret = 0;
6212 break;
6213 default:
6214 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
6215 ret = -1;
6216 break;
6217 }
6218
6219 return ret;
6220 }
6221
kvm_arch_stop_on_emulation_error(CPUState * cs)6222 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
6223 {
6224 X86CPU *cpu = X86_CPU(cs);
6225 CPUX86State *env = &cpu->env;
6226
6227 kvm_cpu_synchronize_state(cs);
6228 return !(env->cr[0] & CR0_PE_MASK) ||
6229 ((env->segs[R_CS].selector & 3) != 3);
6230 }
6231
kvm_arch_init_irq_routing(KVMState * s)6232 void kvm_arch_init_irq_routing(KVMState *s)
6233 {
6234 /* We know at this point that we're using the in-kernel
6235 * irqchip, so we can use irqfds, and on x86 we know
6236 * we can use msi via irqfd and GSI routing.
6237 */
6238 kvm_msi_via_irqfd_allowed = true;
6239 kvm_gsi_routing_allowed = true;
6240
6241 if (kvm_irqchip_is_split()) {
6242 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
6243 int i;
6244
6245 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
6246 MSI routes for signaling interrupts to the local apics. */
6247 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
6248 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
6249 error_report("Could not enable split IRQ mode.");
6250 exit(1);
6251 }
6252 }
6253 kvm_irqchip_commit_route_changes(&c);
6254 }
6255 }
6256
kvm_arch_irqchip_create(KVMState * s)6257 int kvm_arch_irqchip_create(KVMState *s)
6258 {
6259 int ret;
6260 if (kvm_kernel_irqchip_split()) {
6261 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
6262 if (ret) {
6263 error_report("Could not enable split irqchip mode: %s",
6264 strerror(-ret));
6265 exit(1);
6266 } else {
6267 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
6268 kvm_split_irqchip = true;
6269 return 1;
6270 }
6271 } else {
6272 return 0;
6273 }
6274 }
6275
kvm_swizzle_msi_ext_dest_id(uint64_t address)6276 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
6277 {
6278 CPUX86State *env;
6279 uint64_t ext_id;
6280
6281 if (!first_cpu) {
6282 return address;
6283 }
6284 env = &X86_CPU(first_cpu)->env;
6285 if (!(env->features[FEAT_KVM] & CPUID_KVM_MSI_EXT_DEST_ID)) {
6286 return address;
6287 }
6288
6289 /*
6290 * If the remappable format bit is set, or the upper bits are
6291 * already set in address_hi, or the low extended bits aren't
6292 * there anyway, do nothing.
6293 */
6294 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
6295 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
6296 return address;
6297 }
6298
6299 address &= ~ext_id;
6300 address |= ext_id << 35;
6301 return address;
6302 }
6303
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)6304 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
6305 uint64_t address, uint32_t data, PCIDevice *dev)
6306 {
6307 X86IOMMUState *iommu = x86_iommu_get_default();
6308
6309 if (iommu) {
6310 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
6311
6312 if (class->int_remap) {
6313 int ret;
6314 MSIMessage src, dst;
6315
6316 src.address = route->u.msi.address_hi;
6317 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
6318 src.address |= route->u.msi.address_lo;
6319 src.data = route->u.msi.data;
6320
6321 ret = class->int_remap(iommu, &src, &dst, dev ? \
6322 pci_requester_id(dev) : \
6323 X86_IOMMU_SID_INVALID);
6324 if (ret) {
6325 trace_kvm_x86_fixup_msi_error(route->gsi);
6326 return 1;
6327 }
6328
6329 /*
6330 * Handled untranslated compatibility format interrupt with
6331 * extended destination ID in the low bits 11-5. */
6332 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
6333
6334 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
6335 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
6336 route->u.msi.data = dst.data;
6337 return 0;
6338 }
6339 }
6340
6341 #ifdef CONFIG_XEN_EMU
6342 if (xen_mode == XEN_EMULATE) {
6343 int handled = xen_evtchn_translate_pirq_msi(route, address, data);
6344
6345 /*
6346 * If it was a PIRQ and successfully routed (handled == 0) or it was
6347 * an error (handled < 0), return. If it wasn't a PIRQ, keep going.
6348 */
6349 if (handled <= 0) {
6350 return handled;
6351 }
6352 }
6353 #endif
6354
6355 address = kvm_swizzle_msi_ext_dest_id(address);
6356 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
6357 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
6358 return 0;
6359 }
6360
6361 typedef struct MSIRouteEntry MSIRouteEntry;
6362
6363 struct MSIRouteEntry {
6364 PCIDevice *dev; /* Device pointer */
6365 int vector; /* MSI/MSIX vector index */
6366 int virq; /* Virtual IRQ index */
6367 QLIST_ENTRY(MSIRouteEntry) list;
6368 };
6369
6370 /* List of used GSI routes */
6371 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
6372 QLIST_HEAD_INITIALIZER(msi_route_list);
6373
kvm_update_msi_routes_all(void * private,bool global,uint32_t index,uint32_t mask)6374 void kvm_update_msi_routes_all(void *private, bool global,
6375 uint32_t index, uint32_t mask)
6376 {
6377 int cnt = 0, vector;
6378 MSIRouteEntry *entry;
6379 MSIMessage msg;
6380 PCIDevice *dev;
6381
6382 /* TODO: explicit route update */
6383 QLIST_FOREACH(entry, &msi_route_list, list) {
6384 cnt++;
6385 vector = entry->vector;
6386 dev = entry->dev;
6387 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
6388 msg = msix_get_message(dev, vector);
6389 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
6390 msg = msi_get_message(dev, vector);
6391 } else {
6392 /*
6393 * Either MSI/MSIX is disabled for the device, or the
6394 * specific message was masked out. Skip this one.
6395 */
6396 continue;
6397 }
6398 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
6399 }
6400 kvm_irqchip_commit_routes(kvm_state);
6401 trace_kvm_x86_update_msi_routes(cnt);
6402 }
6403
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)6404 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
6405 int vector, PCIDevice *dev)
6406 {
6407 static bool notify_list_inited = false;
6408 MSIRouteEntry *entry;
6409
6410 if (!dev) {
6411 /* These are (possibly) IOAPIC routes only used for split
6412 * kernel irqchip mode, while what we are housekeeping are
6413 * PCI devices only. */
6414 return 0;
6415 }
6416
6417 entry = g_new0(MSIRouteEntry, 1);
6418 entry->dev = dev;
6419 entry->vector = vector;
6420 entry->virq = route->gsi;
6421 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
6422
6423 trace_kvm_x86_add_msi_route(route->gsi);
6424
6425 if (!notify_list_inited) {
6426 /* For the first time we do add route, add ourselves into
6427 * IOMMU's IEC notify list if needed. */
6428 X86IOMMUState *iommu = x86_iommu_get_default();
6429 if (iommu) {
6430 x86_iommu_iec_register_notifier(iommu,
6431 kvm_update_msi_routes_all,
6432 NULL);
6433 }
6434 notify_list_inited = true;
6435 }
6436 return 0;
6437 }
6438
kvm_arch_release_virq_post(int virq)6439 int kvm_arch_release_virq_post(int virq)
6440 {
6441 MSIRouteEntry *entry, *next;
6442 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
6443 if (entry->virq == virq) {
6444 trace_kvm_x86_remove_msi_route(virq);
6445 QLIST_REMOVE(entry, list);
6446 g_free(entry);
6447 break;
6448 }
6449 }
6450 return 0;
6451 }
6452
kvm_arch_msi_data_to_gsi(uint32_t data)6453 int kvm_arch_msi_data_to_gsi(uint32_t data)
6454 {
6455 abort();
6456 }
6457
kvm_has_waitpkg(void)6458 bool kvm_has_waitpkg(void)
6459 {
6460 return has_msr_umwait;
6461 }
6462
6463 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
6464
kvm_request_xsave_components(X86CPU * cpu,uint64_t mask)6465 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
6466 {
6467 KVMState *s = kvm_state;
6468 uint64_t supported;
6469
6470 mask &= XSTATE_DYNAMIC_MASK;
6471 if (!mask) {
6472 return;
6473 }
6474 /*
6475 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
6476 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
6477 * about them already because they are not supported features.
6478 */
6479 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
6480 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
6481 mask &= supported;
6482
6483 while (mask) {
6484 int bit = ctz64(mask);
6485 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
6486 if (rc) {
6487 /*
6488 * Older kernel version (<5.17) do not support
6489 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
6490 * any dynamic feature from kvm_arch_get_supported_cpuid.
6491 */
6492 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
6493 "for feature bit %d", bit);
6494 }
6495 mask &= ~BIT_ULL(bit);
6496 }
6497 }
6498
kvm_arch_get_notify_vmexit(Object * obj,Error ** errp)6499 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
6500 {
6501 KVMState *s = KVM_STATE(obj);
6502 return s->notify_vmexit;
6503 }
6504
kvm_arch_set_notify_vmexit(Object * obj,int value,Error ** errp)6505 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
6506 {
6507 KVMState *s = KVM_STATE(obj);
6508
6509 if (s->fd != -1) {
6510 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6511 return;
6512 }
6513
6514 s->notify_vmexit = value;
6515 }
6516
kvm_arch_get_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6517 static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
6518 const char *name, void *opaque,
6519 Error **errp)
6520 {
6521 KVMState *s = KVM_STATE(obj);
6522 uint32_t value = s->notify_window;
6523
6524 visit_type_uint32(v, name, &value, errp);
6525 }
6526
kvm_arch_set_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6527 static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
6528 const char *name, void *opaque,
6529 Error **errp)
6530 {
6531 KVMState *s = KVM_STATE(obj);
6532 uint32_t value;
6533
6534 if (s->fd != -1) {
6535 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6536 return;
6537 }
6538
6539 if (!visit_type_uint32(v, name, &value, errp)) {
6540 return;
6541 }
6542
6543 s->notify_window = value;
6544 }
6545
kvm_arch_get_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6546 static void kvm_arch_get_xen_version(Object *obj, Visitor *v,
6547 const char *name, void *opaque,
6548 Error **errp)
6549 {
6550 KVMState *s = KVM_STATE(obj);
6551 uint32_t value = s->xen_version;
6552
6553 visit_type_uint32(v, name, &value, errp);
6554 }
6555
kvm_arch_set_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6556 static void kvm_arch_set_xen_version(Object *obj, Visitor *v,
6557 const char *name, void *opaque,
6558 Error **errp)
6559 {
6560 KVMState *s = KVM_STATE(obj);
6561 Error *error = NULL;
6562 uint32_t value;
6563
6564 visit_type_uint32(v, name, &value, &error);
6565 if (error) {
6566 error_propagate(errp, error);
6567 return;
6568 }
6569
6570 s->xen_version = value;
6571 if (value && xen_mode == XEN_DISABLED) {
6572 xen_mode = XEN_EMULATE;
6573 }
6574 }
6575
kvm_arch_get_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6576 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v,
6577 const char *name, void *opaque,
6578 Error **errp)
6579 {
6580 KVMState *s = KVM_STATE(obj);
6581 uint16_t value = s->xen_gnttab_max_frames;
6582
6583 visit_type_uint16(v, name, &value, errp);
6584 }
6585
kvm_arch_set_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6586 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v,
6587 const char *name, void *opaque,
6588 Error **errp)
6589 {
6590 KVMState *s = KVM_STATE(obj);
6591 Error *error = NULL;
6592 uint16_t value;
6593
6594 visit_type_uint16(v, name, &value, &error);
6595 if (error) {
6596 error_propagate(errp, error);
6597 return;
6598 }
6599
6600 s->xen_gnttab_max_frames = value;
6601 }
6602
kvm_arch_get_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6603 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6604 const char *name, void *opaque,
6605 Error **errp)
6606 {
6607 KVMState *s = KVM_STATE(obj);
6608 uint16_t value = s->xen_evtchn_max_pirq;
6609
6610 visit_type_uint16(v, name, &value, errp);
6611 }
6612
kvm_arch_set_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6613 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6614 const char *name, void *opaque,
6615 Error **errp)
6616 {
6617 KVMState *s = KVM_STATE(obj);
6618 Error *error = NULL;
6619 uint16_t value;
6620
6621 visit_type_uint16(v, name, &value, &error);
6622 if (error) {
6623 error_propagate(errp, error);
6624 return;
6625 }
6626
6627 s->xen_evtchn_max_pirq = value;
6628 }
6629
kvm_arch_accel_class_init(ObjectClass * oc)6630 void kvm_arch_accel_class_init(ObjectClass *oc)
6631 {
6632 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
6633 &NotifyVmexitOption_lookup,
6634 kvm_arch_get_notify_vmexit,
6635 kvm_arch_set_notify_vmexit);
6636 object_class_property_set_description(oc, "notify-vmexit",
6637 "Enable notify VM exit");
6638
6639 object_class_property_add(oc, "notify-window", "uint32",
6640 kvm_arch_get_notify_window,
6641 kvm_arch_set_notify_window,
6642 NULL, NULL);
6643 object_class_property_set_description(oc, "notify-window",
6644 "Clock cycles without an event window "
6645 "after which a notification VM exit occurs");
6646
6647 object_class_property_add(oc, "xen-version", "uint32",
6648 kvm_arch_get_xen_version,
6649 kvm_arch_set_xen_version,
6650 NULL, NULL);
6651 object_class_property_set_description(oc, "xen-version",
6652 "Xen version to be emulated "
6653 "(in XENVER_version form "
6654 "e.g. 0x4000a for 4.10)");
6655
6656 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16",
6657 kvm_arch_get_xen_gnttab_max_frames,
6658 kvm_arch_set_xen_gnttab_max_frames,
6659 NULL, NULL);
6660 object_class_property_set_description(oc, "xen-gnttab-max-frames",
6661 "Maximum number of grant table frames");
6662
6663 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16",
6664 kvm_arch_get_xen_evtchn_max_pirq,
6665 kvm_arch_set_xen_evtchn_max_pirq,
6666 NULL, NULL);
6667 object_class_property_set_description(oc, "xen-evtchn-max-pirq",
6668 "Maximum number of Xen PIRQs");
6669 }
6670
kvm_set_max_apic_id(uint32_t max_apic_id)6671 void kvm_set_max_apic_id(uint32_t max_apic_id)
6672 {
6673 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id);
6674 }
6675