1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVKM_DEVICE_TEGRA_H__
3 #define __NVKM_DEVICE_TEGRA_H__
4 #include <core/device.h>
5 #include <core/mm.h>
6 
7 struct nvkm_device_tegra {
8 	const struct nvkm_device_tegra_func *func;
9 	struct nvkm_device device;
10 	struct platform_device *pdev;
11 
12 	struct reset_control *rst;
13 	struct clk *clk;
14 	struct clk *clk_ref;
15 	struct clk *clk_pwr;
16 
17 	struct regulator *vdd;
18 
19 	struct {
20 		/*
21 		 * Protects accesses to mm from subsystems
22 		 */
23 		struct mutex mutex;
24 
25 		struct nvkm_mm mm;
26 		struct iommu_domain *domain;
27 		unsigned long pgshift;
28 	} iommu;
29 
30 	int gpu_speedo;
31 	int gpu_speedo_id;
32 };
33 
34 struct nvkm_device_tegra_func {
35 	/*
36 	 * If an IOMMU is used, indicates which address bit will trigger a
37 	 * IOMMU translation when set (when this bit is not set, IOMMU is
38 	 * bypassed). A value of 0 means an IOMMU is never used.
39 	 */
40 	u8 iommu_bit;
41 	/*
42 	 * Whether the chip requires a reference clock
43 	 */
44 	bool require_ref_clk;
45 	/*
46 	 * Whether the chip requires the VDD regulator
47 	 */
48 	bool require_vdd;
49 };
50 
51 int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
52 			  struct platform_device *,
53 			  const char *cfg, const char *dbg,
54 			  bool detect, bool mmio, u64 subdev_mask,
55 			  struct nvkm_device **);
56 #endif
57