1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "common.h"
20 #include "gdsc.h"
21 #include "reset.h"
22
23 enum {
24 DT_BI_TCXO,
25 DT_GPLL0_OUT_MAIN,
26 DT_GPLL0_OUT_MAIN_DIV,
27 };
28
29 enum {
30 P_BI_TCXO,
31 P_GPLL0_OUT_MAIN,
32 P_GPLL0_OUT_MAIN_DIV,
33 P_GPU_CC_PLL0_OUT_MAIN,
34 P_GPU_CC_PLL1_OUT_MAIN,
35 };
36
37 static const struct pll_vco lucid_ole_vco[] = {
38 { 249600000, 2300000000, 0 },
39 };
40
41 static const struct alpha_pll_config gpu_cc_pll0_config = {
42 /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
43 .l = 0x4444000d,
44 .alpha = 0x0,
45 .config_ctl_val = 0x20485699,
46 .config_ctl_hi_val = 0x00182261,
47 .config_ctl_hi1_val = 0x82aa299c,
48 .test_ctl_val = 0x00000000,
49 .test_ctl_hi_val = 0x00000003,
50 .test_ctl_hi1_val = 0x00009000,
51 .test_ctl_hi2_val = 0x00000034,
52 .user_ctl_val = 0x00000000,
53 .user_ctl_hi_val = 0x00000005,
54 };
55
56 static struct clk_alpha_pll gpu_cc_pll0 = {
57 .offset = 0x0,
58 .vco_table = lucid_ole_vco,
59 .num_vco = ARRAY_SIZE(lucid_ole_vco),
60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
61 .clkr = {
62 .hw.init = &(const struct clk_init_data) {
63 .name = "gpu_cc_pll0",
64 .parent_data = &(const struct clk_parent_data) {
65 .index = DT_BI_TCXO,
66 },
67 .num_parents = 1,
68 .ops = &clk_alpha_pll_lucid_evo_ops,
69 },
70 },
71 };
72
73 static const struct alpha_pll_config gpu_cc_pll1_config = {
74 /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
75 .l = 0x44440016,
76 .alpha = 0xeaaa,
77 .config_ctl_val = 0x20485699,
78 .config_ctl_hi_val = 0x00182261,
79 .config_ctl_hi1_val = 0x82aa299c,
80 .test_ctl_val = 0x00000000,
81 .test_ctl_hi_val = 0x00000003,
82 .test_ctl_hi1_val = 0x00009000,
83 .test_ctl_hi2_val = 0x00000034,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000005,
86 };
87
88 static struct clk_alpha_pll gpu_cc_pll1 = {
89 .offset = 0x1000,
90 .vco_table = lucid_ole_vco,
91 .num_vco = ARRAY_SIZE(lucid_ole_vco),
92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
93 .clkr = {
94 .hw.init = &(const struct clk_init_data) {
95 .name = "gpu_cc_pll1",
96 .parent_data = &(const struct clk_parent_data) {
97 .index = DT_BI_TCXO,
98 },
99 .num_parents = 1,
100 .ops = &clk_alpha_pll_lucid_evo_ops,
101 },
102 },
103 };
104
105 static const struct parent_map gpu_cc_parent_map_0[] = {
106 { P_BI_TCXO, 0 },
107 { P_GPLL0_OUT_MAIN, 5 },
108 { P_GPLL0_OUT_MAIN_DIV, 6 },
109 };
110
111 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
112 { .index = DT_BI_TCXO },
113 { .index = DT_GPLL0_OUT_MAIN },
114 { .index = DT_GPLL0_OUT_MAIN_DIV },
115 };
116
117 static const struct parent_map gpu_cc_parent_map_1[] = {
118 { P_BI_TCXO, 0 },
119 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
120 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
121 { P_GPLL0_OUT_MAIN, 5 },
122 { P_GPLL0_OUT_MAIN_DIV, 6 },
123 };
124
125 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
126 { .index = DT_BI_TCXO },
127 { .hw = &gpu_cc_pll0.clkr.hw },
128 { .hw = &gpu_cc_pll1.clkr.hw },
129 { .index = DT_GPLL0_OUT_MAIN },
130 { .index = DT_GPLL0_OUT_MAIN_DIV },
131 };
132
133 static const struct parent_map gpu_cc_parent_map_2[] = {
134 { P_BI_TCXO, 0 },
135 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
136 { P_GPLL0_OUT_MAIN, 5 },
137 { P_GPLL0_OUT_MAIN_DIV, 6 },
138 };
139
140 static const struct clk_parent_data gpu_cc_parent_data_2[] = {
141 { .index = DT_BI_TCXO },
142 { .hw = &gpu_cc_pll1.clkr.hw },
143 { .index = DT_GPLL0_OUT_MAIN },
144 { .index = DT_GPLL0_OUT_MAIN_DIV },
145 };
146
147 static const struct parent_map gpu_cc_parent_map_3[] = {
148 { P_BI_TCXO, 0 },
149 };
150
151 static const struct clk_parent_data gpu_cc_parent_data_3[] = {
152 { .index = DT_BI_TCXO },
153 };
154
155 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
156 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
157 { }
158 };
159
160 static struct clk_rcg2 gpu_cc_ff_clk_src = {
161 .cmd_rcgr = 0x9474,
162 .mnd_width = 0,
163 .hid_width = 5,
164 .parent_map = gpu_cc_parent_map_0,
165 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
166 .clkr.hw.init = &(const struct clk_init_data) {
167 .name = "gpu_cc_ff_clk_src",
168 .parent_data = gpu_cc_parent_data_0,
169 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
170 .flags = CLK_SET_RATE_PARENT,
171 .ops = &clk_rcg2_shared_ops,
172 },
173 };
174
175 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
176 F(19200000, P_BI_TCXO, 1, 0, 0),
177 F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
178 F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
179 { }
180 };
181
182 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
183 .cmd_rcgr = 0x9318,
184 .mnd_width = 0,
185 .hid_width = 5,
186 .parent_map = gpu_cc_parent_map_1,
187 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
188 .clkr.hw.init = &(const struct clk_init_data) {
189 .name = "gpu_cc_gmu_clk_src",
190 .parent_data = gpu_cc_parent_data_1,
191 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
192 .flags = CLK_SET_RATE_PARENT,
193 .ops = &clk_rcg2_shared_ops,
194 },
195 };
196
197 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
198 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
199 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
200 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
201 { }
202 };
203
204 static struct clk_rcg2 gpu_cc_hub_clk_src = {
205 .cmd_rcgr = 0x93ec,
206 .mnd_width = 0,
207 .hid_width = 5,
208 .parent_map = gpu_cc_parent_map_2,
209 .freq_tbl = ftbl_gpu_cc_hub_clk_src,
210 .clkr.hw.init = &(const struct clk_init_data) {
211 .name = "gpu_cc_hub_clk_src",
212 .parent_data = gpu_cc_parent_data_2,
213 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
214 .flags = CLK_SET_RATE_PARENT,
215 .ops = &clk_rcg2_shared_ops,
216 },
217 };
218
219 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
220 F(19200000, P_BI_TCXO, 1, 0, 0),
221 { }
222 };
223
224 static struct clk_rcg2 gpu_cc_xo_clk_src = {
225 .cmd_rcgr = 0x9010,
226 .mnd_width = 0,
227 .hid_width = 5,
228 .parent_map = gpu_cc_parent_map_3,
229 .freq_tbl = ftbl_gpu_cc_xo_clk_src,
230 .clkr.hw.init = &(const struct clk_init_data) {
231 .name = "gpu_cc_xo_clk_src",
232 .parent_data = gpu_cc_parent_data_3,
233 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
234 .flags = CLK_SET_RATE_PARENT,
235 .ops = &clk_rcg2_shared_ops,
236 },
237 };
238
239 static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
240 .reg = 0x9054,
241 .shift = 0,
242 .width = 4,
243 .clkr.hw.init = &(const struct clk_init_data) {
244 .name = "gpu_cc_demet_div_clk_src",
245 .parent_hws = (const struct clk_hw*[]) {
246 &gpu_cc_xo_clk_src.clkr.hw,
247 },
248 .num_parents = 1,
249 .flags = CLK_SET_RATE_PARENT,
250 .ops = &clk_regmap_div_ro_ops,
251 },
252 };
253
254 static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
255 .reg = 0x9050,
256 .shift = 0,
257 .width = 4,
258 .clkr.hw.init = &(const struct clk_init_data) {
259 .name = "gpu_cc_xo_div_clk_src",
260 .parent_hws = (const struct clk_hw*[]) {
261 &gpu_cc_xo_clk_src.clkr.hw,
262 },
263 .num_parents = 1,
264 .flags = CLK_SET_RATE_PARENT,
265 .ops = &clk_regmap_div_ro_ops,
266 },
267 };
268
269 static struct clk_branch gpu_cc_ahb_clk = {
270 .halt_reg = 0x911c,
271 .halt_check = BRANCH_HALT_DELAY,
272 .clkr = {
273 .enable_reg = 0x911c,
274 .enable_mask = BIT(0),
275 .hw.init = &(const struct clk_init_data) {
276 .name = "gpu_cc_ahb_clk",
277 .parent_hws = (const struct clk_hw*[]) {
278 &gpu_cc_hub_clk_src.clkr.hw,
279 },
280 .num_parents = 1,
281 .flags = CLK_SET_RATE_PARENT,
282 .ops = &clk_branch2_ops,
283 },
284 },
285 };
286
287 static struct clk_branch gpu_cc_crc_ahb_clk = {
288 .halt_reg = 0x9120,
289 .halt_check = BRANCH_HALT_VOTED,
290 .clkr = {
291 .enable_reg = 0x9120,
292 .enable_mask = BIT(0),
293 .hw.init = &(const struct clk_init_data) {
294 .name = "gpu_cc_crc_ahb_clk",
295 .parent_hws = (const struct clk_hw*[]) {
296 &gpu_cc_hub_clk_src.clkr.hw,
297 },
298 .num_parents = 1,
299 .flags = CLK_SET_RATE_PARENT,
300 .ops = &clk_branch2_ops,
301 },
302 },
303 };
304
305 static struct clk_branch gpu_cc_cx_ff_clk = {
306 .halt_reg = 0x914c,
307 .halt_check = BRANCH_HALT,
308 .clkr = {
309 .enable_reg = 0x914c,
310 .enable_mask = BIT(0),
311 .hw.init = &(const struct clk_init_data) {
312 .name = "gpu_cc_cx_ff_clk",
313 .parent_hws = (const struct clk_hw*[]) {
314 &gpu_cc_ff_clk_src.clkr.hw,
315 },
316 .num_parents = 1,
317 .flags = CLK_SET_RATE_PARENT,
318 .ops = &clk_branch2_ops,
319 },
320 },
321 };
322
323 static struct clk_branch gpu_cc_cx_gmu_clk = {
324 .halt_reg = 0x913c,
325 .halt_check = BRANCH_HALT_VOTED,
326 .clkr = {
327 .enable_reg = 0x913c,
328 .enable_mask = BIT(0),
329 .hw.init = &(const struct clk_init_data) {
330 .name = "gpu_cc_cx_gmu_clk",
331 .parent_hws = (const struct clk_hw*[]) {
332 &gpu_cc_gmu_clk_src.clkr.hw,
333 },
334 .num_parents = 1,
335 .flags = CLK_SET_RATE_PARENT,
336 .ops = &clk_branch2_aon_ops,
337 },
338 },
339 };
340
341 static struct clk_branch gpu_cc_cxo_clk = {
342 .halt_reg = 0x9144,
343 .halt_check = BRANCH_HALT,
344 .clkr = {
345 .enable_reg = 0x9144,
346 .enable_mask = BIT(0),
347 .hw.init = &(const struct clk_init_data) {
348 .name = "gpu_cc_cxo_clk",
349 .parent_hws = (const struct clk_hw*[]) {
350 &gpu_cc_xo_clk_src.clkr.hw,
351 },
352 .num_parents = 1,
353 .flags = CLK_SET_RATE_PARENT,
354 .ops = &clk_branch2_ops,
355 },
356 },
357 };
358
359 static struct clk_branch gpu_cc_freq_measure_clk = {
360 .halt_reg = 0x9008,
361 .halt_check = BRANCH_HALT,
362 .clkr = {
363 .enable_reg = 0x9008,
364 .enable_mask = BIT(0),
365 .hw.init = &(const struct clk_init_data) {
366 .name = "gpu_cc_freq_measure_clk",
367 .parent_hws = (const struct clk_hw*[]) {
368 &gpu_cc_xo_div_clk_src.clkr.hw,
369 },
370 .num_parents = 1,
371 .flags = CLK_SET_RATE_PARENT,
372 .ops = &clk_branch2_ops,
373 },
374 },
375 };
376
377 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
378 .halt_reg = 0x7000,
379 .halt_check = BRANCH_HALT_VOTED,
380 .clkr = {
381 .enable_reg = 0x7000,
382 .enable_mask = BIT(0),
383 .hw.init = &(const struct clk_init_data) {
384 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
385 .ops = &clk_branch2_ops,
386 },
387 },
388 };
389
390 static struct clk_branch gpu_cc_hub_aon_clk = {
391 .halt_reg = 0x93e8,
392 .halt_check = BRANCH_HALT,
393 .clkr = {
394 .enable_reg = 0x93e8,
395 .enable_mask = BIT(0),
396 .hw.init = &(const struct clk_init_data) {
397 .name = "gpu_cc_hub_aon_clk",
398 .parent_hws = (const struct clk_hw*[]) {
399 &gpu_cc_hub_clk_src.clkr.hw,
400 },
401 .num_parents = 1,
402 .flags = CLK_SET_RATE_PARENT,
403 .ops = &clk_branch2_aon_ops,
404 },
405 },
406 };
407
408 static struct clk_branch gpu_cc_hub_cx_int_clk = {
409 .halt_reg = 0x9148,
410 .halt_check = BRANCH_HALT_VOTED,
411 .clkr = {
412 .enable_reg = 0x9148,
413 .enable_mask = BIT(0),
414 .hw.init = &(const struct clk_init_data) {
415 .name = "gpu_cc_hub_cx_int_clk",
416 .parent_hws = (const struct clk_hw*[]) {
417 &gpu_cc_hub_clk_src.clkr.hw,
418 },
419 .num_parents = 1,
420 .flags = CLK_SET_RATE_PARENT,
421 .ops = &clk_branch2_aon_ops,
422 },
423 },
424 };
425
426 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
427 .halt_reg = 0x9150,
428 .halt_check = BRANCH_HALT_VOTED,
429 .clkr = {
430 .enable_reg = 0x9150,
431 .enable_mask = BIT(0),
432 .hw.init = &(const struct clk_init_data) {
433 .name = "gpu_cc_memnoc_gfx_clk",
434 .ops = &clk_branch2_ops,
435 },
436 },
437 };
438
439 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
440 .halt_reg = 0x9288,
441 .halt_check = BRANCH_HALT,
442 .clkr = {
443 .enable_reg = 0x9288,
444 .enable_mask = BIT(0),
445 .hw.init = &(const struct clk_init_data) {
446 .name = "gpu_cc_mnd1x_0_gfx3d_clk",
447 .ops = &clk_branch2_ops,
448 },
449 },
450 };
451
452 static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
453 .halt_reg = 0x928c,
454 .halt_check = BRANCH_HALT,
455 .clkr = {
456 .enable_reg = 0x928c,
457 .enable_mask = BIT(0),
458 .hw.init = &(const struct clk_init_data) {
459 .name = "gpu_cc_mnd1x_1_gfx3d_clk",
460 .ops = &clk_branch2_ops,
461 },
462 },
463 };
464
465 static struct clk_branch gpu_cc_sleep_clk = {
466 .halt_reg = 0x9134,
467 .halt_check = BRANCH_HALT_VOTED,
468 .clkr = {
469 .enable_reg = 0x9134,
470 .enable_mask = BIT(0),
471 .hw.init = &(const struct clk_init_data) {
472 .name = "gpu_cc_sleep_clk",
473 .ops = &clk_branch2_ops,
474 },
475 },
476 };
477
478 static struct gdsc gpu_cc_cx_gdsc = {
479 .gdscr = 0x9108,
480 .gds_hw_ctrl = 0x953c,
481 .en_rest_wait_val = 0x2,
482 .en_few_wait_val = 0x2,
483 .clk_dis_wait_val = 0xf,
484 .pd = {
485 .name = "gpu_cc_cx_gdsc",
486 },
487 .pwrsts = PWRSTS_OFF_ON,
488 .flags = RETAIN_FF_ENABLE | VOTABLE,
489 };
490
491 static struct gdsc gpu_cc_gx_gdsc = {
492 .gdscr = 0x905c,
493 .clamp_io_ctrl = 0x9504,
494 .en_rest_wait_val = 0x2,
495 .en_few_wait_val = 0x2,
496 .clk_dis_wait_val = 0xf,
497 .pd = {
498 .name = "gpu_cc_gx_gdsc",
499 .power_on = gdsc_gx_do_nothing_enable,
500 },
501 .pwrsts = PWRSTS_OFF_ON,
502 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
503 };
504
505 static struct clk_regmap *gpu_cc_sm8550_clocks[] = {
506 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
507 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
508 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
509 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
510 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
511 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
512 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
513 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
514 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
515 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
516 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
517 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
518 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
519 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
520 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
521 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
522 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
523 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
524 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
525 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
526 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
527 };
528
529 static struct gdsc *gpu_cc_sm8550_gdscs[] = {
530 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
531 [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
532 };
533
534 static const struct qcom_reset_map gpu_cc_sm8550_resets[] = {
535 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
536 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
537 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
538 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
539 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
540 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
541 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
542 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
543 };
544
545 static const struct regmap_config gpu_cc_sm8550_regmap_config = {
546 .reg_bits = 32,
547 .reg_stride = 4,
548 .val_bits = 32,
549 .max_register = 0x9988,
550 .fast_io = true,
551 };
552
553 static const struct qcom_cc_desc gpu_cc_sm8550_desc = {
554 .config = &gpu_cc_sm8550_regmap_config,
555 .clks = gpu_cc_sm8550_clocks,
556 .num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks),
557 .resets = gpu_cc_sm8550_resets,
558 .num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets),
559 .gdscs = gpu_cc_sm8550_gdscs,
560 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs),
561 };
562
563 static const struct of_device_id gpu_cc_sm8550_match_table[] = {
564 { .compatible = "qcom,sm8550-gpucc" },
565 { }
566 };
567 MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table);
568
gpu_cc_sm8550_probe(struct platform_device * pdev)569 static int gpu_cc_sm8550_probe(struct platform_device *pdev)
570 {
571 struct regmap *regmap;
572
573 regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc);
574 if (IS_ERR(regmap))
575 return PTR_ERR(regmap);
576
577 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
578 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
579
580 /*
581 * Keep clocks always enabled:
582 * gpu_cc_cxo_aon_clk
583 * gpu_cc_demet_clk
584 */
585 regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
586 regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
587
588 return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
589 }
590
591 static struct platform_driver gpu_cc_sm8550_driver = {
592 .probe = gpu_cc_sm8550_probe,
593 .driver = {
594 .name = "gpu_cc-sm8550",
595 .of_match_table = gpu_cc_sm8550_match_table,
596 },
597 };
598
gpu_cc_sm8550_init(void)599 static int __init gpu_cc_sm8550_init(void)
600 {
601 return platform_driver_register(&gpu_cc_sm8550_driver);
602 }
603 subsys_initcall(gpu_cc_sm8550_init);
604
gpu_cc_sm8550_exit(void)605 static void __exit gpu_cc_sm8550_exit(void)
606 {
607 platform_driver_unregister(&gpu_cc_sm8550_driver);
608 }
609 module_exit(gpu_cc_sm8550_exit);
610
611 MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
612 MODULE_LICENSE("GPL");
613