1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
25 
26 #include <drm/drm_cache.h>
27 
28 #include "amdgpu.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "gmc_v11_0.h"
31 #include "umc_v8_10.h"
32 #include "athub/athub_3_0_0_sh_mask.h"
33 #include "athub/athub_3_0_0_offset.h"
34 #include "dcn/dcn_3_2_0_offset.h"
35 #include "dcn/dcn_3_2_0_sh_mask.h"
36 #include "oss/osssys_6_0_0_offset.h"
37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
38 #include "navi10_enum.h"
39 #include "soc15.h"
40 #include "soc15d.h"
41 #include "soc15_common.h"
42 #include "nbio_v4_3.h"
43 #include "gfxhub_v3_0.h"
44 #include "gfxhub_v3_0_3.h"
45 #include "mmhub_v3_0.h"
46 #include "mmhub_v3_0_1.h"
47 #include "mmhub_v3_0_2.h"
48 #include "athub_v3_0.h"
49 
50 
gmc_v11_0_ecc_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)51 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev,
52 					 struct amdgpu_irq_src *src,
53 					 unsigned int type,
54 					 enum amdgpu_interrupt_state state)
55 {
56 	return 0;
57 }
58 
59 static int
gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)60 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
61 				   struct amdgpu_irq_src *src, unsigned int type,
62 				   enum amdgpu_interrupt_state state)
63 {
64 	switch (state) {
65 	case AMDGPU_IRQ_STATE_DISABLE:
66 		/* MM HUB */
67 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
68 		/* GFX HUB */
69 		/* This works because this interrupt is only
70 		 * enabled at init/resume and disabled in
71 		 * fini/suspend, so the overall state doesn't
72 		 * change over the course of suspend/resume.
73 		 */
74 		if (!adev->in_s0ix)
75 			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
76 		break;
77 	case AMDGPU_IRQ_STATE_ENABLE:
78 		/* MM HUB */
79 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);
80 		/* GFX HUB */
81 		/* This works because this interrupt is only
82 		 * enabled at init/resume and disabled in
83 		 * fini/suspend, so the overall state doesn't
84 		 * change over the course of suspend/resume.
85 		 */
86 		if (!adev->in_s0ix)
87 			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);
88 		break;
89 	default:
90 		break;
91 	}
92 
93 	return 0;
94 }
95 
gmc_v11_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)96 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,
97 				       struct amdgpu_irq_src *source,
98 				       struct amdgpu_iv_entry *entry)
99 {
100 	uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ?
101 			       AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0);
102 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index];
103 	uint32_t status = 0;
104 	u64 addr;
105 
106 	addr = (u64)entry->src_data[0] << 12;
107 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
108 
109 	if (!amdgpu_sriov_vf(adev)) {
110 		/*
111 		 * Issue a dummy read to wait for the status register to
112 		 * be updated to avoid reading an incorrect value due to
113 		 * the new fast GRBM interface.
114 		 */
115 		if (entry->vmid_src == AMDGPU_GFXHUB(0))
116 			RREG32(hub->vm_l2_pro_fault_status);
117 
118 		status = RREG32(hub->vm_l2_pro_fault_status);
119 		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
120 	}
121 
122 	if (printk_ratelimit()) {
123 		struct amdgpu_task_info task_info;
124 
125 		memset(&task_info, 0, sizeof(struct amdgpu_task_info));
126 		amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
127 
128 		dev_err(adev->dev,
129 			"[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
130 			entry->vmid_src ? "mmhub" : "gfxhub",
131 			entry->src_id, entry->ring_id, entry->vmid,
132 			entry->pasid, task_info.process_name, task_info.tgid,
133 			task_info.task_name, task_info.pid);
134 		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
135 			addr, entry->client_id);
136 		if (!amdgpu_sriov_vf(adev))
137 			hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
138 	}
139 
140 	return 0;
141 }
142 
143 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = {
144 	.set = gmc_v11_0_vm_fault_interrupt_state,
145 	.process = gmc_v11_0_process_interrupt,
146 };
147 
148 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = {
149 	.set = gmc_v11_0_ecc_interrupt_state,
150 	.process = amdgpu_umc_process_ecc_irq,
151 };
152 
gmc_v11_0_set_irq_funcs(struct amdgpu_device * adev)153 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev)
154 {
155 	adev->gmc.vm_fault.num_types = 1;
156 	adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;
157 
158 	if (!amdgpu_sriov_vf(adev)) {
159 		adev->gmc.ecc_irq.num_types = 1;
160 		adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;
161 	}
162 }
163 
164 /**
165  * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore
166  *
167  * @adev: amdgpu_device pointer
168  * @vmhub: vmhub type
169  *
170  */
gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device * adev,uint32_t vmhub)171 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
172 				       uint32_t vmhub)
173 {
174 	return ((vmhub == AMDGPU_MMHUB0(0)) &&
175 		(!amdgpu_sriov_vf(adev)));
176 }
177 
gmc_v11_0_get_vmid_pasid_mapping_info(struct amdgpu_device * adev,uint8_t vmid,uint16_t * p_pasid)178 static bool gmc_v11_0_get_vmid_pasid_mapping_info(
179 					struct amdgpu_device *adev,
180 					uint8_t vmid, uint16_t *p_pasid)
181 {
182 	*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
183 
184 	return !!(*p_pasid);
185 }
186 
187 /*
188  * GART
189  * VMID 0 is the physical GPU addresses as used by the kernel.
190  * VMIDs 1-15 are used for userspace clients and are handled
191  * by the amdgpu vm/hsa code.
192  */
193 
gmc_v11_0_flush_vm_hub(struct amdgpu_device * adev,uint32_t vmid,unsigned int vmhub,uint32_t flush_type)194 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
195 				   unsigned int vmhub, uint32_t flush_type)
196 {
197 	bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub);
198 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
199 	u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
200 	u32 tmp;
201 	/* Use register 17 for GART */
202 	const unsigned int eng = 17;
203 	unsigned int i;
204 	unsigned char hub_ip = 0;
205 
206 	hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ?
207 		   GC_HWIP : MMHUB_HWIP;
208 
209 	spin_lock(&adev->gmc.invalidate_lock);
210 	/*
211 	 * It may lose gpuvm invalidate acknowldege state across power-gating
212 	 * off cycle, add semaphore acquire before invalidation and semaphore
213 	 * release after invalidation to avoid entering power gated state
214 	 * to WA the Issue
215 	 */
216 
217 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
218 	if (use_semaphore) {
219 		for (i = 0; i < adev->usec_timeout; i++) {
220 			/* a read return value of 1 means semaphore acuqire */
221 			tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
222 					    hub->eng_distance * eng, hub_ip);
223 			if (tmp & 0x1)
224 				break;
225 			udelay(1);
226 		}
227 
228 		if (i >= adev->usec_timeout)
229 			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
230 	}
231 
232 	WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip);
233 
234 	/* Wait for ACK with a delay.*/
235 	for (i = 0; i < adev->usec_timeout; i++) {
236 		tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
237 				    hub->eng_distance * eng, hub_ip);
238 		tmp &= 1 << vmid;
239 		if (tmp)
240 			break;
241 
242 		udelay(1);
243 	}
244 
245 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
246 	if (use_semaphore)
247 		/*
248 		 * add semaphore release after invalidation,
249 		 * write with 0 means semaphore release
250 		 */
251 		WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
252 			      hub->eng_distance * eng, 0, hub_ip);
253 
254 	/* Issue additional private vm invalidation to MMHUB */
255 	if ((vmhub != AMDGPU_GFXHUB(0)) &&
256 	    (hub->vm_l2_bank_select_reserved_cid2) &&
257 		!amdgpu_sriov_vf(adev)) {
258 		inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
259 		/* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
260 		inv_req |= (1 << 25);
261 		/* Issue private invalidation */
262 		WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
263 		/* Read back to ensure invalidation is done*/
264 		RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
265 	}
266 
267 	spin_unlock(&adev->gmc.invalidate_lock);
268 
269 	if (i < adev->usec_timeout)
270 		return;
271 
272 	DRM_ERROR("Timeout waiting for VM flush ACK!\n");
273 }
274 
275 /**
276  * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
277  *
278  * @adev: amdgpu_device pointer
279  * @vmid: vm instance to flush
280  * @vmhub: which hub to flush
281  * @flush_type: the flush type
282  *
283  * Flush the TLB for the requested page table.
284  */
gmc_v11_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)285 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
286 					uint32_t vmhub, uint32_t flush_type)
287 {
288 	if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron)
289 		return;
290 
291 	/* flush hdp cache */
292 	adev->hdp.funcs->flush_hdp(adev, NULL);
293 
294 	/* For SRIOV run time, driver shouldn't access the register through MMIO
295 	 * Directly use kiq to do the vm invalidation instead
296 	 */
297 	if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
298 	    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
299 		struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
300 		const unsigned int eng = 17;
301 		u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
302 		u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
303 		u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
304 
305 		amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
306 				1 << vmid);
307 		return;
308 	}
309 
310 	mutex_lock(&adev->mman.gtt_window_lock);
311 	gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
312 	mutex_unlock(&adev->mman.gtt_window_lock);
313 }
314 
315 /**
316  * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid
317  *
318  * @adev: amdgpu_device pointer
319  * @pasid: pasid to be flush
320  * @flush_type: the flush type
321  * @all_hub: flush all hubs
322  * @inst: is used to select which instance of KIQ to use for the invalidation
323  *
324  * Flush the TLB for the requested pasid.
325  */
gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub,uint32_t inst)326 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
327 					uint16_t pasid, uint32_t flush_type,
328 					bool all_hub, uint32_t inst)
329 {
330 	int vmid, i;
331 	signed long r;
332 	uint32_t seq;
333 	uint16_t queried_pasid;
334 	bool ret;
335 	struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring;
336 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
337 
338 	if (amdgpu_emu_mode == 0 && ring->sched.ready) {
339 		spin_lock(&adev->gfx.kiq[0].ring_lock);
340 		/* 2 dwords flush + 8 dwords fence */
341 		amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
342 		kiq->pmf->kiq_invalidate_tlbs(ring,
343 					pasid, flush_type, all_hub);
344 		r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
345 		if (r) {
346 			amdgpu_ring_undo(ring);
347 			spin_unlock(&adev->gfx.kiq[0].ring_lock);
348 			return -ETIME;
349 		}
350 
351 		amdgpu_ring_commit(ring);
352 		spin_unlock(&adev->gfx.kiq[0].ring_lock);
353 		r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
354 		if (r < 1) {
355 			dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
356 			return -ETIME;
357 		}
358 
359 		return 0;
360 	}
361 
362 	for (vmid = 1; vmid < 16; vmid++) {
363 
364 		ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
365 				&queried_pasid);
366 		if (ret	&& queried_pasid == pasid) {
367 			if (all_hub) {
368 				for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
369 					gmc_v11_0_flush_gpu_tlb(adev, vmid,
370 							i, flush_type);
371 			} else {
372 				gmc_v11_0_flush_gpu_tlb(adev, vmid,
373 						AMDGPU_GFXHUB(0), flush_type);
374 			}
375 		}
376 	}
377 
378 	return 0;
379 }
380 
gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)381 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
382 					     unsigned int vmid, uint64_t pd_addr)
383 {
384 	bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
385 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
386 	uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
387 	unsigned int eng = ring->vm_inv_eng;
388 
389 	/*
390 	 * It may lose gpuvm invalidate acknowldege state across power-gating
391 	 * off cycle, add semaphore acquire before invalidation and semaphore
392 	 * release after invalidation to avoid entering power gated state
393 	 * to WA the Issue
394 	 */
395 
396 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
397 	if (use_semaphore)
398 		/* a read return value of 1 means semaphore acuqire */
399 		amdgpu_ring_emit_reg_wait(ring,
400 					  hub->vm_inv_eng0_sem +
401 					  hub->eng_distance * eng, 0x1, 0x1);
402 
403 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
404 			      (hub->ctx_addr_distance * vmid),
405 			      lower_32_bits(pd_addr));
406 
407 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
408 			      (hub->ctx_addr_distance * vmid),
409 			      upper_32_bits(pd_addr));
410 
411 	amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
412 					    hub->eng_distance * eng,
413 					    hub->vm_inv_eng0_ack +
414 					    hub->eng_distance * eng,
415 					    req, 1 << vmid);
416 
417 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
418 	if (use_semaphore)
419 		/*
420 		 * add semaphore release after invalidation,
421 		 * write with 0 means semaphore release
422 		 */
423 		amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
424 				      hub->eng_distance * eng, 0);
425 
426 	return pd_addr;
427 }
428 
gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned int vmid,unsigned int pasid)429 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
430 					 unsigned int pasid)
431 {
432 	struct amdgpu_device *adev = ring->adev;
433 	uint32_t reg;
434 
435 	/* MES fw manages IH_VMID_x_LUT updating */
436 	if (ring->is_mes_queue)
437 		return;
438 
439 	if (ring->vm_hub == AMDGPU_GFXHUB(0))
440 		reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
441 	else
442 		reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
443 
444 	amdgpu_ring_emit_wreg(ring, reg, pasid);
445 }
446 
447 /*
448  * PTE format:
449  * 63:59 reserved
450  * 58:57 reserved
451  * 56 F
452  * 55 L
453  * 54 reserved
454  * 53:52 SW
455  * 51 T
456  * 50:48 mtype
457  * 47:12 4k physical page base address
458  * 11:7 fragment
459  * 6 write
460  * 5 read
461  * 4 exe
462  * 3 Z
463  * 2 snooped
464  * 1 system
465  * 0 valid
466  *
467  * PDE format:
468  * 63:59 block fragment size
469  * 58:55 reserved
470  * 54 P
471  * 53:48 reserved
472  * 47:6 physical base address of PD or PTE
473  * 5:3 reserved
474  * 2 C
475  * 1 system
476  * 0 valid
477  */
478 
gmc_v11_0_map_mtype(struct amdgpu_device * adev,uint32_t flags)479 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
480 {
481 	switch (flags) {
482 	case AMDGPU_VM_MTYPE_DEFAULT:
483 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
484 	case AMDGPU_VM_MTYPE_NC:
485 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
486 	case AMDGPU_VM_MTYPE_WC:
487 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
488 	case AMDGPU_VM_MTYPE_CC:
489 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
490 	case AMDGPU_VM_MTYPE_UC:
491 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
492 	default:
493 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
494 	}
495 }
496 
gmc_v11_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)497 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,
498 				 uint64_t *addr, uint64_t *flags)
499 {
500 	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
501 		*addr = adev->vm_manager.vram_base_offset + *addr -
502 			adev->gmc.vram_start;
503 	BUG_ON(*addr & 0xFFFF00000000003FULL);
504 
505 	if (!adev->gmc.translate_further)
506 		return;
507 
508 	if (level == AMDGPU_VM_PDB1) {
509 		/* Set the block fragment size */
510 		if (!(*flags & AMDGPU_PDE_PTE))
511 			*flags |= AMDGPU_PDE_BFS(0x9);
512 
513 	} else if (level == AMDGPU_VM_PDB0) {
514 		if (*flags & AMDGPU_PDE_PTE)
515 			*flags &= ~AMDGPU_PDE_PTE;
516 		else
517 			*flags |= AMDGPU_PTE_TF;
518 	}
519 }
520 
gmc_v11_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)521 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
522 				 struct amdgpu_bo_va_mapping *mapping,
523 				 uint64_t *flags)
524 {
525 	struct amdgpu_bo *bo = mapping->bo_va->base.bo;
526 
527 	*flags &= ~AMDGPU_PTE_EXECUTABLE;
528 	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
529 
530 	*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
531 	*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
532 
533 	*flags &= ~AMDGPU_PTE_NOALLOC;
534 	*flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
535 
536 	if (mapping->flags & AMDGPU_PTE_PRT) {
537 		*flags |= AMDGPU_PTE_PRT;
538 		*flags |= AMDGPU_PTE_SNOOPED;
539 		*flags |= AMDGPU_PTE_LOG;
540 		*flags |= AMDGPU_PTE_SYSTEM;
541 		*flags &= ~AMDGPU_PTE_VALID;
542 	}
543 
544 	if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
545 			       AMDGPU_GEM_CREATE_UNCACHED))
546 		*flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
547 			 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
548 }
549 
gmc_v11_0_get_vbios_fb_size(struct amdgpu_device * adev)550 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
551 {
552 	u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);
553 	unsigned int size;
554 
555 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
556 		size = AMDGPU_VBIOS_VGA_ALLOCATION;
557 	} else {
558 		u32 viewport;
559 		u32 pitch;
560 
561 		viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
562 		pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);
563 		size = (REG_GET_FIELD(viewport,
564 					HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
565 				REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
566 				4);
567 	}
568 
569 	return size;
570 }
571 
572 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
573 	.flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb,
574 	.flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,
575 	.emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,
576 	.emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,
577 	.map_mtype = gmc_v11_0_map_mtype,
578 	.get_vm_pde = gmc_v11_0_get_vm_pde,
579 	.get_vm_pte = gmc_v11_0_get_vm_pte,
580 	.get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,
581 };
582 
gmc_v11_0_set_gmc_funcs(struct amdgpu_device * adev)583 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev)
584 {
585 	adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;
586 }
587 
gmc_v11_0_set_umc_funcs(struct amdgpu_device * adev)588 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
589 {
590 	switch (adev->ip_versions[UMC_HWIP][0]) {
591 	case IP_VERSION(8, 10, 0):
592 		adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
593 		adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
594 		adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
595 		adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
596 		adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;
597 		if (adev->umc.node_inst_num == 4)
598 			adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0];
599 		else
600 			adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0];
601 		adev->umc.ras = &umc_v8_10_ras;
602 		break;
603 	case IP_VERSION(8, 11, 0):
604 		break;
605 	default:
606 		break;
607 	}
608 }
609 
610 
gmc_v11_0_set_mmhub_funcs(struct amdgpu_device * adev)611 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
612 {
613 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
614 	case IP_VERSION(3, 0, 1):
615 		adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
616 		break;
617 	case IP_VERSION(3, 0, 2):
618 		adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
619 		break;
620 	default:
621 		adev->mmhub.funcs = &mmhub_v3_0_funcs;
622 		break;
623 	}
624 }
625 
gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device * adev)626 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
627 {
628 	switch (adev->ip_versions[GC_HWIP][0]) {
629 	case IP_VERSION(11, 0, 3):
630 		adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs;
631 		break;
632 	default:
633 		adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
634 		break;
635 	}
636 }
637 
gmc_v11_0_early_init(void * handle)638 static int gmc_v11_0_early_init(void *handle)
639 {
640 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
641 
642 	gmc_v11_0_set_gfxhub_funcs(adev);
643 	gmc_v11_0_set_mmhub_funcs(adev);
644 	gmc_v11_0_set_gmc_funcs(adev);
645 	gmc_v11_0_set_irq_funcs(adev);
646 	gmc_v11_0_set_umc_funcs(adev);
647 
648 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
649 	adev->gmc.shared_aperture_end =
650 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
651 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;
652 	adev->gmc.private_aperture_end =
653 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;
654 	adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
655 
656 	return 0;
657 }
658 
gmc_v11_0_late_init(void * handle)659 static int gmc_v11_0_late_init(void *handle)
660 {
661 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
662 	int r;
663 
664 	r = amdgpu_gmc_allocate_vm_inv_eng(adev);
665 	if (r)
666 		return r;
667 
668 	r = amdgpu_gmc_ras_late_init(adev);
669 	if (r)
670 		return r;
671 
672 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
673 }
674 
gmc_v11_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)675 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
676 					struct amdgpu_gmc *mc)
677 {
678 	u64 base = 0;
679 
680 	base = adev->mmhub.funcs->get_fb_location(adev);
681 
682 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
683 	amdgpu_gmc_gart_location(adev, mc);
684 	amdgpu_gmc_agp_location(adev, mc);
685 
686 	/* base offset of vram pages */
687 	if (amdgpu_sriov_vf(adev))
688 		adev->vm_manager.vram_base_offset = 0;
689 	else
690 		adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
691 }
692 
693 /**
694  * gmc_v11_0_mc_init - initialize the memory controller driver params
695  *
696  * @adev: amdgpu_device pointer
697  *
698  * Look up the amount of vram, vram width, and decide how to place
699  * vram and gart within the GPU's physical address space.
700  * Returns 0 for success.
701  */
gmc_v11_0_mc_init(struct amdgpu_device * adev)702 static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
703 {
704 	int r;
705 
706 	/* size in MB on si */
707 	adev->gmc.mc_vram_size =
708 		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
709 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
710 
711 	if (!(adev->flags & AMD_IS_APU)) {
712 		r = amdgpu_device_resize_fb_bar(adev);
713 		if (r)
714 			return r;
715 	}
716 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
717 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
718 
719 #ifdef CONFIG_X86_64
720 	if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
721 		adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
722 		adev->gmc.aper_size = adev->gmc.real_vram_size;
723 	}
724 #endif
725 	/* In case the PCI BAR is larger than the actual amount of vram */
726 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
727 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
728 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
729 
730 	/* set the gart size */
731 	if (amdgpu_gart_size == -1)
732 		adev->gmc.gart_size = 512ULL << 20;
733 	else
734 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
735 
736 	gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
737 
738 	return 0;
739 }
740 
gmc_v11_0_gart_init(struct amdgpu_device * adev)741 static int gmc_v11_0_gart_init(struct amdgpu_device *adev)
742 {
743 	int r;
744 
745 	if (adev->gart.bo) {
746 		WARN(1, "PCIE GART already initialized\n");
747 		return 0;
748 	}
749 
750 	/* Initialize common gart structure */
751 	r = amdgpu_gart_init(adev);
752 	if (r)
753 		return r;
754 
755 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
756 	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
757 				 AMDGPU_PTE_EXECUTABLE;
758 
759 	return amdgpu_gart_table_vram_alloc(adev);
760 }
761 
gmc_v11_0_sw_init(void * handle)762 static int gmc_v11_0_sw_init(void *handle)
763 {
764 	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
765 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
766 
767 	adev->mmhub.funcs->init(adev);
768 
769 	spin_lock_init(&adev->gmc.invalidate_lock);
770 
771 	r = amdgpu_atomfirmware_get_vram_info(adev,
772 					      &vram_width, &vram_type, &vram_vendor);
773 	adev->gmc.vram_width = vram_width;
774 
775 	adev->gmc.vram_type = vram_type;
776 	adev->gmc.vram_vendor = vram_vendor;
777 
778 	switch (adev->ip_versions[GC_HWIP][0]) {
779 	case IP_VERSION(11, 0, 0):
780 	case IP_VERSION(11, 0, 1):
781 	case IP_VERSION(11, 0, 2):
782 	case IP_VERSION(11, 0, 3):
783 	case IP_VERSION(11, 0, 4):
784 		set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
785 		set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
786 		/*
787 		 * To fulfill 4-level page support,
788 		 * vm size is 256TB (48bit), maximum size,
789 		 * block size 512 (9bit)
790 		 */
791 		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
792 		break;
793 	default:
794 		break;
795 	}
796 
797 	/* This interrupt is VMC page fault.*/
798 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC,
799 			      VMC_1_0__SRCID__VM_FAULT,
800 			      &adev->gmc.vm_fault);
801 
802 	if (r)
803 		return r;
804 
805 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
806 			      UTCL2_1_0__SRCID__FAULT,
807 			      &adev->gmc.vm_fault);
808 	if (r)
809 		return r;
810 
811 	if (!amdgpu_sriov_vf(adev)) {
812 		/* interrupt sent to DF. */
813 		r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
814 				      &adev->gmc.ecc_irq);
815 		if (r)
816 			return r;
817 	}
818 
819 	/*
820 	 * Set the internal MC address mask This is the max address of the GPU's
821 	 * internal address space.
822 	 */
823 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
824 
825 	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
826 	if (r) {
827 		dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
828 		return r;
829 	}
830 
831 	adev->need_swiotlb = drm_need_swiotlb(44);
832 
833 	r = gmc_v11_0_mc_init(adev);
834 	if (r)
835 		return r;
836 
837 	amdgpu_gmc_get_vbios_allocations(adev);
838 
839 	/* Memory manager */
840 	r = amdgpu_bo_init(adev);
841 	if (r)
842 		return r;
843 
844 	r = gmc_v11_0_gart_init(adev);
845 	if (r)
846 		return r;
847 
848 	/*
849 	 * number of VMs
850 	 * VMID 0 is reserved for System
851 	 * amdgpu graphics/compute will use VMIDs 1-7
852 	 * amdkfd will use VMIDs 8-15
853 	 */
854 	adev->vm_manager.first_kfd_vmid = 8;
855 
856 	amdgpu_vm_manager_init(adev);
857 
858 	r = amdgpu_gmc_ras_sw_init(adev);
859 	if (r)
860 		return r;
861 
862 	return 0;
863 }
864 
865 /**
866  * gmc_v11_0_gart_fini - vm fini callback
867  *
868  * @adev: amdgpu_device pointer
869  *
870  * Tears down the driver GART/VM setup (CIK).
871  */
gmc_v11_0_gart_fini(struct amdgpu_device * adev)872 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev)
873 {
874 	amdgpu_gart_table_vram_free(adev);
875 }
876 
gmc_v11_0_sw_fini(void * handle)877 static int gmc_v11_0_sw_fini(void *handle)
878 {
879 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
880 
881 	amdgpu_vm_manager_fini(adev);
882 	gmc_v11_0_gart_fini(adev);
883 	amdgpu_gem_force_release(adev);
884 	amdgpu_bo_fini(adev);
885 
886 	return 0;
887 }
888 
gmc_v11_0_init_golden_registers(struct amdgpu_device * adev)889 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev)
890 {
891 	if (amdgpu_sriov_vf(adev)) {
892 		struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
893 
894 		WREG32(hub->vm_contexts_disable, 0);
895 		return;
896 	}
897 }
898 
899 /**
900  * gmc_v11_0_gart_enable - gart enable
901  *
902  * @adev: amdgpu_device pointer
903  */
gmc_v11_0_gart_enable(struct amdgpu_device * adev)904 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
905 {
906 	int r;
907 	bool value;
908 
909 	if (adev->gart.bo == NULL) {
910 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
911 		return -EINVAL;
912 	}
913 
914 	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
915 
916 	r = adev->mmhub.funcs->gart_enable(adev);
917 	if (r)
918 		return r;
919 
920 	/* Flush HDP after it is initialized */
921 	adev->hdp.funcs->flush_hdp(adev, NULL);
922 
923 	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
924 		false : true;
925 
926 	adev->mmhub.funcs->set_fault_enable_default(adev, value);
927 	gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
928 
929 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
930 		 (unsigned int)(adev->gmc.gart_size >> 20),
931 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
932 
933 	return 0;
934 }
935 
gmc_v11_0_hw_init(void * handle)936 static int gmc_v11_0_hw_init(void *handle)
937 {
938 	int r;
939 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
940 
941 	/* The sequence of these two function calls matters.*/
942 	gmc_v11_0_init_golden_registers(adev);
943 
944 	r = gmc_v11_0_gart_enable(adev);
945 	if (r)
946 		return r;
947 
948 	if (adev->umc.funcs && adev->umc.funcs->init_registers)
949 		adev->umc.funcs->init_registers(adev);
950 
951 	return 0;
952 }
953 
954 /**
955  * gmc_v11_0_gart_disable - gart disable
956  *
957  * @adev: amdgpu_device pointer
958  *
959  * This disables all VM page table.
960  */
gmc_v11_0_gart_disable(struct amdgpu_device * adev)961 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev)
962 {
963 	adev->mmhub.funcs->gart_disable(adev);
964 }
965 
gmc_v11_0_hw_fini(void * handle)966 static int gmc_v11_0_hw_fini(void *handle)
967 {
968 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
969 
970 	if (amdgpu_sriov_vf(adev)) {
971 		/* full access mode, so don't touch any GMC register */
972 		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
973 		return 0;
974 	}
975 
976 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
977 
978 	if (adev->gmc.ecc_irq.funcs &&
979 		amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
980 		amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
981 
982 	gmc_v11_0_gart_disable(adev);
983 
984 	return 0;
985 }
986 
gmc_v11_0_suspend(void * handle)987 static int gmc_v11_0_suspend(void *handle)
988 {
989 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
990 
991 	gmc_v11_0_hw_fini(adev);
992 
993 	return 0;
994 }
995 
gmc_v11_0_resume(void * handle)996 static int gmc_v11_0_resume(void *handle)
997 {
998 	int r;
999 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1000 
1001 	r = gmc_v11_0_hw_init(adev);
1002 	if (r)
1003 		return r;
1004 
1005 	amdgpu_vmid_reset_all(adev);
1006 
1007 	return 0;
1008 }
1009 
gmc_v11_0_is_idle(void * handle)1010 static bool gmc_v11_0_is_idle(void *handle)
1011 {
1012 	/* MC is always ready in GMC v11.*/
1013 	return true;
1014 }
1015 
gmc_v11_0_wait_for_idle(void * handle)1016 static int gmc_v11_0_wait_for_idle(void *handle)
1017 {
1018 	/* There is no need to wait for MC idle in GMC v11.*/
1019 	return 0;
1020 }
1021 
gmc_v11_0_soft_reset(void * handle)1022 static int gmc_v11_0_soft_reset(void *handle)
1023 {
1024 	return 0;
1025 }
1026 
gmc_v11_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1027 static int gmc_v11_0_set_clockgating_state(void *handle,
1028 					   enum amd_clockgating_state state)
1029 {
1030 	int r;
1031 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032 
1033 	r = adev->mmhub.funcs->set_clockgating(adev, state);
1034 	if (r)
1035 		return r;
1036 
1037 	return athub_v3_0_set_clockgating(adev, state);
1038 }
1039 
gmc_v11_0_get_clockgating_state(void * handle,u64 * flags)1040 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
1041 {
1042 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1043 
1044 	adev->mmhub.funcs->get_clockgating(adev, flags);
1045 
1046 	athub_v3_0_get_clockgating(adev, flags);
1047 }
1048 
gmc_v11_0_set_powergating_state(void * handle,enum amd_powergating_state state)1049 static int gmc_v11_0_set_powergating_state(void *handle,
1050 					   enum amd_powergating_state state)
1051 {
1052 	return 0;
1053 }
1054 
1055 const struct amd_ip_funcs gmc_v11_0_ip_funcs = {
1056 	.name = "gmc_v11_0",
1057 	.early_init = gmc_v11_0_early_init,
1058 	.sw_init = gmc_v11_0_sw_init,
1059 	.hw_init = gmc_v11_0_hw_init,
1060 	.late_init = gmc_v11_0_late_init,
1061 	.sw_fini = gmc_v11_0_sw_fini,
1062 	.hw_fini = gmc_v11_0_hw_fini,
1063 	.suspend = gmc_v11_0_suspend,
1064 	.resume = gmc_v11_0_resume,
1065 	.is_idle = gmc_v11_0_is_idle,
1066 	.wait_for_idle = gmc_v11_0_wait_for_idle,
1067 	.soft_reset = gmc_v11_0_soft_reset,
1068 	.set_clockgating_state = gmc_v11_0_set_clockgating_state,
1069 	.set_powergating_state = gmc_v11_0_set_powergating_state,
1070 	.get_clockgating_state = gmc_v11_0_get_clockgating_state,
1071 };
1072 
1073 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = {
1074 	.type = AMD_IP_BLOCK_TYPE_GMC,
1075 	.major = 11,
1076 	.minor = 0,
1077 	.rev = 0,
1078 	.funcs = &gmc_v11_0_ip_funcs,
1079 };
1080