1 // SPDX-License-Identifier: GPL-2.0
2 /* Ethernet device driver for Cortina Systems Gemini SoC
3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
4 * Net Engine and Gigabit Ethernet MAC (GMAC)
5 * This hardware contains a TCP Offload Engine (TOE) but currently the
6 * driver does not make use of it.
7 *
8 * Authors:
9 * Linus Walleij <linus.walleij@linaro.org>
10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
12 * Paulius Zaleckas <paulius.zaleckas@gmail.com>
13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
14 * Gary Chen & Ch Hsu Storlink Semiconductor
15 */
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/cache.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26 #include <linux/clk.h>
27 #include <linux/of.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/of_platform.h>
31 #include <linux/etherdevice.h>
32 #include <linux/if_vlan.h>
33 #include <linux/skbuff.h>
34 #include <linux/phy.h>
35 #include <linux/crc32.h>
36 #include <linux/ethtool.h>
37 #include <linux/tcp.h>
38 #include <linux/u64_stats_sync.h>
39
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/ipv6.h>
43
44 #include "gemini.h"
45
46 #define DRV_NAME "gmac-gemini"
47
48 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
49 static int debug = -1;
50 module_param(debug, int, 0);
51 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
52
53 #define HSIZE_8 0x00
54 #define HSIZE_16 0x01
55 #define HSIZE_32 0x02
56
57 #define HBURST_SINGLE 0x00
58 #define HBURST_INCR 0x01
59 #define HBURST_INCR4 0x02
60 #define HBURST_INCR8 0x03
61
62 #define HPROT_DATA_CACHE BIT(0)
63 #define HPROT_PRIVILIGED BIT(1)
64 #define HPROT_BUFFERABLE BIT(2)
65 #define HPROT_CACHABLE BIT(3)
66
67 #define DEFAULT_RX_COALESCE_NSECS 0
68 #define DEFAULT_GMAC_RXQ_ORDER 9
69 #define DEFAULT_GMAC_TXQ_ORDER 8
70 #define DEFAULT_RX_BUF_ORDER 11
71 #define TX_MAX_FRAGS 16
72 #define TX_QUEUE_NUM 1 /* max: 6 */
73 #define RX_MAX_ALLOC_ORDER 2
74
75 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
76 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
77 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
78 GMAC0_SWTQ00_FIN_INT_BIT)
79 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
80
81 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
82 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
83 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
84
85 /**
86 * struct gmac_queue_page - page buffer per-page info
87 * @page: the page struct
88 * @mapping: the dma address handle
89 */
90 struct gmac_queue_page {
91 struct page *page;
92 dma_addr_t mapping;
93 };
94
95 struct gmac_txq {
96 struct gmac_txdesc *ring;
97 struct sk_buff **skb;
98 unsigned int cptr;
99 unsigned int noirq_packets;
100 };
101
102 struct gemini_ethernet;
103
104 struct gemini_ethernet_port {
105 u8 id; /* 0 or 1 */
106
107 struct gemini_ethernet *geth;
108 struct net_device *netdev;
109 struct device *dev;
110 void __iomem *dma_base;
111 void __iomem *gmac_base;
112 struct clk *pclk;
113 struct reset_control *reset;
114 int irq;
115 __le32 mac_addr[3];
116
117 void __iomem *rxq_rwptr;
118 struct gmac_rxdesc *rxq_ring;
119 unsigned int rxq_order;
120
121 struct napi_struct napi;
122 struct hrtimer rx_coalesce_timer;
123 unsigned int rx_coalesce_nsecs;
124 unsigned int freeq_refill;
125 struct gmac_txq txq[TX_QUEUE_NUM];
126 unsigned int txq_order;
127 unsigned int irq_every_tx_packets;
128
129 dma_addr_t rxq_dma_base;
130 dma_addr_t txq_dma_base;
131
132 unsigned int msg_enable;
133 spinlock_t config_lock; /* Locks config register */
134
135 struct u64_stats_sync tx_stats_syncp;
136 struct u64_stats_sync rx_stats_syncp;
137 struct u64_stats_sync ir_stats_syncp;
138
139 struct rtnl_link_stats64 stats;
140 u64 hw_stats[RX_STATS_NUM];
141 u64 rx_stats[RX_STATUS_NUM];
142 u64 rx_csum_stats[RX_CHKSUM_NUM];
143 u64 rx_napi_exits;
144 u64 tx_frag_stats[TX_MAX_FRAGS];
145 u64 tx_frags_linearized;
146 u64 tx_hw_csummed;
147 };
148
149 struct gemini_ethernet {
150 struct device *dev;
151 void __iomem *base;
152 struct gemini_ethernet_port *port0;
153 struct gemini_ethernet_port *port1;
154 bool initialized;
155
156 spinlock_t irq_lock; /* Locks IRQ-related registers */
157 unsigned int freeq_order;
158 unsigned int freeq_frag_order;
159 struct gmac_rxdesc *freeq_ring;
160 dma_addr_t freeq_dma_base;
161 struct gmac_queue_page *freeq_pages;
162 unsigned int num_freeq_pages;
163 spinlock_t freeq_lock; /* Locks queue from reentrance */
164 };
165
166 #define GMAC_STATS_NUM ( \
167 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
168 TX_MAX_FRAGS + 2)
169
170 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
171 "GMAC_IN_DISCARDS",
172 "GMAC_IN_ERRORS",
173 "GMAC_IN_MCAST",
174 "GMAC_IN_BCAST",
175 "GMAC_IN_MAC1",
176 "GMAC_IN_MAC2",
177 "RX_STATUS_GOOD_FRAME",
178 "RX_STATUS_TOO_LONG_GOOD_CRC",
179 "RX_STATUS_RUNT_FRAME",
180 "RX_STATUS_SFD_NOT_FOUND",
181 "RX_STATUS_CRC_ERROR",
182 "RX_STATUS_TOO_LONG_BAD_CRC",
183 "RX_STATUS_ALIGNMENT_ERROR",
184 "RX_STATUS_TOO_LONG_BAD_ALIGN",
185 "RX_STATUS_RX_ERR",
186 "RX_STATUS_DA_FILTERED",
187 "RX_STATUS_BUFFER_FULL",
188 "RX_STATUS_11",
189 "RX_STATUS_12",
190 "RX_STATUS_13",
191 "RX_STATUS_14",
192 "RX_STATUS_15",
193 "RX_CHKSUM_IP_UDP_TCP_OK",
194 "RX_CHKSUM_IP_OK_ONLY",
195 "RX_CHKSUM_NONE",
196 "RX_CHKSUM_3",
197 "RX_CHKSUM_IP_ERR_UNKNOWN",
198 "RX_CHKSUM_IP_ERR",
199 "RX_CHKSUM_TCP_UDP_ERR",
200 "RX_CHKSUM_7",
201 "RX_NAPI_EXITS",
202 "TX_FRAGS[1]",
203 "TX_FRAGS[2]",
204 "TX_FRAGS[3]",
205 "TX_FRAGS[4]",
206 "TX_FRAGS[5]",
207 "TX_FRAGS[6]",
208 "TX_FRAGS[7]",
209 "TX_FRAGS[8]",
210 "TX_FRAGS[9]",
211 "TX_FRAGS[10]",
212 "TX_FRAGS[11]",
213 "TX_FRAGS[12]",
214 "TX_FRAGS[13]",
215 "TX_FRAGS[14]",
216 "TX_FRAGS[15]",
217 "TX_FRAGS[16+]",
218 "TX_FRAGS_LINEARIZED",
219 "TX_HW_CSUMMED",
220 };
221
222 static void gmac_dump_dma_state(struct net_device *netdev);
223
gmac_update_config0_reg(struct net_device * netdev,u32 val,u32 vmask)224 static void gmac_update_config0_reg(struct net_device *netdev,
225 u32 val, u32 vmask)
226 {
227 struct gemini_ethernet_port *port = netdev_priv(netdev);
228 unsigned long flags;
229 u32 reg;
230
231 spin_lock_irqsave(&port->config_lock, flags);
232
233 reg = readl(port->gmac_base + GMAC_CONFIG0);
234 reg = (reg & ~vmask) | val;
235 writel(reg, port->gmac_base + GMAC_CONFIG0);
236
237 spin_unlock_irqrestore(&port->config_lock, flags);
238 }
239
gmac_enable_tx_rx(struct net_device * netdev)240 static void gmac_enable_tx_rx(struct net_device *netdev)
241 {
242 struct gemini_ethernet_port *port = netdev_priv(netdev);
243 unsigned long flags;
244 u32 reg;
245
246 spin_lock_irqsave(&port->config_lock, flags);
247
248 reg = readl(port->gmac_base + GMAC_CONFIG0);
249 reg &= ~CONFIG0_TX_RX_DISABLE;
250 writel(reg, port->gmac_base + GMAC_CONFIG0);
251
252 spin_unlock_irqrestore(&port->config_lock, flags);
253 }
254
gmac_disable_tx_rx(struct net_device * netdev)255 static void gmac_disable_tx_rx(struct net_device *netdev)
256 {
257 struct gemini_ethernet_port *port = netdev_priv(netdev);
258 unsigned long flags;
259 u32 val;
260
261 spin_lock_irqsave(&port->config_lock, flags);
262
263 val = readl(port->gmac_base + GMAC_CONFIG0);
264 val |= CONFIG0_TX_RX_DISABLE;
265 writel(val, port->gmac_base + GMAC_CONFIG0);
266
267 spin_unlock_irqrestore(&port->config_lock, flags);
268
269 mdelay(10); /* let GMAC consume packet */
270 }
271
gmac_set_flow_control(struct net_device * netdev,bool tx,bool rx)272 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
273 {
274 struct gemini_ethernet_port *port = netdev_priv(netdev);
275 unsigned long flags;
276 u32 val;
277
278 spin_lock_irqsave(&port->config_lock, flags);
279
280 val = readl(port->gmac_base + GMAC_CONFIG0);
281 val &= ~CONFIG0_FLOW_CTL;
282 if (tx)
283 val |= CONFIG0_FLOW_TX;
284 if (rx)
285 val |= CONFIG0_FLOW_RX;
286 writel(val, port->gmac_base + GMAC_CONFIG0);
287
288 spin_unlock_irqrestore(&port->config_lock, flags);
289 }
290
gmac_speed_set(struct net_device * netdev)291 static void gmac_speed_set(struct net_device *netdev)
292 {
293 struct gemini_ethernet_port *port = netdev_priv(netdev);
294 struct phy_device *phydev = netdev->phydev;
295 union gmac_status status, old_status;
296 int pause_tx = 0;
297 int pause_rx = 0;
298
299 status.bits32 = readl(port->gmac_base + GMAC_STATUS);
300 old_status.bits32 = status.bits32;
301 status.bits.link = phydev->link;
302 status.bits.duplex = phydev->duplex;
303
304 switch (phydev->speed) {
305 case 1000:
306 status.bits.speed = GMAC_SPEED_1000;
307 if (phy_interface_mode_is_rgmii(phydev->interface))
308 status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
309 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n",
310 phydev_name(phydev));
311 break;
312 case 100:
313 status.bits.speed = GMAC_SPEED_100;
314 if (phy_interface_mode_is_rgmii(phydev->interface))
315 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
316 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n",
317 phydev_name(phydev));
318 break;
319 case 10:
320 status.bits.speed = GMAC_SPEED_10;
321 if (phy_interface_mode_is_rgmii(phydev->interface))
322 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
323 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n",
324 phydev_name(phydev));
325 break;
326 default:
327 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n",
328 phydev->speed, phydev_name(phydev));
329 }
330
331 if (phydev->duplex == DUPLEX_FULL) {
332 u16 lcladv = phy_read(phydev, MII_ADVERTISE);
333 u16 rmtadv = phy_read(phydev, MII_LPA);
334 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
335
336 if (cap & FLOW_CTRL_RX)
337 pause_rx = 1;
338 if (cap & FLOW_CTRL_TX)
339 pause_tx = 1;
340 }
341
342 gmac_set_flow_control(netdev, pause_tx, pause_rx);
343
344 if (old_status.bits32 == status.bits32)
345 return;
346
347 if (netif_msg_link(port)) {
348 phy_print_status(phydev);
349 netdev_info(netdev, "link flow control: %s\n",
350 phydev->pause
351 ? (phydev->asym_pause ? "tx" : "both")
352 : (phydev->asym_pause ? "rx" : "none")
353 );
354 }
355
356 gmac_disable_tx_rx(netdev);
357 writel(status.bits32, port->gmac_base + GMAC_STATUS);
358 gmac_enable_tx_rx(netdev);
359 }
360
gmac_setup_phy(struct net_device * netdev)361 static int gmac_setup_phy(struct net_device *netdev)
362 {
363 struct gemini_ethernet_port *port = netdev_priv(netdev);
364 union gmac_status status = { .bits32 = 0 };
365 struct device *dev = port->dev;
366 struct phy_device *phy;
367
368 phy = of_phy_get_and_connect(netdev,
369 dev->of_node,
370 gmac_speed_set);
371 if (!phy)
372 return -ENODEV;
373 netdev->phydev = phy;
374
375 phy_set_max_speed(phy, SPEED_1000);
376 phy_support_asym_pause(phy);
377
378 /* set PHY interface type */
379 switch (phy->interface) {
380 case PHY_INTERFACE_MODE_MII:
381 netdev_dbg(netdev,
382 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n");
383 status.bits.mii_rmii = GMAC_PHY_MII;
384 break;
385 case PHY_INTERFACE_MODE_GMII:
386 netdev_dbg(netdev,
387 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n");
388 status.bits.mii_rmii = GMAC_PHY_GMII;
389 break;
390 case PHY_INTERFACE_MODE_RGMII:
391 case PHY_INTERFACE_MODE_RGMII_ID:
392 case PHY_INTERFACE_MODE_RGMII_TXID:
393 case PHY_INTERFACE_MODE_RGMII_RXID:
394 netdev_dbg(netdev,
395 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n");
396 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
397 break;
398 default:
399 netdev_err(netdev, "Unsupported MII interface\n");
400 phy_disconnect(phy);
401 netdev->phydev = NULL;
402 return -EINVAL;
403 }
404 writel(status.bits32, port->gmac_base + GMAC_STATUS);
405
406 if (netif_msg_link(port))
407 phy_attached_info(phy);
408
409 return 0;
410 }
411
412 /* The maximum frame length is not logically enumerated in the
413 * hardware, so we do a table lookup to find the applicable max
414 * frame length.
415 */
416 struct gmac_max_framelen {
417 unsigned int max_l3_len;
418 u8 val;
419 };
420
421 static const struct gmac_max_framelen gmac_maxlens[] = {
422 {
423 .max_l3_len = 1518,
424 .val = CONFIG0_MAXLEN_1518,
425 },
426 {
427 .max_l3_len = 1522,
428 .val = CONFIG0_MAXLEN_1522,
429 },
430 {
431 .max_l3_len = 1536,
432 .val = CONFIG0_MAXLEN_1536,
433 },
434 {
435 .max_l3_len = 1548,
436 .val = CONFIG0_MAXLEN_1548,
437 },
438 {
439 .max_l3_len = 9212,
440 .val = CONFIG0_MAXLEN_9k,
441 },
442 {
443 .max_l3_len = 10236,
444 .val = CONFIG0_MAXLEN_10k,
445 },
446 };
447
gmac_pick_rx_max_len(unsigned int max_l3_len)448 static int gmac_pick_rx_max_len(unsigned int max_l3_len)
449 {
450 const struct gmac_max_framelen *maxlen;
451 int maxtot;
452 int i;
453
454 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN;
455
456 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) {
457 maxlen = &gmac_maxlens[i];
458 if (maxtot <= maxlen->max_l3_len)
459 return maxlen->val;
460 }
461
462 return -1;
463 }
464
gmac_init(struct net_device * netdev)465 static int gmac_init(struct net_device *netdev)
466 {
467 struct gemini_ethernet_port *port = netdev_priv(netdev);
468 union gmac_config0 config0 = { .bits = {
469 .dis_tx = 1,
470 .dis_rx = 1,
471 .ipv4_rx_chksum = 1,
472 .ipv6_rx_chksum = 1,
473 .rx_err_detect = 1,
474 .rgmm_edge = 1,
475 .port0_chk_hwq = 1,
476 .port1_chk_hwq = 1,
477 .port0_chk_toeq = 1,
478 .port1_chk_toeq = 1,
479 .port0_chk_classq = 1,
480 .port1_chk_classq = 1,
481 } };
482 union gmac_ahb_weight ahb_weight = { .bits = {
483 .rx_weight = 1,
484 .tx_weight = 1,
485 .hash_weight = 1,
486 .pre_req = 0x1f,
487 .tq_dv_threshold = 0,
488 } };
489 union gmac_tx_wcr0 hw_weigh = { .bits = {
490 .hw_tq3 = 1,
491 .hw_tq2 = 1,
492 .hw_tq1 = 1,
493 .hw_tq0 = 1,
494 } };
495 union gmac_tx_wcr1 sw_weigh = { .bits = {
496 .sw_tq5 = 1,
497 .sw_tq4 = 1,
498 .sw_tq3 = 1,
499 .sw_tq2 = 1,
500 .sw_tq1 = 1,
501 .sw_tq0 = 1,
502 } };
503 union gmac_config1 config1 = { .bits = {
504 .set_threshold = 16,
505 .rel_threshold = 24,
506 } };
507 union gmac_config2 config2 = { .bits = {
508 .set_threshold = 16,
509 .rel_threshold = 32,
510 } };
511 union gmac_config3 config3 = { .bits = {
512 .set_threshold = 0,
513 .rel_threshold = 0,
514 } };
515 union gmac_config0 tmp;
516
517 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
518 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
519 config0.bits.reserved = tmp.bits.reserved;
520 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
521 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
522 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
523 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
524
525 readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
526 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
527
528 writel(hw_weigh.bits32,
529 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
530 writel(sw_weigh.bits32,
531 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
532
533 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
534 port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
535 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
536
537 /* Mark every quarter of the queue a packet for interrupt
538 * in order to be able to wake up the queue if it was stopped
539 */
540 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
541
542 return 0;
543 }
544
gmac_setup_txqs(struct net_device * netdev)545 static int gmac_setup_txqs(struct net_device *netdev)
546 {
547 struct gemini_ethernet_port *port = netdev_priv(netdev);
548 unsigned int n_txq = netdev->num_tx_queues;
549 struct gemini_ethernet *geth = port->geth;
550 size_t entries = 1 << port->txq_order;
551 struct gmac_txq *txq = port->txq;
552 struct gmac_txdesc *desc_ring;
553 size_t len = n_txq * entries;
554 struct sk_buff **skb_tab;
555 void __iomem *rwptr_reg;
556 unsigned int r;
557 int i;
558
559 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
560
561 skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
562 if (!skb_tab)
563 return -ENOMEM;
564
565 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
566 &port->txq_dma_base, GFP_KERNEL);
567
568 if (!desc_ring) {
569 kfree(skb_tab);
570 return -ENOMEM;
571 }
572
573 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
574 dev_warn(geth->dev, "TX queue base is not aligned\n");
575 dma_free_coherent(geth->dev, len * sizeof(*desc_ring),
576 desc_ring, port->txq_dma_base);
577 kfree(skb_tab);
578 return -ENOMEM;
579 }
580
581 writel(port->txq_dma_base | port->txq_order,
582 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
583
584 for (i = 0; i < n_txq; i++) {
585 txq->ring = desc_ring;
586 txq->skb = skb_tab;
587 txq->noirq_packets = 0;
588
589 r = readw(rwptr_reg);
590 rwptr_reg += 2;
591 writew(r, rwptr_reg);
592 rwptr_reg += 2;
593 txq->cptr = r;
594
595 txq++;
596 desc_ring += entries;
597 skb_tab += entries;
598 }
599
600 return 0;
601 }
602
gmac_clean_txq(struct net_device * netdev,struct gmac_txq * txq,unsigned int r)603 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
604 unsigned int r)
605 {
606 struct gemini_ethernet_port *port = netdev_priv(netdev);
607 unsigned int m = (1 << port->txq_order) - 1;
608 struct gemini_ethernet *geth = port->geth;
609 unsigned int c = txq->cptr;
610 union gmac_txdesc_0 word0;
611 union gmac_txdesc_1 word1;
612 unsigned int hwchksum = 0;
613 unsigned long bytes = 0;
614 struct gmac_txdesc *txd;
615 unsigned short nfrags;
616 unsigned int errs = 0;
617 unsigned int pkts = 0;
618 unsigned int word3;
619 dma_addr_t mapping;
620
621 if (c == r)
622 return;
623
624 while (c != r) {
625 txd = txq->ring + c;
626 word0 = txd->word0;
627 word1 = txd->word1;
628 mapping = txd->word2.buf_adr;
629 word3 = txd->word3.bits32;
630
631 dma_unmap_single(geth->dev, mapping,
632 word0.bits.buffer_size, DMA_TO_DEVICE);
633
634 if (word3 & EOF_BIT)
635 dev_kfree_skb(txq->skb[c]);
636
637 c++;
638 c &= m;
639
640 if (!(word3 & SOF_BIT))
641 continue;
642
643 if (!word0.bits.status_tx_ok) {
644 errs++;
645 continue;
646 }
647
648 pkts++;
649 bytes += txd->word1.bits.byte_count;
650
651 if (word1.bits32 & TSS_CHECKUM_ENABLE)
652 hwchksum++;
653
654 nfrags = word0.bits.desc_count - 1;
655 if (nfrags) {
656 if (nfrags >= TX_MAX_FRAGS)
657 nfrags = TX_MAX_FRAGS - 1;
658
659 u64_stats_update_begin(&port->tx_stats_syncp);
660 port->tx_frag_stats[nfrags]++;
661 u64_stats_update_end(&port->tx_stats_syncp);
662 }
663 }
664
665 u64_stats_update_begin(&port->ir_stats_syncp);
666 port->stats.tx_errors += errs;
667 port->stats.tx_packets += pkts;
668 port->stats.tx_bytes += bytes;
669 port->tx_hw_csummed += hwchksum;
670 u64_stats_update_end(&port->ir_stats_syncp);
671
672 txq->cptr = c;
673 }
674
gmac_cleanup_txqs(struct net_device * netdev)675 static void gmac_cleanup_txqs(struct net_device *netdev)
676 {
677 struct gemini_ethernet_port *port = netdev_priv(netdev);
678 unsigned int n_txq = netdev->num_tx_queues;
679 struct gemini_ethernet *geth = port->geth;
680 void __iomem *rwptr_reg;
681 unsigned int r, i;
682
683 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
684
685 for (i = 0; i < n_txq; i++) {
686 r = readw(rwptr_reg);
687 rwptr_reg += 2;
688 writew(r, rwptr_reg);
689 rwptr_reg += 2;
690
691 gmac_clean_txq(netdev, port->txq + i, r);
692 }
693 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
694
695 kfree(port->txq->skb);
696 dma_free_coherent(geth->dev,
697 n_txq * sizeof(*port->txq->ring) << port->txq_order,
698 port->txq->ring, port->txq_dma_base);
699 }
700
gmac_setup_rxq(struct net_device * netdev)701 static int gmac_setup_rxq(struct net_device *netdev)
702 {
703 struct gemini_ethernet_port *port = netdev_priv(netdev);
704 struct gemini_ethernet *geth = port->geth;
705 struct nontoe_qhdr __iomem *qhdr;
706
707 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
708 port->rxq_rwptr = &qhdr->word1;
709
710 /* Remap a slew of memory to use for the RX queue */
711 port->rxq_ring = dma_alloc_coherent(geth->dev,
712 sizeof(*port->rxq_ring) << port->rxq_order,
713 &port->rxq_dma_base, GFP_KERNEL);
714 if (!port->rxq_ring)
715 return -ENOMEM;
716 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
717 dev_warn(geth->dev, "RX queue base is not aligned\n");
718 return -ENOMEM;
719 }
720
721 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
722 writel(0, port->rxq_rwptr);
723 return 0;
724 }
725
726 static struct gmac_queue_page *
gmac_get_queue_page(struct gemini_ethernet * geth,struct gemini_ethernet_port * port,dma_addr_t addr)727 gmac_get_queue_page(struct gemini_ethernet *geth,
728 struct gemini_ethernet_port *port,
729 dma_addr_t addr)
730 {
731 struct gmac_queue_page *gpage;
732 dma_addr_t mapping;
733 int i;
734
735 /* Only look for even pages */
736 mapping = addr & PAGE_MASK;
737
738 if (!geth->freeq_pages) {
739 dev_err(geth->dev, "try to get page with no page list\n");
740 return NULL;
741 }
742
743 /* Look up a ring buffer page from virtual mapping */
744 for (i = 0; i < geth->num_freeq_pages; i++) {
745 gpage = &geth->freeq_pages[i];
746 if (gpage->mapping == mapping)
747 return gpage;
748 }
749
750 return NULL;
751 }
752
gmac_cleanup_rxq(struct net_device * netdev)753 static void gmac_cleanup_rxq(struct net_device *netdev)
754 {
755 struct gemini_ethernet_port *port = netdev_priv(netdev);
756 struct gemini_ethernet *geth = port->geth;
757 struct gmac_rxdesc *rxd = port->rxq_ring;
758 static struct gmac_queue_page *gpage;
759 struct nontoe_qhdr __iomem *qhdr;
760 void __iomem *dma_reg;
761 void __iomem *ptr_reg;
762 dma_addr_t mapping;
763 union dma_rwptr rw;
764 unsigned int r, w;
765
766 qhdr = geth->base +
767 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
768 dma_reg = &qhdr->word0;
769 ptr_reg = &qhdr->word1;
770
771 rw.bits32 = readl(ptr_reg);
772 r = rw.bits.rptr;
773 w = rw.bits.wptr;
774 writew(r, ptr_reg + 2);
775
776 writel(0, dma_reg);
777
778 /* Loop from read pointer to write pointer of the RX queue
779 * and free up all pages by the queue.
780 */
781 while (r != w) {
782 mapping = rxd[r].word2.buf_adr;
783 r++;
784 r &= ((1 << port->rxq_order) - 1);
785
786 if (!mapping)
787 continue;
788
789 /* Freeq pointers are one page off */
790 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
791 if (!gpage) {
792 dev_err(geth->dev, "could not find page\n");
793 continue;
794 }
795 /* Release the RX queue reference to the page */
796 put_page(gpage->page);
797 }
798
799 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
800 port->rxq_ring, port->rxq_dma_base);
801 }
802
geth_freeq_alloc_map_page(struct gemini_ethernet * geth,int pn)803 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
804 int pn)
805 {
806 struct gmac_rxdesc *freeq_entry;
807 struct gmac_queue_page *gpage;
808 unsigned int fpp_order;
809 unsigned int frag_len;
810 dma_addr_t mapping;
811 struct page *page;
812 int i;
813
814 /* First allocate and DMA map a single page */
815 page = alloc_page(GFP_ATOMIC);
816 if (!page)
817 return NULL;
818
819 mapping = dma_map_single(geth->dev, page_address(page),
820 PAGE_SIZE, DMA_FROM_DEVICE);
821 if (dma_mapping_error(geth->dev, mapping)) {
822 put_page(page);
823 return NULL;
824 }
825
826 /* The assign the page mapping (physical address) to the buffer address
827 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
828 * 4k), and the default RX frag order is 11 (fragments are up 20 2048
829 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
830 * each page normally needs two entries in the queue.
831 */
832 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
833 fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
834 freeq_entry = geth->freeq_ring + (pn << fpp_order);
835 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
836 pn, frag_len, (1 << fpp_order), freeq_entry);
837 for (i = (1 << fpp_order); i > 0; i--) {
838 freeq_entry->word2.buf_adr = mapping;
839 freeq_entry++;
840 mapping += frag_len;
841 }
842
843 /* If the freeq entry already has a page mapped, then unmap it. */
844 gpage = &geth->freeq_pages[pn];
845 if (gpage->page) {
846 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
847 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
848 /* This should be the last reference to the page so it gets
849 * released
850 */
851 put_page(gpage->page);
852 }
853
854 /* Then put our new mapping into the page table */
855 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
856 pn, (unsigned int)mapping, page);
857 gpage->mapping = mapping;
858 gpage->page = page;
859
860 return page;
861 }
862
863 /**
864 * geth_fill_freeq() - Fill the freeq with empty fragments to use
865 * @geth: the ethernet adapter
866 * @refill: whether to reset the queue by filling in all freeq entries or
867 * just refill it, usually the interrupt to refill the queue happens when
868 * the queue is half empty.
869 */
geth_fill_freeq(struct gemini_ethernet * geth,bool refill)870 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
871 {
872 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
873 unsigned int count = 0;
874 unsigned int pn, epn;
875 unsigned long flags;
876 union dma_rwptr rw;
877 unsigned int m_pn;
878
879 /* Mask for page */
880 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
881
882 spin_lock_irqsave(&geth->freeq_lock, flags);
883
884 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
885 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
886 epn = (rw.bits.rptr >> fpp_order) - 1;
887 epn &= m_pn;
888
889 /* Loop over the freeq ring buffer entries */
890 while (pn != epn) {
891 struct gmac_queue_page *gpage;
892 struct page *page;
893
894 gpage = &geth->freeq_pages[pn];
895 page = gpage->page;
896
897 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
898 pn, page_ref_count(page), 1 << fpp_order);
899
900 if (page_ref_count(page) > 1) {
901 unsigned int fl = (pn - epn) & m_pn;
902
903 if (fl > 64 >> fpp_order)
904 break;
905
906 page = geth_freeq_alloc_map_page(geth, pn);
907 if (!page)
908 break;
909 }
910
911 /* Add one reference per fragment in the page */
912 page_ref_add(page, 1 << fpp_order);
913 count += 1 << fpp_order;
914 pn++;
915 pn &= m_pn;
916 }
917
918 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
919
920 spin_unlock_irqrestore(&geth->freeq_lock, flags);
921
922 return count;
923 }
924
geth_setup_freeq(struct gemini_ethernet * geth)925 static int geth_setup_freeq(struct gemini_ethernet *geth)
926 {
927 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
928 unsigned int frag_len = 1 << geth->freeq_frag_order;
929 unsigned int len = 1 << geth->freeq_order;
930 unsigned int pages = len >> fpp_order;
931 union queue_threshold qt;
932 union dma_skb_size skbsz;
933 unsigned int filled;
934 unsigned int pn;
935
936 geth->freeq_ring = dma_alloc_coherent(geth->dev,
937 sizeof(*geth->freeq_ring) << geth->freeq_order,
938 &geth->freeq_dma_base, GFP_KERNEL);
939 if (!geth->freeq_ring)
940 return -ENOMEM;
941 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
942 dev_warn(geth->dev, "queue ring base is not aligned\n");
943 goto err_freeq;
944 }
945
946 /* Allocate a mapping to page look-up index */
947 geth->freeq_pages = kcalloc(pages, sizeof(*geth->freeq_pages),
948 GFP_KERNEL);
949 if (!geth->freeq_pages)
950 goto err_freeq;
951 geth->num_freeq_pages = pages;
952
953 dev_info(geth->dev, "allocate %d pages for queue\n", pages);
954 for (pn = 0; pn < pages; pn++)
955 if (!geth_freeq_alloc_map_page(geth, pn))
956 goto err_freeq_alloc;
957
958 filled = geth_fill_freeq(geth, false);
959 if (!filled)
960 goto err_freeq_alloc;
961
962 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
963 qt.bits.swfq_empty = 32;
964 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
965
966 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
967 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
968 writel(geth->freeq_dma_base | geth->freeq_order,
969 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
970
971 return 0;
972
973 err_freeq_alloc:
974 while (pn > 0) {
975 struct gmac_queue_page *gpage;
976 dma_addr_t mapping;
977
978 --pn;
979 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
980 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
981 gpage = &geth->freeq_pages[pn];
982 put_page(gpage->page);
983 }
984
985 kfree(geth->freeq_pages);
986 err_freeq:
987 dma_free_coherent(geth->dev,
988 sizeof(*geth->freeq_ring) << geth->freeq_order,
989 geth->freeq_ring, geth->freeq_dma_base);
990 geth->freeq_ring = NULL;
991 return -ENOMEM;
992 }
993
994 /**
995 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
996 * @geth: the Gemini global ethernet state
997 */
geth_cleanup_freeq(struct gemini_ethernet * geth)998 static void geth_cleanup_freeq(struct gemini_ethernet *geth)
999 {
1000 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
1001 unsigned int frag_len = 1 << geth->freeq_frag_order;
1002 unsigned int len = 1 << geth->freeq_order;
1003 unsigned int pages = len >> fpp_order;
1004 unsigned int pn;
1005
1006 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
1007 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
1008 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1009
1010 for (pn = 0; pn < pages; pn++) {
1011 struct gmac_queue_page *gpage;
1012 dma_addr_t mapping;
1013
1014 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
1015 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
1016
1017 gpage = &geth->freeq_pages[pn];
1018 while (page_ref_count(gpage->page) > 0)
1019 put_page(gpage->page);
1020 }
1021
1022 kfree(geth->freeq_pages);
1023
1024 dma_free_coherent(geth->dev,
1025 sizeof(*geth->freeq_ring) << geth->freeq_order,
1026 geth->freeq_ring, geth->freeq_dma_base);
1027 }
1028
1029 /**
1030 * geth_resize_freeq() - resize the software queue depth
1031 * @port: the port requesting the change
1032 *
1033 * This gets called at least once during probe() so the device queue gets
1034 * "resized" from the hardware defaults. Since both ports/net devices share
1035 * the same hardware queue, some synchronization between the ports is
1036 * needed.
1037 */
geth_resize_freeq(struct gemini_ethernet_port * port)1038 static int geth_resize_freeq(struct gemini_ethernet_port *port)
1039 {
1040 struct gemini_ethernet *geth = port->geth;
1041 struct net_device *netdev = port->netdev;
1042 struct gemini_ethernet_port *other_port;
1043 struct net_device *other_netdev;
1044 unsigned int new_size = 0;
1045 unsigned int new_order;
1046 unsigned long flags;
1047 u32 en;
1048 int ret;
1049
1050 if (netdev->dev_id == 0)
1051 other_netdev = geth->port1->netdev;
1052 else
1053 other_netdev = geth->port0->netdev;
1054
1055 if (other_netdev && netif_running(other_netdev))
1056 return -EBUSY;
1057
1058 new_size = 1 << (port->rxq_order + 1);
1059 netdev_dbg(netdev, "port %d size: %d order %d\n",
1060 netdev->dev_id,
1061 new_size,
1062 port->rxq_order);
1063 if (other_netdev) {
1064 other_port = netdev_priv(other_netdev);
1065 new_size += 1 << (other_port->rxq_order + 1);
1066 netdev_dbg(other_netdev, "port %d size: %d order %d\n",
1067 other_netdev->dev_id,
1068 (1 << (other_port->rxq_order + 1)),
1069 other_port->rxq_order);
1070 }
1071
1072 new_order = min(15, ilog2(new_size - 1) + 1);
1073 dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
1074 new_size, new_order);
1075 if (geth->freeq_order == new_order)
1076 return 0;
1077
1078 spin_lock_irqsave(&geth->irq_lock, flags);
1079
1080 /* Disable the software queue IRQs */
1081 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1082 en &= ~SWFQ_EMPTY_INT_BIT;
1083 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1084 spin_unlock_irqrestore(&geth->irq_lock, flags);
1085
1086 /* Drop the old queue */
1087 if (geth->freeq_ring)
1088 geth_cleanup_freeq(geth);
1089
1090 /* Allocate a new queue with the desired order */
1091 geth->freeq_order = new_order;
1092 ret = geth_setup_freeq(geth);
1093
1094 /* Restart the interrupts - NOTE if this is the first resize
1095 * after probe(), this is where the interrupts get turned on
1096 * in the first place.
1097 */
1098 spin_lock_irqsave(&geth->irq_lock, flags);
1099 en |= SWFQ_EMPTY_INT_BIT;
1100 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1101 spin_unlock_irqrestore(&geth->irq_lock, flags);
1102
1103 return ret;
1104 }
1105
gmac_tx_irq_enable(struct net_device * netdev,unsigned int txq,int en)1106 static void gmac_tx_irq_enable(struct net_device *netdev,
1107 unsigned int txq, int en)
1108 {
1109 struct gemini_ethernet_port *port = netdev_priv(netdev);
1110 struct gemini_ethernet *geth = port->geth;
1111 unsigned long flags;
1112 u32 val, mask;
1113
1114 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
1115
1116 spin_lock_irqsave(&geth->irq_lock, flags);
1117
1118 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
1119
1120 if (en)
1121 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1122
1123 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1124 val = en ? val | mask : val & ~mask;
1125 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1126
1127 spin_unlock_irqrestore(&geth->irq_lock, flags);
1128 }
1129
gmac_tx_irq(struct net_device * netdev,unsigned int txq_num)1130 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
1131 {
1132 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
1133
1134 gmac_tx_irq_enable(netdev, txq_num, 0);
1135 netif_tx_wake_queue(ntxq);
1136 }
1137
gmac_map_tx_bufs(struct net_device * netdev,struct sk_buff * skb,struct gmac_txq * txq,unsigned short * desc)1138 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
1139 struct gmac_txq *txq, unsigned short *desc)
1140 {
1141 struct gemini_ethernet_port *port = netdev_priv(netdev);
1142 struct skb_shared_info *skb_si = skb_shinfo(skb);
1143 unsigned short m = (1 << port->txq_order) - 1;
1144 short frag, last_frag = skb_si->nr_frags - 1;
1145 struct gemini_ethernet *geth = port->geth;
1146 unsigned int word1, word3, buflen;
1147 unsigned short w = *desc;
1148 struct gmac_txdesc *txd;
1149 skb_frag_t *skb_frag;
1150 dma_addr_t mapping;
1151 unsigned short mtu;
1152 void *buffer;
1153 int ret;
1154
1155 mtu = ETH_HLEN;
1156 mtu += netdev->mtu;
1157 if (skb->protocol == htons(ETH_P_8021Q))
1158 mtu += VLAN_HLEN;
1159
1160 word1 = skb->len;
1161 word3 = SOF_BIT;
1162
1163 if (word1 > mtu) {
1164 word1 |= TSS_MTU_ENABLE_BIT;
1165 word3 |= mtu;
1166 }
1167
1168 if (skb->len >= ETH_FRAME_LEN) {
1169 /* Hardware offloaded checksumming isn't working on frames
1170 * bigger than 1514 bytes. A hypothesis about this is that the
1171 * checksum buffer is only 1518 bytes, so when the frames get
1172 * bigger they get truncated, or the last few bytes get
1173 * overwritten by the FCS.
1174 *
1175 * Just use software checksumming and bypass on bigger frames.
1176 */
1177 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1178 ret = skb_checksum_help(skb);
1179 if (ret)
1180 return ret;
1181 }
1182 word1 |= TSS_BYPASS_BIT;
1183 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1184 int tcp = 0;
1185
1186 /* We do not switch off the checksumming on non TCP/UDP
1187 * frames: as is shown from tests, the checksumming engine
1188 * is smart enough to see that a frame is not actually TCP
1189 * or UDP and then just pass it through without any changes
1190 * to the frame.
1191 */
1192 if (skb->protocol == htons(ETH_P_IP)) {
1193 word1 |= TSS_IP_CHKSUM_BIT;
1194 tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1195 } else { /* IPv6 */
1196 word1 |= TSS_IPV6_ENABLE_BIT;
1197 tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1198 }
1199
1200 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1201 }
1202
1203 frag = -1;
1204 while (frag <= last_frag) {
1205 if (frag == -1) {
1206 buffer = skb->data;
1207 buflen = skb_headlen(skb);
1208 } else {
1209 skb_frag = skb_si->frags + frag;
1210 buffer = skb_frag_address(skb_frag);
1211 buflen = skb_frag_size(skb_frag);
1212 }
1213
1214 if (frag == last_frag) {
1215 word3 |= EOF_BIT;
1216 txq->skb[w] = skb;
1217 }
1218
1219 mapping = dma_map_single(geth->dev, buffer, buflen,
1220 DMA_TO_DEVICE);
1221 if (dma_mapping_error(geth->dev, mapping))
1222 goto map_error;
1223
1224 txd = txq->ring + w;
1225 txd->word0.bits32 = buflen;
1226 txd->word1.bits32 = word1;
1227 txd->word2.buf_adr = mapping;
1228 txd->word3.bits32 = word3;
1229
1230 word3 &= MTU_SIZE_BIT_MASK;
1231 w++;
1232 w &= m;
1233 frag++;
1234 }
1235
1236 *desc = w;
1237 return 0;
1238
1239 map_error:
1240 while (w != *desc) {
1241 w--;
1242 w &= m;
1243
1244 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
1245 txq->ring[w].word0.bits.buffer_size,
1246 DMA_TO_DEVICE);
1247 }
1248 return -ENOMEM;
1249 }
1250
gmac_start_xmit(struct sk_buff * skb,struct net_device * netdev)1251 static netdev_tx_t gmac_start_xmit(struct sk_buff *skb,
1252 struct net_device *netdev)
1253 {
1254 struct gemini_ethernet_port *port = netdev_priv(netdev);
1255 unsigned short m = (1 << port->txq_order) - 1;
1256 struct netdev_queue *ntxq;
1257 unsigned short r, w, d;
1258 void __iomem *ptr_reg;
1259 struct gmac_txq *txq;
1260 int txq_num, nfrags;
1261 union dma_rwptr rw;
1262
1263 if (skb->len >= 0x10000)
1264 goto out_drop_free;
1265
1266 txq_num = skb_get_queue_mapping(skb);
1267 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1268 txq = &port->txq[txq_num];
1269 ntxq = netdev_get_tx_queue(netdev, txq_num);
1270 nfrags = skb_shinfo(skb)->nr_frags;
1271
1272 rw.bits32 = readl(ptr_reg);
1273 r = rw.bits.rptr;
1274 w = rw.bits.wptr;
1275
1276 d = txq->cptr - w - 1;
1277 d &= m;
1278
1279 if (d < nfrags + 2) {
1280 gmac_clean_txq(netdev, txq, r);
1281 d = txq->cptr - w - 1;
1282 d &= m;
1283
1284 if (d < nfrags + 2) {
1285 netif_tx_stop_queue(ntxq);
1286
1287 d = txq->cptr + nfrags + 16;
1288 d &= m;
1289 txq->ring[d].word3.bits.eofie = 1;
1290 gmac_tx_irq_enable(netdev, txq_num, 1);
1291
1292 u64_stats_update_begin(&port->tx_stats_syncp);
1293 netdev->stats.tx_fifo_errors++;
1294 u64_stats_update_end(&port->tx_stats_syncp);
1295 return NETDEV_TX_BUSY;
1296 }
1297 }
1298
1299 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
1300 if (skb_linearize(skb))
1301 goto out_drop;
1302
1303 u64_stats_update_begin(&port->tx_stats_syncp);
1304 port->tx_frags_linearized++;
1305 u64_stats_update_end(&port->tx_stats_syncp);
1306
1307 if (gmac_map_tx_bufs(netdev, skb, txq, &w))
1308 goto out_drop_free;
1309 }
1310
1311 writew(w, ptr_reg + 2);
1312
1313 gmac_clean_txq(netdev, txq, r);
1314 return NETDEV_TX_OK;
1315
1316 out_drop_free:
1317 dev_kfree_skb(skb);
1318 out_drop:
1319 u64_stats_update_begin(&port->tx_stats_syncp);
1320 port->stats.tx_dropped++;
1321 u64_stats_update_end(&port->tx_stats_syncp);
1322 return NETDEV_TX_OK;
1323 }
1324
gmac_tx_timeout(struct net_device * netdev,unsigned int txqueue)1325 static void gmac_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1326 {
1327 netdev_err(netdev, "Tx timeout\n");
1328 gmac_dump_dma_state(netdev);
1329 }
1330
gmac_enable_irq(struct net_device * netdev,int enable)1331 static void gmac_enable_irq(struct net_device *netdev, int enable)
1332 {
1333 struct gemini_ethernet_port *port = netdev_priv(netdev);
1334 struct gemini_ethernet *geth = port->geth;
1335 unsigned long flags;
1336 u32 val, mask;
1337
1338 netdev_dbg(netdev, "%s device %d %s\n", __func__,
1339 netdev->dev_id, enable ? "enable" : "disable");
1340 spin_lock_irqsave(&geth->irq_lock, flags);
1341
1342 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
1343 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1344 val = enable ? (val | mask) : (val & ~mask);
1345 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1346
1347 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1348 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1349 val = enable ? (val | mask) : (val & ~mask);
1350 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1351
1352 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
1353 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1354 val = enable ? (val | mask) : (val & ~mask);
1355 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1356
1357 spin_unlock_irqrestore(&geth->irq_lock, flags);
1358 }
1359
gmac_enable_rx_irq(struct net_device * netdev,int enable)1360 static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
1361 {
1362 struct gemini_ethernet_port *port = netdev_priv(netdev);
1363 struct gemini_ethernet *geth = port->geth;
1364 unsigned long flags;
1365 u32 val, mask;
1366
1367 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
1368 enable ? "enable" : "disable");
1369 spin_lock_irqsave(&geth->irq_lock, flags);
1370 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1371
1372 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1373 val = enable ? (val | mask) : (val & ~mask);
1374 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1375
1376 spin_unlock_irqrestore(&geth->irq_lock, flags);
1377 }
1378
gmac_skb_if_good_frame(struct gemini_ethernet_port * port,union gmac_rxdesc_0 word0,unsigned int frame_len)1379 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
1380 union gmac_rxdesc_0 word0,
1381 unsigned int frame_len)
1382 {
1383 unsigned int rx_csum = word0.bits.chksum_status;
1384 unsigned int rx_status = word0.bits.status;
1385 struct sk_buff *skb = NULL;
1386
1387 port->rx_stats[rx_status]++;
1388 port->rx_csum_stats[rx_csum]++;
1389
1390 if (word0.bits.derr || word0.bits.perr ||
1391 rx_status || frame_len < ETH_ZLEN ||
1392 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1393 port->stats.rx_errors++;
1394
1395 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1396 port->stats.rx_length_errors++;
1397 if (RX_ERROR_OVER(rx_status))
1398 port->stats.rx_over_errors++;
1399 if (RX_ERROR_CRC(rx_status))
1400 port->stats.rx_crc_errors++;
1401 if (RX_ERROR_FRAME(rx_status))
1402 port->stats.rx_frame_errors++;
1403 return NULL;
1404 }
1405
1406 skb = napi_get_frags(&port->napi);
1407 if (!skb)
1408 goto update_exit;
1409
1410 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1411 skb->ip_summed = CHECKSUM_UNNECESSARY;
1412
1413 update_exit:
1414 port->stats.rx_bytes += frame_len;
1415 port->stats.rx_packets++;
1416 return skb;
1417 }
1418
gmac_rx(struct net_device * netdev,unsigned int budget)1419 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
1420 {
1421 struct gemini_ethernet_port *port = netdev_priv(netdev);
1422 unsigned short m = (1 << port->rxq_order) - 1;
1423 struct gemini_ethernet *geth = port->geth;
1424 void __iomem *ptr_reg = port->rxq_rwptr;
1425 unsigned int frame_len, frag_len;
1426 struct gmac_rxdesc *rx = NULL;
1427 struct gmac_queue_page *gpage;
1428 static struct sk_buff *skb;
1429 union gmac_rxdesc_0 word0;
1430 union gmac_rxdesc_1 word1;
1431 union gmac_rxdesc_3 word3;
1432 struct page *page = NULL;
1433 unsigned int page_offs;
1434 unsigned long flags;
1435 unsigned short r, w;
1436 union dma_rwptr rw;
1437 dma_addr_t mapping;
1438 int frag_nr = 0;
1439
1440 spin_lock_irqsave(&geth->irq_lock, flags);
1441 rw.bits32 = readl(ptr_reg);
1442 /* Reset interrupt as all packages until here are taken into account */
1443 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
1444 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1445 spin_unlock_irqrestore(&geth->irq_lock, flags);
1446
1447 r = rw.bits.rptr;
1448 w = rw.bits.wptr;
1449
1450 while (budget && w != r) {
1451 rx = port->rxq_ring + r;
1452 word0 = rx->word0;
1453 word1 = rx->word1;
1454 mapping = rx->word2.buf_adr;
1455 word3 = rx->word3;
1456
1457 r++;
1458 r &= m;
1459
1460 frag_len = word0.bits.buffer_size;
1461 frame_len = word1.bits.byte_count;
1462 page_offs = mapping & ~PAGE_MASK;
1463
1464 if (!mapping) {
1465 netdev_err(netdev,
1466 "rxq[%u]: HW BUG: zero DMA desc\n", r);
1467 goto err_drop;
1468 }
1469
1470 /* Freeq pointers are one page off */
1471 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
1472 if (!gpage) {
1473 dev_err(geth->dev, "could not find mapping\n");
1474 continue;
1475 }
1476 page = gpage->page;
1477
1478 if (word3.bits32 & SOF_BIT) {
1479 if (skb) {
1480 napi_free_frags(&port->napi);
1481 port->stats.rx_dropped++;
1482 }
1483
1484 skb = gmac_skb_if_good_frame(port, word0, frame_len);
1485 if (!skb)
1486 goto err_drop;
1487
1488 page_offs += NET_IP_ALIGN;
1489 frag_len -= NET_IP_ALIGN;
1490 frag_nr = 0;
1491
1492 } else if (!skb) {
1493 put_page(page);
1494 continue;
1495 }
1496
1497 if (word3.bits32 & EOF_BIT)
1498 frag_len = frame_len - skb->len;
1499
1500 /* append page frag to skb */
1501 if (frag_nr == MAX_SKB_FRAGS)
1502 goto err_drop;
1503
1504 if (frag_len == 0)
1505 netdev_err(netdev, "Received fragment with len = 0\n");
1506
1507 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1508 skb->len += frag_len;
1509 skb->data_len += frag_len;
1510 skb->truesize += frag_len;
1511 frag_nr++;
1512
1513 if (word3.bits32 & EOF_BIT) {
1514 napi_gro_frags(&port->napi);
1515 skb = NULL;
1516 --budget;
1517 }
1518 continue;
1519
1520 err_drop:
1521 if (skb) {
1522 napi_free_frags(&port->napi);
1523 skb = NULL;
1524 }
1525
1526 if (mapping)
1527 put_page(page);
1528
1529 port->stats.rx_dropped++;
1530 }
1531
1532 writew(r, ptr_reg);
1533 return budget;
1534 }
1535
gmac_napi_poll(struct napi_struct * napi,int budget)1536 static int gmac_napi_poll(struct napi_struct *napi, int budget)
1537 {
1538 struct gemini_ethernet_port *port = netdev_priv(napi->dev);
1539 struct gemini_ethernet *geth = port->geth;
1540 unsigned int freeq_threshold;
1541 unsigned int received;
1542
1543 freeq_threshold = 1 << (geth->freeq_order - 1);
1544 u64_stats_update_begin(&port->rx_stats_syncp);
1545
1546 received = gmac_rx(napi->dev, budget);
1547 if (received < budget) {
1548 napi_gro_flush(napi, false);
1549 napi_complete_done(napi, received);
1550 gmac_enable_rx_irq(napi->dev, 1);
1551 ++port->rx_napi_exits;
1552 }
1553
1554 port->freeq_refill += (budget - received);
1555 if (port->freeq_refill > freeq_threshold) {
1556 port->freeq_refill -= freeq_threshold;
1557 geth_fill_freeq(geth, true);
1558 }
1559
1560 u64_stats_update_end(&port->rx_stats_syncp);
1561 return received;
1562 }
1563
gmac_dump_dma_state(struct net_device * netdev)1564 static void gmac_dump_dma_state(struct net_device *netdev)
1565 {
1566 struct gemini_ethernet_port *port = netdev_priv(netdev);
1567 struct gemini_ethernet *geth = port->geth;
1568 void __iomem *ptr_reg;
1569 u32 reg[5];
1570
1571 /* Interrupt status */
1572 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1573 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1574 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
1575 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
1576 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1577 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1578 reg[0], reg[1], reg[2], reg[3], reg[4]);
1579
1580 /* Interrupt enable */
1581 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1582 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1583 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1584 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1585 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1586 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1587 reg[0], reg[1], reg[2], reg[3], reg[4]);
1588
1589 /* RX DMA status */
1590 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
1591 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
1592 reg[2] = GET_RPTR(port->rxq_rwptr);
1593 reg[3] = GET_WPTR(port->rxq_rwptr);
1594 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1595 reg[0], reg[1], reg[2], reg[3]);
1596
1597 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
1598 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
1599 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
1600 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
1601 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1602 reg[0], reg[1], reg[2], reg[3]);
1603
1604 /* TX DMA status */
1605 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
1606
1607 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
1608 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
1609 reg[2] = GET_RPTR(ptr_reg);
1610 reg[3] = GET_WPTR(ptr_reg);
1611 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1612 reg[0], reg[1], reg[2], reg[3]);
1613
1614 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
1615 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
1616 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
1617 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
1618 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1619 reg[0], reg[1], reg[2], reg[3]);
1620
1621 /* FREE queues status */
1622 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
1623
1624 reg[0] = GET_RPTR(ptr_reg);
1625 reg[1] = GET_WPTR(ptr_reg);
1626
1627 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
1628
1629 reg[2] = GET_RPTR(ptr_reg);
1630 reg[3] = GET_WPTR(ptr_reg);
1631 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1632 reg[0], reg[1], reg[2], reg[3]);
1633 }
1634
gmac_update_hw_stats(struct net_device * netdev)1635 static void gmac_update_hw_stats(struct net_device *netdev)
1636 {
1637 struct gemini_ethernet_port *port = netdev_priv(netdev);
1638 unsigned int rx_discards, rx_mcast, rx_bcast;
1639 struct gemini_ethernet *geth = port->geth;
1640 unsigned long flags;
1641
1642 spin_lock_irqsave(&geth->irq_lock, flags);
1643 u64_stats_update_begin(&port->ir_stats_syncp);
1644
1645 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
1646 port->hw_stats[0] += rx_discards;
1647 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
1648 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
1649 port->hw_stats[2] += rx_mcast;
1650 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
1651 port->hw_stats[3] += rx_bcast;
1652 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
1653 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
1654
1655 port->stats.rx_missed_errors += rx_discards;
1656 port->stats.multicast += rx_mcast;
1657 port->stats.multicast += rx_bcast;
1658
1659 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
1660 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1661
1662 u64_stats_update_end(&port->ir_stats_syncp);
1663 spin_unlock_irqrestore(&geth->irq_lock, flags);
1664 }
1665
1666 /**
1667 * gmac_get_intr_flags() - get interrupt status flags for a port from
1668 * @netdev: the net device for the port to get flags from
1669 * @i: the interrupt status register 0..4
1670 */
gmac_get_intr_flags(struct net_device * netdev,int i)1671 static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
1672 {
1673 struct gemini_ethernet_port *port = netdev_priv(netdev);
1674 struct gemini_ethernet *geth = port->geth;
1675 void __iomem *irqif_reg, *irqen_reg;
1676 unsigned int offs, val;
1677
1678 /* Calculate the offset using the stride of the status registers */
1679 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
1680 GLOBAL_INTERRUPT_STATUS_0_REG);
1681
1682 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1683 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1684
1685 val = readl(irqif_reg) & readl(irqen_reg);
1686 return val;
1687 }
1688
gmac_coalesce_delay_expired(struct hrtimer * timer)1689 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
1690 {
1691 struct gemini_ethernet_port *port =
1692 container_of(timer, struct gemini_ethernet_port,
1693 rx_coalesce_timer);
1694
1695 napi_schedule(&port->napi);
1696 return HRTIMER_NORESTART;
1697 }
1698
gmac_irq(int irq,void * data)1699 static irqreturn_t gmac_irq(int irq, void *data)
1700 {
1701 struct gemini_ethernet_port *port;
1702 struct net_device *netdev = data;
1703 struct gemini_ethernet *geth;
1704 u32 val, orr = 0;
1705
1706 port = netdev_priv(netdev);
1707 geth = port->geth;
1708
1709 val = gmac_get_intr_flags(netdev, 0);
1710 orr |= val;
1711
1712 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
1713 /* Oh, crap */
1714 netdev_err(netdev, "hw failure/sw bug\n");
1715 gmac_dump_dma_state(netdev);
1716
1717 /* don't know how to recover, just reduce losses */
1718 gmac_enable_irq(netdev, 0);
1719 return IRQ_HANDLED;
1720 }
1721
1722 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
1723 gmac_tx_irq(netdev, 0);
1724
1725 val = gmac_get_intr_flags(netdev, 1);
1726 orr |= val;
1727
1728 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
1729 gmac_enable_rx_irq(netdev, 0);
1730
1731 if (!port->rx_coalesce_nsecs) {
1732 napi_schedule(&port->napi);
1733 } else {
1734 ktime_t ktime;
1735
1736 ktime = ktime_set(0, port->rx_coalesce_nsecs);
1737 hrtimer_start(&port->rx_coalesce_timer, ktime,
1738 HRTIMER_MODE_REL);
1739 }
1740 }
1741
1742 val = gmac_get_intr_flags(netdev, 4);
1743 orr |= val;
1744
1745 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
1746 gmac_update_hw_stats(netdev);
1747
1748 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
1749 spin_lock(&geth->irq_lock);
1750 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
1751 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1752 u64_stats_update_begin(&port->ir_stats_syncp);
1753 ++port->stats.rx_fifo_errors;
1754 u64_stats_update_end(&port->ir_stats_syncp);
1755 spin_unlock(&geth->irq_lock);
1756 }
1757
1758 return orr ? IRQ_HANDLED : IRQ_NONE;
1759 }
1760
gmac_start_dma(struct gemini_ethernet_port * port)1761 static void gmac_start_dma(struct gemini_ethernet_port *port)
1762 {
1763 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1764 union gmac_dma_ctrl dma_ctrl;
1765
1766 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1767 dma_ctrl.bits.rd_enable = 1;
1768 dma_ctrl.bits.td_enable = 1;
1769 dma_ctrl.bits.loopback = 0;
1770 dma_ctrl.bits.drop_small_ack = 0;
1771 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1772 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1773 dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1774 dma_ctrl.bits.rd_bus = HSIZE_8;
1775 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1776 dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1777 dma_ctrl.bits.td_bus = HSIZE_8;
1778
1779 writel(dma_ctrl.bits32, dma_ctrl_reg);
1780 }
1781
gmac_stop_dma(struct gemini_ethernet_port * port)1782 static void gmac_stop_dma(struct gemini_ethernet_port *port)
1783 {
1784 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1785 union gmac_dma_ctrl dma_ctrl;
1786
1787 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1788 dma_ctrl.bits.rd_enable = 0;
1789 dma_ctrl.bits.td_enable = 0;
1790 writel(dma_ctrl.bits32, dma_ctrl_reg);
1791 }
1792
gmac_open(struct net_device * netdev)1793 static int gmac_open(struct net_device *netdev)
1794 {
1795 struct gemini_ethernet_port *port = netdev_priv(netdev);
1796 int err;
1797
1798 err = request_irq(netdev->irq, gmac_irq,
1799 IRQF_SHARED, netdev->name, netdev);
1800 if (err) {
1801 netdev_err(netdev, "no IRQ\n");
1802 return err;
1803 }
1804
1805 netif_carrier_off(netdev);
1806 phy_start(netdev->phydev);
1807
1808 err = geth_resize_freeq(port);
1809 /* It's fine if it's just busy, the other port has set up
1810 * the freeq in that case.
1811 */
1812 if (err && (err != -EBUSY)) {
1813 netdev_err(netdev, "could not resize freeq\n");
1814 goto err_stop_phy;
1815 }
1816
1817 err = gmac_setup_rxq(netdev);
1818 if (err) {
1819 netdev_err(netdev, "could not setup RXQ\n");
1820 goto err_stop_phy;
1821 }
1822
1823 err = gmac_setup_txqs(netdev);
1824 if (err) {
1825 netdev_err(netdev, "could not setup TXQs\n");
1826 gmac_cleanup_rxq(netdev);
1827 goto err_stop_phy;
1828 }
1829
1830 napi_enable(&port->napi);
1831
1832 gmac_start_dma(port);
1833 gmac_enable_irq(netdev, 1);
1834 gmac_enable_tx_rx(netdev);
1835 netif_tx_start_all_queues(netdev);
1836
1837 hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
1838 HRTIMER_MODE_REL);
1839 port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1840
1841 netdev_dbg(netdev, "opened\n");
1842
1843 return 0;
1844
1845 err_stop_phy:
1846 phy_stop(netdev->phydev);
1847 free_irq(netdev->irq, netdev);
1848 return err;
1849 }
1850
gmac_stop(struct net_device * netdev)1851 static int gmac_stop(struct net_device *netdev)
1852 {
1853 struct gemini_ethernet_port *port = netdev_priv(netdev);
1854
1855 hrtimer_cancel(&port->rx_coalesce_timer);
1856 netif_tx_stop_all_queues(netdev);
1857 gmac_disable_tx_rx(netdev);
1858 gmac_stop_dma(port);
1859 napi_disable(&port->napi);
1860
1861 gmac_enable_irq(netdev, 0);
1862 gmac_cleanup_rxq(netdev);
1863 gmac_cleanup_txqs(netdev);
1864
1865 phy_stop(netdev->phydev);
1866 free_irq(netdev->irq, netdev);
1867
1868 gmac_update_hw_stats(netdev);
1869 return 0;
1870 }
1871
gmac_set_rx_mode(struct net_device * netdev)1872 static void gmac_set_rx_mode(struct net_device *netdev)
1873 {
1874 struct gemini_ethernet_port *port = netdev_priv(netdev);
1875 union gmac_rx_fltr filter = { .bits = {
1876 .broadcast = 1,
1877 .multicast = 1,
1878 .unicast = 1,
1879 } };
1880 struct netdev_hw_addr *ha;
1881 unsigned int bit_nr;
1882 u32 mc_filter[2];
1883
1884 mc_filter[1] = 0;
1885 mc_filter[0] = 0;
1886
1887 if (netdev->flags & IFF_PROMISC) {
1888 filter.bits.error = 1;
1889 filter.bits.promiscuous = 1;
1890 mc_filter[1] = ~0;
1891 mc_filter[0] = ~0;
1892 } else if (netdev->flags & IFF_ALLMULTI) {
1893 mc_filter[1] = ~0;
1894 mc_filter[0] = ~0;
1895 } else {
1896 netdev_for_each_mc_addr(ha, netdev) {
1897 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1898 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1899 }
1900 }
1901
1902 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
1903 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
1904 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
1905 }
1906
gmac_write_mac_address(struct net_device * netdev)1907 static void gmac_write_mac_address(struct net_device *netdev)
1908 {
1909 struct gemini_ethernet_port *port = netdev_priv(netdev);
1910 __le32 addr[3];
1911
1912 memset(addr, 0, sizeof(addr));
1913 memcpy(addr, netdev->dev_addr, ETH_ALEN);
1914
1915 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
1916 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
1917 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
1918 }
1919
gmac_set_mac_address(struct net_device * netdev,void * addr)1920 static int gmac_set_mac_address(struct net_device *netdev, void *addr)
1921 {
1922 struct sockaddr *sa = addr;
1923
1924 eth_hw_addr_set(netdev, sa->sa_data);
1925 gmac_write_mac_address(netdev);
1926
1927 return 0;
1928 }
1929
gmac_clear_hw_stats(struct net_device * netdev)1930 static void gmac_clear_hw_stats(struct net_device *netdev)
1931 {
1932 struct gemini_ethernet_port *port = netdev_priv(netdev);
1933
1934 readl(port->gmac_base + GMAC_IN_DISCARDS);
1935 readl(port->gmac_base + GMAC_IN_ERRORS);
1936 readl(port->gmac_base + GMAC_IN_MCAST);
1937 readl(port->gmac_base + GMAC_IN_BCAST);
1938 readl(port->gmac_base + GMAC_IN_MAC1);
1939 readl(port->gmac_base + GMAC_IN_MAC2);
1940 }
1941
gmac_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)1942 static void gmac_get_stats64(struct net_device *netdev,
1943 struct rtnl_link_stats64 *stats)
1944 {
1945 struct gemini_ethernet_port *port = netdev_priv(netdev);
1946 unsigned int start;
1947
1948 gmac_update_hw_stats(netdev);
1949
1950 /* Racing with RX NAPI */
1951 do {
1952 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
1953
1954 stats->rx_packets = port->stats.rx_packets;
1955 stats->rx_bytes = port->stats.rx_bytes;
1956 stats->rx_errors = port->stats.rx_errors;
1957 stats->rx_dropped = port->stats.rx_dropped;
1958
1959 stats->rx_length_errors = port->stats.rx_length_errors;
1960 stats->rx_over_errors = port->stats.rx_over_errors;
1961 stats->rx_crc_errors = port->stats.rx_crc_errors;
1962 stats->rx_frame_errors = port->stats.rx_frame_errors;
1963
1964 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
1965
1966 /* Racing with MIB and TX completion interrupts */
1967 do {
1968 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
1969
1970 stats->tx_errors = port->stats.tx_errors;
1971 stats->tx_packets = port->stats.tx_packets;
1972 stats->tx_bytes = port->stats.tx_bytes;
1973
1974 stats->multicast = port->stats.multicast;
1975 stats->rx_missed_errors = port->stats.rx_missed_errors;
1976 stats->rx_fifo_errors = port->stats.rx_fifo_errors;
1977
1978 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
1979
1980 /* Racing with hard_start_xmit */
1981 do {
1982 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
1983
1984 stats->tx_dropped = port->stats.tx_dropped;
1985
1986 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
1987
1988 stats->rx_dropped += stats->rx_missed_errors;
1989 }
1990
gmac_change_mtu(struct net_device * netdev,int new_mtu)1991 static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
1992 {
1993 int max_len = gmac_pick_rx_max_len(new_mtu);
1994
1995 if (max_len < 0)
1996 return -EINVAL;
1997
1998 gmac_disable_tx_rx(netdev);
1999
2000 netdev->mtu = new_mtu;
2001 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
2002 CONFIG0_MAXLEN_MASK);
2003
2004 netdev_update_features(netdev);
2005
2006 gmac_enable_tx_rx(netdev);
2007
2008 return 0;
2009 }
2010
gmac_set_features(struct net_device * netdev,netdev_features_t features)2011 static int gmac_set_features(struct net_device *netdev,
2012 netdev_features_t features)
2013 {
2014 struct gemini_ethernet_port *port = netdev_priv(netdev);
2015 int enable = features & NETIF_F_RXCSUM;
2016 unsigned long flags;
2017 u32 reg;
2018
2019 spin_lock_irqsave(&port->config_lock, flags);
2020
2021 reg = readl(port->gmac_base + GMAC_CONFIG0);
2022 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
2023 writel(reg, port->gmac_base + GMAC_CONFIG0);
2024
2025 spin_unlock_irqrestore(&port->config_lock, flags);
2026 return 0;
2027 }
2028
gmac_get_sset_count(struct net_device * netdev,int sset)2029 static int gmac_get_sset_count(struct net_device *netdev, int sset)
2030 {
2031 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
2032 }
2033
gmac_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2034 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2035 {
2036 if (stringset != ETH_SS_STATS)
2037 return;
2038
2039 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
2040 }
2041
gmac_get_ethtool_stats(struct net_device * netdev,struct ethtool_stats * estats,u64 * values)2042 static void gmac_get_ethtool_stats(struct net_device *netdev,
2043 struct ethtool_stats *estats, u64 *values)
2044 {
2045 struct gemini_ethernet_port *port = netdev_priv(netdev);
2046 unsigned int start;
2047 u64 *p;
2048 int i;
2049
2050 gmac_update_hw_stats(netdev);
2051
2052 /* Racing with MIB interrupt */
2053 do {
2054 p = values;
2055 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
2056
2057 for (i = 0; i < RX_STATS_NUM; i++)
2058 *p++ = port->hw_stats[i];
2059
2060 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
2061 values = p;
2062
2063 /* Racing with RX NAPI */
2064 do {
2065 p = values;
2066 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
2067
2068 for (i = 0; i < RX_STATUS_NUM; i++)
2069 *p++ = port->rx_stats[i];
2070 for (i = 0; i < RX_CHKSUM_NUM; i++)
2071 *p++ = port->rx_csum_stats[i];
2072 *p++ = port->rx_napi_exits;
2073
2074 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
2075 values = p;
2076
2077 /* Racing with TX start_xmit */
2078 do {
2079 p = values;
2080 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
2081
2082 for (i = 0; i < TX_MAX_FRAGS; i++) {
2083 *values++ = port->tx_frag_stats[i];
2084 port->tx_frag_stats[i] = 0;
2085 }
2086 *values++ = port->tx_frags_linearized;
2087 *values++ = port->tx_hw_csummed;
2088
2089 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
2090 }
2091
gmac_get_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)2092 static int gmac_get_ksettings(struct net_device *netdev,
2093 struct ethtool_link_ksettings *cmd)
2094 {
2095 if (!netdev->phydev)
2096 return -ENXIO;
2097 phy_ethtool_ksettings_get(netdev->phydev, cmd);
2098
2099 return 0;
2100 }
2101
gmac_set_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * cmd)2102 static int gmac_set_ksettings(struct net_device *netdev,
2103 const struct ethtool_link_ksettings *cmd)
2104 {
2105 if (!netdev->phydev)
2106 return -ENXIO;
2107 return phy_ethtool_ksettings_set(netdev->phydev, cmd);
2108 }
2109
gmac_nway_reset(struct net_device * netdev)2110 static int gmac_nway_reset(struct net_device *netdev)
2111 {
2112 if (!netdev->phydev)
2113 return -ENXIO;
2114 return phy_start_aneg(netdev->phydev);
2115 }
2116
gmac_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pparam)2117 static void gmac_get_pauseparam(struct net_device *netdev,
2118 struct ethtool_pauseparam *pparam)
2119 {
2120 struct gemini_ethernet_port *port = netdev_priv(netdev);
2121 union gmac_config0 config0;
2122
2123 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2124
2125 pparam->rx_pause = config0.bits.rx_fc_en;
2126 pparam->tx_pause = config0.bits.tx_fc_en;
2127 pparam->autoneg = true;
2128 }
2129
gmac_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * rp,struct kernel_ethtool_ringparam * kernel_rp,struct netlink_ext_ack * extack)2130 static void gmac_get_ringparam(struct net_device *netdev,
2131 struct ethtool_ringparam *rp,
2132 struct kernel_ethtool_ringparam *kernel_rp,
2133 struct netlink_ext_ack *extack)
2134 {
2135 struct gemini_ethernet_port *port = netdev_priv(netdev);
2136
2137 readl(port->gmac_base + GMAC_CONFIG0);
2138
2139 rp->rx_max_pending = 1 << 15;
2140 rp->rx_mini_max_pending = 0;
2141 rp->rx_jumbo_max_pending = 0;
2142 rp->tx_max_pending = 1 << 15;
2143
2144 rp->rx_pending = 1 << port->rxq_order;
2145 rp->rx_mini_pending = 0;
2146 rp->rx_jumbo_pending = 0;
2147 rp->tx_pending = 1 << port->txq_order;
2148 }
2149
gmac_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * rp,struct kernel_ethtool_ringparam * kernel_rp,struct netlink_ext_ack * extack)2150 static int gmac_set_ringparam(struct net_device *netdev,
2151 struct ethtool_ringparam *rp,
2152 struct kernel_ethtool_ringparam *kernel_rp,
2153 struct netlink_ext_ack *extack)
2154 {
2155 struct gemini_ethernet_port *port = netdev_priv(netdev);
2156 int err = 0;
2157
2158 if (netif_running(netdev))
2159 return -EBUSY;
2160
2161 if (rp->rx_pending) {
2162 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2163 err = geth_resize_freeq(port);
2164 }
2165 if (rp->tx_pending) {
2166 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2167 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
2168 }
2169
2170 return err;
2171 }
2172
gmac_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * ecmd,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)2173 static int gmac_get_coalesce(struct net_device *netdev,
2174 struct ethtool_coalesce *ecmd,
2175 struct kernel_ethtool_coalesce *kernel_coal,
2176 struct netlink_ext_ack *extack)
2177 {
2178 struct gemini_ethernet_port *port = netdev_priv(netdev);
2179
2180 ecmd->rx_max_coalesced_frames = 1;
2181 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
2182 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
2183
2184 return 0;
2185 }
2186
gmac_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * ecmd,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)2187 static int gmac_set_coalesce(struct net_device *netdev,
2188 struct ethtool_coalesce *ecmd,
2189 struct kernel_ethtool_coalesce *kernel_coal,
2190 struct netlink_ext_ack *extack)
2191 {
2192 struct gemini_ethernet_port *port = netdev_priv(netdev);
2193
2194 if (ecmd->tx_max_coalesced_frames < 1)
2195 return -EINVAL;
2196 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
2197 return -EINVAL;
2198
2199 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2200 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2201
2202 return 0;
2203 }
2204
gmac_get_msglevel(struct net_device * netdev)2205 static u32 gmac_get_msglevel(struct net_device *netdev)
2206 {
2207 struct gemini_ethernet_port *port = netdev_priv(netdev);
2208
2209 return port->msg_enable;
2210 }
2211
gmac_set_msglevel(struct net_device * netdev,u32 level)2212 static void gmac_set_msglevel(struct net_device *netdev, u32 level)
2213 {
2214 struct gemini_ethernet_port *port = netdev_priv(netdev);
2215
2216 port->msg_enable = level;
2217 }
2218
gmac_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * info)2219 static void gmac_get_drvinfo(struct net_device *netdev,
2220 struct ethtool_drvinfo *info)
2221 {
2222 strcpy(info->driver, DRV_NAME);
2223 strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
2224 }
2225
2226 static const struct net_device_ops gmac_351x_ops = {
2227 .ndo_init = gmac_init,
2228 .ndo_open = gmac_open,
2229 .ndo_stop = gmac_stop,
2230 .ndo_start_xmit = gmac_start_xmit,
2231 .ndo_tx_timeout = gmac_tx_timeout,
2232 .ndo_set_rx_mode = gmac_set_rx_mode,
2233 .ndo_set_mac_address = gmac_set_mac_address,
2234 .ndo_get_stats64 = gmac_get_stats64,
2235 .ndo_change_mtu = gmac_change_mtu,
2236 .ndo_set_features = gmac_set_features,
2237 };
2238
2239 static const struct ethtool_ops gmac_351x_ethtool_ops = {
2240 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
2241 ETHTOOL_COALESCE_MAX_FRAMES,
2242 .get_sset_count = gmac_get_sset_count,
2243 .get_strings = gmac_get_strings,
2244 .get_ethtool_stats = gmac_get_ethtool_stats,
2245 .get_link = ethtool_op_get_link,
2246 .get_link_ksettings = gmac_get_ksettings,
2247 .set_link_ksettings = gmac_set_ksettings,
2248 .nway_reset = gmac_nway_reset,
2249 .get_pauseparam = gmac_get_pauseparam,
2250 .get_ringparam = gmac_get_ringparam,
2251 .set_ringparam = gmac_set_ringparam,
2252 .get_coalesce = gmac_get_coalesce,
2253 .set_coalesce = gmac_set_coalesce,
2254 .get_msglevel = gmac_get_msglevel,
2255 .set_msglevel = gmac_set_msglevel,
2256 .get_drvinfo = gmac_get_drvinfo,
2257 };
2258
gemini_port_irq_thread(int irq,void * data)2259 static irqreturn_t gemini_port_irq_thread(int irq, void *data)
2260 {
2261 unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2262 struct gemini_ethernet_port *port = data;
2263 struct gemini_ethernet *geth;
2264 unsigned long flags;
2265
2266 geth = port->geth;
2267 /* The queue is half empty so refill it */
2268 geth_fill_freeq(geth, true);
2269
2270 spin_lock_irqsave(&geth->irq_lock, flags);
2271 /* ACK queue interrupt */
2272 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2273 /* Enable queue interrupt again */
2274 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2275 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2276 spin_unlock_irqrestore(&geth->irq_lock, flags);
2277
2278 return IRQ_HANDLED;
2279 }
2280
gemini_port_irq(int irq,void * data)2281 static irqreturn_t gemini_port_irq(int irq, void *data)
2282 {
2283 struct gemini_ethernet_port *port = data;
2284 struct gemini_ethernet *geth;
2285 irqreturn_t ret = IRQ_NONE;
2286 u32 val, en;
2287
2288 geth = port->geth;
2289 spin_lock(&geth->irq_lock);
2290
2291 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2292 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2293
2294 if (val & en & SWFQ_EMPTY_INT_BIT) {
2295 /* Disable the queue empty interrupt while we work on
2296 * processing the queue. Also disable overrun interrupts
2297 * as there is not much we can do about it here.
2298 */
2299 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2300 | GMAC1_RX_OVERRUN_INT_BIT);
2301 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2302 ret = IRQ_WAKE_THREAD;
2303 }
2304
2305 spin_unlock(&geth->irq_lock);
2306
2307 return ret;
2308 }
2309
gemini_port_remove(struct gemini_ethernet_port * port)2310 static void gemini_port_remove(struct gemini_ethernet_port *port)
2311 {
2312 if (port->netdev) {
2313 phy_disconnect(port->netdev->phydev);
2314 unregister_netdev(port->netdev);
2315 }
2316 clk_disable_unprepare(port->pclk);
2317 geth_cleanup_freeq(port->geth);
2318 }
2319
gemini_ethernet_init(struct gemini_ethernet * geth)2320 static void gemini_ethernet_init(struct gemini_ethernet *geth)
2321 {
2322 /* Only do this once both ports are online */
2323 if (geth->initialized)
2324 return;
2325 if (geth->port0 && geth->port1)
2326 geth->initialized = true;
2327 else
2328 return;
2329
2330 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
2331 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
2332 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
2333 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
2334 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2335
2336 /* Interrupt config:
2337 *
2338 * GMAC0 intr bits ------> int0 ----> eth0
2339 * GMAC1 intr bits ------> int1 ----> eth1
2340 * TOE intr -------------> int1 ----> eth1
2341 * Classification Intr --> int0 ----> eth0
2342 * Default Q0 -----------> int0 ----> eth0
2343 * Default Q1 -----------> int1 ----> eth1
2344 * FreeQ intr -----------> int1 ----> eth1
2345 */
2346 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
2347 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
2348 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
2349 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
2350 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
2351
2352 /* edge-triggered interrupts packed to level-triggered one... */
2353 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
2354 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
2355 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
2356 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
2357 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2358
2359 /* Set up queue */
2360 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2361 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2362 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
2363 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
2364
2365 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2366 /* This makes the queue resize on probe() so that we
2367 * set up and enable the queue IRQ. FIXME: fragile.
2368 */
2369 geth->freeq_order = 1;
2370 }
2371
gemini_port_save_mac_addr(struct gemini_ethernet_port * port)2372 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
2373 {
2374 port->mac_addr[0] =
2375 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
2376 port->mac_addr[1] =
2377 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
2378 port->mac_addr[2] =
2379 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
2380 }
2381
gemini_ethernet_port_probe(struct platform_device * pdev)2382 static int gemini_ethernet_port_probe(struct platform_device *pdev)
2383 {
2384 char *port_names[2] = { "ethernet0", "ethernet1" };
2385 struct device_node *np = pdev->dev.of_node;
2386 struct gemini_ethernet_port *port;
2387 struct device *dev = &pdev->dev;
2388 struct gemini_ethernet *geth;
2389 struct net_device *netdev;
2390 struct device *parent;
2391 u8 mac[ETH_ALEN];
2392 unsigned int id;
2393 int irq;
2394 int ret;
2395
2396 parent = dev->parent;
2397 geth = dev_get_drvdata(parent);
2398
2399 if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
2400 id = 0;
2401 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
2402 id = 1;
2403 else
2404 return -ENODEV;
2405
2406 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
2407
2408 netdev = devm_alloc_etherdev_mqs(dev, sizeof(*port), TX_QUEUE_NUM, TX_QUEUE_NUM);
2409 if (!netdev) {
2410 dev_err(dev, "Can't allocate ethernet device #%d\n", id);
2411 return -ENOMEM;
2412 }
2413
2414 port = netdev_priv(netdev);
2415 SET_NETDEV_DEV(netdev, dev);
2416 port->netdev = netdev;
2417 port->id = id;
2418 port->geth = geth;
2419 port->dev = dev;
2420 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2421
2422 /* DMA memory */
2423 port->dma_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
2424 if (IS_ERR(port->dma_base)) {
2425 dev_err(dev, "get DMA address failed\n");
2426 return PTR_ERR(port->dma_base);
2427 }
2428
2429 /* GMAC config memory */
2430 port->gmac_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
2431 if (IS_ERR(port->gmac_base)) {
2432 dev_err(dev, "get GMAC address failed\n");
2433 return PTR_ERR(port->gmac_base);
2434 }
2435
2436 /* Interrupt */
2437 irq = platform_get_irq(pdev, 0);
2438 if (irq < 0)
2439 return irq;
2440 port->irq = irq;
2441
2442 /* Clock the port */
2443 port->pclk = devm_clk_get(dev, "PCLK");
2444 if (IS_ERR(port->pclk)) {
2445 dev_err(dev, "no PCLK\n");
2446 return PTR_ERR(port->pclk);
2447 }
2448 ret = clk_prepare_enable(port->pclk);
2449 if (ret)
2450 return ret;
2451
2452 /* Maybe there is a nice ethernet address we should use */
2453 gemini_port_save_mac_addr(port);
2454
2455 /* Reset the port */
2456 port->reset = devm_reset_control_get_exclusive(dev, NULL);
2457 if (IS_ERR(port->reset)) {
2458 dev_err(dev, "no reset\n");
2459 ret = PTR_ERR(port->reset);
2460 goto unprepare;
2461 }
2462 reset_control_reset(port->reset);
2463 usleep_range(100, 500);
2464
2465 /* Assign pointer in the main state container */
2466 if (!id)
2467 geth->port0 = port;
2468 else
2469 geth->port1 = port;
2470
2471 /* This will just be done once both ports are up and reset */
2472 gemini_ethernet_init(geth);
2473
2474 platform_set_drvdata(pdev, port);
2475
2476 /* Set up and register the netdev */
2477 netdev->dev_id = port->id;
2478 netdev->irq = irq;
2479 netdev->netdev_ops = &gmac_351x_ops;
2480 netdev->ethtool_ops = &gmac_351x_ethtool_ops;
2481
2482 spin_lock_init(&port->config_lock);
2483 gmac_clear_hw_stats(netdev);
2484
2485 netdev->hw_features = GMAC_OFFLOAD_FEATURES;
2486 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2487 /* We can receive jumbo frames up to 10236 bytes but only
2488 * transmit 2047 bytes so, let's accept payloads of 2047
2489 * bytes minus VLAN and ethernet header
2490 */
2491 netdev->min_mtu = ETH_MIN_MTU;
2492 netdev->max_mtu = MTU_SIZE_BIT_MASK - VLAN_ETH_HLEN;
2493
2494 port->freeq_refill = 0;
2495 netif_napi_add(netdev, &port->napi, gmac_napi_poll);
2496
2497 ret = of_get_mac_address(np, mac);
2498 if (!ret) {
2499 dev_info(dev, "Setting macaddr from DT %pM\n", mac);
2500 memcpy(port->mac_addr, mac, ETH_ALEN);
2501 }
2502
2503 if (is_valid_ether_addr((void *)port->mac_addr)) {
2504 eth_hw_addr_set(netdev, (u8 *)port->mac_addr);
2505 } else {
2506 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
2507 port->mac_addr[0], port->mac_addr[1],
2508 port->mac_addr[2]);
2509 dev_info(dev, "using a random ethernet address\n");
2510 eth_hw_addr_random(netdev);
2511 }
2512 gmac_write_mac_address(netdev);
2513
2514 ret = devm_request_threaded_irq(port->dev,
2515 port->irq,
2516 gemini_port_irq,
2517 gemini_port_irq_thread,
2518 IRQF_SHARED,
2519 port_names[port->id],
2520 port);
2521 if (ret)
2522 goto unprepare;
2523
2524 ret = gmac_setup_phy(netdev);
2525 if (ret) {
2526 netdev_err(netdev,
2527 "PHY init failed\n");
2528 goto unprepare;
2529 }
2530
2531 ret = register_netdev(netdev);
2532 if (ret)
2533 goto unprepare;
2534
2535 return 0;
2536
2537 unprepare:
2538 clk_disable_unprepare(port->pclk);
2539 return ret;
2540 }
2541
gemini_ethernet_port_remove(struct platform_device * pdev)2542 static int gemini_ethernet_port_remove(struct platform_device *pdev)
2543 {
2544 struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
2545
2546 gemini_port_remove(port);
2547
2548 return 0;
2549 }
2550
2551 static const struct of_device_id gemini_ethernet_port_of_match[] = {
2552 {
2553 .compatible = "cortina,gemini-ethernet-port",
2554 },
2555 {},
2556 };
2557 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
2558
2559 static struct platform_driver gemini_ethernet_port_driver = {
2560 .driver = {
2561 .name = "gemini-ethernet-port",
2562 .of_match_table = gemini_ethernet_port_of_match,
2563 },
2564 .probe = gemini_ethernet_port_probe,
2565 .remove = gemini_ethernet_port_remove,
2566 };
2567
gemini_ethernet_probe(struct platform_device * pdev)2568 static int gemini_ethernet_probe(struct platform_device *pdev)
2569 {
2570 struct device *dev = &pdev->dev;
2571 struct gemini_ethernet *geth;
2572 unsigned int retry = 5;
2573 u32 val;
2574
2575 /* Global registers */
2576 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
2577 if (!geth)
2578 return -ENOMEM;
2579 geth->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
2580 if (IS_ERR(geth->base))
2581 return PTR_ERR(geth->base);
2582 geth->dev = dev;
2583
2584 /* Wait for ports to stabilize */
2585 do {
2586 udelay(2);
2587 val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
2588 barrier();
2589 } while (!val && --retry);
2590 if (!retry) {
2591 dev_err(dev, "failed to reset ethernet\n");
2592 return -EIO;
2593 }
2594 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
2595 (val >> 4) & 0xFFFU, val & 0xFU);
2596
2597 spin_lock_init(&geth->irq_lock);
2598 spin_lock_init(&geth->freeq_lock);
2599
2600 /* The children will use this */
2601 platform_set_drvdata(pdev, geth);
2602
2603 /* Spawn child devices for the two ports */
2604 return devm_of_platform_populate(dev);
2605 }
2606
gemini_ethernet_remove(struct platform_device * pdev)2607 static int gemini_ethernet_remove(struct platform_device *pdev)
2608 {
2609 struct gemini_ethernet *geth = platform_get_drvdata(pdev);
2610
2611 geth_cleanup_freeq(geth);
2612 geth->initialized = false;
2613
2614 return 0;
2615 }
2616
2617 static const struct of_device_id gemini_ethernet_of_match[] = {
2618 {
2619 .compatible = "cortina,gemini-ethernet",
2620 },
2621 {},
2622 };
2623 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
2624
2625 static struct platform_driver gemini_ethernet_driver = {
2626 .driver = {
2627 .name = DRV_NAME,
2628 .of_match_table = gemini_ethernet_of_match,
2629 },
2630 .probe = gemini_ethernet_probe,
2631 .remove = gemini_ethernet_remove,
2632 };
2633
gemini_ethernet_module_init(void)2634 static int __init gemini_ethernet_module_init(void)
2635 {
2636 int ret;
2637
2638 ret = platform_driver_register(&gemini_ethernet_port_driver);
2639 if (ret)
2640 return ret;
2641
2642 ret = platform_driver_register(&gemini_ethernet_driver);
2643 if (ret) {
2644 platform_driver_unregister(&gemini_ethernet_port_driver);
2645 return ret;
2646 }
2647
2648 return 0;
2649 }
2650 module_init(gemini_ethernet_module_init);
2651
gemini_ethernet_module_exit(void)2652 static void __exit gemini_ethernet_module_exit(void)
2653 {
2654 platform_driver_unregister(&gemini_ethernet_driver);
2655 platform_driver_unregister(&gemini_ethernet_port_driver);
2656 }
2657 module_exit(gemini_ethernet_module_exit);
2658
2659 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2660 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
2661 MODULE_LICENSE("GPL");
2662 MODULE_ALIAS("platform:" DRV_NAME);
2663