1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AM33XX Arch Power Management Routines
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
6 * Dave Gerlach
7 */
8
9 #include <linux/cpuidle.h>
10 #include <linux/platform_data/pm33xx.h>
11 #include <linux/suspend.h>
12 #include <asm/cpuidle.h>
13 #include <asm/smp_scu.h>
14 #include <asm/suspend.h>
15 #include <linux/errno.h>
16 #include <linux/clk.h>
17 #include <linux/cpu.h>
18 #include <linux/platform_data/gpio-omap.h>
19 #include <linux/wkup_m3_ipc.h>
20 #include <linux/of.h>
21 #include <linux/rtc.h>
22
23 #include "cm33xx.h"
24 #include "common.h"
25 #include "control.h"
26 #include "clockdomain.h"
27 #include "iomap.h"
28 #include "pm.h"
29 #include "powerdomain.h"
30 #include "prm33xx.h"
31 #include "soc.h"
32 #include "sram.h"
33 #include "omap-secure.h"
34
35 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
36 static struct clockdomain *gfx_l4ls_clkdm;
37 static void __iomem *scu_base;
38
39 static int (*idle_fn)(u32 wfi_flags);
40
41 struct amx3_idle_state {
42 int wfi_flags;
43 };
44
45 static struct amx3_idle_state *idle_states;
46
am43xx_map_scu(void)47 static int am43xx_map_scu(void)
48 {
49 scu_base = ioremap(scu_a9_get_base(), SZ_256);
50
51 if (!scu_base)
52 return -ENOMEM;
53
54 return 0;
55 }
56
am33xx_check_off_mode_enable(void)57 static int am33xx_check_off_mode_enable(void)
58 {
59 if (enable_off_mode)
60 pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n");
61
62 /* off mode not supported on am335x so return 0 always */
63 return 0;
64 }
65
am43xx_check_off_mode_enable(void)66 static int am43xx_check_off_mode_enable(void)
67 {
68 /*
69 * Check for am437x-gp-evm which has the right Hardware design to
70 * support this mode reliably.
71 */
72 if (of_machine_is_compatible("ti,am437x-gp-evm") && enable_off_mode)
73 return enable_off_mode;
74 else if (enable_off_mode)
75 pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n");
76
77 return 0;
78 }
79
amx3_common_init(int (* idle)(u32 wfi_flags))80 static int amx3_common_init(int (*idle)(u32 wfi_flags))
81 {
82 gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
83 per_pwrdm = pwrdm_lookup("per_pwrdm");
84 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
85
86 if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm))
87 return -ENODEV;
88
89 (void)clkdm_for_each(omap_pm_clkdms_setup, NULL);
90
91 /* CEFUSE domain can be turned off post bootup */
92 cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
93 if (!cefuse_pwrdm)
94 pr_err("PM: Failed to get cefuse_pwrdm\n");
95 else if (omap_type() != OMAP2_DEVICE_TYPE_GP)
96 pr_info("PM: Leaving EFUSE power domain active\n");
97 else
98 omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
99
100 idle_fn = idle;
101
102 return 0;
103 }
104
am33xx_suspend_init(int (* idle)(u32 wfi_flags))105 static int am33xx_suspend_init(int (*idle)(u32 wfi_flags))
106 {
107 gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
108
109 if (!gfx_l4ls_clkdm) {
110 pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n");
111 return -ENODEV;
112 }
113
114 return amx3_common_init(idle);
115 }
116
am43xx_suspend_init(int (* idle)(u32 wfi_flags))117 static int am43xx_suspend_init(int (*idle)(u32 wfi_flags))
118 {
119 int ret = 0;
120
121 ret = am43xx_map_scu();
122 if (ret) {
123 pr_err("PM: Could not ioremap SCU\n");
124 return ret;
125 }
126
127 ret = amx3_common_init(idle);
128
129 return ret;
130 }
131
amx3_suspend_deinit(void)132 static int amx3_suspend_deinit(void)
133 {
134 idle_fn = NULL;
135 return 0;
136 }
137
amx3_pre_suspend_common(void)138 static void amx3_pre_suspend_common(void)
139 {
140 omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
141 }
142
amx3_post_suspend_common(void)143 static void amx3_post_suspend_common(void)
144 {
145 int status;
146 /*
147 * Because gfx_pwrdm is the only one under MPU control,
148 * comment on transition status
149 */
150 status = pwrdm_read_pwrst(gfx_pwrdm);
151 if (status != PWRDM_POWER_OFF)
152 pr_err("PM: GFX domain did not transition: %x\n", status);
153 }
154
am33xx_suspend(unsigned int state,int (* fn)(unsigned long),unsigned long args)155 static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long),
156 unsigned long args)
157 {
158 int ret = 0;
159
160 amx3_pre_suspend_common();
161 ret = cpu_suspend(args, fn);
162 amx3_post_suspend_common();
163
164 /*
165 * BUG: GFX_L4LS clock domain needs to be woken up to
166 * ensure thet L4LS clock domain does not get stuck in
167 * transition. If that happens L3 module does not get
168 * disabled, thereby leading to PER power domain
169 * transition failing
170 */
171
172 clkdm_wakeup(gfx_l4ls_clkdm);
173 clkdm_sleep(gfx_l4ls_clkdm);
174
175 return ret;
176 }
177
am43xx_suspend(unsigned int state,int (* fn)(unsigned long),unsigned long args)178 static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long),
179 unsigned long args)
180 {
181 int ret = 0;
182
183 /* Suspend secure side on HS devices */
184 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
185 if (optee_available)
186 omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0);
187 else
188 omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND,
189 FLAG_START_CRITICAL,
190 0, 0, 0, 0, 0);
191 }
192
193 amx3_pre_suspend_common();
194 scu_power_mode(scu_base, SCU_PM_POWEROFF);
195 ret = cpu_suspend(args, fn);
196 scu_power_mode(scu_base, SCU_PM_NORMAL);
197
198 if (!am43xx_check_off_mode_enable())
199 amx3_post_suspend_common();
200
201 /*
202 * Resume secure side on HS devices.
203 *
204 * Note that even on systems with OP-TEE available this resume call is
205 * issued to the ROM. This is because upon waking from suspend the ROM
206 * is restored as the secure monitor. On systems with OP-TEE ROM will
207 * restore OP-TEE during this call.
208 */
209 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
210 omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME,
211 FLAG_START_CRITICAL,
212 0, 0, 0, 0, 0);
213
214 return ret;
215 }
216
am33xx_cpu_suspend(int (* fn)(unsigned long),unsigned long args)217 static int am33xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
218 {
219 int ret = 0;
220
221 if (omap_irq_pending() || need_resched())
222 return ret;
223
224 ret = cpu_suspend(args, fn);
225
226 return ret;
227 }
228
am43xx_cpu_suspend(int (* fn)(unsigned long),unsigned long args)229 static int am43xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
230 {
231 int ret = 0;
232
233 if (!scu_base)
234 return 0;
235
236 scu_power_mode(scu_base, SCU_PM_DORMANT);
237 ret = cpu_suspend(args, fn);
238 scu_power_mode(scu_base, SCU_PM_NORMAL);
239
240 return ret;
241 }
242
amx3_begin_suspend(void)243 static void amx3_begin_suspend(void)
244 {
245 cpu_idle_poll_ctrl(true);
246 }
247
amx3_finish_suspend(void)248 static void amx3_finish_suspend(void)
249 {
250 cpu_idle_poll_ctrl(false);
251 }
252
253
amx3_get_sram_addrs(void)254 static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
255 {
256 if (soc_is_am33xx())
257 return &am33xx_pm_sram;
258 else if (soc_is_am437x())
259 return &am43xx_pm_sram;
260 else
261 return NULL;
262 }
263
am43xx_save_context(void)264 static void am43xx_save_context(void)
265 {
266 }
267
am33xx_save_context(void)268 static void am33xx_save_context(void)
269 {
270 omap_intc_save_context();
271 }
272
am33xx_restore_context(void)273 static void am33xx_restore_context(void)
274 {
275 omap_intc_restore_context();
276 }
277
am43xx_restore_context(void)278 static void am43xx_restore_context(void)
279 {
280 /*
281 * HACK: restore dpll_per_clkdcoldo register contents, to avoid
282 * breaking suspend-resume
283 */
284 writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
285 }
286
287 static struct am33xx_pm_platform_data am33xx_ops = {
288 .init = am33xx_suspend_init,
289 .deinit = amx3_suspend_deinit,
290 .soc_suspend = am33xx_suspend,
291 .cpu_suspend = am33xx_cpu_suspend,
292 .begin_suspend = amx3_begin_suspend,
293 .finish_suspend = amx3_finish_suspend,
294 .get_sram_addrs = amx3_get_sram_addrs,
295 .save_context = am33xx_save_context,
296 .restore_context = am33xx_restore_context,
297 .check_off_mode_enable = am33xx_check_off_mode_enable,
298 };
299
300 static struct am33xx_pm_platform_data am43xx_ops = {
301 .init = am43xx_suspend_init,
302 .deinit = amx3_suspend_deinit,
303 .soc_suspend = am43xx_suspend,
304 .cpu_suspend = am43xx_cpu_suspend,
305 .begin_suspend = amx3_begin_suspend,
306 .finish_suspend = amx3_finish_suspend,
307 .get_sram_addrs = amx3_get_sram_addrs,
308 .save_context = am43xx_save_context,
309 .restore_context = am43xx_restore_context,
310 .check_off_mode_enable = am43xx_check_off_mode_enable,
311 };
312
am33xx_pm_get_pdata(void)313 static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
314 {
315 if (soc_is_am33xx())
316 return &am33xx_ops;
317 else if (soc_is_am437x())
318 return &am43xx_ops;
319 else
320 return NULL;
321 }
322
323 #ifdef CONFIG_SUSPEND
324 /*
325 * Block system suspend initially. Later on pm33xx sets up it's own
326 * platform_suspend_ops after probe. That depends also on loaded
327 * wkup_m3_ipc and booted am335x-pm-firmware.elf.
328 */
amx3_suspend_block(suspend_state_t state)329 static int amx3_suspend_block(suspend_state_t state)
330 {
331 pr_warn("PM not initialized for pm33xx, wkup_m3_ipc, or am335x-pm-firmware.elf\n");
332
333 return -EINVAL;
334 }
335
amx3_pm_valid(suspend_state_t state)336 static int amx3_pm_valid(suspend_state_t state)
337 {
338 switch (state) {
339 case PM_SUSPEND_STANDBY:
340 return 1;
341 default:
342 return 0;
343 }
344 }
345
346 static const struct platform_suspend_ops amx3_blocked_pm_ops = {
347 .begin = amx3_suspend_block,
348 .valid = amx3_pm_valid,
349 };
350
amx3_block_suspend(void)351 static void __init amx3_block_suspend(void)
352 {
353 suspend_set_ops(&amx3_blocked_pm_ops);
354 }
355 #else
amx3_block_suspend(void)356 static inline void amx3_block_suspend(void)
357 {
358 }
359 #endif /* CONFIG_SUSPEND */
360
amx3_common_pm_init(void)361 int __init amx3_common_pm_init(void)
362 {
363 struct am33xx_pm_platform_data *pdata;
364 struct platform_device_info devinfo;
365
366 pdata = am33xx_pm_get_pdata();
367
368 memset(&devinfo, 0, sizeof(devinfo));
369 devinfo.name = "pm33xx";
370 devinfo.data = pdata;
371 devinfo.size_data = sizeof(*pdata);
372 devinfo.id = -1;
373 platform_device_register_full(&devinfo);
374 amx3_block_suspend();
375
376 return 0;
377 }
378
amx3_idle_init(struct device_node * cpu_node,int cpu)379 static int __init amx3_idle_init(struct device_node *cpu_node, int cpu)
380 {
381 struct device_node *state_node;
382 struct amx3_idle_state states[CPUIDLE_STATE_MAX];
383 int i;
384 int state_count = 1;
385
386 for (i = 0; ; i++) {
387 state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
388 if (!state_node)
389 break;
390
391 if (!of_device_is_available(state_node))
392 continue;
393
394 if (i == CPUIDLE_STATE_MAX) {
395 pr_warn("%s: cpuidle states reached max possible\n",
396 __func__);
397 break;
398 }
399
400 states[state_count].wfi_flags = 0;
401
402 if (of_property_read_bool(state_node, "ti,idle-wkup-m3"))
403 states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 |
404 WFI_FLAG_FLUSH_CACHE;
405
406 state_count++;
407 }
408
409 idle_states = kcalloc(state_count, sizeof(*idle_states), GFP_KERNEL);
410 if (!idle_states)
411 return -ENOMEM;
412
413 for (i = 1; i < state_count; i++)
414 idle_states[i].wfi_flags = states[i].wfi_flags;
415
416 return 0;
417 }
418
amx3_idle_enter(unsigned long index)419 static int amx3_idle_enter(unsigned long index)
420 {
421 struct amx3_idle_state *idle_state = &idle_states[index];
422
423 if (!idle_state)
424 return -EINVAL;
425
426 if (idle_fn)
427 idle_fn(idle_state->wfi_flags);
428
429 return 0;
430 }
431
432 static struct cpuidle_ops amx3_cpuidle_ops __initdata = {
433 .init = amx3_idle_init,
434 .suspend = amx3_idle_enter,
435 };
436
437 CPUIDLE_METHOD_OF_DECLARE(pm33xx_idle, "ti,am3352", &amx3_cpuidle_ops);
438 CPUIDLE_METHOD_OF_DECLARE(pm43xx_idle, "ti,am4372", &amx3_cpuidle_ops);
439