1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Lineo, Inc. <www.lineo.com>
5 * Bernhard Kuhn <bkuhn@lineo.com>
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
10 *
11 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Alex Zuepke <azu@sysgo.de>
14 */
15
16 #include <common.h>
17
18 #include <asm/io.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/at91_tc.h>
21 #include <asm/arch/clk.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* the number of clocks per CONFIG_SYS_HZ */
26 #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
27
timer_init(void)28 int timer_init(void)
29 {
30 at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
31
32 at91_periph_clk_enable(ATMEL_ID_TC0);
33
34 writel(0, &tc->bcr);
35 writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
36 AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
37
38 writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
39 /* set to MCLK/2 and restart the timer
40 when the value in TC_RC is reached */
41 writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
42
43 writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
44 writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
45
46 writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
47 gd->arch.lastinc = 0;
48 gd->arch.tbl = 0;
49
50 return 0;
51 }
52
53 /*
54 * timer without interrupts
55 */
get_timer_raw(void)56 ulong get_timer_raw(void)
57 {
58 at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
59 u32 now;
60
61 now = readl(&tc->tc[0].cv) & 0x0000ffff;
62
63 if (now >= gd->arch.lastinc) {
64 /* normal mode */
65 gd->arch.tbl += now - gd->arch.lastinc;
66 } else {
67 /* we have an overflow ... */
68 gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
69 }
70 gd->arch.lastinc = now;
71
72 return gd->arch.tbl;
73 }
74
get_timer_masked(void)75 static ulong get_timer_masked(void)
76 {
77 return get_timer_raw()/TIMER_LOAD_VAL;
78 }
79
get_timer(ulong base)80 ulong get_timer(ulong base)
81 {
82 return get_timer_masked() - base;
83 }
84
__udelay(unsigned long usec)85 void __udelay(unsigned long usec)
86 {
87 u32 tmo;
88 u32 endtime;
89 signed long diff;
90
91 tmo = CONFIG_SYS_HZ_CLOCK / 1000;
92 tmo *= usec;
93 tmo /= 1000;
94
95 endtime = get_timer_raw() + tmo;
96
97 do {
98 u32 now = get_timer_raw();
99 diff = endtime - now;
100 } while (diff >= 0);
101 }
102
103 /*
104 * This function is derived from PowerPC code (read timebase as long long).
105 * On ARM it just returns the timer value.
106 */
get_ticks(void)107 unsigned long long get_ticks(void)
108 {
109 return get_timer(0);
110 }
111
112 /*
113 * This function is derived from PowerPC code (timebase clock frequency).
114 * On ARM it returns the number of timer ticks per second.
115 */
get_tbclk(void)116 ulong get_tbclk(void)
117 {
118 return CONFIG_SYS_HZ;
119 }
120