1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 
29 #include "dc_types.h"
30 #include "core_types.h"
31 
32 #include "include/grph_object_id.h"
33 #include "include/logger_interface.h"
34 
35 #include "dce_clock_source.h"
36 #include "clk_mgr.h"
37 
38 #include "reg_helper.h"
39 
40 #define REG(reg)\
41 	(clk_src->regs->reg)
42 
43 #define CTX \
44 	clk_src->base.ctx
45 
46 #define DC_LOGGER_INIT()
47 
48 #undef FN
49 #define FN(reg_name, field_name) \
50 	clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
51 
52 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
53 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
54 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF
55 
56 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
57 
get_ss_data_entry(struct dce110_clk_src * clk_src,enum signal_type signal,uint32_t pix_clk_khz)58 static const struct spread_spectrum_data *get_ss_data_entry(
59 		struct dce110_clk_src *clk_src,
60 		enum signal_type signal,
61 		uint32_t pix_clk_khz)
62 {
63 
64 	uint32_t entrys_num;
65 	uint32_t i;
66 	struct spread_spectrum_data *ss_parm = NULL;
67 	struct spread_spectrum_data *ret = NULL;
68 
69 	switch (signal) {
70 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
71 	case SIGNAL_TYPE_DVI_DUAL_LINK:
72 		ss_parm = clk_src->dvi_ss_params;
73 		entrys_num = clk_src->dvi_ss_params_cnt;
74 		break;
75 
76 	case SIGNAL_TYPE_HDMI_TYPE_A:
77 		ss_parm = clk_src->hdmi_ss_params;
78 		entrys_num = clk_src->hdmi_ss_params_cnt;
79 		break;
80 
81 	case SIGNAL_TYPE_LVDS:
82 		ss_parm = clk_src->lvds_ss_params;
83 		entrys_num = clk_src->lvds_ss_params_cnt;
84 		break;
85 
86 	case SIGNAL_TYPE_DISPLAY_PORT:
87 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
88 	case SIGNAL_TYPE_EDP:
89 	case SIGNAL_TYPE_VIRTUAL:
90 		ss_parm = clk_src->dp_ss_params;
91 		entrys_num = clk_src->dp_ss_params_cnt;
92 		break;
93 
94 	default:
95 		ss_parm = NULL;
96 		entrys_num = 0;
97 		break;
98 	}
99 
100 	if (ss_parm == NULL)
101 		return ret;
102 
103 	for (i = 0; i < entrys_num; ++i, ++ss_parm) {
104 		if (ss_parm->freq_range_khz >= pix_clk_khz) {
105 			ret = ss_parm;
106 			break;
107 		}
108 	}
109 
110 	return ret;
111 }
112 
113 /**
114  * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional
115  *                                          feedback dividers values
116  *
117  * @calc_pll_cs:	    Pointer to clock source information
118  * @target_pix_clk_100hz:   Desired frequency in 100 Hz
119  * @ref_divider:            Reference divider (already known)
120  * @post_divider:           Post Divider (already known)
121  * @feedback_divider_param: Pointer where to store
122  *			    calculated feedback divider value
123  * @fract_feedback_divider_param: Pointer where to store
124  *			    calculated fract feedback divider value
125  *
126  * return:
127  * It fills the locations pointed by feedback_divider_param
128  *					and fract_feedback_divider_param
129  * It returns	- true if feedback divider not 0
130  *		- false should never happen)
131  */
calculate_fb_and_fractional_fb_divider(struct calc_pll_clock_source * calc_pll_cs,uint32_t target_pix_clk_100hz,uint32_t ref_divider,uint32_t post_divider,uint32_t * feedback_divider_param,uint32_t * fract_feedback_divider_param)132 static bool calculate_fb_and_fractional_fb_divider(
133 		struct calc_pll_clock_source *calc_pll_cs,
134 		uint32_t target_pix_clk_100hz,
135 		uint32_t ref_divider,
136 		uint32_t post_divider,
137 		uint32_t *feedback_divider_param,
138 		uint32_t *fract_feedback_divider_param)
139 {
140 	uint64_t feedback_divider;
141 
142 	feedback_divider =
143 		(uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
144 	feedback_divider *= 10;
145 	/* additional factor, since we divide by 10 afterwards */
146 	feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
147 	feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
148 
149 /*Round to the number of precision
150  * The following code replace the old code (ullfeedbackDivider + 5)/10
151  * for example if the difference between the number
152  * of fractional feedback decimal point and the fractional FB Divider precision
153  * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
154 
155 	feedback_divider += 5ULL *
156 			    calc_pll_cs->fract_fb_divider_precision_factor;
157 	feedback_divider =
158 		div_u64(feedback_divider,
159 			calc_pll_cs->fract_fb_divider_precision_factor * 10);
160 	feedback_divider *= (uint64_t)
161 			(calc_pll_cs->fract_fb_divider_precision_factor);
162 
163 	*feedback_divider_param =
164 		div_u64_rem(
165 			feedback_divider,
166 			calc_pll_cs->fract_fb_divider_factor,
167 			fract_feedback_divider_param);
168 
169 	if (*feedback_divider_param != 0)
170 		return true;
171 	return false;
172 }
173 
174 /**
175  * calc_fb_divider_checking_tolerance - Calculates Feedback and
176  *                                      Fractional Feedback divider values
177  *		                        for passed Reference and Post divider,
178  *                                      checking for tolerance.
179  * @calc_pll_cs:	Pointer to clock source information
180  * @pll_settings:	Pointer to PLL settings
181  * @ref_divider:	Reference divider (already known)
182  * @post_divider:	Post Divider (already known)
183  * @tolerance:		Tolerance for Calculated Pixel Clock to be within
184  *
185  * return:
186  *  It fills the PLLSettings structure with PLL Dividers values
187  *  if calculated values are within required tolerance
188  *  It returns	- true if error is within tolerance
189  *		- false if error is not within tolerance
190  */
calc_fb_divider_checking_tolerance(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t ref_divider,uint32_t post_divider,uint32_t tolerance)191 static bool calc_fb_divider_checking_tolerance(
192 		struct calc_pll_clock_source *calc_pll_cs,
193 		struct pll_settings *pll_settings,
194 		uint32_t ref_divider,
195 		uint32_t post_divider,
196 		uint32_t tolerance)
197 {
198 	uint32_t feedback_divider;
199 	uint32_t fract_feedback_divider;
200 	uint32_t actual_calculated_clock_100hz;
201 	uint32_t abs_err;
202 	uint64_t actual_calc_clk_100hz;
203 
204 	calculate_fb_and_fractional_fb_divider(
205 			calc_pll_cs,
206 			pll_settings->adjusted_pix_clk_100hz,
207 			ref_divider,
208 			post_divider,
209 			&feedback_divider,
210 			&fract_feedback_divider);
211 
212 	/*Actual calculated value*/
213 	actual_calc_clk_100hz = (uint64_t)feedback_divider *
214 					calc_pll_cs->fract_fb_divider_factor +
215 							fract_feedback_divider;
216 	actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10;
217 	actual_calc_clk_100hz =
218 		div_u64(actual_calc_clk_100hz,
219 			ref_divider * post_divider *
220 				calc_pll_cs->fract_fb_divider_factor);
221 
222 	actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
223 
224 	abs_err = (actual_calculated_clock_100hz >
225 					pll_settings->adjusted_pix_clk_100hz)
226 			? actual_calculated_clock_100hz -
227 					pll_settings->adjusted_pix_clk_100hz
228 			: pll_settings->adjusted_pix_clk_100hz -
229 						actual_calculated_clock_100hz;
230 
231 	if (abs_err <= tolerance) {
232 		/*found good values*/
233 		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
234 		pll_settings->reference_divider = ref_divider;
235 		pll_settings->feedback_divider = feedback_divider;
236 		pll_settings->fract_feedback_divider = fract_feedback_divider;
237 		pll_settings->pix_clk_post_divider = post_divider;
238 		pll_settings->calculated_pix_clk_100hz =
239 			actual_calculated_clock_100hz;
240 		pll_settings->vco_freq =
241 			div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
242 		return true;
243 	}
244 	return false;
245 }
246 
calc_pll_dividers_in_range(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t min_ref_divider,uint32_t max_ref_divider,uint32_t min_post_divider,uint32_t max_post_divider,uint32_t err_tolerance)247 static bool calc_pll_dividers_in_range(
248 		struct calc_pll_clock_source *calc_pll_cs,
249 		struct pll_settings *pll_settings,
250 		uint32_t min_ref_divider,
251 		uint32_t max_ref_divider,
252 		uint32_t min_post_divider,
253 		uint32_t max_post_divider,
254 		uint32_t err_tolerance)
255 {
256 	uint32_t ref_divider;
257 	uint32_t post_divider;
258 	uint32_t tolerance;
259 
260 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
261  * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
262 	tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
263 									100000;
264 	if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
265 		tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
266 
267 	for (
268 			post_divider = max_post_divider;
269 			post_divider >= min_post_divider;
270 			--post_divider) {
271 		for (
272 				ref_divider = min_ref_divider;
273 				ref_divider <= max_ref_divider;
274 				++ref_divider) {
275 			if (calc_fb_divider_checking_tolerance(
276 					calc_pll_cs,
277 					pll_settings,
278 					ref_divider,
279 					post_divider,
280 					tolerance)) {
281 				return true;
282 			}
283 		}
284 	}
285 
286 	return false;
287 }
288 
calculate_pixel_clock_pll_dividers(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings)289 static uint32_t calculate_pixel_clock_pll_dividers(
290 		struct calc_pll_clock_source *calc_pll_cs,
291 		struct pll_settings *pll_settings)
292 {
293 	uint32_t err_tolerance;
294 	uint32_t min_post_divider;
295 	uint32_t max_post_divider;
296 	uint32_t min_ref_divider;
297 	uint32_t max_ref_divider;
298 
299 	if (pll_settings->adjusted_pix_clk_100hz == 0) {
300 		DC_LOG_ERROR(
301 			"%s Bad requested pixel clock", __func__);
302 		return MAX_PLL_CALC_ERROR;
303 	}
304 
305 /* 1) Find Post divider ranges */
306 	if (pll_settings->pix_clk_post_divider) {
307 		min_post_divider = pll_settings->pix_clk_post_divider;
308 		max_post_divider = pll_settings->pix_clk_post_divider;
309 	} else {
310 		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
311 		if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
312 						calc_pll_cs->min_vco_khz * 10) {
313 			min_post_divider = calc_pll_cs->min_vco_khz * 10 /
314 					pll_settings->adjusted_pix_clk_100hz;
315 			if ((min_post_divider *
316 					pll_settings->adjusted_pix_clk_100hz) <
317 						calc_pll_cs->min_vco_khz * 10)
318 				min_post_divider++;
319 		}
320 
321 		max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
322 		if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
323 				> calc_pll_cs->max_vco_khz * 10)
324 			max_post_divider = calc_pll_cs->max_vco_khz * 10 /
325 					pll_settings->adjusted_pix_clk_100hz;
326 	}
327 
328 /* 2) Find Reference divider ranges
329  * When SS is enabled, or for Display Port even without SS,
330  * pll_settings->referenceDivider is not zero.
331  * So calculate PPLL FB and fractional FB divider
332  * using the passed reference divider*/
333 
334 	if (pll_settings->reference_divider) {
335 		min_ref_divider = pll_settings->reference_divider;
336 		max_ref_divider = pll_settings->reference_divider;
337 	} else {
338 		min_ref_divider = ((calc_pll_cs->ref_freq_khz
339 				/ calc_pll_cs->max_pll_input_freq_khz)
340 				> calc_pll_cs->min_pll_ref_divider)
341 			? calc_pll_cs->ref_freq_khz
342 					/ calc_pll_cs->max_pll_input_freq_khz
343 			: calc_pll_cs->min_pll_ref_divider;
344 
345 		max_ref_divider = ((calc_pll_cs->ref_freq_khz
346 				/ calc_pll_cs->min_pll_input_freq_khz)
347 				< calc_pll_cs->max_pll_ref_divider)
348 			? calc_pll_cs->ref_freq_khz /
349 					calc_pll_cs->min_pll_input_freq_khz
350 			: calc_pll_cs->max_pll_ref_divider;
351 	}
352 
353 /* If some parameters are invalid we could have scenario when  "min">"max"
354  * which produced endless loop later.
355  * We should investigate why we get the wrong parameters.
356  * But to follow the similar logic when "adjustedPixelClock" is set to be 0
357  * it is better to return here than cause system hang/watchdog timeout later.
358  *  ## SVS Wed 15 Jul 2009 */
359 
360 	if (min_post_divider > max_post_divider) {
361 		DC_LOG_ERROR(
362 			"%s Post divider range is invalid", __func__);
363 		return MAX_PLL_CALC_ERROR;
364 	}
365 
366 	if (min_ref_divider > max_ref_divider) {
367 		DC_LOG_ERROR(
368 			"%s Reference divider range is invalid", __func__);
369 		return MAX_PLL_CALC_ERROR;
370 	}
371 
372 /* 3) Try to find PLL dividers given ranges
373  * starting with minimal error tolerance.
374  * Increase error tolerance until PLL dividers found*/
375 	err_tolerance = MAX_PLL_CALC_ERROR;
376 
377 	while (!calc_pll_dividers_in_range(
378 			calc_pll_cs,
379 			pll_settings,
380 			min_ref_divider,
381 			max_ref_divider,
382 			min_post_divider,
383 			max_post_divider,
384 			err_tolerance))
385 		err_tolerance += (err_tolerance > 10)
386 				? (err_tolerance / 10)
387 				: 1;
388 
389 	return err_tolerance;
390 }
391 
pll_adjust_pix_clk(struct dce110_clk_src * clk_src,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)392 static bool pll_adjust_pix_clk(
393 		struct dce110_clk_src *clk_src,
394 		struct pixel_clk_params *pix_clk_params,
395 		struct pll_settings *pll_settings)
396 {
397 	uint32_t actual_pix_clk_100hz = 0;
398 	uint32_t requested_clk_100hz = 0;
399 	struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
400 							0 };
401 	enum bp_result bp_result;
402 	switch (pix_clk_params->signal_type) {
403 	case SIGNAL_TYPE_HDMI_TYPE_A: {
404 		requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
405 		if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
406 			switch (pix_clk_params->color_depth) {
407 			case COLOR_DEPTH_101010:
408 				requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
409 				break; /* x1.25*/
410 			case COLOR_DEPTH_121212:
411 				requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
412 				break; /* x1.5*/
413 			case COLOR_DEPTH_161616:
414 				requested_clk_100hz = requested_clk_100hz * 2;
415 				break; /* x2.0*/
416 			default:
417 				break;
418 			}
419 		}
420 		actual_pix_clk_100hz = requested_clk_100hz;
421 	}
422 		break;
423 
424 	case SIGNAL_TYPE_DISPLAY_PORT:
425 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
426 	case SIGNAL_TYPE_EDP:
427 		requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
428 		actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
429 		break;
430 
431 	default:
432 		requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
433 		actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
434 		break;
435 	}
436 
437 	bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
438 	bp_adjust_pixel_clock_params.
439 		encoder_object_id = pix_clk_params->encoder_object_id;
440 	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
441 	bp_adjust_pixel_clock_params.
442 		ss_enable = pix_clk_params->flags.ENABLE_SS;
443 	bp_result = clk_src->bios->funcs->adjust_pixel_clock(
444 			clk_src->bios, &bp_adjust_pixel_clock_params);
445 	if (bp_result == BP_RESULT_OK) {
446 		pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
447 		pll_settings->adjusted_pix_clk_100hz =
448 			bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
449 		pll_settings->reference_divider =
450 			bp_adjust_pixel_clock_params.reference_divider;
451 		pll_settings->pix_clk_post_divider =
452 			bp_adjust_pixel_clock_params.pixel_clock_post_divider;
453 
454 		return true;
455 	}
456 
457 	return false;
458 }
459 
460 /*
461  * Calculate PLL Dividers for given Clock Value.
462  * First will call VBIOS Adjust Exec table to check if requested Pixel clock
463  * will be Adjusted based on usage.
464  * Then it will calculate PLL Dividers for this Adjusted clock using preferred
465  * method (Maximum VCO frequency).
466  *
467  * \return
468  *     Calculation error in units of 0.01%
469  */
470 
dce110_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)471 static uint32_t dce110_get_pix_clk_dividers_helper (
472 		struct dce110_clk_src *clk_src,
473 		struct pll_settings *pll_settings,
474 		struct pixel_clk_params *pix_clk_params)
475 {
476 	uint32_t field = 0;
477 	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
478 	DC_LOGGER_INIT();
479 	/* Check if reference clock is external (not pcie/xtalin)
480 	* HW Dce80 spec:
481 	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
482 	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
483 	REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
484 	pll_settings->use_external_clk = (field > 1);
485 
486 	/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
487 	 * (we do not care any more from SI for some older DP Sink which
488 	 * does not report SS support, no known issues) */
489 	if ((pix_clk_params->flags.ENABLE_SS) ||
490 			(dc_is_dp_signal(pix_clk_params->signal_type))) {
491 
492 		const struct spread_spectrum_data *ss_data = get_ss_data_entry(
493 					clk_src,
494 					pix_clk_params->signal_type,
495 					pll_settings->adjusted_pix_clk_100hz / 10);
496 
497 		if (NULL != ss_data)
498 			pll_settings->ss_percentage = ss_data->percentage;
499 	}
500 
501 	/* Check VBIOS AdjustPixelClock Exec table */
502 	if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
503 		/* Should never happen, ASSERT and fill up values to be able
504 		 * to continue. */
505 		DC_LOG_ERROR(
506 			"%s: Failed to adjust pixel clock!!", __func__);
507 		pll_settings->actual_pix_clk_100hz =
508 				pix_clk_params->requested_pix_clk_100hz;
509 		pll_settings->adjusted_pix_clk_100hz =
510 				pix_clk_params->requested_pix_clk_100hz;
511 
512 		if (dc_is_dp_signal(pix_clk_params->signal_type))
513 			pll_settings->adjusted_pix_clk_100hz = 1000000;
514 	}
515 
516 	/* Calculate Dividers */
517 	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
518 		/*Calculate Dividers by HDMI object, no SS case or SS case */
519 		pll_calc_error =
520 			calculate_pixel_clock_pll_dividers(
521 					&clk_src->calc_pll_hdmi,
522 					pll_settings);
523 	else
524 		/*Calculate Dividers by default object, no SS case or SS case */
525 		pll_calc_error =
526 			calculate_pixel_clock_pll_dividers(
527 					&clk_src->calc_pll,
528 					pll_settings);
529 
530 	return pll_calc_error;
531 }
532 
dce112_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)533 static void dce112_get_pix_clk_dividers_helper (
534 		struct dce110_clk_src *clk_src,
535 		struct pll_settings *pll_settings,
536 		struct pixel_clk_params *pix_clk_params)
537 {
538 	uint32_t actual_pixel_clock_100hz;
539 
540 	actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
541 	/* Calculate Dividers */
542 	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
543 		switch (pix_clk_params->color_depth) {
544 		case COLOR_DEPTH_101010:
545 			actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
546 			actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
547 			break;
548 		case COLOR_DEPTH_121212:
549 			actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
550 			actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
551 			break;
552 		case COLOR_DEPTH_161616:
553 			actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
554 			break;
555 		default:
556 			break;
557 		}
558 	}
559 	pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
560 	pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
561 	pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
562 }
563 
dce110_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)564 static uint32_t dce110_get_pix_clk_dividers(
565 		struct clock_source *cs,
566 		struct pixel_clk_params *pix_clk_params,
567 		struct pll_settings *pll_settings)
568 {
569 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
570 	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
571 	DC_LOGGER_INIT();
572 
573 	if (pix_clk_params == NULL || pll_settings == NULL
574 			|| pix_clk_params->requested_pix_clk_100hz == 0) {
575 		DC_LOG_ERROR(
576 			"%s: Invalid parameters!!\n", __func__);
577 		return pll_calc_error;
578 	}
579 
580 	memset(pll_settings, 0, sizeof(*pll_settings));
581 
582 	if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
583 			cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
584 		pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
585 		pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
586 		pll_settings->actual_pix_clk_100hz =
587 					pix_clk_params->requested_pix_clk_100hz;
588 		return 0;
589 	}
590 
591 	pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src,
592 			pll_settings, pix_clk_params);
593 
594 	return pll_calc_error;
595 }
596 
dce112_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)597 static uint32_t dce112_get_pix_clk_dividers(
598 		struct clock_source *cs,
599 		struct pixel_clk_params *pix_clk_params,
600 		struct pll_settings *pll_settings)
601 {
602 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
603 	DC_LOGGER_INIT();
604 
605 	if (pix_clk_params == NULL || pll_settings == NULL
606 			|| pix_clk_params->requested_pix_clk_100hz == 0) {
607 		DC_LOG_ERROR(
608 			"%s: Invalid parameters!!\n", __func__);
609 		return -1;
610 	}
611 
612 	memset(pll_settings, 0, sizeof(*pll_settings));
613 
614 	if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
615 			cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
616 		pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
617 		pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
618 		pll_settings->actual_pix_clk_100hz =
619 					pix_clk_params->requested_pix_clk_100hz;
620 		return -1;
621 	}
622 
623 	dce112_get_pix_clk_dividers_helper(clk_src,
624 			pll_settings, pix_clk_params);
625 
626 	return 0;
627 }
628 
disable_spread_spectrum(struct dce110_clk_src * clk_src)629 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
630 {
631 	enum bp_result result;
632 	struct bp_spread_spectrum_parameters bp_ss_params = {0};
633 
634 	bp_ss_params.pll_id = clk_src->base.id;
635 
636 	/*Call ASICControl to process ATOMBIOS Exec table*/
637 	result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
638 			clk_src->bios,
639 			&bp_ss_params,
640 			false);
641 
642 	return result == BP_RESULT_OK;
643 }
644 
calculate_ss(const struct pll_settings * pll_settings,const struct spread_spectrum_data * ss_data,struct delta_sigma_data * ds_data)645 static bool calculate_ss(
646 		const struct pll_settings *pll_settings,
647 		const struct spread_spectrum_data *ss_data,
648 		struct delta_sigma_data *ds_data)
649 {
650 	struct fixed31_32 fb_div;
651 	struct fixed31_32 ss_amount;
652 	struct fixed31_32 ss_nslip_amount;
653 	struct fixed31_32 ss_ds_frac_amount;
654 	struct fixed31_32 ss_step_size;
655 	struct fixed31_32 modulation_time;
656 
657 	if (ds_data == NULL)
658 		return false;
659 	if (ss_data == NULL)
660 		return false;
661 	if (ss_data->percentage == 0)
662 		return false;
663 	if (pll_settings == NULL)
664 		return false;
665 
666 	memset(ds_data, 0, sizeof(struct delta_sigma_data));
667 
668 	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
669 	/* 6 decimal point support in fractional feedback divider */
670 	fb_div  = dc_fixpt_from_fraction(
671 		pll_settings->fract_feedback_divider, 1000000);
672 	fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
673 
674 	ds_data->ds_frac_amount = 0;
675 	/*spreadSpectrumPercentage is in the unit of .01%,
676 	 * so have to divided by 100 * 100*/
677 	ss_amount = dc_fixpt_mul(
678 		fb_div, dc_fixpt_from_fraction(ss_data->percentage,
679 					100 * ss_data->percentage_divider));
680 	ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
681 
682 	ss_nslip_amount = dc_fixpt_sub(ss_amount,
683 		dc_fixpt_from_int(ds_data->feedback_amount));
684 	ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
685 	ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
686 
687 	ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
688 		dc_fixpt_from_int(ds_data->nfrac_amount));
689 	ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
690 	ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
691 
692 	/* compute SS_STEP_SIZE_DSFRAC */
693 	modulation_time = dc_fixpt_from_fraction(
694 		pll_settings->reference_freq * 1000,
695 		pll_settings->reference_divider * ss_data->modulation_freq_hz);
696 
697 	if (ss_data->flags.CENTER_SPREAD)
698 		modulation_time = dc_fixpt_div_int(modulation_time, 4);
699 	else
700 		modulation_time = dc_fixpt_div_int(modulation_time, 2);
701 
702 	ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
703 	/* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
704 	ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
705 	ds_data->ds_frac_size =  dc_fixpt_floor(ss_step_size);
706 
707 	return true;
708 }
709 
enable_spread_spectrum(struct dce110_clk_src * clk_src,enum signal_type signal,struct pll_settings * pll_settings)710 static bool enable_spread_spectrum(
711 		struct dce110_clk_src *clk_src,
712 		enum signal_type signal, struct pll_settings *pll_settings)
713 {
714 	struct bp_spread_spectrum_parameters bp_params = {0};
715 	struct delta_sigma_data d_s_data;
716 	const struct spread_spectrum_data *ss_data = NULL;
717 
718 	ss_data = get_ss_data_entry(
719 			clk_src,
720 			signal,
721 			pll_settings->calculated_pix_clk_100hz / 10);
722 
723 /* Pixel clock PLL has been programmed to generate desired pixel clock,
724  * now enable SS on pixel clock */
725 /* TODO is it OK to return true not doing anything ??*/
726 	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
727 		if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
728 			bp_params.ds.feedback_amount =
729 					d_s_data.feedback_amount;
730 			bp_params.ds.nfrac_amount =
731 					d_s_data.nfrac_amount;
732 			bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
733 			bp_params.ds_frac_amount =
734 					d_s_data.ds_frac_amount;
735 			bp_params.flags.DS_TYPE = 1;
736 			bp_params.pll_id = clk_src->base.id;
737 			bp_params.percentage = ss_data->percentage;
738 			if (ss_data->flags.CENTER_SPREAD)
739 				bp_params.flags.CENTER_SPREAD = 1;
740 			if (ss_data->flags.EXTERNAL_SS)
741 				bp_params.flags.EXTERNAL_SS = 1;
742 
743 			if (BP_RESULT_OK !=
744 				clk_src->bios->funcs->
745 					enable_spread_spectrum_on_ppll(
746 							clk_src->bios,
747 							&bp_params,
748 							true))
749 				return false;
750 		} else
751 			return false;
752 	}
753 	return true;
754 }
755 
dce110_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth)756 static void dce110_program_pixel_clk_resync(
757 		struct dce110_clk_src *clk_src,
758 		enum signal_type signal_type,
759 		enum dc_color_depth colordepth)
760 {
761 	REG_UPDATE(RESYNC_CNTL,
762 			DCCG_DEEP_COLOR_CNTL1, 0);
763 	/*
764 	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
765 	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
766 	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
767 	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
768 	 */
769 	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
770 		return;
771 
772 	switch (colordepth) {
773 	case COLOR_DEPTH_888:
774 		REG_UPDATE(RESYNC_CNTL,
775 				DCCG_DEEP_COLOR_CNTL1, 0);
776 		break;
777 	case COLOR_DEPTH_101010:
778 		REG_UPDATE(RESYNC_CNTL,
779 				DCCG_DEEP_COLOR_CNTL1, 1);
780 		break;
781 	case COLOR_DEPTH_121212:
782 		REG_UPDATE(RESYNC_CNTL,
783 				DCCG_DEEP_COLOR_CNTL1, 2);
784 		break;
785 	case COLOR_DEPTH_161616:
786 		REG_UPDATE(RESYNC_CNTL,
787 				DCCG_DEEP_COLOR_CNTL1, 3);
788 		break;
789 	default:
790 		break;
791 	}
792 }
793 
dce112_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth,bool enable_ycbcr420)794 static void dce112_program_pixel_clk_resync(
795 		struct dce110_clk_src *clk_src,
796 		enum signal_type signal_type,
797 		enum dc_color_depth colordepth,
798 		bool enable_ycbcr420)
799 {
800 	uint32_t deep_color_cntl = 0;
801 	uint32_t double_rate_enable = 0;
802 
803 	/*
804 	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
805 	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
806 	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
807 	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
808 	 */
809 	if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
810 		double_rate_enable = enable_ycbcr420 ? 1 : 0;
811 
812 		switch (colordepth) {
813 		case COLOR_DEPTH_888:
814 			deep_color_cntl = 0;
815 			break;
816 		case COLOR_DEPTH_101010:
817 			deep_color_cntl = 1;
818 			break;
819 		case COLOR_DEPTH_121212:
820 			deep_color_cntl = 2;
821 			break;
822 		case COLOR_DEPTH_161616:
823 			deep_color_cntl = 3;
824 			break;
825 		default:
826 			break;
827 		}
828 	}
829 
830 	if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
831 		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
832 				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
833 				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
834 	else
835 		REG_UPDATE(PIXCLK_RESYNC_CNTL,
836 				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
837 
838 }
839 
dce110_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)840 static bool dce110_program_pix_clk(
841 		struct clock_source *clock_source,
842 		struct pixel_clk_params *pix_clk_params,
843 		enum dp_link_encoding encoding,
844 		struct pll_settings *pll_settings)
845 {
846 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
847 	struct bp_pixel_clock_parameters bp_pc_params = {0};
848 
849 	/* First disable SS
850 	 * ATOMBIOS will enable by default SS on PLL for DP,
851 	 * do not disable it here
852 	 */
853 	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
854 			!dc_is_dp_signal(pix_clk_params->signal_type) &&
855 			clock_source->ctx->dce_version <= DCE_VERSION_11_0)
856 		disable_spread_spectrum(clk_src);
857 
858 	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
859 	bp_pc_params.controller_id = pix_clk_params->controller_id;
860 	bp_pc_params.pll_id = clock_source->id;
861 	bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
862 	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
863 	bp_pc_params.signal_type = pix_clk_params->signal_type;
864 
865 	bp_pc_params.reference_divider = pll_settings->reference_divider;
866 	bp_pc_params.feedback_divider = pll_settings->feedback_divider;
867 	bp_pc_params.fractional_feedback_divider =
868 			pll_settings->fract_feedback_divider;
869 	bp_pc_params.pixel_clock_post_divider =
870 			pll_settings->pix_clk_post_divider;
871 	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
872 					pll_settings->use_external_clk;
873 
874 	switch (pix_clk_params->color_depth) {
875 	case COLOR_DEPTH_101010:
876 		bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30;
877 		break;
878 	case COLOR_DEPTH_121212:
879 		bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36;
880 		break;
881 	case COLOR_DEPTH_161616:
882 		bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48;
883 		break;
884 	default:
885 		break;
886 	}
887 
888 	if (clk_src->bios->funcs->set_pixel_clock(
889 			clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
890 		return false;
891 	/* Enable SS
892 	 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
893 	 * based on HW display PLL team, SS control settings should be programmed
894 	 * during PLL Reset, but they do not have effect
895 	 * until SS_EN is asserted.*/
896 	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
897 			&& !dc_is_dp_signal(pix_clk_params->signal_type)) {
898 
899 		if (pix_clk_params->flags.ENABLE_SS)
900 			if (!enable_spread_spectrum(clk_src,
901 							pix_clk_params->signal_type,
902 							pll_settings))
903 				return false;
904 
905 		/* Resync deep color DTO */
906 		dce110_program_pixel_clk_resync(clk_src,
907 					pix_clk_params->signal_type,
908 					pix_clk_params->color_depth);
909 	}
910 
911 	return true;
912 }
913 
dce112_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)914 static bool dce112_program_pix_clk(
915 		struct clock_source *clock_source,
916 		struct pixel_clk_params *pix_clk_params,
917 		enum dp_link_encoding encoding,
918 		struct pll_settings *pll_settings)
919 {
920 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
921 	struct bp_pixel_clock_parameters bp_pc_params = {0};
922 
923 	/* First disable SS
924 	 * ATOMBIOS will enable by default SS on PLL for DP,
925 	 * do not disable it here
926 	 */
927 	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
928 			!dc_is_dp_signal(pix_clk_params->signal_type) &&
929 			clock_source->ctx->dce_version <= DCE_VERSION_11_0)
930 		disable_spread_spectrum(clk_src);
931 
932 	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
933 	bp_pc_params.controller_id = pix_clk_params->controller_id;
934 	bp_pc_params.pll_id = clock_source->id;
935 	bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
936 	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
937 	bp_pc_params.signal_type = pix_clk_params->signal_type;
938 
939 	if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
940 		bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
941 						pll_settings->use_external_clk;
942 		bp_pc_params.flags.SET_XTALIN_REF_SRC =
943 						!pll_settings->use_external_clk;
944 		if (pix_clk_params->flags.SUPPORT_YCBCR420) {
945 			bp_pc_params.flags.SUPPORT_YUV_420 = 1;
946 		}
947 	}
948 	if (clk_src->bios->funcs->set_pixel_clock(
949 			clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
950 		return false;
951 	/* Resync deep color DTO */
952 	if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
953 		dce112_program_pixel_clk_resync(clk_src,
954 					pix_clk_params->signal_type,
955 					pix_clk_params->color_depth,
956 					pix_clk_params->flags.SUPPORT_YCBCR420);
957 
958 	return true;
959 }
960 
dcn31_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)961 static bool dcn31_program_pix_clk(
962 		struct clock_source *clock_source,
963 		struct pixel_clk_params *pix_clk_params,
964 		enum dp_link_encoding encoding,
965 		struct pll_settings *pll_settings)
966 {
967 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
968 	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
969 	unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
970 	const struct pixel_rate_range_table_entry *e =
971 			look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
972 	struct bp_pixel_clock_parameters bp_pc_params = {0};
973 	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
974 	// For these signal types Driver to program DP_DTO without calling VBIOS Command table
975 	if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) {
976 		if (e) {
977 			/* Set DTO values: phase = target clock, modulo = reference clock*/
978 			REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
979 			REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
980 		} else {
981 			/* Set DTO values: phase = target clock, modulo = reference clock*/
982 			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
983 			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
984 		}
985 		/* Enable DTO */
986 		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
987 			if (encoding == DP_128b_132b_ENCODING)
988 				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
989 						DP_DTO0_ENABLE, 1,
990 						PIPE0_DTO_SRC_SEL, 2);
991 			else
992 				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
993 						DP_DTO0_ENABLE, 1,
994 						PIPE0_DTO_SRC_SEL, 1);
995 		else
996 			REG_UPDATE(PIXEL_RATE_CNTL[inst],
997 					DP_DTO0_ENABLE, 1);
998 	} else {
999 
1000 		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1001 			REG_UPDATE(PIXEL_RATE_CNTL[inst],
1002 					PIPE0_DTO_SRC_SEL, 0);
1003 
1004 		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
1005 		bp_pc_params.controller_id = pix_clk_params->controller_id;
1006 		bp_pc_params.pll_id = clock_source->id;
1007 		bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
1008 		bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
1009 		bp_pc_params.signal_type = pix_clk_params->signal_type;
1010 
1011 		// Make sure we send the correct color depth to DMUB for HDMI
1012 		if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1013 			switch (pix_clk_params->color_depth) {
1014 			case COLOR_DEPTH_888:
1015 				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1016 				break;
1017 			case COLOR_DEPTH_101010:
1018 				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
1019 				break;
1020 			case COLOR_DEPTH_121212:
1021 				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
1022 				break;
1023 			case COLOR_DEPTH_161616:
1024 				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
1025 				break;
1026 			default:
1027 				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1028 				break;
1029 			}
1030 			bp_pc_params.color_depth = bp_pc_colour_depth;
1031 		}
1032 
1033 		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
1034 			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
1035 							pll_settings->use_external_clk;
1036 			bp_pc_params.flags.SET_XTALIN_REF_SRC =
1037 							!pll_settings->use_external_clk;
1038 			if (pix_clk_params->flags.SUPPORT_YCBCR420) {
1039 				bp_pc_params.flags.SUPPORT_YUV_420 = 1;
1040 			}
1041 		}
1042 		if (clk_src->bios->funcs->set_pixel_clock(
1043 				clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
1044 			return false;
1045 		/* Resync deep color DTO */
1046 		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
1047 			dce112_program_pixel_clk_resync(clk_src,
1048 						pix_clk_params->signal_type,
1049 						pix_clk_params->color_depth,
1050 						pix_clk_params->flags.SUPPORT_YCBCR420);
1051 	}
1052 
1053 	return true;
1054 }
1055 
dce110_clock_source_power_down(struct clock_source * clk_src)1056 static bool dce110_clock_source_power_down(
1057 		struct clock_source *clk_src)
1058 {
1059 	struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
1060 	enum bp_result bp_result;
1061 	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
1062 
1063 	if (clk_src->dp_clk_src)
1064 		return true;
1065 
1066 	/* If Pixel Clock is 0 it means Power Down Pll*/
1067 	bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
1068 	bp_pixel_clock_params.pll_id = clk_src->id;
1069 	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
1070 
1071 	/*Call ASICControl to process ATOMBIOS Exec table*/
1072 	bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
1073 			dce110_clk_src->bios,
1074 			&bp_pixel_clock_params);
1075 
1076 	return bp_result == BP_RESULT_OK;
1077 }
1078 
get_pixel_clk_frequency_100hz(const struct clock_source * clock_source,unsigned int inst,unsigned int * pixel_clk_khz)1079 static bool get_pixel_clk_frequency_100hz(
1080 		const struct clock_source *clock_source,
1081 		unsigned int inst,
1082 		unsigned int *pixel_clk_khz)
1083 {
1084 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1085 	unsigned int clock_hz = 0;
1086 	unsigned int modulo_hz = 0;
1087 
1088 	if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
1089 		clock_hz = REG_READ(PHASE[inst]);
1090 
1091 		if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1092 			clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1093 			/* NOTE: In case VBLANK syncronization is enabled, MODULO may
1094 			 * not be programmed equal to DPREFCLK
1095 			 */
1096 			modulo_hz = REG_READ(MODULO[inst]);
1097 			if (modulo_hz)
1098 				*pixel_clk_khz = div_u64((uint64_t)clock_hz*
1099 					clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,
1100 					modulo_hz);
1101 			else
1102 				*pixel_clk_khz = 0;
1103 		} else {
1104 			/* NOTE: There is agreement with VBIOS here that MODULO is
1105 			 * programmed equal to DPREFCLK, in which case PHASE will be
1106 			 * equivalent to pixel clock.
1107 			 */
1108 			*pixel_clk_khz = clock_hz / 100;
1109 		}
1110 		return true;
1111 	}
1112 
1113 	return false;
1114 }
1115 
1116 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
1117 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
1118 	// /1.001 rates
1119 	{25170, 25180, 25200, 1000, 1001},	//25.2MHz   ->   25.17
1120 	{59340, 59350, 59400, 1000, 1001},	//59.4Mhz   ->   59.340
1121 	{74170, 74180, 74250, 1000, 1001},	//74.25Mhz  ->   74.1758
1122 	{89910, 90000, 90000, 1000, 1001},	//90Mhz     ->   89.91
1123 	{125870, 125880, 126000, 1000, 1001},	//126Mhz    ->  125.87
1124 	{148350, 148360, 148500, 1000, 1001},	//148.5Mhz  ->  148.3516
1125 	{167830, 167840, 168000, 1000, 1001},	//168Mhz    ->  167.83
1126 	{222520, 222530, 222750, 1000, 1001},	//222.75Mhz ->  222.527
1127 	{257140, 257150, 257400, 1000, 1001},	//257.4Mhz  ->  257.1429
1128 	{296700, 296710, 297000, 1000, 1001},	//297Mhz    ->  296.7033
1129 	{342850, 342860, 343200, 1000, 1001},	//343.2Mhz  ->  342.857
1130 	{395600, 395610, 396000, 1000, 1001},	//396Mhz    ->  395.6
1131 	{409090, 409100, 409500, 1000, 1001},	//409.5Mhz  ->  409.091
1132 	{445050, 445060, 445500, 1000, 1001},	//445.5Mhz  ->  445.055
1133 	{467530, 467540, 468000, 1000, 1001},	//468Mhz    ->  467.5325
1134 	{519230, 519240, 519750, 1000, 1001},	//519.75Mhz ->  519.231
1135 	{525970, 525980, 526500, 1000, 1001},	//526.5Mhz  ->  525.974
1136 	{545450, 545460, 546000, 1000, 1001},	//546Mhz    ->  545.455
1137 	{593400, 593410, 594000, 1000, 1001},	//594Mhz    ->  593.4066
1138 	{623370, 623380, 624000, 1000, 1001},	//624Mhz    ->  623.377
1139 	{692300, 692310, 693000, 1000, 1001},	//693Mhz    ->  692.308
1140 	{701290, 701300, 702000, 1000, 1001},	//702Mhz    ->  701.2987
1141 	{791200, 791210, 792000, 1000, 1001},	//792Mhz    ->  791.209
1142 	{890100, 890110, 891000, 1000, 1001},	//891Mhz    ->  890.1099
1143 	{1186810, 1186820, 1188000, 1000, 1001},//1188Mhz   -> 1186.8131
1144 
1145 	// *1.001 rates
1146 	{27020, 27030, 27000, 1001, 1000}, //27Mhz
1147 	{54050, 54060, 54000, 1001, 1000}, //54Mhz
1148 	{108100, 108110, 108000, 1001, 1000},//108Mhz
1149 };
1150 
look_up_in_video_optimized_rate_tlb(unsigned int pixel_rate_khz)1151 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
1152 		unsigned int pixel_rate_khz)
1153 {
1154 	int i;
1155 
1156 	for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
1157 		const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
1158 
1159 		if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {
1160 			return e;
1161 		}
1162 	}
1163 
1164 	return NULL;
1165 }
1166 
dcn20_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)1167 static bool dcn20_program_pix_clk(
1168 		struct clock_source *clock_source,
1169 		struct pixel_clk_params *pix_clk_params,
1170 		enum dp_link_encoding encoding,
1171 		struct pll_settings *pll_settings)
1172 {
1173 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1174 	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1175 
1176 	dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1177 
1178 	if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1179 			clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1180 		/* NOTE: In case VBLANK syncronization is enabled,
1181 		 * we need to set modulo to default DPREFCLK first
1182 		 * dce112_program_pix_clk does not set default DPREFCLK
1183 		 */
1184 		REG_WRITE(MODULO[inst],
1185 			clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);
1186 	}
1187 	return true;
1188 }
1189 
dcn20_override_dp_pix_clk(struct clock_source * clock_source,unsigned int inst,unsigned int pixel_clk,unsigned int ref_clk)1190 static bool dcn20_override_dp_pix_clk(
1191 		struct clock_source *clock_source,
1192 		unsigned int inst,
1193 		unsigned int pixel_clk,
1194 		unsigned int ref_clk)
1195 {
1196 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1197 
1198 	REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);
1199 	REG_WRITE(PHASE[inst], pixel_clk);
1200 	REG_WRITE(MODULO[inst], ref_clk);
1201 	REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1202 	return true;
1203 }
1204 
1205 static const struct clock_source_funcs dcn20_clk_src_funcs = {
1206 	.cs_power_down = dce110_clock_source_power_down,
1207 	.program_pix_clk = dcn20_program_pix_clk,
1208 	.get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1209 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz,
1210 	.override_dp_pix_clk = dcn20_override_dp_pix_clk
1211 };
1212 
dcn3_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,enum dp_link_encoding encoding,struct pll_settings * pll_settings)1213 static bool dcn3_program_pix_clk(
1214 		struct clock_source *clock_source,
1215 		struct pixel_clk_params *pix_clk_params,
1216 		enum dp_link_encoding encoding,
1217 		struct pll_settings *pll_settings)
1218 {
1219 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1220 	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1221 	unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1222 	const struct pixel_rate_range_table_entry *e =
1223 			look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1224 
1225 	// For these signal types Driver to program DP_DTO without calling VBIOS Command table
1226 	if (dc_is_dp_signal(pix_clk_params->signal_type)) {
1227 		if (e) {
1228 			/* Set DTO values: phase = target clock, modulo = reference clock*/
1229 			REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
1230 			REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
1231 		} else {
1232 			/* Set DTO values: phase = target clock, modulo = reference clock*/
1233 			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1234 			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
1235 		}
1236 		/* Enable DTO */
1237 		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1238 			REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1239 					DP_DTO0_ENABLE, 1,
1240 					PIPE0_DTO_SRC_SEL, 1);
1241 		else
1242 			REG_UPDATE(PIXEL_RATE_CNTL[inst],
1243 					DP_DTO0_ENABLE, 1);
1244 	} else
1245 		// For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
1246 		dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1247 
1248 	return true;
1249 }
1250 
dcn3_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1251 static uint32_t dcn3_get_pix_clk_dividers(
1252 		struct clock_source *cs,
1253 		struct pixel_clk_params *pix_clk_params,
1254 		struct pll_settings *pll_settings)
1255 {
1256 	unsigned long long actual_pix_clk_100Hz = pix_clk_params ? pix_clk_params->requested_pix_clk_100hz : 0;
1257 
1258 	DC_LOGGER_INIT();
1259 
1260 	if (pix_clk_params == NULL || pll_settings == NULL
1261 			|| pix_clk_params->requested_pix_clk_100hz == 0) {
1262 		DC_LOG_ERROR(
1263 			"%s: Invalid parameters!!\n", __func__);
1264 		return -1;
1265 	}
1266 
1267 	memset(pll_settings, 0, sizeof(*pll_settings));
1268 	/* Adjust for HDMI Type A deep color */
1269 	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1270 		switch (pix_clk_params->color_depth) {
1271 		case COLOR_DEPTH_101010:
1272 			actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
1273 			break;
1274 		case COLOR_DEPTH_121212:
1275 			actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
1276 			break;
1277 		case COLOR_DEPTH_161616:
1278 			actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
1279 			break;
1280 		default:
1281 			break;
1282 		}
1283 	}
1284 	pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1285 	pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1286 	pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1287 
1288 	return 0;
1289 }
1290 
1291 static const struct clock_source_funcs dcn3_clk_src_funcs = {
1292 	.cs_power_down = dce110_clock_source_power_down,
1293 	.program_pix_clk = dcn3_program_pix_clk,
1294 	.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1295 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1296 };
1297 
1298 static const struct clock_source_funcs dcn31_clk_src_funcs = {
1299 	.cs_power_down = dce110_clock_source_power_down,
1300 	.program_pix_clk = dcn31_program_pix_clk,
1301 	.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1302 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1303 };
1304 
1305 /*****************************************/
1306 /* Constructor                           */
1307 /*****************************************/
1308 
1309 static const struct clock_source_funcs dce112_clk_src_funcs = {
1310 	.cs_power_down = dce110_clock_source_power_down,
1311 	.program_pix_clk = dce112_program_pix_clk,
1312 	.get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1313 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1314 };
1315 static const struct clock_source_funcs dce110_clk_src_funcs = {
1316 	.cs_power_down = dce110_clock_source_power_down,
1317 	.program_pix_clk = dce110_program_pix_clk,
1318 	.get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1319 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1320 };
1321 
1322 
get_ss_info_from_atombios(struct dce110_clk_src * clk_src,enum as_signal_type as_signal,struct spread_spectrum_data * spread_spectrum_data[],uint32_t * ss_entries_num)1323 static void get_ss_info_from_atombios(
1324 		struct dce110_clk_src *clk_src,
1325 		enum as_signal_type as_signal,
1326 		struct spread_spectrum_data *spread_spectrum_data[],
1327 		uint32_t *ss_entries_num)
1328 {
1329 	enum bp_result bp_result = BP_RESULT_FAILURE;
1330 	struct spread_spectrum_info *ss_info;
1331 	struct spread_spectrum_data *ss_data;
1332 	struct spread_spectrum_info *ss_info_cur;
1333 	struct spread_spectrum_data *ss_data_cur;
1334 	uint32_t i;
1335 	DC_LOGGER_INIT();
1336 	if (ss_entries_num == NULL) {
1337 		DC_LOG_SYNC(
1338 			"Invalid entry !!!\n");
1339 		return;
1340 	}
1341 	if (spread_spectrum_data == NULL) {
1342 		DC_LOG_SYNC(
1343 			"Invalid array pointer!!!\n");
1344 		return;
1345 	}
1346 
1347 	spread_spectrum_data[0] = NULL;
1348 	*ss_entries_num = 0;
1349 
1350 	*ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
1351 			clk_src->bios,
1352 			as_signal);
1353 
1354 	if (*ss_entries_num == 0)
1355 		return;
1356 
1357 	ss_info = kcalloc(*ss_entries_num,
1358 			  sizeof(struct spread_spectrum_info),
1359 			  GFP_KERNEL);
1360 	ss_info_cur = ss_info;
1361 	if (ss_info == NULL)
1362 		return;
1363 
1364 	ss_data = kcalloc(*ss_entries_num,
1365 			  sizeof(struct spread_spectrum_data),
1366 			  GFP_KERNEL);
1367 	if (ss_data == NULL)
1368 		goto out_free_info;
1369 
1370 	for (i = 0, ss_info_cur = ss_info;
1371 		i < (*ss_entries_num);
1372 		++i, ++ss_info_cur) {
1373 
1374 		bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
1375 				clk_src->bios,
1376 				as_signal,
1377 				i,
1378 				ss_info_cur);
1379 
1380 		if (bp_result != BP_RESULT_OK)
1381 			goto out_free_data;
1382 	}
1383 
1384 	for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
1385 		i < (*ss_entries_num);
1386 		++i, ++ss_info_cur, ++ss_data_cur) {
1387 
1388 		if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
1389 			DC_LOG_SYNC(
1390 				"Invalid ATOMBIOS SS Table!!!\n");
1391 			goto out_free_data;
1392 		}
1393 
1394 		/* for HDMI check SS percentage,
1395 		 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
1396 		if (as_signal == AS_SIGNAL_TYPE_HDMI
1397 				&& ss_info_cur->spread_spectrum_percentage > 6){
1398 			/* invalid input, do nothing */
1399 			DC_LOG_SYNC(
1400 				"Invalid SS percentage ");
1401 			DC_LOG_SYNC(
1402 				"for HDMI in ATOMBIOS info Table!!!\n");
1403 			continue;
1404 		}
1405 		if (ss_info_cur->spread_percentage_divider == 1000) {
1406 			/* Keep previous precision from ATOMBIOS for these
1407 			* in case new precision set by ATOMBIOS for these
1408 			* (otherwise all code in DCE specific classes
1409 			* for all previous ASICs would need
1410 			* to be updated for SS calculations,
1411 			* Audio SS compensation and DP DTO SS compensation
1412 			* which assumes fixed SS percentage Divider = 100)*/
1413 			ss_info_cur->spread_spectrum_percentage /= 10;
1414 			ss_info_cur->spread_percentage_divider = 100;
1415 		}
1416 
1417 		ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
1418 		ss_data_cur->percentage =
1419 				ss_info_cur->spread_spectrum_percentage;
1420 		ss_data_cur->percentage_divider =
1421 				ss_info_cur->spread_percentage_divider;
1422 		ss_data_cur->modulation_freq_hz =
1423 				ss_info_cur->spread_spectrum_range;
1424 
1425 		if (ss_info_cur->type.CENTER_MODE)
1426 			ss_data_cur->flags.CENTER_SPREAD = 1;
1427 
1428 		if (ss_info_cur->type.EXTERNAL)
1429 			ss_data_cur->flags.EXTERNAL_SS = 1;
1430 
1431 	}
1432 
1433 	*spread_spectrum_data = ss_data;
1434 	kfree(ss_info);
1435 	return;
1436 
1437 out_free_data:
1438 	kfree(ss_data);
1439 	*ss_entries_num = 0;
1440 out_free_info:
1441 	kfree(ss_info);
1442 }
1443 
ss_info_from_atombios_create(struct dce110_clk_src * clk_src)1444 static void ss_info_from_atombios_create(
1445 	struct dce110_clk_src *clk_src)
1446 {
1447 	get_ss_info_from_atombios(
1448 		clk_src,
1449 		AS_SIGNAL_TYPE_DISPLAY_PORT,
1450 		&clk_src->dp_ss_params,
1451 		&clk_src->dp_ss_params_cnt);
1452 	get_ss_info_from_atombios(
1453 		clk_src,
1454 		AS_SIGNAL_TYPE_HDMI,
1455 		&clk_src->hdmi_ss_params,
1456 		&clk_src->hdmi_ss_params_cnt);
1457 	get_ss_info_from_atombios(
1458 		clk_src,
1459 		AS_SIGNAL_TYPE_DVI,
1460 		&clk_src->dvi_ss_params,
1461 		&clk_src->dvi_ss_params_cnt);
1462 	get_ss_info_from_atombios(
1463 		clk_src,
1464 		AS_SIGNAL_TYPE_LVDS,
1465 		&clk_src->lvds_ss_params,
1466 		&clk_src->lvds_ss_params_cnt);
1467 }
1468 
calc_pll_max_vco_construct(struct calc_pll_clock_source * calc_pll_cs,struct calc_pll_clock_source_init_data * init_data)1469 static bool calc_pll_max_vco_construct(
1470 			struct calc_pll_clock_source *calc_pll_cs,
1471 			struct calc_pll_clock_source_init_data *init_data)
1472 {
1473 	uint32_t i;
1474 	struct dc_firmware_info *fw_info;
1475 	if (calc_pll_cs == NULL ||
1476 			init_data == NULL ||
1477 			init_data->bp == NULL)
1478 		return false;
1479 
1480 	if (!init_data->bp->fw_info_valid)
1481 		return false;
1482 
1483 	fw_info = &init_data->bp->fw_info;
1484 	calc_pll_cs->ctx = init_data->ctx;
1485 	calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
1486 	calc_pll_cs->min_vco_khz =
1487 			fw_info->pll_info.min_output_pxl_clk_pll_frequency;
1488 	calc_pll_cs->max_vco_khz =
1489 			fw_info->pll_info.max_output_pxl_clk_pll_frequency;
1490 
1491 	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
1492 		calc_pll_cs->max_pll_input_freq_khz =
1493 			init_data->max_override_input_pxl_clk_pll_freq_khz;
1494 	else
1495 		calc_pll_cs->max_pll_input_freq_khz =
1496 			fw_info->pll_info.max_input_pxl_clk_pll_frequency;
1497 
1498 	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
1499 		calc_pll_cs->min_pll_input_freq_khz =
1500 			init_data->min_override_input_pxl_clk_pll_freq_khz;
1501 	else
1502 		calc_pll_cs->min_pll_input_freq_khz =
1503 			fw_info->pll_info.min_input_pxl_clk_pll_frequency;
1504 
1505 	calc_pll_cs->min_pix_clock_pll_post_divider =
1506 			init_data->min_pix_clk_pll_post_divider;
1507 	calc_pll_cs->max_pix_clock_pll_post_divider =
1508 			init_data->max_pix_clk_pll_post_divider;
1509 	calc_pll_cs->min_pll_ref_divider =
1510 			init_data->min_pll_ref_divider;
1511 	calc_pll_cs->max_pll_ref_divider =
1512 			init_data->max_pll_ref_divider;
1513 
1514 	if (init_data->num_fract_fb_divider_decimal_point == 0 ||
1515 		init_data->num_fract_fb_divider_decimal_point_precision >
1516 				init_data->num_fract_fb_divider_decimal_point) {
1517 		DC_LOG_ERROR(
1518 			"The dec point num or precision is incorrect!");
1519 		return false;
1520 	}
1521 	if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
1522 		DC_LOG_ERROR(
1523 			"Incorrect fract feedback divider precision num!");
1524 		return false;
1525 	}
1526 
1527 	calc_pll_cs->fract_fb_divider_decimal_points_num =
1528 				init_data->num_fract_fb_divider_decimal_point;
1529 	calc_pll_cs->fract_fb_divider_precision =
1530 			init_data->num_fract_fb_divider_decimal_point_precision;
1531 	calc_pll_cs->fract_fb_divider_factor = 1;
1532 	for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
1533 		calc_pll_cs->fract_fb_divider_factor *= 10;
1534 
1535 	calc_pll_cs->fract_fb_divider_precision_factor = 1;
1536 	for (
1537 		i = 0;
1538 		i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
1539 				calc_pll_cs->fract_fb_divider_precision);
1540 		++i)
1541 		calc_pll_cs->fract_fb_divider_precision_factor *= 10;
1542 
1543 	return true;
1544 }
1545 
dce110_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1546 bool dce110_clk_src_construct(
1547 	struct dce110_clk_src *clk_src,
1548 	struct dc_context *ctx,
1549 	struct dc_bios *bios,
1550 	enum clock_source_id id,
1551 	const struct dce110_clk_src_regs *regs,
1552 	const struct dce110_clk_src_shift *cs_shift,
1553 	const struct dce110_clk_src_mask *cs_mask)
1554 {
1555 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
1556 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
1557 
1558 	clk_src->base.ctx = ctx;
1559 	clk_src->bios = bios;
1560 	clk_src->base.id = id;
1561 	clk_src->base.funcs = &dce110_clk_src_funcs;
1562 
1563 	clk_src->regs = regs;
1564 	clk_src->cs_shift = cs_shift;
1565 	clk_src->cs_mask = cs_mask;
1566 
1567 	if (!clk_src->bios->fw_info_valid) {
1568 		ASSERT_CRITICAL(false);
1569 		goto unexpected_failure;
1570 	}
1571 
1572 	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1573 
1574 	/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
1575 	calc_pll_cs_init_data.bp = bios;
1576 	calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
1577 	calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
1578 			clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1579 	calc_pll_cs_init_data.min_pll_ref_divider =	1;
1580 	calc_pll_cs_init_data.max_pll_ref_divider =	clk_src->cs_mask->PLL_REF_DIV;
1581 	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1582 	calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz =	0;
1583 	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1584 	calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz =	0;
1585 	/*numberOfFractFBDividerDecimalPoints*/
1586 	calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
1587 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1588 	/*number of decimal point to round off for fractional feedback divider value*/
1589 	calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
1590 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1591 	calc_pll_cs_init_data.ctx =	ctx;
1592 
1593 	/*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
1594 	calc_pll_cs_init_data_hdmi.bp = bios;
1595 	calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
1596 	calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
1597 			clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1598 	calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
1599 	calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1600 	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1601 	calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
1602 	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1603 	calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
1604 	/*numberOfFractFBDividerDecimalPoints*/
1605 	calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
1606 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1607 	/*number of decimal point to round off for fractional feedback divider value*/
1608 	calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
1609 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1610 	calc_pll_cs_init_data_hdmi.ctx = ctx;
1611 
1612 	clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
1613 
1614 	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
1615 		return true;
1616 
1617 	/* PLL only from here on */
1618 	ss_info_from_atombios_create(clk_src);
1619 
1620 	if (!calc_pll_max_vco_construct(
1621 			&clk_src->calc_pll,
1622 			&calc_pll_cs_init_data)) {
1623 		ASSERT_CRITICAL(false);
1624 		goto unexpected_failure;
1625 	}
1626 
1627 
1628 	calc_pll_cs_init_data_hdmi.
1629 			min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
1630 	calc_pll_cs_init_data_hdmi.
1631 			max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
1632 
1633 
1634 	if (!calc_pll_max_vco_construct(
1635 			&clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
1636 		ASSERT_CRITICAL(false);
1637 		goto unexpected_failure;
1638 	}
1639 
1640 	return true;
1641 
1642 unexpected_failure:
1643 	return false;
1644 }
1645 
dce112_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1646 bool dce112_clk_src_construct(
1647 	struct dce110_clk_src *clk_src,
1648 	struct dc_context *ctx,
1649 	struct dc_bios *bios,
1650 	enum clock_source_id id,
1651 	const struct dce110_clk_src_regs *regs,
1652 	const struct dce110_clk_src_shift *cs_shift,
1653 	const struct dce110_clk_src_mask *cs_mask)
1654 {
1655 	clk_src->base.ctx = ctx;
1656 	clk_src->bios = bios;
1657 	clk_src->base.id = id;
1658 	clk_src->base.funcs = &dce112_clk_src_funcs;
1659 
1660 	clk_src->regs = regs;
1661 	clk_src->cs_shift = cs_shift;
1662 	clk_src->cs_mask = cs_mask;
1663 
1664 	if (!clk_src->bios->fw_info_valid) {
1665 		ASSERT_CRITICAL(false);
1666 		return false;
1667 	}
1668 
1669 	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1670 
1671 	return true;
1672 }
1673 
dcn20_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1674 bool dcn20_clk_src_construct(
1675 	struct dce110_clk_src *clk_src,
1676 	struct dc_context *ctx,
1677 	struct dc_bios *bios,
1678 	enum clock_source_id id,
1679 	const struct dce110_clk_src_regs *regs,
1680 	const struct dce110_clk_src_shift *cs_shift,
1681 	const struct dce110_clk_src_mask *cs_mask)
1682 {
1683 	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1684 
1685 	clk_src->base.funcs = &dcn20_clk_src_funcs;
1686 
1687 	return ret;
1688 }
1689 
dcn3_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1690 bool dcn3_clk_src_construct(
1691 	struct dce110_clk_src *clk_src,
1692 	struct dc_context *ctx,
1693 	struct dc_bios *bios,
1694 	enum clock_source_id id,
1695 	const struct dce110_clk_src_regs *regs,
1696 	const struct dce110_clk_src_shift *cs_shift,
1697 	const struct dce110_clk_src_mask *cs_mask)
1698 {
1699 	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1700 
1701 	clk_src->base.funcs = &dcn3_clk_src_funcs;
1702 
1703 	return ret;
1704 }
1705 
dcn31_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1706 bool dcn31_clk_src_construct(
1707 	struct dce110_clk_src *clk_src,
1708 	struct dc_context *ctx,
1709 	struct dc_bios *bios,
1710 	enum clock_source_id id,
1711 	const struct dce110_clk_src_regs *regs,
1712 	const struct dce110_clk_src_shift *cs_shift,
1713 	const struct dce110_clk_src_mask *cs_mask)
1714 {
1715 	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1716 
1717 	clk_src->base.funcs = &dcn31_clk_src_funcs;
1718 
1719 	return ret;
1720 }
1721 
dcn301_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1722 bool dcn301_clk_src_construct(
1723 	struct dce110_clk_src *clk_src,
1724 	struct dc_context *ctx,
1725 	struct dc_bios *bios,
1726 	enum clock_source_id id,
1727 	const struct dce110_clk_src_regs *regs,
1728 	const struct dce110_clk_src_shift *cs_shift,
1729 	const struct dce110_clk_src_mask *cs_mask)
1730 {
1731 	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1732 
1733 	clk_src->base.funcs = &dcn3_clk_src_funcs;
1734 
1735 	return ret;
1736 }
1737