1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * tools/testing/selftests/kvm/include/x86_64/processor.h 4 * 5 * Copyright (C) 2018, Google LLC. 6 */ 7 8 #ifndef SELFTEST_KVM_PROCESSOR_H 9 #define SELFTEST_KVM_PROCESSOR_H 10 11 #include <assert.h> 12 #include <stdint.h> 13 #include <syscall.h> 14 15 #include <asm/msr-index.h> 16 #include <asm/prctl.h> 17 18 #include <linux/stringify.h> 19 20 #include "../kvm_util.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 25 #define NMI_VECTOR 0x02 26 27 #define X86_EFLAGS_FIXED (1u << 1) 28 29 #define X86_CR4_VME (1ul << 0) 30 #define X86_CR4_PVI (1ul << 1) 31 #define X86_CR4_TSD (1ul << 2) 32 #define X86_CR4_DE (1ul << 3) 33 #define X86_CR4_PSE (1ul << 4) 34 #define X86_CR4_PAE (1ul << 5) 35 #define X86_CR4_MCE (1ul << 6) 36 #define X86_CR4_PGE (1ul << 7) 37 #define X86_CR4_PCE (1ul << 8) 38 #define X86_CR4_OSFXSR (1ul << 9) 39 #define X86_CR4_OSXMMEXCPT (1ul << 10) 40 #define X86_CR4_UMIP (1ul << 11) 41 #define X86_CR4_LA57 (1ul << 12) 42 #define X86_CR4_VMXE (1ul << 13) 43 #define X86_CR4_SMXE (1ul << 14) 44 #define X86_CR4_FSGSBASE (1ul << 16) 45 #define X86_CR4_PCIDE (1ul << 17) 46 #define X86_CR4_OSXSAVE (1ul << 18) 47 #define X86_CR4_SMEP (1ul << 20) 48 #define X86_CR4_SMAP (1ul << 21) 49 #define X86_CR4_PKE (1ul << 22) 50 51 struct xstate_header { 52 u64 xstate_bv; 53 u64 xcomp_bv; 54 u64 reserved[6]; 55 } __attribute__((packed)); 56 57 struct xstate { 58 u8 i387[512]; 59 struct xstate_header header; 60 u8 extended_state_area[0]; 61 } __attribute__ ((packed, aligned (64))); 62 63 #define XFEATURE_MASK_FP BIT_ULL(0) 64 #define XFEATURE_MASK_SSE BIT_ULL(1) 65 #define XFEATURE_MASK_YMM BIT_ULL(2) 66 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 67 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 68 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 69 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 70 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 71 #define XFEATURE_MASK_PT BIT_ULL(8) 72 #define XFEATURE_MASK_PKRU BIT_ULL(9) 73 #define XFEATURE_MASK_PASID BIT_ULL(10) 74 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 75 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 76 #define XFEATURE_MASK_LBR BIT_ULL(15) 77 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 78 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 79 80 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 81 XFEATURE_MASK_ZMM_Hi256 | \ 82 XFEATURE_MASK_Hi16_ZMM) 83 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 84 XFEATURE_MASK_XTILE_CFG) 85 86 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 87 enum cpuid_output_regs { 88 KVM_CPUID_EAX, 89 KVM_CPUID_EBX, 90 KVM_CPUID_ECX, 91 KVM_CPUID_EDX 92 }; 93 94 /* 95 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 96 * passed by value with no overhead. 97 */ 98 struct kvm_x86_cpu_feature { 99 u32 function; 100 u16 index; 101 u8 reg; 102 u8 bit; 103 }; 104 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 105 ({ \ 106 struct kvm_x86_cpu_feature feature = { \ 107 .function = fn, \ 108 .index = idx, \ 109 .reg = KVM_CPUID_##gpr, \ 110 .bit = __bit, \ 111 }; \ 112 \ 113 kvm_static_assert((fn & 0xc0000000) == 0 || \ 114 (fn & 0xc0000000) == 0x40000000 || \ 115 (fn & 0xc0000000) == 0x80000000 || \ 116 (fn & 0xc0000000) == 0xc0000000); \ 117 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 118 feature; \ 119 }) 120 121 /* 122 * Basic Leafs, a.k.a. Intel defined 123 */ 124 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 125 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 126 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 127 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 128 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 129 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 130 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 131 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 132 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 133 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 134 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 135 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 136 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 137 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 138 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 139 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 140 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 141 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 142 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 143 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 144 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 145 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 146 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 147 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 148 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 149 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 150 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 151 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 152 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 153 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 154 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 155 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 156 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 157 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 158 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 159 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 160 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 161 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 162 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 163 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 164 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 165 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 166 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 167 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 168 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 169 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 170 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 171 172 /* 173 * Extended Leafs, a.k.a. AMD defined 174 */ 175 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 176 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 177 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 178 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 179 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 180 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 181 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 182 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 183 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 184 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 185 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 186 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 187 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 188 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 189 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 190 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 191 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 192 193 /* 194 * KVM defined paravirt features. 195 */ 196 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 197 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 198 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 199 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 200 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 201 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 202 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 203 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 204 /* Bit 8 apparently isn't used?!?! */ 205 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 206 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 207 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 208 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 209 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 210 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 211 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 212 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 213 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 214 215 /* 216 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 217 * value/property as opposed to a single-bit feature. Again, pack the info 218 * into a 64-bit value to pass by value with no overhead. 219 */ 220 struct kvm_x86_cpu_property { 221 u32 function; 222 u8 index; 223 u8 reg; 224 u8 lo_bit; 225 u8 hi_bit; 226 }; 227 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 228 ({ \ 229 struct kvm_x86_cpu_property property = { \ 230 .function = fn, \ 231 .index = idx, \ 232 .reg = KVM_CPUID_##gpr, \ 233 .lo_bit = low_bit, \ 234 .hi_bit = high_bit, \ 235 }; \ 236 \ 237 kvm_static_assert(low_bit < high_bit); \ 238 kvm_static_assert((fn & 0xc0000000) == 0 || \ 239 (fn & 0xc0000000) == 0x40000000 || \ 240 (fn & 0xc0000000) == 0x80000000 || \ 241 (fn & 0xc0000000) == 0xc0000000); \ 242 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 243 property; \ 244 }) 245 246 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 247 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 248 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 249 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 250 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 251 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7) 252 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 253 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 254 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 255 256 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 257 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 258 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 259 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 260 261 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 262 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 263 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 264 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 265 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 266 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 267 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 268 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 269 270 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 271 272 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 273 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 274 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 275 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 276 277 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 278 279 /* 280 * Intel's architectural PMU events are bizarre. They have a "feature" bit 281 * that indicates the feature is _not_ supported, and a property that states 282 * the length of the bit mask of unsupported features. A feature is supported 283 * if the size of the bit mask is larger than the "unavailable" bit, and said 284 * bit is not set. 285 * 286 * Wrap the "unavailable" feature to simplify checking whether or not a given 287 * architectural event is supported. 288 */ 289 struct kvm_x86_pmu_feature { 290 struct kvm_x86_cpu_feature anti_feature; 291 }; 292 #define KVM_X86_PMU_FEATURE(name, __bit) \ 293 ({ \ 294 struct kvm_x86_pmu_feature feature = { \ 295 .anti_feature = KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit), \ 296 }; \ 297 \ 298 feature; \ 299 }) 300 301 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(BRANCH_INSNS_RETIRED, 5) 302 x86_family(unsigned int eax)303 static inline unsigned int x86_family(unsigned int eax) 304 { 305 unsigned int x86; 306 307 x86 = (eax >> 8) & 0xf; 308 309 if (x86 == 0xf) 310 x86 += (eax >> 20) & 0xff; 311 312 return x86; 313 } 314 x86_model(unsigned int eax)315 static inline unsigned int x86_model(unsigned int eax) 316 { 317 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 318 } 319 320 /* Page table bitfield declarations */ 321 #define PTE_PRESENT_MASK BIT_ULL(0) 322 #define PTE_WRITABLE_MASK BIT_ULL(1) 323 #define PTE_USER_MASK BIT_ULL(2) 324 #define PTE_ACCESSED_MASK BIT_ULL(5) 325 #define PTE_DIRTY_MASK BIT_ULL(6) 326 #define PTE_LARGE_MASK BIT_ULL(7) 327 #define PTE_GLOBAL_MASK BIT_ULL(8) 328 #define PTE_NX_MASK BIT_ULL(63) 329 330 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 331 332 #define PAGE_SHIFT 12 333 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 334 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 335 336 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 337 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 338 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 339 340 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 341 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 342 343 /* General Registers in 64-Bit Mode */ 344 struct gpr64_regs { 345 u64 rax; 346 u64 rcx; 347 u64 rdx; 348 u64 rbx; 349 u64 rsp; 350 u64 rbp; 351 u64 rsi; 352 u64 rdi; 353 u64 r8; 354 u64 r9; 355 u64 r10; 356 u64 r11; 357 u64 r12; 358 u64 r13; 359 u64 r14; 360 u64 r15; 361 }; 362 363 struct desc64 { 364 uint16_t limit0; 365 uint16_t base0; 366 unsigned base1:8, type:4, s:1, dpl:2, p:1; 367 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 368 uint32_t base3; 369 uint32_t zero1; 370 } __attribute__((packed)); 371 372 struct desc_ptr { 373 uint16_t size; 374 uint64_t address; 375 } __attribute__((packed)); 376 377 struct kvm_x86_state { 378 struct kvm_xsave *xsave; 379 struct kvm_vcpu_events events; 380 struct kvm_mp_state mp_state; 381 struct kvm_regs regs; 382 struct kvm_xcrs xcrs; 383 struct kvm_sregs sregs; 384 struct kvm_debugregs debugregs; 385 union { 386 struct kvm_nested_state nested; 387 char nested_[16384]; 388 }; 389 struct kvm_msrs msrs; 390 }; 391 get_desc64_base(const struct desc64 * desc)392 static inline uint64_t get_desc64_base(const struct desc64 *desc) 393 { 394 return ((uint64_t)desc->base3 << 32) | 395 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 396 } 397 rdtsc(void)398 static inline uint64_t rdtsc(void) 399 { 400 uint32_t eax, edx; 401 uint64_t tsc_val; 402 /* 403 * The lfence is to wait (on Intel CPUs) until all previous 404 * instructions have been executed. If software requires RDTSC to be 405 * executed prior to execution of any subsequent instruction, it can 406 * execute LFENCE immediately after RDTSC 407 */ 408 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 409 tsc_val = ((uint64_t)edx) << 32 | eax; 410 return tsc_val; 411 } 412 rdtscp(uint32_t * aux)413 static inline uint64_t rdtscp(uint32_t *aux) 414 { 415 uint32_t eax, edx; 416 417 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 418 return ((uint64_t)edx) << 32 | eax; 419 } 420 rdmsr(uint32_t msr)421 static inline uint64_t rdmsr(uint32_t msr) 422 { 423 uint32_t a, d; 424 425 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 426 427 return a | ((uint64_t) d << 32); 428 } 429 wrmsr(uint32_t msr,uint64_t value)430 static inline void wrmsr(uint32_t msr, uint64_t value) 431 { 432 uint32_t a = value; 433 uint32_t d = value >> 32; 434 435 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 436 } 437 438 inw(uint16_t port)439 static inline uint16_t inw(uint16_t port) 440 { 441 uint16_t tmp; 442 443 __asm__ __volatile__("in %%dx, %%ax" 444 : /* output */ "=a" (tmp) 445 : /* input */ "d" (port)); 446 447 return tmp; 448 } 449 get_es(void)450 static inline uint16_t get_es(void) 451 { 452 uint16_t es; 453 454 __asm__ __volatile__("mov %%es, %[es]" 455 : /* output */ [es]"=rm"(es)); 456 return es; 457 } 458 get_cs(void)459 static inline uint16_t get_cs(void) 460 { 461 uint16_t cs; 462 463 __asm__ __volatile__("mov %%cs, %[cs]" 464 : /* output */ [cs]"=rm"(cs)); 465 return cs; 466 } 467 get_ss(void)468 static inline uint16_t get_ss(void) 469 { 470 uint16_t ss; 471 472 __asm__ __volatile__("mov %%ss, %[ss]" 473 : /* output */ [ss]"=rm"(ss)); 474 return ss; 475 } 476 get_ds(void)477 static inline uint16_t get_ds(void) 478 { 479 uint16_t ds; 480 481 __asm__ __volatile__("mov %%ds, %[ds]" 482 : /* output */ [ds]"=rm"(ds)); 483 return ds; 484 } 485 get_fs(void)486 static inline uint16_t get_fs(void) 487 { 488 uint16_t fs; 489 490 __asm__ __volatile__("mov %%fs, %[fs]" 491 : /* output */ [fs]"=rm"(fs)); 492 return fs; 493 } 494 get_gs(void)495 static inline uint16_t get_gs(void) 496 { 497 uint16_t gs; 498 499 __asm__ __volatile__("mov %%gs, %[gs]" 500 : /* output */ [gs]"=rm"(gs)); 501 return gs; 502 } 503 get_tr(void)504 static inline uint16_t get_tr(void) 505 { 506 uint16_t tr; 507 508 __asm__ __volatile__("str %[tr]" 509 : /* output */ [tr]"=rm"(tr)); 510 return tr; 511 } 512 get_cr0(void)513 static inline uint64_t get_cr0(void) 514 { 515 uint64_t cr0; 516 517 __asm__ __volatile__("mov %%cr0, %[cr0]" 518 : /* output */ [cr0]"=r"(cr0)); 519 return cr0; 520 } 521 get_cr3(void)522 static inline uint64_t get_cr3(void) 523 { 524 uint64_t cr3; 525 526 __asm__ __volatile__("mov %%cr3, %[cr3]" 527 : /* output */ [cr3]"=r"(cr3)); 528 return cr3; 529 } 530 get_cr4(void)531 static inline uint64_t get_cr4(void) 532 { 533 uint64_t cr4; 534 535 __asm__ __volatile__("mov %%cr4, %[cr4]" 536 : /* output */ [cr4]"=r"(cr4)); 537 return cr4; 538 } 539 set_cr4(uint64_t val)540 static inline void set_cr4(uint64_t val) 541 { 542 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 543 } 544 xgetbv(u32 index)545 static inline u64 xgetbv(u32 index) 546 { 547 u32 eax, edx; 548 549 __asm__ __volatile__("xgetbv;" 550 : "=a" (eax), "=d" (edx) 551 : "c" (index)); 552 return eax | ((u64)edx << 32); 553 } 554 xsetbv(u32 index,u64 value)555 static inline void xsetbv(u32 index, u64 value) 556 { 557 u32 eax = value; 558 u32 edx = value >> 32; 559 560 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 561 } 562 wrpkru(u32 pkru)563 static inline void wrpkru(u32 pkru) 564 { 565 /* Note, ECX and EDX are architecturally required to be '0'. */ 566 asm volatile(".byte 0x0f,0x01,0xef\n\t" 567 : : "a" (pkru), "c"(0), "d"(0)); 568 } 569 get_gdt(void)570 static inline struct desc_ptr get_gdt(void) 571 { 572 struct desc_ptr gdt; 573 __asm__ __volatile__("sgdt %[gdt]" 574 : /* output */ [gdt]"=m"(gdt)); 575 return gdt; 576 } 577 get_idt(void)578 static inline struct desc_ptr get_idt(void) 579 { 580 struct desc_ptr idt; 581 __asm__ __volatile__("sidt %[idt]" 582 : /* output */ [idt]"=m"(idt)); 583 return idt; 584 } 585 outl(uint16_t port,uint32_t value)586 static inline void outl(uint16_t port, uint32_t value) 587 { 588 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 589 } 590 __cpuid(uint32_t function,uint32_t index,uint32_t * eax,uint32_t * ebx,uint32_t * ecx,uint32_t * edx)591 static inline void __cpuid(uint32_t function, uint32_t index, 592 uint32_t *eax, uint32_t *ebx, 593 uint32_t *ecx, uint32_t *edx) 594 { 595 *eax = function; 596 *ecx = index; 597 598 asm volatile("cpuid" 599 : "=a" (*eax), 600 "=b" (*ebx), 601 "=c" (*ecx), 602 "=d" (*edx) 603 : "0" (*eax), "2" (*ecx) 604 : "memory"); 605 } 606 cpuid(uint32_t function,uint32_t * eax,uint32_t * ebx,uint32_t * ecx,uint32_t * edx)607 static inline void cpuid(uint32_t function, 608 uint32_t *eax, uint32_t *ebx, 609 uint32_t *ecx, uint32_t *edx) 610 { 611 return __cpuid(function, 0, eax, ebx, ecx, edx); 612 } 613 this_cpu_fms(void)614 static inline uint32_t this_cpu_fms(void) 615 { 616 uint32_t eax, ebx, ecx, edx; 617 618 cpuid(1, &eax, &ebx, &ecx, &edx); 619 return eax; 620 } 621 this_cpu_family(void)622 static inline uint32_t this_cpu_family(void) 623 { 624 return x86_family(this_cpu_fms()); 625 } 626 this_cpu_model(void)627 static inline uint32_t this_cpu_model(void) 628 { 629 return x86_model(this_cpu_fms()); 630 } 631 this_cpu_vendor_string_is(const char * vendor)632 static inline bool this_cpu_vendor_string_is(const char *vendor) 633 { 634 const uint32_t *chunk = (const uint32_t *)vendor; 635 uint32_t eax, ebx, ecx, edx; 636 637 cpuid(0, &eax, &ebx, &ecx, &edx); 638 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 639 } 640 this_cpu_is_intel(void)641 static inline bool this_cpu_is_intel(void) 642 { 643 return this_cpu_vendor_string_is("GenuineIntel"); 644 } 645 646 /* 647 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 648 */ this_cpu_is_amd(void)649 static inline bool this_cpu_is_amd(void) 650 { 651 return this_cpu_vendor_string_is("AuthenticAMD"); 652 } 653 __this_cpu_has(uint32_t function,uint32_t index,uint8_t reg,uint8_t lo,uint8_t hi)654 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, 655 uint8_t reg, uint8_t lo, uint8_t hi) 656 { 657 uint32_t gprs[4]; 658 659 __cpuid(function, index, 660 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 661 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 662 663 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 664 } 665 this_cpu_has(struct kvm_x86_cpu_feature feature)666 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 667 { 668 return __this_cpu_has(feature.function, feature.index, 669 feature.reg, feature.bit, feature.bit); 670 } 671 this_cpu_property(struct kvm_x86_cpu_property property)672 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) 673 { 674 return __this_cpu_has(property.function, property.index, 675 property.reg, property.lo_bit, property.hi_bit); 676 } 677 this_cpu_has_p(struct kvm_x86_cpu_property property)678 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 679 { 680 uint32_t max_leaf; 681 682 switch (property.function & 0xc0000000) { 683 case 0: 684 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 685 break; 686 case 0x40000000: 687 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 688 break; 689 case 0x80000000: 690 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 691 break; 692 case 0xc0000000: 693 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 694 } 695 return max_leaf >= property.function; 696 } 697 this_pmu_has(struct kvm_x86_pmu_feature feature)698 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 699 { 700 uint32_t nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 701 702 return nr_bits > feature.anti_feature.bit && 703 !this_cpu_has(feature.anti_feature); 704 } 705 this_cpu_supported_xcr0(void)706 static __always_inline uint64_t this_cpu_supported_xcr0(void) 707 { 708 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 709 return 0; 710 711 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 712 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 713 } 714 715 typedef u32 __attribute__((vector_size(16))) sse128_t; 716 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 717 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 718 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 719 read_sse_reg(int reg,sse128_t * data)720 static inline void read_sse_reg(int reg, sse128_t *data) 721 { 722 switch (reg) { 723 case 0: 724 asm("movdqa %%xmm0, %0" : "=m"(*data)); 725 break; 726 case 1: 727 asm("movdqa %%xmm1, %0" : "=m"(*data)); 728 break; 729 case 2: 730 asm("movdqa %%xmm2, %0" : "=m"(*data)); 731 break; 732 case 3: 733 asm("movdqa %%xmm3, %0" : "=m"(*data)); 734 break; 735 case 4: 736 asm("movdqa %%xmm4, %0" : "=m"(*data)); 737 break; 738 case 5: 739 asm("movdqa %%xmm5, %0" : "=m"(*data)); 740 break; 741 case 6: 742 asm("movdqa %%xmm6, %0" : "=m"(*data)); 743 break; 744 case 7: 745 asm("movdqa %%xmm7, %0" : "=m"(*data)); 746 break; 747 default: 748 BUG(); 749 } 750 } 751 write_sse_reg(int reg,const sse128_t * data)752 static inline void write_sse_reg(int reg, const sse128_t *data) 753 { 754 switch (reg) { 755 case 0: 756 asm("movdqa %0, %%xmm0" : : "m"(*data)); 757 break; 758 case 1: 759 asm("movdqa %0, %%xmm1" : : "m"(*data)); 760 break; 761 case 2: 762 asm("movdqa %0, %%xmm2" : : "m"(*data)); 763 break; 764 case 3: 765 asm("movdqa %0, %%xmm3" : : "m"(*data)); 766 break; 767 case 4: 768 asm("movdqa %0, %%xmm4" : : "m"(*data)); 769 break; 770 case 5: 771 asm("movdqa %0, %%xmm5" : : "m"(*data)); 772 break; 773 case 6: 774 asm("movdqa %0, %%xmm6" : : "m"(*data)); 775 break; 776 case 7: 777 asm("movdqa %0, %%xmm7" : : "m"(*data)); 778 break; 779 default: 780 BUG(); 781 } 782 } 783 cpu_relax(void)784 static inline void cpu_relax(void) 785 { 786 asm volatile("rep; nop" ::: "memory"); 787 } 788 789 #define ud2() \ 790 __asm__ __volatile__( \ 791 "ud2\n" \ 792 ) 793 794 #define hlt() \ 795 __asm__ __volatile__( \ 796 "hlt\n" \ 797 ) 798 799 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 800 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 801 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 802 803 const struct kvm_msr_list *kvm_get_msr_index_list(void); 804 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 805 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); 806 uint64_t kvm_get_feature_msr(uint64_t msr_index); 807 vcpu_msrs_get(struct kvm_vcpu * vcpu,struct kvm_msrs * msrs)808 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 809 struct kvm_msrs *msrs) 810 { 811 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 812 813 TEST_ASSERT(r == msrs->nmsrs, 814 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 815 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 816 } vcpu_msrs_set(struct kvm_vcpu * vcpu,struct kvm_msrs * msrs)817 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 818 { 819 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 820 821 TEST_ASSERT(r == msrs->nmsrs, 822 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 823 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 824 } vcpu_debugregs_get(struct kvm_vcpu * vcpu,struct kvm_debugregs * debugregs)825 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 826 struct kvm_debugregs *debugregs) 827 { 828 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 829 } vcpu_debugregs_set(struct kvm_vcpu * vcpu,struct kvm_debugregs * debugregs)830 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 831 struct kvm_debugregs *debugregs) 832 { 833 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 834 } vcpu_xsave_get(struct kvm_vcpu * vcpu,struct kvm_xsave * xsave)835 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 836 struct kvm_xsave *xsave) 837 { 838 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 839 } vcpu_xsave2_get(struct kvm_vcpu * vcpu,struct kvm_xsave * xsave)840 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 841 struct kvm_xsave *xsave) 842 { 843 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 844 } vcpu_xsave_set(struct kvm_vcpu * vcpu,struct kvm_xsave * xsave)845 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 846 struct kvm_xsave *xsave) 847 { 848 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 849 } vcpu_xcrs_get(struct kvm_vcpu * vcpu,struct kvm_xcrs * xcrs)850 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 851 struct kvm_xcrs *xcrs) 852 { 853 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 854 } vcpu_xcrs_set(struct kvm_vcpu * vcpu,struct kvm_xcrs * xcrs)855 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 856 { 857 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 858 } 859 860 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 861 uint32_t function, uint32_t index); 862 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 863 const struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void); 864 const struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vcpu *vcpu); 865 kvm_cpu_fms(void)866 static inline uint32_t kvm_cpu_fms(void) 867 { 868 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 869 } 870 kvm_cpu_family(void)871 static inline uint32_t kvm_cpu_family(void) 872 { 873 return x86_family(kvm_cpu_fms()); 874 } 875 kvm_cpu_model(void)876 static inline uint32_t kvm_cpu_model(void) 877 { 878 return x86_model(kvm_cpu_fms()); 879 } 880 881 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 882 struct kvm_x86_cpu_feature feature); 883 kvm_cpu_has(struct kvm_x86_cpu_feature feature)884 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 885 { 886 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 887 } 888 889 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 890 struct kvm_x86_cpu_property property); 891 kvm_cpu_property(struct kvm_x86_cpu_property property)892 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) 893 { 894 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 895 } 896 kvm_cpu_has_p(struct kvm_x86_cpu_property property)897 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 898 { 899 uint32_t max_leaf; 900 901 switch (property.function & 0xc0000000) { 902 case 0: 903 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 904 break; 905 case 0x40000000: 906 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 907 break; 908 case 0x80000000: 909 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 910 break; 911 case 0xc0000000: 912 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 913 } 914 return max_leaf >= property.function; 915 } 916 kvm_pmu_has(struct kvm_x86_pmu_feature feature)917 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 918 { 919 uint32_t nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 920 921 return nr_bits > feature.anti_feature.bit && 922 !kvm_cpu_has(feature.anti_feature); 923 } 924 kvm_cpu_supported_xcr0(void)925 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) 926 { 927 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 928 return 0; 929 930 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 931 ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 932 } 933 kvm_cpuid2_size(int nr_entries)934 static inline size_t kvm_cpuid2_size(int nr_entries) 935 { 936 return sizeof(struct kvm_cpuid2) + 937 sizeof(struct kvm_cpuid_entry2) * nr_entries; 938 } 939 940 /* 941 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 942 * entries sized to hold @nr_entries. The caller is responsible for freeing 943 * the struct. 944 */ allocate_kvm_cpuid2(int nr_entries)945 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 946 { 947 struct kvm_cpuid2 *cpuid; 948 949 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 950 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 951 952 cpuid->nent = nr_entries; 953 954 return cpuid; 955 } 956 957 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 958 void vcpu_set_hv_cpuid(struct kvm_vcpu *vcpu); 959 __vcpu_get_cpuid_entry(struct kvm_vcpu * vcpu,uint32_t function,uint32_t index)960 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 961 uint32_t function, 962 uint32_t index) 963 { 964 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 965 function, index); 966 } 967 vcpu_get_cpuid_entry(struct kvm_vcpu * vcpu,uint32_t function)968 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 969 uint32_t function) 970 { 971 return __vcpu_get_cpuid_entry(vcpu, function, 0); 972 } 973 __vcpu_set_cpuid(struct kvm_vcpu * vcpu)974 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 975 { 976 int r; 977 978 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 979 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 980 if (r) 981 return r; 982 983 /* On success, refresh the cache to pick up adjustments made by KVM. */ 984 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 985 return 0; 986 } 987 vcpu_set_cpuid(struct kvm_vcpu * vcpu)988 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 989 { 990 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 991 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 992 993 /* Refresh the cache to pick up adjustments made by KVM. */ 994 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 995 } 996 997 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); 998 999 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); 1000 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1001 struct kvm_x86_cpu_feature feature, 1002 bool set); 1003 vcpu_set_cpuid_feature(struct kvm_vcpu * vcpu,struct kvm_x86_cpu_feature feature)1004 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1005 struct kvm_x86_cpu_feature feature) 1006 { 1007 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1008 1009 } 1010 vcpu_clear_cpuid_feature(struct kvm_vcpu * vcpu,struct kvm_x86_cpu_feature feature)1011 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1012 struct kvm_x86_cpu_feature feature) 1013 { 1014 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1015 } 1016 1017 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); 1018 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); 1019 1020 /* 1021 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1022 * Note, the caller provides the stringified name so that the name of macro is 1023 * printed, not the value the macro resolves to (due to macro expansion). 1024 */ 1025 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1026 do { \ 1027 if (__builtin_constant_p(msr)) { \ 1028 TEST_ASSERT(cond, fmt, str, args); \ 1029 } else if (!(cond)) { \ 1030 char buf[16]; \ 1031 \ 1032 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1033 TEST_ASSERT(cond, fmt, buf, args); \ 1034 } \ 1035 } while (0) 1036 1037 /* 1038 * Returns true if KVM should return the last written value when reading an MSR 1039 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1040 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1041 * out MSRs that are not durable _and_ that a selftest wants to write. 1042 */ is_durable_msr(uint32_t msr)1043 static inline bool is_durable_msr(uint32_t msr) 1044 { 1045 return msr != MSR_IA32_TSC; 1046 } 1047 1048 #define vcpu_set_msr(vcpu, msr, val) \ 1049 do { \ 1050 uint64_t r, v = val; \ 1051 \ 1052 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1053 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1054 if (!is_durable_msr(msr)) \ 1055 break; \ 1056 r = vcpu_get_msr(vcpu, msr); \ 1057 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1058 } while (0) 1059 1060 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1061 bool vm_is_unrestricted_guest(struct kvm_vm *vm); 1062 1063 struct ex_regs { 1064 uint64_t rax, rcx, rdx, rbx; 1065 uint64_t rbp, rsi, rdi; 1066 uint64_t r8, r9, r10, r11; 1067 uint64_t r12, r13, r14, r15; 1068 uint64_t vector; 1069 uint64_t error_code; 1070 uint64_t rip; 1071 uint64_t cs; 1072 uint64_t rflags; 1073 }; 1074 1075 struct idt_entry { 1076 uint16_t offset0; 1077 uint16_t selector; 1078 uint16_t ist : 3; 1079 uint16_t : 5; 1080 uint16_t type : 4; 1081 uint16_t : 1; 1082 uint16_t dpl : 2; 1083 uint16_t p : 1; 1084 uint16_t offset1; 1085 uint32_t offset2; uint32_t reserved; 1086 }; 1087 1088 void vm_init_descriptor_tables(struct kvm_vm *vm); 1089 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu); 1090 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1091 void (*handler)(struct ex_regs *)); 1092 1093 /* If a toddler were to say "abracadabra". */ 1094 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1095 1096 /* 1097 * KVM selftest exception fixup uses registers to coordinate with the exception 1098 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1099 * per-CPU data. Using only registers avoids having to map memory into the 1100 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1101 * for recursive faults when accessing memory in the handler. The downside to 1102 * using registers is that it restricts what registers can be used by the actual 1103 * instruction. But, selftests are 64-bit only, making register* pressure a 1104 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1105 * by the callee, and except for r11 are not implicit parameters to any 1106 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1107 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1108 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1109 * 1110 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1111 * is guaranteed to be non-zero on fault. 1112 * 1113 * REGISTER INPUTS: 1114 * r9 = MAGIC 1115 * r10 = RIP 1116 * r11 = new RIP on fault 1117 * 1118 * REGISTER OUTPUTS: 1119 * r9 = exception vector (non-zero) 1120 * r10 = error code 1121 */ 1122 #define KVM_ASM_SAFE(insn) \ 1123 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1124 "lea 1f(%%rip), %%r10\n\t" \ 1125 "lea 2f(%%rip), %%r11\n\t" \ 1126 "1: " insn "\n\t" \ 1127 "xor %%r9, %%r9\n\t" \ 1128 "2:\n\t" \ 1129 "mov %%r9b, %[vector]\n\t" \ 1130 "mov %%r10, %[error_code]\n\t" 1131 1132 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1133 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1134 1135 #define kvm_asm_safe(insn, inputs...) \ 1136 ({ \ 1137 uint64_t ign_error_code; \ 1138 uint8_t vector; \ 1139 \ 1140 asm volatile(KVM_ASM_SAFE(insn) \ 1141 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1142 : inputs \ 1143 : KVM_ASM_SAFE_CLOBBERS); \ 1144 vector; \ 1145 }) 1146 1147 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1148 ({ \ 1149 uint8_t vector; \ 1150 \ 1151 asm volatile(KVM_ASM_SAFE(insn) \ 1152 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1153 : inputs \ 1154 : KVM_ASM_SAFE_CLOBBERS); \ 1155 vector; \ 1156 }) 1157 rdmsr_safe(uint32_t msr,uint64_t * val)1158 static inline uint8_t rdmsr_safe(uint32_t msr, uint64_t *val) 1159 { 1160 uint64_t error_code; 1161 uint8_t vector; 1162 uint32_t a, d; 1163 1164 asm volatile(KVM_ASM_SAFE("rdmsr") 1165 : "=a"(a), "=d"(d), KVM_ASM_SAFE_OUTPUTS(vector, error_code) 1166 : "c"(msr) 1167 : KVM_ASM_SAFE_CLOBBERS); 1168 1169 *val = (uint64_t)a | ((uint64_t)d << 32); 1170 return vector; 1171 } 1172 wrmsr_safe(uint32_t msr,uint64_t val)1173 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) 1174 { 1175 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1176 } 1177 xsetbv_safe(uint32_t index,uint64_t value)1178 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) 1179 { 1180 u32 eax = value; 1181 u32 edx = value >> 32; 1182 1183 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1184 } 1185 1186 bool kvm_is_tdp_enabled(void); 1187 1188 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, 1189 int *level); 1190 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); 1191 1192 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1193 uint64_t a3); 1194 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1195 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1196 1197 void __vm_xsave_require_permission(uint64_t xfeature, const char *name); 1198 1199 #define vm_xsave_require_permission(xfeature) \ 1200 __vm_xsave_require_permission(xfeature, #xfeature) 1201 1202 enum pg_level { 1203 PG_LEVEL_NONE, 1204 PG_LEVEL_4K, 1205 PG_LEVEL_2M, 1206 PG_LEVEL_1G, 1207 PG_LEVEL_512G, 1208 PG_LEVEL_NUM 1209 }; 1210 1211 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1212 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1213 1214 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1215 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1216 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1217 1218 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level); 1219 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 1220 uint64_t nr_bytes, int level); 1221 1222 /* 1223 * Basic CPU control in CR0 1224 */ 1225 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1226 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1227 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1228 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1229 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1230 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1231 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1232 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1233 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1234 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1235 #define X86_CR0_PG (1UL<<31) /* Paging */ 1236 1237 #define PFERR_PRESENT_BIT 0 1238 #define PFERR_WRITE_BIT 1 1239 #define PFERR_USER_BIT 2 1240 #define PFERR_RSVD_BIT 3 1241 #define PFERR_FETCH_BIT 4 1242 #define PFERR_PK_BIT 5 1243 #define PFERR_SGX_BIT 15 1244 #define PFERR_GUEST_FINAL_BIT 32 1245 #define PFERR_GUEST_PAGE_BIT 33 1246 #define PFERR_IMPLICIT_ACCESS_BIT 48 1247 1248 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1249 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1250 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1251 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1252 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1253 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1254 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1255 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1256 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1257 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1258 1259 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1260