1 /*
2 * Copyright 2021 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "priv.h"
23 #include "cgrp.h"
24 #include "chan.h"
25 #include "chid.h"
26 #include "runl.h"
27 #include "runq.h"
28
29 #include <core/gpuobj.h>
30 #include <subdev/top.h>
31 #include <subdev/vfn.h>
32
33 #include <nvif/class.h>
34
35 static u32
ga100_chan_doorbell_handle(struct nvkm_chan * chan)36 ga100_chan_doorbell_handle(struct nvkm_chan *chan)
37 {
38 return (chan->cgrp->runl->doorbell << 16) | chan->id;
39 }
40
41 static void
ga100_chan_stop(struct nvkm_chan * chan)42 ga100_chan_stop(struct nvkm_chan *chan)
43 {
44 struct nvkm_runl *runl = chan->cgrp->runl;
45
46 nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0x00000003);
47 }
48
49 static void
ga100_chan_start(struct nvkm_chan * chan)50 ga100_chan_start(struct nvkm_chan *chan)
51 {
52 struct nvkm_runl *runl = chan->cgrp->runl;
53 struct nvkm_device *device = runl->fifo->engine.subdev.device;
54 const int gfid = 0;
55
56 nvkm_wr32(device, runl->chan + (chan->id * 4), 0x00000002);
57 nvkm_wr32(device, runl->addr + 0x0090, (gfid << 16) | chan->id); /* INTERNAL_DOORBELL. */
58 }
59
60 static void
ga100_chan_unbind(struct nvkm_chan * chan)61 ga100_chan_unbind(struct nvkm_chan *chan)
62 {
63 struct nvkm_runl *runl = chan->cgrp->runl;
64
65 nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0xffffffff);
66 }
67
68 static int
ga100_chan_ramfc_write(struct nvkm_chan * chan,u64 offset,u64 length,u32 devm,bool priv)69 ga100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
70 {
71 const u32 limit2 = ilog2(length / 8);
72
73 nvkm_kmap(chan->inst);
74 nvkm_wo32(chan->inst, 0x010, 0x0000face);
75 nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
76 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
77 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
78 nvkm_wo32(chan->inst, 0x084, 0x20400000);
79 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
80 nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
81 nvkm_wo32(chan->inst, 0x0e8, chan->id);
82 nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));
83 nvkm_wo32(chan->inst, 0x0f8, 0x80000000 | chan->cgrp->runl->nonstall.vector);
84 nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
85 nvkm_done(chan->inst);
86 return 0;
87 }
88
89 static const struct nvkm_chan_func_ramfc
90 ga100_chan_ramfc = {
91 .write = ga100_chan_ramfc_write,
92 .devm = 0xfff,
93 .priv = true,
94 };
95
96 const struct nvkm_chan_func
97 ga100_chan = {
98 .inst = &gf100_chan_inst,
99 .userd = &gv100_chan_userd,
100 .ramfc = &ga100_chan_ramfc,
101 .unbind = ga100_chan_unbind,
102 .start = ga100_chan_start,
103 .stop = ga100_chan_stop,
104 .preempt = gk110_chan_preempt,
105 .doorbell_handle = ga100_chan_doorbell_handle,
106 };
107
108 static void
ga100_cgrp_preempt(struct nvkm_cgrp * cgrp)109 ga100_cgrp_preempt(struct nvkm_cgrp *cgrp)
110 {
111 struct nvkm_runl *runl = cgrp->runl;
112
113 nvkm_wr32(runl->fifo->engine.subdev.device, runl->addr + 0x098, 0x01000000 | cgrp->id);
114 }
115
116 const struct nvkm_cgrp_func
117 ga100_cgrp = {
118 .preempt = ga100_cgrp_preempt,
119 };
120
121 static int
ga100_engn_cxid(struct nvkm_engn * engn,bool * cgid)122 ga100_engn_cxid(struct nvkm_engn *engn, bool *cgid)
123 {
124 struct nvkm_runl *runl = engn->runl;
125 struct nvkm_device *device = runl->fifo->engine.subdev.device;
126 u32 stat = nvkm_rd32(device, runl->addr + 0x200 + engn->id * 0x40);
127
128 ENGN_DEBUG(engn, "status %08x", stat);
129 *cgid = true;
130
131 switch ((stat & 0x0000e000) >> 13) {
132 case 0 /* INVALID */: return -ENODEV;
133 case 1 /* VALID */:
134 case 5 /* SAVE */: return (stat & 0x00000fff);
135 case 6 /* LOAD */: return (stat & 0x0fff0000) >> 16;
136 case 7 /* SWITCH */:
137 if (nvkm_engine_chsw_load(engn->engine))
138 return (stat & 0x0fff0000) >> 16;
139 return (stat & 0x00000fff);
140 default:
141 WARN_ON(1);
142 break;
143 }
144
145 return -ENODEV;
146 }
147
148 static int
ga100_engn_nonstall(struct nvkm_engn * engn)149 ga100_engn_nonstall(struct nvkm_engn *engn)
150 {
151 struct nvkm_engine *engine = engn->engine;
152
153 if (WARN_ON(!engine->func->nonstall))
154 return -EINVAL;
155
156 return engine->func->nonstall(engine);
157 }
158
159 const struct nvkm_engn_func
160 ga100_engn = {
161 .nonstall = ga100_engn_nonstall,
162 .cxid = ga100_engn_cxid,
163 .ctor = gk104_ectx_ctor,
164 .bind = gv100_ectx_bind,
165 };
166
167 const struct nvkm_engn_func
168 ga100_engn_ce = {
169 .nonstall = ga100_engn_nonstall,
170 .cxid = ga100_engn_cxid,
171 .ctor = gv100_ectx_ce_ctor,
172 .bind = gv100_ectx_ce_bind,
173 };
174
175 static bool
ga100_runq_idle(struct nvkm_runq * runq)176 ga100_runq_idle(struct nvkm_runq *runq)
177 {
178 struct nvkm_device *device = runq->fifo->engine.subdev.device;
179
180 return !(nvkm_rd32(device, 0x04015c + (runq->id * 0x800)) & 0x0000e000);
181 }
182
183 static bool
ga100_runq_intr_1(struct nvkm_runq * runq,struct nvkm_runl * runl)184 ga100_runq_intr_1(struct nvkm_runq *runq, struct nvkm_runl *runl)
185 {
186 struct nvkm_device *device = runq->fifo->engine.subdev.device;
187 u32 inte = nvkm_rd32(device, 0x040180 + (runq->id * 0x800));
188 u32 intr = nvkm_rd32(device, 0x040148 + (runq->id * 0x800));
189 u32 stat = intr & inte;
190
191 if (!stat) {
192 RUNQ_DEBUG(runq, "inte1 %08x %08x", intr, inte);
193 return false;
194 }
195
196 if (stat & 0x80000000) {
197 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask;
198 struct nvkm_chan *chan;
199 unsigned long flags;
200
201 RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid);
202 chan = nvkm_runl_chan_get_chid(runl, chid, &flags);
203 if (chan) {
204 nvkm_chan_error(chan, true);
205 nvkm_chan_put(&chan, flags);
206 }
207
208 nvkm_mask(device, 0x0400ac + (runq->id * 0x800), 0x00030000, 0x00030000);
209 stat &= ~0x80000000;
210 }
211
212 if (stat) {
213 RUNQ_ERROR(runq, "intr1 %08x", stat);
214 nvkm_wr32(device, 0x0401a0 + (runq->id * 0x800), stat);
215 }
216
217 nvkm_wr32(device, 0x040148 + (runq->id * 0x800), intr);
218 return true;
219 }
220
221 static bool
ga100_runq_intr_0(struct nvkm_runq * runq,struct nvkm_runl * runl)222 ga100_runq_intr_0(struct nvkm_runq *runq, struct nvkm_runl *runl)
223 {
224 struct nvkm_device *device = runq->fifo->engine.subdev.device;
225 u32 inte = nvkm_rd32(device, 0x040170 + (runq->id * 0x800));
226 u32 intr = nvkm_rd32(device, 0x040108 + (runq->id * 0x800));
227 u32 stat = intr & inte;
228
229 if (!stat) {
230 RUNQ_DEBUG(runq, "inte0 %08x %08x", intr, inte);
231 return false;
232 }
233
234 /*TODO: expand on this when fixing up gf100's version. */
235 if (stat & 0xc6afe000) {
236 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x0800)) & runl->chid->mask;
237 struct nvkm_chan *chan;
238 unsigned long flags;
239
240 RUNQ_ERROR(runq, "intr0 %08x", stat);
241 chan = nvkm_runl_chan_get_chid(runl, chid, &flags);
242 if (chan) {
243 nvkm_chan_error(chan, true);
244 nvkm_chan_put(&chan, flags);
245 }
246
247 stat &= ~0xc6afe000;
248 }
249
250 if (stat) {
251 RUNQ_ERROR(runq, "intr0 %08x", stat);
252 nvkm_wr32(device, 0x040190 + (runq->id * 0x800), stat);
253 }
254
255 nvkm_wr32(device, 0x040108 + (runq->id * 0x800), intr);
256 return true;
257 }
258
259 static bool
ga100_runq_intr(struct nvkm_runq * runq,struct nvkm_runl * runl)260 ga100_runq_intr(struct nvkm_runq *runq, struct nvkm_runl *runl)
261 {
262 bool intr0 = ga100_runq_intr_0(runq, runl);
263 bool intr1 = ga100_runq_intr_1(runq, runl);
264
265 return intr0 || intr1;
266 }
267
268 static void
ga100_runq_init(struct nvkm_runq * runq)269 ga100_runq_init(struct nvkm_runq *runq)
270 {
271 struct nvkm_device *device = runq->fifo->engine.subdev.device;
272
273 nvkm_wr32(device, 0x040108 + (runq->id * 0x800), 0xffffffff); /* INTR_0 */
274 nvkm_wr32(device, 0x040148 + (runq->id * 0x800), 0xffffffff); /* INTR_1 */
275 nvkm_wr32(device, 0x040170 + (runq->id * 0x800), 0xffffffff); /* INTR_0_EN_SET_TREE */
276 nvkm_wr32(device, 0x040180 + (runq->id * 0x800), 0xffffffff); /* INTR_1_EN_SET_TREE */
277 }
278
279 const struct nvkm_runq_func
280 ga100_runq = {
281 .init = ga100_runq_init,
282 .intr = ga100_runq_intr,
283 .idle = ga100_runq_idle,
284 };
285
286 static bool
ga100_runl_preempt_pending(struct nvkm_runl * runl)287 ga100_runl_preempt_pending(struct nvkm_runl *runl)
288 {
289 return nvkm_rd32(runl->fifo->engine.subdev.device, runl->addr + 0x098) & 0x00100000;
290 }
291
292 static void
ga100_runl_preempt(struct nvkm_runl * runl)293 ga100_runl_preempt(struct nvkm_runl *runl)
294 {
295 nvkm_wr32(runl->fifo->engine.subdev.device, runl->addr + 0x098, 0x00000000);
296 }
297
298 static void
ga100_runl_allow(struct nvkm_runl * runl,u32 engm)299 ga100_runl_allow(struct nvkm_runl *runl, u32 engm)
300 {
301 nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x094, 0x00000001, 0x00000000);
302 }
303
304 static void
ga100_runl_block(struct nvkm_runl * runl,u32 engm)305 ga100_runl_block(struct nvkm_runl *runl, u32 engm)
306 {
307 nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x094, 0x00000001, 0x00000001);
308 }
309
310 static bool
ga100_runl_pending(struct nvkm_runl * runl)311 ga100_runl_pending(struct nvkm_runl *runl)
312 {
313 struct nvkm_device *device = runl->fifo->engine.subdev.device;
314
315 return nvkm_rd32(device, runl->addr + 0x08c) & 0x00008000;
316 }
317
318 static void
ga100_runl_commit(struct nvkm_runl * runl,struct nvkm_memory * memory,u32 start,int count)319 ga100_runl_commit(struct nvkm_runl *runl, struct nvkm_memory *memory, u32 start, int count)
320 {
321 struct nvkm_device *device = runl->fifo->engine.subdev.device;
322 u64 addr = nvkm_memory_addr(memory) + start;
323
324 nvkm_wr32(device, runl->addr + 0x080, lower_32_bits(addr));
325 nvkm_wr32(device, runl->addr + 0x084, upper_32_bits(addr));
326 nvkm_wr32(device, runl->addr + 0x088, count);
327 }
328
329 static irqreturn_t
ga100_runl_intr(struct nvkm_inth * inth)330 ga100_runl_intr(struct nvkm_inth *inth)
331 {
332 struct nvkm_runl *runl = container_of(inth, typeof(*runl), inth);
333 struct nvkm_engn *engn;
334 struct nvkm_device *device = runl->fifo->engine.subdev.device;
335 u32 inte = nvkm_rd32(device, runl->addr + 0x120);
336 u32 intr = nvkm_rd32(device, runl->addr + 0x100);
337 u32 stat = intr & inte;
338 u32 info;
339
340 if (!stat) {
341 RUNL_DEBUG(runl, "inte %08x %08x", intr, inte);
342 return IRQ_NONE;
343 }
344
345 if (stat & 0x00000007) {
346 nvkm_runl_foreach_engn_cond(engn, runl, stat & BIT(engn->id)) {
347 info = nvkm_rd32(device, runl->addr + 0x224 + (engn->id * 0x40));
348
349 tu102_fifo_intr_ctxsw_timeout_info(engn, info);
350
351 nvkm_wr32(device, runl->addr + 0x100, BIT(engn->id));
352 stat &= ~BIT(engn->id);
353 }
354 }
355
356 if (stat & 0x00000300) {
357 nvkm_wr32(device, runl->addr + 0x100, stat & 0x00000300);
358 stat &= ~0x00000300;
359 }
360
361 if (stat & 0x00010000) {
362 if (runl->runq[0]) {
363 if (runl->runq[0]->func->intr(runl->runq[0], runl))
364 stat &= ~0x00010000;
365 }
366 }
367
368 if (stat & 0x00020000) {
369 if (runl->runq[1]) {
370 if (runl->runq[1]->func->intr(runl->runq[1], runl))
371 stat &= ~0x00020000;
372 }
373 }
374
375 if (stat) {
376 RUNL_ERROR(runl, "intr %08x", stat);
377 nvkm_wr32(device, runl->addr + 0x140, stat);
378 }
379
380 nvkm_wr32(device, runl->addr + 0x180, 0x00000001);
381 return IRQ_HANDLED;
382 }
383
384 static void
ga100_runl_fini(struct nvkm_runl * runl)385 ga100_runl_fini(struct nvkm_runl *runl)
386 {
387 nvkm_mask(runl->fifo->engine.subdev.device, runl->addr + 0x300, 0x80000000, 0x00000000);
388 nvkm_inth_block(&runl->inth);
389 }
390
391 static void
ga100_runl_init(struct nvkm_runl * runl)392 ga100_runl_init(struct nvkm_runl *runl)
393 {
394 struct nvkm_fifo *fifo = runl->fifo;
395 struct nvkm_runq *runq;
396 struct nvkm_device *device = fifo->engine.subdev.device;
397 int i;
398
399 /* Submit NULL runlist and preempt. */
400 nvkm_wr32(device, runl->addr + 0x088, 0x00000000);
401 runl->func->preempt(runl);
402
403 /* Enable doorbell. */
404 nvkm_mask(device, runl->addr + 0x300, 0x80000000, 0x80000000);
405
406 nvkm_wr32(device, runl->addr + 0x100, 0xffffffff); /* INTR_0 */
407 nvkm_wr32(device, runl->addr + 0x140, 0xffffffff); /* INTR_0_EN_CLEAR_TREE(0) */
408 nvkm_wr32(device, runl->addr + 0x120, 0x000f1307); /* INTR_0_EN_SET_TREE(0) */
409 nvkm_wr32(device, runl->addr + 0x148, 0xffffffff); /* INTR_0_EN_CLEAR_TREE(1) */
410 nvkm_wr32(device, runl->addr + 0x128, 0x00000000); /* INTR_0_EN_SET_TREE(1) */
411
412 /* Init PBDMA(s). */
413 for (i = 0; i < runl->runq_nr; i++) {
414 runq = runl->runq[i];
415 runq->func->init(runq);
416 }
417
418 nvkm_inth_allow(&runl->inth);
419 }
420
421 const struct nvkm_runl_func
422 ga100_runl = {
423 .init = ga100_runl_init,
424 .fini = ga100_runl_fini,
425 .size = 16,
426 .update = nv50_runl_update,
427 .insert_cgrp = gv100_runl_insert_cgrp,
428 .insert_chan = gv100_runl_insert_chan,
429 .commit = ga100_runl_commit,
430 .wait = nv50_runl_wait,
431 .pending = ga100_runl_pending,
432 .block = ga100_runl_block,
433 .allow = ga100_runl_allow,
434 .preempt = ga100_runl_preempt,
435 .preempt_pending = ga100_runl_preempt_pending,
436 };
437
438 static int
ga100_runl_new(struct nvkm_fifo * fifo,int id,u32 addr,struct nvkm_runl ** prunl)439 ga100_runl_new(struct nvkm_fifo *fifo, int id, u32 addr, struct nvkm_runl **prunl)
440 {
441 struct nvkm_device *device = fifo->engine.subdev.device;
442 struct nvkm_top_device *tdev;
443 struct nvkm_runl *runl;
444 struct nvkm_engn *engn;
445 u32 chcfg = nvkm_rd32(device, addr + 0x004);
446 u32 chnum = 1 << (chcfg & 0x0000000f);
447 u32 chaddr = (chcfg & 0xfffffff0);
448 u32 dbcfg = nvkm_rd32(device, addr + 0x008);
449 u32 vector = nvkm_rd32(device, addr + 0x160);
450 int i, ret;
451
452 runl = nvkm_runl_new(fifo, id, addr, chnum);
453 if (IS_ERR(runl))
454 return PTR_ERR(runl);
455
456 *prunl = runl;
457
458 for (i = 0; i < 2; i++) {
459 u32 pbcfg = nvkm_rd32(device, addr + 0x010 + (i * 0x04));
460 if (pbcfg & 0x80000000) {
461 runl->runq[runl->runq_nr] =
462 nvkm_runq_new(fifo, ((pbcfg & 0x03fffc00) - 0x040000) / 0x800);
463 if (!runl->runq[runl->runq_nr]) {
464 RUNL_ERROR(runl, "runq %d", runl->runq_nr);
465 return -ENOMEM;
466 }
467
468 runl->runq_nr++;
469 }
470 }
471
472 nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist == runl->addr) {
473 if (tdev->engine < 0) {
474 RUNL_DEBUG(runl, "engn !top");
475 return -EINVAL;
476 }
477
478 engn = nvkm_runl_add(runl, tdev->engine, (tdev->type == NVKM_ENGINE_CE) ?
479 fifo->func->engn_ce : fifo->func->engn,
480 tdev->type, tdev->inst);
481 if (!engn)
482 return -EINVAL;
483
484 if (!engn->engine->func->nonstall) {
485 RUNL_DEBUG(runl, "engn %s !nonstall", engn->engine->subdev.name);
486 return -EINVAL;
487 }
488 }
489
490 if (list_empty(&runl->engns)) {
491 RUNL_DEBUG(runl, "!engns");
492 return -EINVAL;
493 }
494
495 ret = nvkm_inth_add(&device->vfn->intr, vector & 0x00000fff, NVKM_INTR_PRIO_NORMAL,
496 &fifo->engine.subdev, ga100_runl_intr, &runl->inth);
497 if (ret) {
498 RUNL_ERROR(runl, "inth %d", ret);
499 return ret;
500 }
501
502 runl->chan = chaddr;
503 runl->doorbell = dbcfg >> 16;
504 return 0;
505 }
506
507 static irqreturn_t
ga100_fifo_nonstall_intr(struct nvkm_inth * inth)508 ga100_fifo_nonstall_intr(struct nvkm_inth *inth)
509 {
510 struct nvkm_runl *runl = container_of(inth, typeof(*runl), nonstall.inth);
511
512 nvkm_event_ntfy(&runl->fifo->nonstall.event, runl->id, NVKM_FIFO_NONSTALL_EVENT);
513 return IRQ_HANDLED;
514 }
515
516 static void
ga100_fifo_nonstall_block(struct nvkm_event * event,int type,int index)517 ga100_fifo_nonstall_block(struct nvkm_event *event, int type, int index)
518 {
519 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
520 struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0);
521
522 nvkm_inth_block(&runl->nonstall.inth);
523 }
524
525 static void
ga100_fifo_nonstall_allow(struct nvkm_event * event,int type,int index)526 ga100_fifo_nonstall_allow(struct nvkm_event *event, int type, int index)
527 {
528 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
529 struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0);
530
531 nvkm_inth_allow(&runl->nonstall.inth);
532 }
533
534 const struct nvkm_event_func
535 ga100_fifo_nonstall = {
536 .init = ga100_fifo_nonstall_allow,
537 .fini = ga100_fifo_nonstall_block,
538 };
539
540 int
ga100_fifo_nonstall_ctor(struct nvkm_fifo * fifo)541 ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)
542 {
543 struct nvkm_subdev *subdev = &fifo->engine.subdev;
544 struct nvkm_vfn *vfn = subdev->device->vfn;
545 struct nvkm_runl *runl;
546 int ret, nr = 0;
547
548 nvkm_runl_foreach(runl, fifo) {
549 struct nvkm_engn *engn = list_first_entry(&runl->engns, typeof(*engn), head);
550
551 runl->nonstall.vector = engn->func->nonstall(engn);
552 if (runl->nonstall.vector < 0) {
553 RUNL_ERROR(runl, "nonstall %d", runl->nonstall.vector);
554 return runl->nonstall.vector;
555 }
556
557 ret = nvkm_inth_add(&vfn->intr, runl->nonstall.vector, NVKM_INTR_PRIO_NORMAL,
558 subdev, ga100_fifo_nonstall_intr, &runl->nonstall.inth);
559 if (ret)
560 return ret;
561
562 nr = max(nr, runl->id + 1);
563 }
564
565 return nr;
566 }
567
568 int
ga100_fifo_runl_ctor(struct nvkm_fifo * fifo)569 ga100_fifo_runl_ctor(struct nvkm_fifo *fifo)
570 {
571 struct nvkm_device *device = fifo->engine.subdev.device;
572 struct nvkm_top_device *tdev;
573 struct nvkm_runl *runl;
574 int id = 0, ret;
575
576 nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist >= 0) {
577 runl = nvkm_runl_get(fifo, -1, tdev->runlist);
578 if (!runl) {
579 ret = ga100_runl_new(fifo, id++, tdev->runlist, &runl);
580 if (ret) {
581 if (runl)
582 nvkm_runl_del(runl);
583
584 continue;
585 }
586 }
587 }
588
589 return 0;
590 }
591
592 static const struct nvkm_fifo_func
593 ga100_fifo = {
594 .runl_ctor = ga100_fifo_runl_ctor,
595 .mmu_fault = &tu102_fifo_mmu_fault,
596 .nonstall_ctor = ga100_fifo_nonstall_ctor,
597 .nonstall = &ga100_fifo_nonstall,
598 .runl = &ga100_runl,
599 .runq = &ga100_runq,
600 .engn = &ga100_engn,
601 .engn_ce = &ga100_engn_ce,
602 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &ga100_cgrp, .force = true },
603 .chan = {{ 0, 0, AMPERE_CHANNEL_GPFIFO_A }, &ga100_chan },
604 };
605
606 int
ga100_fifo_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)607 ga100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
608 struct nvkm_fifo **pfifo)
609 {
610 return nvkm_fifo_new_(&ga100_fifo, device, type, inst, pfifo);
611 }
612