xref: /openbmc/linux/drivers/clk/meson/g12a.c (revision ccbfbd36)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Amlogic Meson-G12A Clock Controller Driver
4  *
5  * Copyright (c) 2016 Baylibre SAS.
6  * Author: Michael Turquette <mturquette@baylibre.com>
7  *
8  * Copyright (c) 2018 Amlogic, inc.
9  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10  * Author: Jian Hu <jian.hu@amlogic.com>
11  */
12 
13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
19 
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
25 #include "meson-eeclk.h"
26 #include "g12a.h"
27 
28 #include <dt-bindings/clock/g12a-clkc.h>
29 
30 static DEFINE_SPINLOCK(meson_clk_lock);
31 
32 static struct clk_regmap g12a_fixed_pll_dco = {
33 	.data = &(struct meson_clk_pll_data){
34 		.en = {
35 			.reg_off = HHI_FIX_PLL_CNTL0,
36 			.shift   = 28,
37 			.width   = 1,
38 		},
39 		.m = {
40 			.reg_off = HHI_FIX_PLL_CNTL0,
41 			.shift   = 0,
42 			.width   = 8,
43 		},
44 		.n = {
45 			.reg_off = HHI_FIX_PLL_CNTL0,
46 			.shift   = 10,
47 			.width   = 5,
48 		},
49 		.frac = {
50 			.reg_off = HHI_FIX_PLL_CNTL1,
51 			.shift   = 0,
52 			.width   = 17,
53 		},
54 		.l = {
55 			.reg_off = HHI_FIX_PLL_CNTL0,
56 			.shift   = 31,
57 			.width   = 1,
58 		},
59 		.rst = {
60 			.reg_off = HHI_FIX_PLL_CNTL0,
61 			.shift   = 29,
62 			.width   = 1,
63 		},
64 	},
65 	.hw.init = &(struct clk_init_data){
66 		.name = "fixed_pll_dco",
67 		.ops = &meson_clk_pll_ro_ops,
68 		.parent_data = &(const struct clk_parent_data) {
69 			.fw_name = "xtal",
70 		},
71 		.num_parents = 1,
72 	},
73 };
74 
75 static struct clk_regmap g12a_fixed_pll = {
76 	.data = &(struct clk_regmap_div_data){
77 		.offset = HHI_FIX_PLL_CNTL0,
78 		.shift = 16,
79 		.width = 2,
80 		.flags = CLK_DIVIDER_POWER_OF_TWO,
81 	},
82 	.hw.init = &(struct clk_init_data){
83 		.name = "fixed_pll",
84 		.ops = &clk_regmap_divider_ro_ops,
85 		.parent_hws = (const struct clk_hw *[]) {
86 			&g12a_fixed_pll_dco.hw
87 		},
88 		.num_parents = 1,
89 		/*
90 		 * This clock won't ever change at runtime so
91 		 * CLK_SET_RATE_PARENT is not required
92 		 */
93 	},
94 };
95 
96 static const struct pll_mult_range g12a_sys_pll_mult_range = {
97 	.min = 128,
98 	.max = 250,
99 };
100 
101 static struct clk_regmap g12a_sys_pll_dco = {
102 	.data = &(struct meson_clk_pll_data){
103 		.en = {
104 			.reg_off = HHI_SYS_PLL_CNTL0,
105 			.shift   = 28,
106 			.width   = 1,
107 		},
108 		.m = {
109 			.reg_off = HHI_SYS_PLL_CNTL0,
110 			.shift   = 0,
111 			.width   = 8,
112 		},
113 		.n = {
114 			.reg_off = HHI_SYS_PLL_CNTL0,
115 			.shift   = 10,
116 			.width   = 5,
117 		},
118 		.l = {
119 			.reg_off = HHI_SYS_PLL_CNTL0,
120 			.shift   = 31,
121 			.width   = 1,
122 		},
123 		.rst = {
124 			.reg_off = HHI_SYS_PLL_CNTL0,
125 			.shift   = 29,
126 			.width   = 1,
127 		},
128 		.range = &g12a_sys_pll_mult_range,
129 	},
130 	.hw.init = &(struct clk_init_data){
131 		.name = "sys_pll_dco",
132 		.ops = &meson_clk_pll_ops,
133 		.parent_data = &(const struct clk_parent_data) {
134 			.fw_name = "xtal",
135 		},
136 		.num_parents = 1,
137 		/* This clock feeds the CPU, avoid disabling it */
138 		.flags = CLK_IS_CRITICAL,
139 	},
140 };
141 
142 static struct clk_regmap g12a_sys_pll = {
143 	.data = &(struct clk_regmap_div_data){
144 		.offset = HHI_SYS_PLL_CNTL0,
145 		.shift = 16,
146 		.width = 3,
147 		.flags = CLK_DIVIDER_POWER_OF_TWO,
148 	},
149 	.hw.init = &(struct clk_init_data){
150 		.name = "sys_pll",
151 		.ops = &clk_regmap_divider_ops,
152 		.parent_hws = (const struct clk_hw *[]) {
153 			&g12a_sys_pll_dco.hw
154 		},
155 		.num_parents = 1,
156 		.flags = CLK_SET_RATE_PARENT,
157 	},
158 };
159 
160 static struct clk_regmap g12b_sys1_pll_dco = {
161 	.data = &(struct meson_clk_pll_data){
162 		.en = {
163 			.reg_off = HHI_SYS1_PLL_CNTL0,
164 			.shift   = 28,
165 			.width   = 1,
166 		},
167 		.m = {
168 			.reg_off = HHI_SYS1_PLL_CNTL0,
169 			.shift   = 0,
170 			.width   = 8,
171 		},
172 		.n = {
173 			.reg_off = HHI_SYS1_PLL_CNTL0,
174 			.shift   = 10,
175 			.width   = 5,
176 		},
177 		.l = {
178 			.reg_off = HHI_SYS1_PLL_CNTL0,
179 			.shift   = 31,
180 			.width   = 1,
181 		},
182 		.rst = {
183 			.reg_off = HHI_SYS1_PLL_CNTL0,
184 			.shift   = 29,
185 			.width   = 1,
186 		},
187 		.range = &g12a_sys_pll_mult_range,
188 	},
189 	.hw.init = &(struct clk_init_data){
190 		.name = "sys1_pll_dco",
191 		.ops = &meson_clk_pll_ops,
192 		.parent_data = &(const struct clk_parent_data) {
193 			.fw_name = "xtal",
194 		},
195 		.num_parents = 1,
196 		/* This clock feeds the CPU, avoid disabling it */
197 		.flags = CLK_IS_CRITICAL,
198 	},
199 };
200 
201 static struct clk_regmap g12b_sys1_pll = {
202 	.data = &(struct clk_regmap_div_data){
203 		.offset = HHI_SYS1_PLL_CNTL0,
204 		.shift = 16,
205 		.width = 3,
206 		.flags = CLK_DIVIDER_POWER_OF_TWO,
207 	},
208 	.hw.init = &(struct clk_init_data){
209 		.name = "sys1_pll",
210 		.ops = &clk_regmap_divider_ops,
211 		.parent_hws = (const struct clk_hw *[]) {
212 			&g12b_sys1_pll_dco.hw
213 		},
214 		.num_parents = 1,
215 		.flags = CLK_SET_RATE_PARENT,
216 	},
217 };
218 
219 static struct clk_regmap g12a_sys_pll_div16_en = {
220 	.data = &(struct clk_regmap_gate_data){
221 		.offset = HHI_SYS_CPU_CLK_CNTL1,
222 		.bit_idx = 24,
223 	},
224 	.hw.init = &(struct clk_init_data) {
225 		.name = "sys_pll_div16_en",
226 		.ops = &clk_regmap_gate_ro_ops,
227 		.parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
228 		.num_parents = 1,
229 		/*
230 		 * This clock is used to debug the sys_pll range
231 		 * Linux should not change it at runtime
232 		 */
233 	},
234 };
235 
236 static struct clk_regmap g12b_sys1_pll_div16_en = {
237 	.data = &(struct clk_regmap_gate_data){
238 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
239 		.bit_idx = 24,
240 	},
241 	.hw.init = &(struct clk_init_data) {
242 		.name = "sys1_pll_div16_en",
243 		.ops = &clk_regmap_gate_ro_ops,
244 		.parent_hws = (const struct clk_hw *[]) {
245 			&g12b_sys1_pll.hw
246 		},
247 		.num_parents = 1,
248 		/*
249 		 * This clock is used to debug the sys_pll range
250 		 * Linux should not change it at runtime
251 		 */
252 	},
253 };
254 
255 static struct clk_fixed_factor g12a_sys_pll_div16 = {
256 	.mult = 1,
257 	.div = 16,
258 	.hw.init = &(struct clk_init_data){
259 		.name = "sys_pll_div16",
260 		.ops = &clk_fixed_factor_ops,
261 		.parent_hws = (const struct clk_hw *[]) {
262 			&g12a_sys_pll_div16_en.hw
263 		},
264 		.num_parents = 1,
265 	},
266 };
267 
268 static struct clk_fixed_factor g12b_sys1_pll_div16 = {
269 	.mult = 1,
270 	.div = 16,
271 	.hw.init = &(struct clk_init_data){
272 		.name = "sys1_pll_div16",
273 		.ops = &clk_fixed_factor_ops,
274 		.parent_hws = (const struct clk_hw *[]) {
275 			&g12b_sys1_pll_div16_en.hw
276 		},
277 		.num_parents = 1,
278 	},
279 };
280 
281 static struct clk_fixed_factor g12a_fclk_div2_div = {
282 	.mult = 1,
283 	.div = 2,
284 	.hw.init = &(struct clk_init_data){
285 		.name = "fclk_div2_div",
286 		.ops = &clk_fixed_factor_ops,
287 		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
288 		.num_parents = 1,
289 	},
290 };
291 
292 static struct clk_regmap g12a_fclk_div2 = {
293 	.data = &(struct clk_regmap_gate_data){
294 		.offset = HHI_FIX_PLL_CNTL1,
295 		.bit_idx = 24,
296 	},
297 	.hw.init = &(struct clk_init_data){
298 		.name = "fclk_div2",
299 		.ops = &clk_regmap_gate_ops,
300 		.parent_hws = (const struct clk_hw *[]) {
301 			&g12a_fclk_div2_div.hw
302 		},
303 		.num_parents = 1,
304 		/*
305 		 * Similar to fclk_div3, it seems that this clock is used by
306 		 * the resident firmware and is required by the platform to
307 		 * operate correctly.
308 		 * Until the following condition are met, we need this clock to
309 		 * be marked as critical:
310 		 * a) Mark the clock used by a firmware resource, if possible
311 		 * b) CCF has a clock hand-off mechanism to make the sure the
312 		 *    clock stays on until the proper driver comes along
313 		 */
314 		.flags = CLK_IS_CRITICAL,
315 	},
316 };
317 
318 static struct clk_fixed_factor g12a_fclk_div3_div = {
319 	.mult = 1,
320 	.div = 3,
321 	.hw.init = &(struct clk_init_data){
322 		.name = "fclk_div3_div",
323 		.ops = &clk_fixed_factor_ops,
324 		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
325 		.num_parents = 1,
326 	},
327 };
328 
329 static struct clk_regmap g12a_fclk_div3 = {
330 	.data = &(struct clk_regmap_gate_data){
331 		.offset = HHI_FIX_PLL_CNTL1,
332 		.bit_idx = 20,
333 	},
334 	.hw.init = &(struct clk_init_data){
335 		.name = "fclk_div3",
336 		.ops = &clk_regmap_gate_ops,
337 		.parent_hws = (const struct clk_hw *[]) {
338 			&g12a_fclk_div3_div.hw
339 		},
340 		.num_parents = 1,
341 		/*
342 		 * This clock is used by the resident firmware and is required
343 		 * by the platform to operate correctly.
344 		 * Until the following condition are met, we need this clock to
345 		 * be marked as critical:
346 		 * a) Mark the clock used by a firmware resource, if possible
347 		 * b) CCF has a clock hand-off mechanism to make the sure the
348 		 *    clock stays on until the proper driver comes along
349 		 */
350 		.flags = CLK_IS_CRITICAL,
351 	},
352 };
353 
354 /* Datasheet names this field as "premux0" */
355 static struct clk_regmap g12a_cpu_clk_premux0 = {
356 	.data = &(struct clk_regmap_mux_data){
357 		.offset = HHI_SYS_CPU_CLK_CNTL0,
358 		.mask = 0x3,
359 		.shift = 0,
360 		.flags = CLK_MUX_ROUND_CLOSEST,
361 	},
362 	.hw.init = &(struct clk_init_data){
363 		.name = "cpu_clk_dyn0_sel",
364 		.ops = &clk_regmap_mux_ops,
365 		.parent_data = (const struct clk_parent_data []) {
366 			{ .fw_name = "xtal", },
367 			{ .hw = &g12a_fclk_div2.hw },
368 			{ .hw = &g12a_fclk_div3.hw },
369 		},
370 		.num_parents = 3,
371 		.flags = CLK_SET_RATE_PARENT,
372 	},
373 };
374 
375 /* Datasheet names this field as "premux1" */
376 static struct clk_regmap g12a_cpu_clk_premux1 = {
377 	.data = &(struct clk_regmap_mux_data){
378 		.offset = HHI_SYS_CPU_CLK_CNTL0,
379 		.mask = 0x3,
380 		.shift = 16,
381 	},
382 	.hw.init = &(struct clk_init_data){
383 		.name = "cpu_clk_dyn1_sel",
384 		.ops = &clk_regmap_mux_ops,
385 		.parent_data = (const struct clk_parent_data []) {
386 			{ .fw_name = "xtal", },
387 			{ .hw = &g12a_fclk_div2.hw },
388 			{ .hw = &g12a_fclk_div3.hw },
389 		},
390 		.num_parents = 3,
391 		/* This sub-tree is used a parking clock */
392 		.flags = CLK_SET_RATE_NO_REPARENT
393 	},
394 };
395 
396 /* Datasheet names this field as "mux0_divn_tcnt" */
397 static struct clk_regmap g12a_cpu_clk_mux0_div = {
398 	.data = &(struct meson_clk_cpu_dyndiv_data){
399 		.div = {
400 			.reg_off = HHI_SYS_CPU_CLK_CNTL0,
401 			.shift = 4,
402 			.width = 6,
403 		},
404 		.dyn = {
405 			.reg_off = HHI_SYS_CPU_CLK_CNTL0,
406 			.shift = 26,
407 			.width = 1,
408 		},
409 	},
410 	.hw.init = &(struct clk_init_data){
411 		.name = "cpu_clk_dyn0_div",
412 		.ops = &meson_clk_cpu_dyndiv_ops,
413 		.parent_hws = (const struct clk_hw *[]) {
414 			&g12a_cpu_clk_premux0.hw
415 		},
416 		.num_parents = 1,
417 		.flags = CLK_SET_RATE_PARENT,
418 	},
419 };
420 
421 /* Datasheet names this field as "postmux0" */
422 static struct clk_regmap g12a_cpu_clk_postmux0 = {
423 	.data = &(struct clk_regmap_mux_data){
424 		.offset = HHI_SYS_CPU_CLK_CNTL0,
425 		.mask = 0x1,
426 		.shift = 2,
427 		.flags = CLK_MUX_ROUND_CLOSEST,
428 	},
429 	.hw.init = &(struct clk_init_data){
430 		.name = "cpu_clk_dyn0",
431 		.ops = &clk_regmap_mux_ops,
432 		.parent_hws = (const struct clk_hw *[]) {
433 			&g12a_cpu_clk_premux0.hw,
434 			&g12a_cpu_clk_mux0_div.hw,
435 		},
436 		.num_parents = 2,
437 		.flags = CLK_SET_RATE_PARENT,
438 	},
439 };
440 
441 /* Datasheet names this field as "Mux1_divn_tcnt" */
442 static struct clk_regmap g12a_cpu_clk_mux1_div = {
443 	.data = &(struct clk_regmap_div_data){
444 		.offset = HHI_SYS_CPU_CLK_CNTL0,
445 		.shift = 20,
446 		.width = 6,
447 	},
448 	.hw.init = &(struct clk_init_data){
449 		.name = "cpu_clk_dyn1_div",
450 		.ops = &clk_regmap_divider_ro_ops,
451 		.parent_hws = (const struct clk_hw *[]) {
452 			&g12a_cpu_clk_premux1.hw
453 		},
454 		.num_parents = 1,
455 	},
456 };
457 
458 /* Datasheet names this field as "postmux1" */
459 static struct clk_regmap g12a_cpu_clk_postmux1 = {
460 	.data = &(struct clk_regmap_mux_data){
461 		.offset = HHI_SYS_CPU_CLK_CNTL0,
462 		.mask = 0x1,
463 		.shift = 18,
464 	},
465 	.hw.init = &(struct clk_init_data){
466 		.name = "cpu_clk_dyn1",
467 		.ops = &clk_regmap_mux_ops,
468 		.parent_hws = (const struct clk_hw *[]) {
469 			&g12a_cpu_clk_premux1.hw,
470 			&g12a_cpu_clk_mux1_div.hw,
471 		},
472 		.num_parents = 2,
473 		/* This sub-tree is used a parking clock */
474 		.flags = CLK_SET_RATE_NO_REPARENT,
475 	},
476 };
477 
478 /* Datasheet names this field as "Final_dyn_mux_sel" */
479 static struct clk_regmap g12a_cpu_clk_dyn = {
480 	.data = &(struct clk_regmap_mux_data){
481 		.offset = HHI_SYS_CPU_CLK_CNTL0,
482 		.mask = 0x1,
483 		.shift = 10,
484 		.flags = CLK_MUX_ROUND_CLOSEST,
485 	},
486 	.hw.init = &(struct clk_init_data){
487 		.name = "cpu_clk_dyn",
488 		.ops = &clk_regmap_mux_ops,
489 		.parent_hws = (const struct clk_hw *[]) {
490 			&g12a_cpu_clk_postmux0.hw,
491 			&g12a_cpu_clk_postmux1.hw,
492 		},
493 		.num_parents = 2,
494 		.flags = CLK_SET_RATE_PARENT,
495 	},
496 };
497 
498 /* Datasheet names this field as "Final_mux_sel" */
499 static struct clk_regmap g12a_cpu_clk = {
500 	.data = &(struct clk_regmap_mux_data){
501 		.offset = HHI_SYS_CPU_CLK_CNTL0,
502 		.mask = 0x1,
503 		.shift = 11,
504 		.flags = CLK_MUX_ROUND_CLOSEST,
505 	},
506 	.hw.init = &(struct clk_init_data){
507 		.name = "cpu_clk",
508 		.ops = &clk_regmap_mux_ops,
509 		.parent_hws = (const struct clk_hw *[]) {
510 			&g12a_cpu_clk_dyn.hw,
511 			&g12a_sys_pll.hw,
512 		},
513 		.num_parents = 2,
514 		.flags = CLK_SET_RATE_PARENT,
515 	},
516 };
517 
518 /* Datasheet names this field as "Final_mux_sel" */
519 static struct clk_regmap g12b_cpu_clk = {
520 	.data = &(struct clk_regmap_mux_data){
521 		.offset = HHI_SYS_CPU_CLK_CNTL0,
522 		.mask = 0x1,
523 		.shift = 11,
524 		.flags = CLK_MUX_ROUND_CLOSEST,
525 	},
526 	.hw.init = &(struct clk_init_data){
527 		.name = "cpu_clk",
528 		.ops = &clk_regmap_mux_ops,
529 		.parent_hws = (const struct clk_hw *[]) {
530 			&g12a_cpu_clk_dyn.hw,
531 			&g12b_sys1_pll.hw
532 		},
533 		.num_parents = 2,
534 		.flags = CLK_SET_RATE_PARENT,
535 	},
536 };
537 
538 /* Datasheet names this field as "premux0" */
539 static struct clk_regmap g12b_cpub_clk_premux0 = {
540 	.data = &(struct clk_regmap_mux_data){
541 		.offset = HHI_SYS_CPUB_CLK_CNTL,
542 		.mask = 0x3,
543 		.shift = 0,
544 		.flags = CLK_MUX_ROUND_CLOSEST,
545 	},
546 	.hw.init = &(struct clk_init_data){
547 		.name = "cpub_clk_dyn0_sel",
548 		.ops = &clk_regmap_mux_ops,
549 		.parent_data = (const struct clk_parent_data []) {
550 			{ .fw_name = "xtal", },
551 			{ .hw = &g12a_fclk_div2.hw },
552 			{ .hw = &g12a_fclk_div3.hw },
553 		},
554 		.num_parents = 3,
555 		.flags = CLK_SET_RATE_PARENT,
556 	},
557 };
558 
559 /* Datasheet names this field as "mux0_divn_tcnt" */
560 static struct clk_regmap g12b_cpub_clk_mux0_div = {
561 	.data = &(struct meson_clk_cpu_dyndiv_data){
562 		.div = {
563 			.reg_off = HHI_SYS_CPUB_CLK_CNTL,
564 			.shift = 4,
565 			.width = 6,
566 		},
567 		.dyn = {
568 			.reg_off = HHI_SYS_CPUB_CLK_CNTL,
569 			.shift = 26,
570 			.width = 1,
571 		},
572 	},
573 	.hw.init = &(struct clk_init_data){
574 		.name = "cpub_clk_dyn0_div",
575 		.ops = &meson_clk_cpu_dyndiv_ops,
576 		.parent_hws = (const struct clk_hw *[]) {
577 			&g12b_cpub_clk_premux0.hw
578 		},
579 		.num_parents = 1,
580 		.flags = CLK_SET_RATE_PARENT,
581 	},
582 };
583 
584 /* Datasheet names this field as "postmux0" */
585 static struct clk_regmap g12b_cpub_clk_postmux0 = {
586 	.data = &(struct clk_regmap_mux_data){
587 		.offset = HHI_SYS_CPUB_CLK_CNTL,
588 		.mask = 0x1,
589 		.shift = 2,
590 		.flags = CLK_MUX_ROUND_CLOSEST,
591 	},
592 	.hw.init = &(struct clk_init_data){
593 		.name = "cpub_clk_dyn0",
594 		.ops = &clk_regmap_mux_ops,
595 		.parent_hws = (const struct clk_hw *[]) {
596 			&g12b_cpub_clk_premux0.hw,
597 			&g12b_cpub_clk_mux0_div.hw
598 		},
599 		.num_parents = 2,
600 		.flags = CLK_SET_RATE_PARENT,
601 	},
602 };
603 
604 /* Datasheet names this field as "premux1" */
605 static struct clk_regmap g12b_cpub_clk_premux1 = {
606 	.data = &(struct clk_regmap_mux_data){
607 		.offset = HHI_SYS_CPUB_CLK_CNTL,
608 		.mask = 0x3,
609 		.shift = 16,
610 	},
611 	.hw.init = &(struct clk_init_data){
612 		.name = "cpub_clk_dyn1_sel",
613 		.ops = &clk_regmap_mux_ops,
614 		.parent_data = (const struct clk_parent_data []) {
615 			{ .fw_name = "xtal", },
616 			{ .hw = &g12a_fclk_div2.hw },
617 			{ .hw = &g12a_fclk_div3.hw },
618 		},
619 		.num_parents = 3,
620 		/* This sub-tree is used a parking clock */
621 		.flags = CLK_SET_RATE_NO_REPARENT,
622 	},
623 };
624 
625 /* Datasheet names this field as "Mux1_divn_tcnt" */
626 static struct clk_regmap g12b_cpub_clk_mux1_div = {
627 	.data = &(struct clk_regmap_div_data){
628 		.offset = HHI_SYS_CPUB_CLK_CNTL,
629 		.shift = 20,
630 		.width = 6,
631 	},
632 	.hw.init = &(struct clk_init_data){
633 		.name = "cpub_clk_dyn1_div",
634 		.ops = &clk_regmap_divider_ro_ops,
635 		.parent_hws = (const struct clk_hw *[]) {
636 			&g12b_cpub_clk_premux1.hw
637 		},
638 		.num_parents = 1,
639 	},
640 };
641 
642 /* Datasheet names this field as "postmux1" */
643 static struct clk_regmap g12b_cpub_clk_postmux1 = {
644 	.data = &(struct clk_regmap_mux_data){
645 		.offset = HHI_SYS_CPUB_CLK_CNTL,
646 		.mask = 0x1,
647 		.shift = 18,
648 	},
649 	.hw.init = &(struct clk_init_data){
650 		.name = "cpub_clk_dyn1",
651 		.ops = &clk_regmap_mux_ops,
652 		.parent_hws = (const struct clk_hw *[]) {
653 			&g12b_cpub_clk_premux1.hw,
654 			&g12b_cpub_clk_mux1_div.hw
655 		},
656 		.num_parents = 2,
657 		/* This sub-tree is used a parking clock */
658 		.flags = CLK_SET_RATE_NO_REPARENT,
659 	},
660 };
661 
662 /* Datasheet names this field as "Final_dyn_mux_sel" */
663 static struct clk_regmap g12b_cpub_clk_dyn = {
664 	.data = &(struct clk_regmap_mux_data){
665 		.offset = HHI_SYS_CPUB_CLK_CNTL,
666 		.mask = 0x1,
667 		.shift = 10,
668 		.flags = CLK_MUX_ROUND_CLOSEST,
669 	},
670 	.hw.init = &(struct clk_init_data){
671 		.name = "cpub_clk_dyn",
672 		.ops = &clk_regmap_mux_ops,
673 		.parent_hws = (const struct clk_hw *[]) {
674 			&g12b_cpub_clk_postmux0.hw,
675 			&g12b_cpub_clk_postmux1.hw
676 		},
677 		.num_parents = 2,
678 		.flags = CLK_SET_RATE_PARENT,
679 	},
680 };
681 
682 /* Datasheet names this field as "Final_mux_sel" */
683 static struct clk_regmap g12b_cpub_clk = {
684 	.data = &(struct clk_regmap_mux_data){
685 		.offset = HHI_SYS_CPUB_CLK_CNTL,
686 		.mask = 0x1,
687 		.shift = 11,
688 		.flags = CLK_MUX_ROUND_CLOSEST,
689 	},
690 	.hw.init = &(struct clk_init_data){
691 		.name = "cpub_clk",
692 		.ops = &clk_regmap_mux_ops,
693 		.parent_hws = (const struct clk_hw *[]) {
694 			&g12b_cpub_clk_dyn.hw,
695 			&g12a_sys_pll.hw
696 		},
697 		.num_parents = 2,
698 		.flags = CLK_SET_RATE_PARENT,
699 	},
700 };
701 
702 static struct clk_regmap sm1_gp1_pll;
703 
704 /* Datasheet names this field as "premux0" */
705 static struct clk_regmap sm1_dsu_clk_premux0 = {
706 	.data = &(struct clk_regmap_mux_data){
707 		.offset = HHI_SYS_CPU_CLK_CNTL5,
708 		.mask = 0x3,
709 		.shift = 0,
710 	},
711 	.hw.init = &(struct clk_init_data){
712 		.name = "dsu_clk_dyn0_sel",
713 		.ops = &clk_regmap_mux_ro_ops,
714 		.parent_data = (const struct clk_parent_data []) {
715 			{ .fw_name = "xtal", },
716 			{ .hw = &g12a_fclk_div2.hw },
717 			{ .hw = &g12a_fclk_div3.hw },
718 			{ .hw = &sm1_gp1_pll.hw },
719 		},
720 		.num_parents = 4,
721 	},
722 };
723 
724 /* Datasheet names this field as "premux1" */
725 static struct clk_regmap sm1_dsu_clk_premux1 = {
726 	.data = &(struct clk_regmap_mux_data){
727 		.offset = HHI_SYS_CPU_CLK_CNTL5,
728 		.mask = 0x3,
729 		.shift = 16,
730 	},
731 	.hw.init = &(struct clk_init_data){
732 		.name = "dsu_clk_dyn1_sel",
733 		.ops = &clk_regmap_mux_ro_ops,
734 		.parent_data = (const struct clk_parent_data []) {
735 			{ .fw_name = "xtal", },
736 			{ .hw = &g12a_fclk_div2.hw },
737 			{ .hw = &g12a_fclk_div3.hw },
738 			{ .hw = &sm1_gp1_pll.hw },
739 		},
740 		.num_parents = 4,
741 	},
742 };
743 
744 /* Datasheet names this field as "Mux0_divn_tcnt" */
745 static struct clk_regmap sm1_dsu_clk_mux0_div = {
746 	.data = &(struct clk_regmap_div_data){
747 		.offset = HHI_SYS_CPU_CLK_CNTL5,
748 		.shift = 4,
749 		.width = 6,
750 	},
751 	.hw.init = &(struct clk_init_data){
752 		.name = "dsu_clk_dyn0_div",
753 		.ops = &clk_regmap_divider_ro_ops,
754 		.parent_hws = (const struct clk_hw *[]) {
755 			&sm1_dsu_clk_premux0.hw
756 		},
757 		.num_parents = 1,
758 	},
759 };
760 
761 /* Datasheet names this field as "postmux0" */
762 static struct clk_regmap sm1_dsu_clk_postmux0 = {
763 	.data = &(struct clk_regmap_mux_data){
764 		.offset = HHI_SYS_CPU_CLK_CNTL5,
765 		.mask = 0x1,
766 		.shift = 2,
767 	},
768 	.hw.init = &(struct clk_init_data){
769 		.name = "dsu_clk_dyn0",
770 		.ops = &clk_regmap_mux_ro_ops,
771 		.parent_hws = (const struct clk_hw *[]) {
772 			&sm1_dsu_clk_premux0.hw,
773 			&sm1_dsu_clk_mux0_div.hw,
774 		},
775 		.num_parents = 2,
776 	},
777 };
778 
779 /* Datasheet names this field as "Mux1_divn_tcnt" */
780 static struct clk_regmap sm1_dsu_clk_mux1_div = {
781 	.data = &(struct clk_regmap_div_data){
782 		.offset = HHI_SYS_CPU_CLK_CNTL5,
783 		.shift = 20,
784 		.width = 6,
785 	},
786 	.hw.init = &(struct clk_init_data){
787 		.name = "dsu_clk_dyn1_div",
788 		.ops = &clk_regmap_divider_ro_ops,
789 		.parent_hws = (const struct clk_hw *[]) {
790 			&sm1_dsu_clk_premux1.hw
791 		},
792 		.num_parents = 1,
793 	},
794 };
795 
796 /* Datasheet names this field as "postmux1" */
797 static struct clk_regmap sm1_dsu_clk_postmux1 = {
798 	.data = &(struct clk_regmap_mux_data){
799 		.offset = HHI_SYS_CPU_CLK_CNTL5,
800 		.mask = 0x1,
801 		.shift = 18,
802 	},
803 	.hw.init = &(struct clk_init_data){
804 		.name = "dsu_clk_dyn1",
805 		.ops = &clk_regmap_mux_ro_ops,
806 		.parent_hws = (const struct clk_hw *[]) {
807 			&sm1_dsu_clk_premux1.hw,
808 			&sm1_dsu_clk_mux1_div.hw,
809 		},
810 		.num_parents = 2,
811 	},
812 };
813 
814 /* Datasheet names this field as "Final_dyn_mux_sel" */
815 static struct clk_regmap sm1_dsu_clk_dyn = {
816 	.data = &(struct clk_regmap_mux_data){
817 		.offset = HHI_SYS_CPU_CLK_CNTL5,
818 		.mask = 0x1,
819 		.shift = 10,
820 	},
821 	.hw.init = &(struct clk_init_data){
822 		.name = "dsu_clk_dyn",
823 		.ops = &clk_regmap_mux_ro_ops,
824 		.parent_hws = (const struct clk_hw *[]) {
825 			&sm1_dsu_clk_postmux0.hw,
826 			&sm1_dsu_clk_postmux1.hw,
827 		},
828 		.num_parents = 2,
829 	},
830 };
831 
832 /* Datasheet names this field as "Final_mux_sel" */
833 static struct clk_regmap sm1_dsu_final_clk = {
834 	.data = &(struct clk_regmap_mux_data){
835 		.offset = HHI_SYS_CPU_CLK_CNTL5,
836 		.mask = 0x1,
837 		.shift = 11,
838 	},
839 	.hw.init = &(struct clk_init_data){
840 		.name = "dsu_clk_final",
841 		.ops = &clk_regmap_mux_ro_ops,
842 		.parent_hws = (const struct clk_hw *[]) {
843 			&sm1_dsu_clk_dyn.hw,
844 			&g12a_sys_pll.hw,
845 		},
846 		.num_parents = 2,
847 	},
848 };
849 
850 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
851 static struct clk_regmap sm1_cpu1_clk = {
852 	.data = &(struct clk_regmap_mux_data){
853 		.offset = HHI_SYS_CPU_CLK_CNTL6,
854 		.mask = 0x1,
855 		.shift = 24,
856 	},
857 	.hw.init = &(struct clk_init_data){
858 		.name = "cpu1_clk",
859 		.ops = &clk_regmap_mux_ro_ops,
860 		.parent_hws = (const struct clk_hw *[]) {
861 			&g12a_cpu_clk.hw,
862 			/* This CPU also have a dedicated clock tree */
863 		},
864 		.num_parents = 1,
865 	},
866 };
867 
868 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
869 static struct clk_regmap sm1_cpu2_clk = {
870 	.data = &(struct clk_regmap_mux_data){
871 		.offset = HHI_SYS_CPU_CLK_CNTL6,
872 		.mask = 0x1,
873 		.shift = 25,
874 	},
875 	.hw.init = &(struct clk_init_data){
876 		.name = "cpu2_clk",
877 		.ops = &clk_regmap_mux_ro_ops,
878 		.parent_hws = (const struct clk_hw *[]) {
879 			&g12a_cpu_clk.hw,
880 			/* This CPU also have a dedicated clock tree */
881 		},
882 		.num_parents = 1,
883 	},
884 };
885 
886 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
887 static struct clk_regmap sm1_cpu3_clk = {
888 	.data = &(struct clk_regmap_mux_data){
889 		.offset = HHI_SYS_CPU_CLK_CNTL6,
890 		.mask = 0x1,
891 		.shift = 26,
892 	},
893 	.hw.init = &(struct clk_init_data){
894 		.name = "cpu3_clk",
895 		.ops = &clk_regmap_mux_ro_ops,
896 		.parent_hws = (const struct clk_hw *[]) {
897 			&g12a_cpu_clk.hw,
898 			/* This CPU also have a dedicated clock tree */
899 		},
900 		.num_parents = 1,
901 	},
902 };
903 
904 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
905 static struct clk_regmap sm1_dsu_clk = {
906 	.data = &(struct clk_regmap_mux_data){
907 		.offset = HHI_SYS_CPU_CLK_CNTL6,
908 		.mask = 0x1,
909 		.shift = 27,
910 	},
911 	.hw.init = &(struct clk_init_data){
912 		.name = "dsu_clk",
913 		.ops = &clk_regmap_mux_ro_ops,
914 		.parent_hws = (const struct clk_hw *[]) {
915 			&g12a_cpu_clk.hw,
916 			&sm1_dsu_final_clk.hw,
917 		},
918 		.num_parents = 2,
919 	},
920 };
921 
g12a_cpu_clk_mux_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)922 static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
923 					unsigned long event, void *data)
924 {
925 	if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
926 		/* Wait for clock propagation before/after changing the mux */
927 		udelay(100);
928 		return NOTIFY_OK;
929 	}
930 
931 	return NOTIFY_DONE;
932 }
933 
934 static struct notifier_block g12a_cpu_clk_mux_nb = {
935 	.notifier_call = g12a_cpu_clk_mux_notifier_cb,
936 };
937 
938 struct g12a_cpu_clk_postmux_nb_data {
939 	struct notifier_block nb;
940 	struct clk_hw *xtal;
941 	struct clk_hw *cpu_clk_dyn;
942 	struct clk_hw *cpu_clk_postmux0;
943 	struct clk_hw *cpu_clk_postmux1;
944 	struct clk_hw *cpu_clk_premux1;
945 };
946 
g12a_cpu_clk_postmux_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)947 static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
948 					    unsigned long event, void *data)
949 {
950 	struct g12a_cpu_clk_postmux_nb_data *nb_data =
951 		container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
952 
953 	switch (event) {
954 	case PRE_RATE_CHANGE:
955 		/*
956 		 * This notifier means cpu_clk_postmux0 clock will be changed
957 		 * to feed cpu_clk, this is the current path :
958 		 * cpu_clk
959 		 *    \- cpu_clk_dyn
960 		 *          \- cpu_clk_postmux0
961 		 *                \- cpu_clk_muxX_div
962 		 *                      \- cpu_clk_premux0
963 		 *				\- fclk_div3 or fclk_div2
964 		 *		OR
965 		 *                \- cpu_clk_premux0
966 		 *			\- fclk_div3 or fclk_div2
967 		 */
968 
969 		/* Setup cpu_clk_premux1 to xtal */
970 		clk_hw_set_parent(nb_data->cpu_clk_premux1,
971 				  nb_data->xtal);
972 
973 		/* Setup cpu_clk_postmux1 to bypass divider */
974 		clk_hw_set_parent(nb_data->cpu_clk_postmux1,
975 				  nb_data->cpu_clk_premux1);
976 
977 		/* Switch to parking clk on cpu_clk_postmux1 */
978 		clk_hw_set_parent(nb_data->cpu_clk_dyn,
979 				  nb_data->cpu_clk_postmux1);
980 
981 		/*
982 		 * Now, cpu_clk is 24MHz in the current path :
983 		 * cpu_clk
984 		 *    \- cpu_clk_dyn
985 		 *          \- cpu_clk_postmux1
986 		 *                \- cpu_clk_premux1
987 		 *                      \- xtal
988 		 */
989 
990 		udelay(100);
991 
992 		return NOTIFY_OK;
993 
994 	case POST_RATE_CHANGE:
995 		/*
996 		 * The cpu_clk_postmux0 has ben updated, now switch back
997 		 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
998 		 * in account.
999 		 */
1000 
1001 		/* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
1002 		clk_hw_set_parent(nb_data->cpu_clk_dyn,
1003 				  nb_data->cpu_clk_postmux0);
1004 
1005 		/*
1006 		 * new path :
1007 		 * cpu_clk
1008 		 *    \- cpu_clk_dyn
1009 		 *          \- cpu_clk_postmux0
1010 		 *                \- cpu_clk_muxX_div
1011 		 *                      \- cpu_clk_premux0
1012 		 *				\- fclk_div3 or fclk_div2
1013 		 *		OR
1014 		 *                \- cpu_clk_premux0
1015 		 *			\- fclk_div3 or fclk_div2
1016 		 */
1017 
1018 		udelay(100);
1019 
1020 		return NOTIFY_OK;
1021 
1022 	default:
1023 		return NOTIFY_DONE;
1024 	}
1025 }
1026 
1027 static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1028 	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1029 	.cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1030 	.cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1031 	.cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1032 	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1033 };
1034 
1035 static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1036 	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1037 	.cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1038 	.cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1039 	.cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1040 	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1041 };
1042 
1043 struct g12a_sys_pll_nb_data {
1044 	struct notifier_block nb;
1045 	struct clk_hw *sys_pll;
1046 	struct clk_hw *cpu_clk;
1047 	struct clk_hw *cpu_clk_dyn;
1048 };
1049 
g12a_sys_pll_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)1050 static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1051 				    unsigned long event, void *data)
1052 {
1053 	struct g12a_sys_pll_nb_data *nb_data =
1054 		container_of(nb, struct g12a_sys_pll_nb_data, nb);
1055 
1056 	switch (event) {
1057 	case PRE_RATE_CHANGE:
1058 		/*
1059 		 * This notifier means sys_pll clock will be changed
1060 		 * to feed cpu_clk, this the current path :
1061 		 * cpu_clk
1062 		 *    \- sys_pll
1063 		 *          \- sys_pll_dco
1064 		 */
1065 
1066 		/* Configure cpu_clk to use cpu_clk_dyn */
1067 		clk_hw_set_parent(nb_data->cpu_clk,
1068 				  nb_data->cpu_clk_dyn);
1069 
1070 		/*
1071 		 * Now, cpu_clk uses the dyn path
1072 		 * cpu_clk
1073 		 *    \- cpu_clk_dyn
1074 		 *          \- cpu_clk_dynX
1075 		 *                \- cpu_clk_dynX_sel
1076 		 *		     \- cpu_clk_dynX_div
1077 		 *                      \- xtal/fclk_div2/fclk_div3
1078 		 *                   \- xtal/fclk_div2/fclk_div3
1079 		 */
1080 
1081 		udelay(100);
1082 
1083 		return NOTIFY_OK;
1084 
1085 	case POST_RATE_CHANGE:
1086 		/*
1087 		 * The sys_pll has ben updated, now switch back cpu_clk to
1088 		 * sys_pll
1089 		 */
1090 
1091 		/* Configure cpu_clk to use sys_pll */
1092 		clk_hw_set_parent(nb_data->cpu_clk,
1093 				  nb_data->sys_pll);
1094 
1095 		udelay(100);
1096 
1097 		/* new path :
1098 		 * cpu_clk
1099 		 *    \- sys_pll
1100 		 *          \- sys_pll_dco
1101 		 */
1102 
1103 		return NOTIFY_OK;
1104 
1105 	default:
1106 		return NOTIFY_DONE;
1107 	}
1108 }
1109 
1110 static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1111 	.sys_pll = &g12a_sys_pll.hw,
1112 	.cpu_clk = &g12a_cpu_clk.hw,
1113 	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1114 	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1115 };
1116 
1117 /* G12B first CPU cluster uses sys1_pll */
1118 static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1119 	.sys_pll = &g12b_sys1_pll.hw,
1120 	.cpu_clk = &g12b_cpu_clk.hw,
1121 	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1122 	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1123 };
1124 
1125 /* G12B second CPU cluster uses sys_pll */
1126 static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1127 	.sys_pll = &g12a_sys_pll.hw,
1128 	.cpu_clk = &g12b_cpub_clk.hw,
1129 	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1130 	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1131 };
1132 
1133 static struct clk_regmap g12a_cpu_clk_div16_en = {
1134 	.data = &(struct clk_regmap_gate_data){
1135 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1136 		.bit_idx = 1,
1137 	},
1138 	.hw.init = &(struct clk_init_data) {
1139 		.name = "cpu_clk_div16_en",
1140 		.ops = &clk_regmap_gate_ro_ops,
1141 		.parent_hws = (const struct clk_hw *[]) {
1142 			&g12a_cpu_clk.hw
1143 		},
1144 		.num_parents = 1,
1145 		/*
1146 		 * This clock is used to debug the cpu_clk range
1147 		 * Linux should not change it at runtime
1148 		 */
1149 	},
1150 };
1151 
1152 static struct clk_regmap g12b_cpub_clk_div16_en = {
1153 	.data = &(struct clk_regmap_gate_data){
1154 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1155 		.bit_idx = 1,
1156 	},
1157 	.hw.init = &(struct clk_init_data) {
1158 		.name = "cpub_clk_div16_en",
1159 		.ops = &clk_regmap_gate_ro_ops,
1160 		.parent_hws = (const struct clk_hw *[]) {
1161 			&g12b_cpub_clk.hw
1162 		},
1163 		.num_parents = 1,
1164 		/*
1165 		 * This clock is used to debug the cpu_clk range
1166 		 * Linux should not change it at runtime
1167 		 */
1168 	},
1169 };
1170 
1171 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
1172 	.mult = 1,
1173 	.div = 16,
1174 	.hw.init = &(struct clk_init_data){
1175 		.name = "cpu_clk_div16",
1176 		.ops = &clk_fixed_factor_ops,
1177 		.parent_hws = (const struct clk_hw *[]) {
1178 			&g12a_cpu_clk_div16_en.hw
1179 		},
1180 		.num_parents = 1,
1181 	},
1182 };
1183 
1184 static struct clk_fixed_factor g12b_cpub_clk_div16 = {
1185 	.mult = 1,
1186 	.div = 16,
1187 	.hw.init = &(struct clk_init_data){
1188 		.name = "cpub_clk_div16",
1189 		.ops = &clk_fixed_factor_ops,
1190 		.parent_hws = (const struct clk_hw *[]) {
1191 			&g12b_cpub_clk_div16_en.hw
1192 		},
1193 		.num_parents = 1,
1194 	},
1195 };
1196 
1197 static struct clk_regmap g12a_cpu_clk_apb_div = {
1198 	.data = &(struct clk_regmap_div_data){
1199 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1200 		.shift = 3,
1201 		.width = 3,
1202 		.flags = CLK_DIVIDER_POWER_OF_TWO,
1203 	},
1204 	.hw.init = &(struct clk_init_data){
1205 		.name = "cpu_clk_apb_div",
1206 		.ops = &clk_regmap_divider_ro_ops,
1207 		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1208 		.num_parents = 1,
1209 	},
1210 };
1211 
1212 static struct clk_regmap g12a_cpu_clk_apb = {
1213 	.data = &(struct clk_regmap_gate_data){
1214 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1215 		.bit_idx = 1,
1216 	},
1217 	.hw.init = &(struct clk_init_data) {
1218 		.name = "cpu_clk_apb",
1219 		.ops = &clk_regmap_gate_ro_ops,
1220 		.parent_hws = (const struct clk_hw *[]) {
1221 			&g12a_cpu_clk_apb_div.hw
1222 		},
1223 		.num_parents = 1,
1224 		/*
1225 		 * This clock is set by the ROM monitor code,
1226 		 * Linux should not change it at runtime
1227 		 */
1228 	},
1229 };
1230 
1231 static struct clk_regmap g12a_cpu_clk_atb_div = {
1232 	.data = &(struct clk_regmap_div_data){
1233 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1234 		.shift = 6,
1235 		.width = 3,
1236 		.flags = CLK_DIVIDER_POWER_OF_TWO,
1237 	},
1238 	.hw.init = &(struct clk_init_data){
1239 		.name = "cpu_clk_atb_div",
1240 		.ops = &clk_regmap_divider_ro_ops,
1241 		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1242 		.num_parents = 1,
1243 	},
1244 };
1245 
1246 static struct clk_regmap g12a_cpu_clk_atb = {
1247 	.data = &(struct clk_regmap_gate_data){
1248 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1249 		.bit_idx = 17,
1250 	},
1251 	.hw.init = &(struct clk_init_data) {
1252 		.name = "cpu_clk_atb",
1253 		.ops = &clk_regmap_gate_ro_ops,
1254 		.parent_hws = (const struct clk_hw *[]) {
1255 			&g12a_cpu_clk_atb_div.hw
1256 		},
1257 		.num_parents = 1,
1258 		/*
1259 		 * This clock is set by the ROM monitor code,
1260 		 * Linux should not change it at runtime
1261 		 */
1262 	},
1263 };
1264 
1265 static struct clk_regmap g12a_cpu_clk_axi_div = {
1266 	.data = &(struct clk_regmap_div_data){
1267 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1268 		.shift = 9,
1269 		.width = 3,
1270 		.flags = CLK_DIVIDER_POWER_OF_TWO,
1271 	},
1272 	.hw.init = &(struct clk_init_data){
1273 		.name = "cpu_clk_axi_div",
1274 		.ops = &clk_regmap_divider_ro_ops,
1275 		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1276 		.num_parents = 1,
1277 	},
1278 };
1279 
1280 static struct clk_regmap g12a_cpu_clk_axi = {
1281 	.data = &(struct clk_regmap_gate_data){
1282 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1283 		.bit_idx = 18,
1284 	},
1285 	.hw.init = &(struct clk_init_data) {
1286 		.name = "cpu_clk_axi",
1287 		.ops = &clk_regmap_gate_ro_ops,
1288 		.parent_hws = (const struct clk_hw *[]) {
1289 			&g12a_cpu_clk_axi_div.hw
1290 		},
1291 		.num_parents = 1,
1292 		/*
1293 		 * This clock is set by the ROM monitor code,
1294 		 * Linux should not change it at runtime
1295 		 */
1296 	},
1297 };
1298 
1299 static struct clk_regmap g12a_cpu_clk_trace_div = {
1300 	.data = &(struct clk_regmap_div_data){
1301 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1302 		.shift = 20,
1303 		.width = 3,
1304 		.flags = CLK_DIVIDER_POWER_OF_TWO,
1305 	},
1306 	.hw.init = &(struct clk_init_data){
1307 		.name = "cpu_clk_trace_div",
1308 		.ops = &clk_regmap_divider_ro_ops,
1309 		.parent_data = &(const struct clk_parent_data) {
1310 			/*
1311 			 * Note:
1312 			 * G12A and G12B have different cpu_clks (with
1313 			 * different struct clk_hw). We fallback to the global
1314 			 * naming string mechanism so cpu_clk_trace_div picks
1315 			 * up the appropriate one.
1316 			 */
1317 			.name = "cpu_clk",
1318 			.index = -1,
1319 		},
1320 		.num_parents = 1,
1321 	},
1322 };
1323 
1324 static struct clk_regmap g12a_cpu_clk_trace = {
1325 	.data = &(struct clk_regmap_gate_data){
1326 		.offset = HHI_SYS_CPU_CLK_CNTL1,
1327 		.bit_idx = 23,
1328 	},
1329 	.hw.init = &(struct clk_init_data) {
1330 		.name = "cpu_clk_trace",
1331 		.ops = &clk_regmap_gate_ro_ops,
1332 		.parent_hws = (const struct clk_hw *[]) {
1333 			&g12a_cpu_clk_trace_div.hw
1334 		},
1335 		.num_parents = 1,
1336 		/*
1337 		 * This clock is set by the ROM monitor code,
1338 		 * Linux should not change it at runtime
1339 		 */
1340 	},
1341 };
1342 
1343 static struct clk_fixed_factor g12b_cpub_clk_div2 = {
1344 	.mult = 1,
1345 	.div = 2,
1346 	.hw.init = &(struct clk_init_data){
1347 		.name = "cpub_clk_div2",
1348 		.ops = &clk_fixed_factor_ops,
1349 		.parent_hws = (const struct clk_hw *[]) {
1350 			&g12b_cpub_clk.hw
1351 		},
1352 		.num_parents = 1,
1353 	},
1354 };
1355 
1356 static struct clk_fixed_factor g12b_cpub_clk_div3 = {
1357 	.mult = 1,
1358 	.div = 3,
1359 	.hw.init = &(struct clk_init_data){
1360 		.name = "cpub_clk_div3",
1361 		.ops = &clk_fixed_factor_ops,
1362 		.parent_hws = (const struct clk_hw *[]) {
1363 			&g12b_cpub_clk.hw
1364 		},
1365 		.num_parents = 1,
1366 	},
1367 };
1368 
1369 static struct clk_fixed_factor g12b_cpub_clk_div4 = {
1370 	.mult = 1,
1371 	.div = 4,
1372 	.hw.init = &(struct clk_init_data){
1373 		.name = "cpub_clk_div4",
1374 		.ops = &clk_fixed_factor_ops,
1375 		.parent_hws = (const struct clk_hw *[]) {
1376 			&g12b_cpub_clk.hw
1377 		},
1378 		.num_parents = 1,
1379 	},
1380 };
1381 
1382 static struct clk_fixed_factor g12b_cpub_clk_div5 = {
1383 	.mult = 1,
1384 	.div = 5,
1385 	.hw.init = &(struct clk_init_data){
1386 		.name = "cpub_clk_div5",
1387 		.ops = &clk_fixed_factor_ops,
1388 		.parent_hws = (const struct clk_hw *[]) {
1389 			&g12b_cpub_clk.hw
1390 		},
1391 		.num_parents = 1,
1392 	},
1393 };
1394 
1395 static struct clk_fixed_factor g12b_cpub_clk_div6 = {
1396 	.mult = 1,
1397 	.div = 6,
1398 	.hw.init = &(struct clk_init_data){
1399 		.name = "cpub_clk_div6",
1400 		.ops = &clk_fixed_factor_ops,
1401 		.parent_hws = (const struct clk_hw *[]) {
1402 			&g12b_cpub_clk.hw
1403 		},
1404 		.num_parents = 1,
1405 	},
1406 };
1407 
1408 static struct clk_fixed_factor g12b_cpub_clk_div7 = {
1409 	.mult = 1,
1410 	.div = 7,
1411 	.hw.init = &(struct clk_init_data){
1412 		.name = "cpub_clk_div7",
1413 		.ops = &clk_fixed_factor_ops,
1414 		.parent_hws = (const struct clk_hw *[]) {
1415 			&g12b_cpub_clk.hw
1416 		},
1417 		.num_parents = 1,
1418 	},
1419 };
1420 
1421 static struct clk_fixed_factor g12b_cpub_clk_div8 = {
1422 	.mult = 1,
1423 	.div = 8,
1424 	.hw.init = &(struct clk_init_data){
1425 		.name = "cpub_clk_div8",
1426 		.ops = &clk_fixed_factor_ops,
1427 		.parent_hws = (const struct clk_hw *[]) {
1428 			&g12b_cpub_clk.hw
1429 		},
1430 		.num_parents = 1,
1431 	},
1432 };
1433 
1434 static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1435 static struct clk_regmap g12b_cpub_clk_apb_sel = {
1436 	.data = &(struct clk_regmap_mux_data){
1437 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1438 		.mask = 7,
1439 		.shift = 3,
1440 		.table = mux_table_cpub,
1441 	},
1442 	.hw.init = &(struct clk_init_data){
1443 		.name = "cpub_clk_apb_sel",
1444 		.ops = &clk_regmap_mux_ro_ops,
1445 		.parent_hws = (const struct clk_hw *[]) {
1446 			&g12b_cpub_clk_div2.hw,
1447 			&g12b_cpub_clk_div3.hw,
1448 			&g12b_cpub_clk_div4.hw,
1449 			&g12b_cpub_clk_div5.hw,
1450 			&g12b_cpub_clk_div6.hw,
1451 			&g12b_cpub_clk_div7.hw,
1452 			&g12b_cpub_clk_div8.hw
1453 		},
1454 		.num_parents = 7,
1455 	},
1456 };
1457 
1458 static struct clk_regmap g12b_cpub_clk_apb = {
1459 	.data = &(struct clk_regmap_gate_data){
1460 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1461 		.bit_idx = 16,
1462 		.flags = CLK_GATE_SET_TO_DISABLE,
1463 	},
1464 	.hw.init = &(struct clk_init_data) {
1465 		.name = "cpub_clk_apb",
1466 		.ops = &clk_regmap_gate_ro_ops,
1467 		.parent_hws = (const struct clk_hw *[]) {
1468 			&g12b_cpub_clk_apb_sel.hw
1469 		},
1470 		.num_parents = 1,
1471 		/*
1472 		 * This clock is set by the ROM monitor code,
1473 		 * Linux should not change it at runtime
1474 		 */
1475 	},
1476 };
1477 
1478 static struct clk_regmap g12b_cpub_clk_atb_sel = {
1479 	.data = &(struct clk_regmap_mux_data){
1480 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1481 		.mask = 7,
1482 		.shift = 6,
1483 		.table = mux_table_cpub,
1484 	},
1485 	.hw.init = &(struct clk_init_data){
1486 		.name = "cpub_clk_atb_sel",
1487 		.ops = &clk_regmap_mux_ro_ops,
1488 		.parent_hws = (const struct clk_hw *[]) {
1489 			&g12b_cpub_clk_div2.hw,
1490 			&g12b_cpub_clk_div3.hw,
1491 			&g12b_cpub_clk_div4.hw,
1492 			&g12b_cpub_clk_div5.hw,
1493 			&g12b_cpub_clk_div6.hw,
1494 			&g12b_cpub_clk_div7.hw,
1495 			&g12b_cpub_clk_div8.hw
1496 		},
1497 		.num_parents = 7,
1498 	},
1499 };
1500 
1501 static struct clk_regmap g12b_cpub_clk_atb = {
1502 	.data = &(struct clk_regmap_gate_data){
1503 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1504 		.bit_idx = 17,
1505 		.flags = CLK_GATE_SET_TO_DISABLE,
1506 	},
1507 	.hw.init = &(struct clk_init_data) {
1508 		.name = "cpub_clk_atb",
1509 		.ops = &clk_regmap_gate_ro_ops,
1510 		.parent_hws = (const struct clk_hw *[]) {
1511 			&g12b_cpub_clk_atb_sel.hw
1512 		},
1513 		.num_parents = 1,
1514 		/*
1515 		 * This clock is set by the ROM monitor code,
1516 		 * Linux should not change it at runtime
1517 		 */
1518 	},
1519 };
1520 
1521 static struct clk_regmap g12b_cpub_clk_axi_sel = {
1522 	.data = &(struct clk_regmap_mux_data){
1523 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1524 		.mask = 7,
1525 		.shift = 9,
1526 		.table = mux_table_cpub,
1527 	},
1528 	.hw.init = &(struct clk_init_data){
1529 		.name = "cpub_clk_axi_sel",
1530 		.ops = &clk_regmap_mux_ro_ops,
1531 		.parent_hws = (const struct clk_hw *[]) {
1532 			&g12b_cpub_clk_div2.hw,
1533 			&g12b_cpub_clk_div3.hw,
1534 			&g12b_cpub_clk_div4.hw,
1535 			&g12b_cpub_clk_div5.hw,
1536 			&g12b_cpub_clk_div6.hw,
1537 			&g12b_cpub_clk_div7.hw,
1538 			&g12b_cpub_clk_div8.hw
1539 		},
1540 		.num_parents = 7,
1541 	},
1542 };
1543 
1544 static struct clk_regmap g12b_cpub_clk_axi = {
1545 	.data = &(struct clk_regmap_gate_data){
1546 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1547 		.bit_idx = 18,
1548 		.flags = CLK_GATE_SET_TO_DISABLE,
1549 	},
1550 	.hw.init = &(struct clk_init_data) {
1551 		.name = "cpub_clk_axi",
1552 		.ops = &clk_regmap_gate_ro_ops,
1553 		.parent_hws = (const struct clk_hw *[]) {
1554 			&g12b_cpub_clk_axi_sel.hw
1555 		},
1556 		.num_parents = 1,
1557 		/*
1558 		 * This clock is set by the ROM monitor code,
1559 		 * Linux should not change it at runtime
1560 		 */
1561 	},
1562 };
1563 
1564 static struct clk_regmap g12b_cpub_clk_trace_sel = {
1565 	.data = &(struct clk_regmap_mux_data){
1566 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1567 		.mask = 7,
1568 		.shift = 20,
1569 		.table = mux_table_cpub,
1570 	},
1571 	.hw.init = &(struct clk_init_data){
1572 		.name = "cpub_clk_trace_sel",
1573 		.ops = &clk_regmap_mux_ro_ops,
1574 		.parent_hws = (const struct clk_hw *[]) {
1575 			&g12b_cpub_clk_div2.hw,
1576 			&g12b_cpub_clk_div3.hw,
1577 			&g12b_cpub_clk_div4.hw,
1578 			&g12b_cpub_clk_div5.hw,
1579 			&g12b_cpub_clk_div6.hw,
1580 			&g12b_cpub_clk_div7.hw,
1581 			&g12b_cpub_clk_div8.hw
1582 		},
1583 		.num_parents = 7,
1584 	},
1585 };
1586 
1587 static struct clk_regmap g12b_cpub_clk_trace = {
1588 	.data = &(struct clk_regmap_gate_data){
1589 		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1590 		.bit_idx = 23,
1591 		.flags = CLK_GATE_SET_TO_DISABLE,
1592 	},
1593 	.hw.init = &(struct clk_init_data) {
1594 		.name = "cpub_clk_trace",
1595 		.ops = &clk_regmap_gate_ro_ops,
1596 		.parent_hws = (const struct clk_hw *[]) {
1597 			&g12b_cpub_clk_trace_sel.hw
1598 		},
1599 		.num_parents = 1,
1600 		/*
1601 		 * This clock is set by the ROM monitor code,
1602 		 * Linux should not change it at runtime
1603 		 */
1604 	},
1605 };
1606 
1607 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
1608 	.min = 125,
1609 	.max = 255,
1610 };
1611 
1612 /*
1613  * Internal gp0 pll emulation configuration parameters
1614  */
1615 static const struct reg_sequence g12a_gp0_init_regs[] = {
1616 	{ .reg = HHI_GP0_PLL_CNTL1,	.def = 0x00000000 },
1617 	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0x00000000 },
1618 	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x48681c00 },
1619 	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0x33771290 },
1620 	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x39272000 },
1621 	{ .reg = HHI_GP0_PLL_CNTL6,	.def = 0x56540000 },
1622 };
1623 
1624 static struct clk_regmap g12a_gp0_pll_dco = {
1625 	.data = &(struct meson_clk_pll_data){
1626 		.en = {
1627 			.reg_off = HHI_GP0_PLL_CNTL0,
1628 			.shift   = 28,
1629 			.width   = 1,
1630 		},
1631 		.m = {
1632 			.reg_off = HHI_GP0_PLL_CNTL0,
1633 			.shift   = 0,
1634 			.width   = 8,
1635 		},
1636 		.n = {
1637 			.reg_off = HHI_GP0_PLL_CNTL0,
1638 			.shift   = 10,
1639 			.width   = 5,
1640 		},
1641 		.frac = {
1642 			.reg_off = HHI_GP0_PLL_CNTL1,
1643 			.shift   = 0,
1644 			.width   = 17,
1645 		},
1646 		.l = {
1647 			.reg_off = HHI_GP0_PLL_CNTL0,
1648 			.shift   = 31,
1649 			.width   = 1,
1650 		},
1651 		.rst = {
1652 			.reg_off = HHI_GP0_PLL_CNTL0,
1653 			.shift   = 29,
1654 			.width   = 1,
1655 		},
1656 		.range = &g12a_gp0_pll_mult_range,
1657 		.init_regs = g12a_gp0_init_regs,
1658 		.init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1659 	},
1660 	.hw.init = &(struct clk_init_data){
1661 		.name = "gp0_pll_dco",
1662 		.ops = &meson_clk_pll_ops,
1663 		.parent_data = &(const struct clk_parent_data) {
1664 			.fw_name = "xtal",
1665 		},
1666 		.num_parents = 1,
1667 	},
1668 };
1669 
1670 static struct clk_regmap g12a_gp0_pll = {
1671 	.data = &(struct clk_regmap_div_data){
1672 		.offset = HHI_GP0_PLL_CNTL0,
1673 		.shift = 16,
1674 		.width = 3,
1675 		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1676 			  CLK_DIVIDER_ROUND_CLOSEST),
1677 	},
1678 	.hw.init = &(struct clk_init_data){
1679 		.name = "gp0_pll",
1680 		.ops = &clk_regmap_divider_ops,
1681 		.parent_hws = (const struct clk_hw *[]) {
1682 			&g12a_gp0_pll_dco.hw
1683 		},
1684 		.num_parents = 1,
1685 		.flags = CLK_SET_RATE_PARENT,
1686 	},
1687 };
1688 
1689 static struct clk_regmap sm1_gp1_pll_dco = {
1690 	.data = &(struct meson_clk_pll_data){
1691 		.en = {
1692 			.reg_off = HHI_GP1_PLL_CNTL0,
1693 			.shift   = 28,
1694 			.width   = 1,
1695 		},
1696 		.m = {
1697 			.reg_off = HHI_GP1_PLL_CNTL0,
1698 			.shift   = 0,
1699 			.width   = 8,
1700 		},
1701 		.n = {
1702 			.reg_off = HHI_GP1_PLL_CNTL0,
1703 			.shift   = 10,
1704 			.width   = 5,
1705 		},
1706 		.frac = {
1707 			.reg_off = HHI_GP1_PLL_CNTL1,
1708 			.shift   = 0,
1709 			.width   = 17,
1710 		},
1711 		.l = {
1712 			.reg_off = HHI_GP1_PLL_CNTL0,
1713 			.shift   = 31,
1714 			.width   = 1,
1715 		},
1716 		.rst = {
1717 			.reg_off = HHI_GP1_PLL_CNTL0,
1718 			.shift   = 29,
1719 			.width   = 1,
1720 		},
1721 	},
1722 	.hw.init = &(struct clk_init_data){
1723 		.name = "gp1_pll_dco",
1724 		.ops = &meson_clk_pll_ro_ops,
1725 		.parent_data = &(const struct clk_parent_data) {
1726 			.fw_name = "xtal",
1727 		},
1728 		.num_parents = 1,
1729 		/* This clock feeds the DSU, avoid disabling it */
1730 		.flags = CLK_IS_CRITICAL,
1731 	},
1732 };
1733 
1734 static struct clk_regmap sm1_gp1_pll = {
1735 	.data = &(struct clk_regmap_div_data){
1736 		.offset = HHI_GP1_PLL_CNTL0,
1737 		.shift = 16,
1738 		.width = 3,
1739 		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1740 			  CLK_DIVIDER_ROUND_CLOSEST),
1741 	},
1742 	.hw.init = &(struct clk_init_data){
1743 		.name = "gp1_pll",
1744 		.ops = &clk_regmap_divider_ro_ops,
1745 		.parent_hws = (const struct clk_hw *[]) {
1746 			&sm1_gp1_pll_dco.hw
1747 		},
1748 		.num_parents = 1,
1749 	},
1750 };
1751 
1752 /*
1753  * Internal hifi pll emulation configuration parameters
1754  */
1755 static const struct reg_sequence g12a_hifi_init_regs[] = {
1756 	{ .reg = HHI_HIFI_PLL_CNTL1,	.def = 0x00000000 },
1757 	{ .reg = HHI_HIFI_PLL_CNTL2,	.def = 0x00000000 },
1758 	{ .reg = HHI_HIFI_PLL_CNTL3,	.def = 0x6a285c00 },
1759 	{ .reg = HHI_HIFI_PLL_CNTL4,	.def = 0x65771290 },
1760 	{ .reg = HHI_HIFI_PLL_CNTL5,	.def = 0x39272000 },
1761 	{ .reg = HHI_HIFI_PLL_CNTL6,	.def = 0x56540000 },
1762 };
1763 
1764 static struct clk_regmap g12a_hifi_pll_dco = {
1765 	.data = &(struct meson_clk_pll_data){
1766 		.en = {
1767 			.reg_off = HHI_HIFI_PLL_CNTL0,
1768 			.shift   = 28,
1769 			.width   = 1,
1770 		},
1771 		.m = {
1772 			.reg_off = HHI_HIFI_PLL_CNTL0,
1773 			.shift   = 0,
1774 			.width   = 8,
1775 		},
1776 		.n = {
1777 			.reg_off = HHI_HIFI_PLL_CNTL0,
1778 			.shift   = 10,
1779 			.width   = 5,
1780 		},
1781 		.frac = {
1782 			.reg_off = HHI_HIFI_PLL_CNTL1,
1783 			.shift   = 0,
1784 			.width   = 17,
1785 		},
1786 		.l = {
1787 			.reg_off = HHI_HIFI_PLL_CNTL0,
1788 			.shift   = 31,
1789 			.width   = 1,
1790 		},
1791 		.rst = {
1792 			.reg_off = HHI_HIFI_PLL_CNTL0,
1793 			.shift   = 29,
1794 			.width   = 1,
1795 		},
1796 		.range = &g12a_gp0_pll_mult_range,
1797 		.init_regs = g12a_hifi_init_regs,
1798 		.init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1799 		.flags = CLK_MESON_PLL_ROUND_CLOSEST,
1800 	},
1801 	.hw.init = &(struct clk_init_data){
1802 		.name = "hifi_pll_dco",
1803 		.ops = &meson_clk_pll_ops,
1804 		.parent_data = &(const struct clk_parent_data) {
1805 			.fw_name = "xtal",
1806 		},
1807 		.num_parents = 1,
1808 	},
1809 };
1810 
1811 static struct clk_regmap g12a_hifi_pll = {
1812 	.data = &(struct clk_regmap_div_data){
1813 		.offset = HHI_HIFI_PLL_CNTL0,
1814 		.shift = 16,
1815 		.width = 2,
1816 		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1817 			  CLK_DIVIDER_ROUND_CLOSEST),
1818 	},
1819 	.hw.init = &(struct clk_init_data){
1820 		.name = "hifi_pll",
1821 		.ops = &clk_regmap_divider_ops,
1822 		.parent_hws = (const struct clk_hw *[]) {
1823 			&g12a_hifi_pll_dco.hw
1824 		},
1825 		.num_parents = 1,
1826 		.flags = CLK_SET_RATE_PARENT,
1827 	},
1828 };
1829 
1830 /*
1831  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1832  * 100MHz reference clock for the PCIe Analog PHY, and thus requires
1833  * a strict register sequence to enable the PLL.
1834  */
1835 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1836 	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x20090496 },
1837 	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x30090496 },
1838 	{ .reg = HHI_PCIE_PLL_CNTL1,	.def = 0x00000000 },
1839 	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0x00001100 },
1840 	{ .reg = HHI_PCIE_PLL_CNTL3,	.def = 0x10058e00 },
1841 	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0x000100c0 },
1842 	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x68000048 },
1843 	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x68000068, .delay_us = 20 },
1844 	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0x008100c0, .delay_us = 10 },
1845 	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x34090496 },
1846 	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x14090496, .delay_us = 10 },
1847 	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0x00001000 },
1848 };
1849 
1850 /* Keep a single entry table for recalc/round_rate() ops */
1851 static const struct pll_params_table g12a_pcie_pll_table[] = {
1852 	PLL_PARAMS(150, 1),
1853 	{0, 0},
1854 };
1855 
1856 static struct clk_regmap g12a_pcie_pll_dco = {
1857 	.data = &(struct meson_clk_pll_data){
1858 		.en = {
1859 			.reg_off = HHI_PCIE_PLL_CNTL0,
1860 			.shift   = 28,
1861 			.width   = 1,
1862 		},
1863 		.m = {
1864 			.reg_off = HHI_PCIE_PLL_CNTL0,
1865 			.shift   = 0,
1866 			.width   = 8,
1867 		},
1868 		.n = {
1869 			.reg_off = HHI_PCIE_PLL_CNTL0,
1870 			.shift   = 10,
1871 			.width   = 5,
1872 		},
1873 		.frac = {
1874 			.reg_off = HHI_PCIE_PLL_CNTL1,
1875 			.shift   = 0,
1876 			.width   = 12,
1877 		},
1878 		.l = {
1879 			.reg_off = HHI_PCIE_PLL_CNTL0,
1880 			.shift   = 31,
1881 			.width   = 1,
1882 		},
1883 		.rst = {
1884 			.reg_off = HHI_PCIE_PLL_CNTL0,
1885 			.shift   = 29,
1886 			.width   = 1,
1887 		},
1888 		.table = g12a_pcie_pll_table,
1889 		.init_regs = g12a_pcie_pll_init_regs,
1890 		.init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1891 	},
1892 	.hw.init = &(struct clk_init_data){
1893 		.name = "pcie_pll_dco",
1894 		.ops = &meson_clk_pcie_pll_ops,
1895 		.parent_data = &(const struct clk_parent_data) {
1896 			.fw_name = "xtal",
1897 		},
1898 		.num_parents = 1,
1899 	},
1900 };
1901 
1902 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1903 	.mult = 1,
1904 	.div = 2,
1905 	.hw.init = &(struct clk_init_data){
1906 		.name = "pcie_pll_dco_div2",
1907 		.ops = &clk_fixed_factor_ops,
1908 		.parent_hws = (const struct clk_hw *[]) {
1909 			&g12a_pcie_pll_dco.hw
1910 		},
1911 		.num_parents = 1,
1912 		.flags = CLK_SET_RATE_PARENT,
1913 	},
1914 };
1915 
1916 static struct clk_regmap g12a_pcie_pll_od = {
1917 	.data = &(struct clk_regmap_div_data){
1918 		.offset = HHI_PCIE_PLL_CNTL0,
1919 		.shift = 16,
1920 		.width = 5,
1921 		.flags = CLK_DIVIDER_ROUND_CLOSEST |
1922 			 CLK_DIVIDER_ONE_BASED |
1923 			 CLK_DIVIDER_ALLOW_ZERO,
1924 	},
1925 	.hw.init = &(struct clk_init_data){
1926 		.name = "pcie_pll_od",
1927 		.ops = &clk_regmap_divider_ops,
1928 		.parent_hws = (const struct clk_hw *[]) {
1929 			&g12a_pcie_pll_dco_div2.hw
1930 		},
1931 		.num_parents = 1,
1932 		.flags = CLK_SET_RATE_PARENT,
1933 	},
1934 };
1935 
1936 static struct clk_fixed_factor g12a_pcie_pll = {
1937 	.mult = 1,
1938 	.div = 2,
1939 	.hw.init = &(struct clk_init_data){
1940 		.name = "pcie_pll_pll",
1941 		.ops = &clk_fixed_factor_ops,
1942 		.parent_hws = (const struct clk_hw *[]) {
1943 			&g12a_pcie_pll_od.hw
1944 		},
1945 		.num_parents = 1,
1946 		.flags = CLK_SET_RATE_PARENT,
1947 	},
1948 };
1949 
1950 static struct clk_regmap g12a_hdmi_pll_dco = {
1951 	.data = &(struct meson_clk_pll_data){
1952 		.en = {
1953 			.reg_off = HHI_HDMI_PLL_CNTL0,
1954 			.shift   = 28,
1955 			.width   = 1,
1956 		},
1957 		.m = {
1958 			.reg_off = HHI_HDMI_PLL_CNTL0,
1959 			.shift   = 0,
1960 			.width   = 8,
1961 		},
1962 		.n = {
1963 			.reg_off = HHI_HDMI_PLL_CNTL0,
1964 			.shift   = 10,
1965 			.width   = 5,
1966 		},
1967 		.frac = {
1968 			.reg_off = HHI_HDMI_PLL_CNTL1,
1969 			.shift   = 0,
1970 			.width   = 16,
1971 		},
1972 		.l = {
1973 			.reg_off = HHI_HDMI_PLL_CNTL0,
1974 			.shift   = 30,
1975 			.width   = 1,
1976 		},
1977 		.rst = {
1978 			.reg_off = HHI_HDMI_PLL_CNTL0,
1979 			.shift   = 29,
1980 			.width   = 1,
1981 		},
1982 	},
1983 	.hw.init = &(struct clk_init_data){
1984 		.name = "hdmi_pll_dco",
1985 		.ops = &meson_clk_pll_ro_ops,
1986 		.parent_data = &(const struct clk_parent_data) {
1987 			.fw_name = "xtal",
1988 		},
1989 		.num_parents = 1,
1990 		/*
1991 		 * Display directly handle hdmi pll registers ATM, we need
1992 		 * NOCACHE to keep our view of the clock as accurate as possible
1993 		 */
1994 		.flags = CLK_GET_RATE_NOCACHE,
1995 	},
1996 };
1997 
1998 static struct clk_regmap g12a_hdmi_pll_od = {
1999 	.data = &(struct clk_regmap_div_data){
2000 		.offset = HHI_HDMI_PLL_CNTL0,
2001 		.shift = 16,
2002 		.width = 2,
2003 		.flags = CLK_DIVIDER_POWER_OF_TWO,
2004 	},
2005 	.hw.init = &(struct clk_init_data){
2006 		.name = "hdmi_pll_od",
2007 		.ops = &clk_regmap_divider_ro_ops,
2008 		.parent_hws = (const struct clk_hw *[]) {
2009 			&g12a_hdmi_pll_dco.hw
2010 		},
2011 		.num_parents = 1,
2012 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2013 	},
2014 };
2015 
2016 static struct clk_regmap g12a_hdmi_pll_od2 = {
2017 	.data = &(struct clk_regmap_div_data){
2018 		.offset = HHI_HDMI_PLL_CNTL0,
2019 		.shift = 18,
2020 		.width = 2,
2021 		.flags = CLK_DIVIDER_POWER_OF_TWO,
2022 	},
2023 	.hw.init = &(struct clk_init_data){
2024 		.name = "hdmi_pll_od2",
2025 		.ops = &clk_regmap_divider_ro_ops,
2026 		.parent_hws = (const struct clk_hw *[]) {
2027 			&g12a_hdmi_pll_od.hw
2028 		},
2029 		.num_parents = 1,
2030 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2031 	},
2032 };
2033 
2034 static struct clk_regmap g12a_hdmi_pll = {
2035 	.data = &(struct clk_regmap_div_data){
2036 		.offset = HHI_HDMI_PLL_CNTL0,
2037 		.shift = 20,
2038 		.width = 2,
2039 		.flags = CLK_DIVIDER_POWER_OF_TWO,
2040 	},
2041 	.hw.init = &(struct clk_init_data){
2042 		.name = "hdmi_pll",
2043 		.ops = &clk_regmap_divider_ro_ops,
2044 		.parent_hws = (const struct clk_hw *[]) {
2045 			&g12a_hdmi_pll_od2.hw
2046 		},
2047 		.num_parents = 1,
2048 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2049 	},
2050 };
2051 
2052 static struct clk_fixed_factor g12a_fclk_div4_div = {
2053 	.mult = 1,
2054 	.div = 4,
2055 	.hw.init = &(struct clk_init_data){
2056 		.name = "fclk_div4_div",
2057 		.ops = &clk_fixed_factor_ops,
2058 		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2059 		.num_parents = 1,
2060 	},
2061 };
2062 
2063 static struct clk_regmap g12a_fclk_div4 = {
2064 	.data = &(struct clk_regmap_gate_data){
2065 		.offset = HHI_FIX_PLL_CNTL1,
2066 		.bit_idx = 21,
2067 	},
2068 	.hw.init = &(struct clk_init_data){
2069 		.name = "fclk_div4",
2070 		.ops = &clk_regmap_gate_ops,
2071 		.parent_hws = (const struct clk_hw *[]) {
2072 			&g12a_fclk_div4_div.hw
2073 		},
2074 		.num_parents = 1,
2075 	},
2076 };
2077 
2078 static struct clk_fixed_factor g12a_fclk_div5_div = {
2079 	.mult = 1,
2080 	.div = 5,
2081 	.hw.init = &(struct clk_init_data){
2082 		.name = "fclk_div5_div",
2083 		.ops = &clk_fixed_factor_ops,
2084 		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2085 		.num_parents = 1,
2086 	},
2087 };
2088 
2089 static struct clk_regmap g12a_fclk_div5 = {
2090 	.data = &(struct clk_regmap_gate_data){
2091 		.offset = HHI_FIX_PLL_CNTL1,
2092 		.bit_idx = 22,
2093 	},
2094 	.hw.init = &(struct clk_init_data){
2095 		.name = "fclk_div5",
2096 		.ops = &clk_regmap_gate_ops,
2097 		.parent_hws = (const struct clk_hw *[]) {
2098 			&g12a_fclk_div5_div.hw
2099 		},
2100 		.num_parents = 1,
2101 	},
2102 };
2103 
2104 static struct clk_fixed_factor g12a_fclk_div7_div = {
2105 	.mult = 1,
2106 	.div = 7,
2107 	.hw.init = &(struct clk_init_data){
2108 		.name = "fclk_div7_div",
2109 		.ops = &clk_fixed_factor_ops,
2110 		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2111 		.num_parents = 1,
2112 	},
2113 };
2114 
2115 static struct clk_regmap g12a_fclk_div7 = {
2116 	.data = &(struct clk_regmap_gate_data){
2117 		.offset = HHI_FIX_PLL_CNTL1,
2118 		.bit_idx = 23,
2119 	},
2120 	.hw.init = &(struct clk_init_data){
2121 		.name = "fclk_div7",
2122 		.ops = &clk_regmap_gate_ops,
2123 		.parent_hws = (const struct clk_hw *[]) {
2124 			&g12a_fclk_div7_div.hw
2125 		},
2126 		.num_parents = 1,
2127 	},
2128 };
2129 
2130 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
2131 	.mult = 1,
2132 	.div = 5,
2133 	.hw.init = &(struct clk_init_data){
2134 		.name = "fclk_div2p5_div",
2135 		.ops = &clk_fixed_factor_ops,
2136 		.parent_hws = (const struct clk_hw *[]) {
2137 			&g12a_fixed_pll_dco.hw
2138 		},
2139 		.num_parents = 1,
2140 	},
2141 };
2142 
2143 static struct clk_regmap g12a_fclk_div2p5 = {
2144 	.data = &(struct clk_regmap_gate_data){
2145 		.offset = HHI_FIX_PLL_CNTL1,
2146 		.bit_idx = 25,
2147 	},
2148 	.hw.init = &(struct clk_init_data){
2149 		.name = "fclk_div2p5",
2150 		.ops = &clk_regmap_gate_ops,
2151 		.parent_hws = (const struct clk_hw *[]) {
2152 			&g12a_fclk_div2p5_div.hw
2153 		},
2154 		.num_parents = 1,
2155 	},
2156 };
2157 
2158 static struct clk_fixed_factor g12a_mpll_50m_div = {
2159 	.mult = 1,
2160 	.div = 80,
2161 	.hw.init = &(struct clk_init_data){
2162 		.name = "mpll_50m_div",
2163 		.ops = &clk_fixed_factor_ops,
2164 		.parent_hws = (const struct clk_hw *[]) {
2165 			&g12a_fixed_pll_dco.hw
2166 		},
2167 		.num_parents = 1,
2168 	},
2169 };
2170 
2171 static struct clk_regmap g12a_mpll_50m = {
2172 	.data = &(struct clk_regmap_mux_data){
2173 		.offset = HHI_FIX_PLL_CNTL3,
2174 		.mask = 0x1,
2175 		.shift = 5,
2176 	},
2177 	.hw.init = &(struct clk_init_data){
2178 		.name = "mpll_50m",
2179 		.ops = &clk_regmap_mux_ro_ops,
2180 		.parent_data = (const struct clk_parent_data []) {
2181 			{ .fw_name = "xtal", },
2182 			{ .hw = &g12a_mpll_50m_div.hw },
2183 		},
2184 		.num_parents = 2,
2185 	},
2186 };
2187 
2188 static struct clk_fixed_factor g12a_mpll_prediv = {
2189 	.mult = 1,
2190 	.div = 2,
2191 	.hw.init = &(struct clk_init_data){
2192 		.name = "mpll_prediv",
2193 		.ops = &clk_fixed_factor_ops,
2194 		.parent_hws = (const struct clk_hw *[]) {
2195 			&g12a_fixed_pll_dco.hw
2196 		},
2197 		.num_parents = 1,
2198 	},
2199 };
2200 
2201 static const struct reg_sequence g12a_mpll0_init_regs[] = {
2202 	{ .reg = HHI_MPLL_CNTL2,	.def = 0x40000033 },
2203 };
2204 
2205 static struct clk_regmap g12a_mpll0_div = {
2206 	.data = &(struct meson_clk_mpll_data){
2207 		.sdm = {
2208 			.reg_off = HHI_MPLL_CNTL1,
2209 			.shift   = 0,
2210 			.width   = 14,
2211 		},
2212 		.sdm_en = {
2213 			.reg_off = HHI_MPLL_CNTL1,
2214 			.shift   = 30,
2215 			.width	 = 1,
2216 		},
2217 		.n2 = {
2218 			.reg_off = HHI_MPLL_CNTL1,
2219 			.shift   = 20,
2220 			.width   = 9,
2221 		},
2222 		.ssen = {
2223 			.reg_off = HHI_MPLL_CNTL1,
2224 			.shift   = 29,
2225 			.width	 = 1,
2226 		},
2227 		.lock = &meson_clk_lock,
2228 		.init_regs = g12a_mpll0_init_regs,
2229 		.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
2230 	},
2231 	.hw.init = &(struct clk_init_data){
2232 		.name = "mpll0_div",
2233 		.ops = &meson_clk_mpll_ops,
2234 		.parent_hws = (const struct clk_hw *[]) {
2235 			&g12a_mpll_prediv.hw
2236 		},
2237 		.num_parents = 1,
2238 	},
2239 };
2240 
2241 static struct clk_regmap g12a_mpll0 = {
2242 	.data = &(struct clk_regmap_gate_data){
2243 		.offset = HHI_MPLL_CNTL1,
2244 		.bit_idx = 31,
2245 	},
2246 	.hw.init = &(struct clk_init_data){
2247 		.name = "mpll0",
2248 		.ops = &clk_regmap_gate_ops,
2249 		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2250 		.num_parents = 1,
2251 		.flags = CLK_SET_RATE_PARENT,
2252 	},
2253 };
2254 
2255 static const struct reg_sequence g12a_mpll1_init_regs[] = {
2256 	{ .reg = HHI_MPLL_CNTL4,	.def = 0x40000033 },
2257 };
2258 
2259 static struct clk_regmap g12a_mpll1_div = {
2260 	.data = &(struct meson_clk_mpll_data){
2261 		.sdm = {
2262 			.reg_off = HHI_MPLL_CNTL3,
2263 			.shift   = 0,
2264 			.width   = 14,
2265 		},
2266 		.sdm_en = {
2267 			.reg_off = HHI_MPLL_CNTL3,
2268 			.shift   = 30,
2269 			.width	 = 1,
2270 		},
2271 		.n2 = {
2272 			.reg_off = HHI_MPLL_CNTL3,
2273 			.shift   = 20,
2274 			.width   = 9,
2275 		},
2276 		.ssen = {
2277 			.reg_off = HHI_MPLL_CNTL3,
2278 			.shift   = 29,
2279 			.width	 = 1,
2280 		},
2281 		.lock = &meson_clk_lock,
2282 		.init_regs = g12a_mpll1_init_regs,
2283 		.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
2284 	},
2285 	.hw.init = &(struct clk_init_data){
2286 		.name = "mpll1_div",
2287 		.ops = &meson_clk_mpll_ops,
2288 		.parent_hws = (const struct clk_hw *[]) {
2289 			&g12a_mpll_prediv.hw
2290 		},
2291 		.num_parents = 1,
2292 	},
2293 };
2294 
2295 static struct clk_regmap g12a_mpll1 = {
2296 	.data = &(struct clk_regmap_gate_data){
2297 		.offset = HHI_MPLL_CNTL3,
2298 		.bit_idx = 31,
2299 	},
2300 	.hw.init = &(struct clk_init_data){
2301 		.name = "mpll1",
2302 		.ops = &clk_regmap_gate_ops,
2303 		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2304 		.num_parents = 1,
2305 		.flags = CLK_SET_RATE_PARENT,
2306 	},
2307 };
2308 
2309 static const struct reg_sequence g12a_mpll2_init_regs[] = {
2310 	{ .reg = HHI_MPLL_CNTL6,	.def = 0x40000033 },
2311 };
2312 
2313 static struct clk_regmap g12a_mpll2_div = {
2314 	.data = &(struct meson_clk_mpll_data){
2315 		.sdm = {
2316 			.reg_off = HHI_MPLL_CNTL5,
2317 			.shift   = 0,
2318 			.width   = 14,
2319 		},
2320 		.sdm_en = {
2321 			.reg_off = HHI_MPLL_CNTL5,
2322 			.shift   = 30,
2323 			.width	 = 1,
2324 		},
2325 		.n2 = {
2326 			.reg_off = HHI_MPLL_CNTL5,
2327 			.shift   = 20,
2328 			.width   = 9,
2329 		},
2330 		.ssen = {
2331 			.reg_off = HHI_MPLL_CNTL5,
2332 			.shift   = 29,
2333 			.width	 = 1,
2334 		},
2335 		.lock = &meson_clk_lock,
2336 		.init_regs = g12a_mpll2_init_regs,
2337 		.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2338 	},
2339 	.hw.init = &(struct clk_init_data){
2340 		.name = "mpll2_div",
2341 		.ops = &meson_clk_mpll_ops,
2342 		.parent_hws = (const struct clk_hw *[]) {
2343 			&g12a_mpll_prediv.hw
2344 		},
2345 		.num_parents = 1,
2346 	},
2347 };
2348 
2349 static struct clk_regmap g12a_mpll2 = {
2350 	.data = &(struct clk_regmap_gate_data){
2351 		.offset = HHI_MPLL_CNTL5,
2352 		.bit_idx = 31,
2353 	},
2354 	.hw.init = &(struct clk_init_data){
2355 		.name = "mpll2",
2356 		.ops = &clk_regmap_gate_ops,
2357 		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2358 		.num_parents = 1,
2359 		.flags = CLK_SET_RATE_PARENT,
2360 	},
2361 };
2362 
2363 static const struct reg_sequence g12a_mpll3_init_regs[] = {
2364 	{ .reg = HHI_MPLL_CNTL8,	.def = 0x40000033 },
2365 };
2366 
2367 static struct clk_regmap g12a_mpll3_div = {
2368 	.data = &(struct meson_clk_mpll_data){
2369 		.sdm = {
2370 			.reg_off = HHI_MPLL_CNTL7,
2371 			.shift   = 0,
2372 			.width   = 14,
2373 		},
2374 		.sdm_en = {
2375 			.reg_off = HHI_MPLL_CNTL7,
2376 			.shift   = 30,
2377 			.width	 = 1,
2378 		},
2379 		.n2 = {
2380 			.reg_off = HHI_MPLL_CNTL7,
2381 			.shift   = 20,
2382 			.width   = 9,
2383 		},
2384 		.ssen = {
2385 			.reg_off = HHI_MPLL_CNTL7,
2386 			.shift   = 29,
2387 			.width	 = 1,
2388 		},
2389 		.lock = &meson_clk_lock,
2390 		.init_regs = g12a_mpll3_init_regs,
2391 		.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2392 	},
2393 	.hw.init = &(struct clk_init_data){
2394 		.name = "mpll3_div",
2395 		.ops = &meson_clk_mpll_ops,
2396 		.parent_hws = (const struct clk_hw *[]) {
2397 			&g12a_mpll_prediv.hw
2398 		},
2399 		.num_parents = 1,
2400 	},
2401 };
2402 
2403 static struct clk_regmap g12a_mpll3 = {
2404 	.data = &(struct clk_regmap_gate_data){
2405 		.offset = HHI_MPLL_CNTL7,
2406 		.bit_idx = 31,
2407 	},
2408 	.hw.init = &(struct clk_init_data){
2409 		.name = "mpll3",
2410 		.ops = &clk_regmap_gate_ops,
2411 		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2412 		.num_parents = 1,
2413 		.flags = CLK_SET_RATE_PARENT,
2414 	},
2415 };
2416 
2417 static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };
2418 static const struct clk_parent_data clk81_parent_data[] = {
2419 	{ .fw_name = "xtal", },
2420 	{ .hw = &g12a_fclk_div7.hw },
2421 	{ .hw = &g12a_mpll1.hw },
2422 	{ .hw = &g12a_mpll2.hw },
2423 	{ .hw = &g12a_fclk_div4.hw },
2424 	{ .hw = &g12a_fclk_div3.hw },
2425 	{ .hw = &g12a_fclk_div5.hw },
2426 };
2427 
2428 static struct clk_regmap g12a_mpeg_clk_sel = {
2429 	.data = &(struct clk_regmap_mux_data){
2430 		.offset = HHI_MPEG_CLK_CNTL,
2431 		.mask = 0x7,
2432 		.shift = 12,
2433 		.table = mux_table_clk81,
2434 	},
2435 	.hw.init = &(struct clk_init_data){
2436 		.name = "mpeg_clk_sel",
2437 		.ops = &clk_regmap_mux_ro_ops,
2438 		.parent_data = clk81_parent_data,
2439 		.num_parents = ARRAY_SIZE(clk81_parent_data),
2440 	},
2441 };
2442 
2443 static struct clk_regmap g12a_mpeg_clk_div = {
2444 	.data = &(struct clk_regmap_div_data){
2445 		.offset = HHI_MPEG_CLK_CNTL,
2446 		.shift = 0,
2447 		.width = 7,
2448 	},
2449 	.hw.init = &(struct clk_init_data){
2450 		.name = "mpeg_clk_div",
2451 		.ops = &clk_regmap_divider_ops,
2452 		.parent_hws = (const struct clk_hw *[]) {
2453 			&g12a_mpeg_clk_sel.hw
2454 		},
2455 		.num_parents = 1,
2456 		.flags = CLK_SET_RATE_PARENT,
2457 	},
2458 };
2459 
2460 static struct clk_regmap g12a_clk81 = {
2461 	.data = &(struct clk_regmap_gate_data){
2462 		.offset = HHI_MPEG_CLK_CNTL,
2463 		.bit_idx = 7,
2464 	},
2465 	.hw.init = &(struct clk_init_data){
2466 		.name = "clk81",
2467 		.ops = &clk_regmap_gate_ops,
2468 		.parent_hws = (const struct clk_hw *[]) {
2469 			&g12a_mpeg_clk_div.hw
2470 		},
2471 		.num_parents = 1,
2472 		.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2473 	},
2474 };
2475 
2476 static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2477 	{ .fw_name = "xtal", },
2478 	{ .hw = &g12a_fclk_div2.hw },
2479 	{ .hw = &g12a_fclk_div3.hw },
2480 	{ .hw = &g12a_fclk_div5.hw },
2481 	{ .hw = &g12a_fclk_div7.hw },
2482 	/*
2483 	 * Following these parent clocks, we should also have had mpll2, mpll3
2484 	 * and gp0_pll but these clocks are too precious to be used here. All
2485 	 * the necessary rates for MMC and NAND operation can be acheived using
2486 	 * g12a_ee_core or fclk_div clocks
2487 	 */
2488 };
2489 
2490 /* SDIO clock */
2491 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2492 	.data = &(struct clk_regmap_mux_data){
2493 		.offset = HHI_SD_EMMC_CLK_CNTL,
2494 		.mask = 0x7,
2495 		.shift = 9,
2496 	},
2497 	.hw.init = &(struct clk_init_data) {
2498 		.name = "sd_emmc_a_clk0_sel",
2499 		.ops = &clk_regmap_mux_ops,
2500 		.parent_data = g12a_sd_emmc_clk0_parent_data,
2501 		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2502 		.flags = CLK_SET_RATE_PARENT,
2503 	},
2504 };
2505 
2506 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2507 	.data = &(struct clk_regmap_div_data){
2508 		.offset = HHI_SD_EMMC_CLK_CNTL,
2509 		.shift = 0,
2510 		.width = 7,
2511 	},
2512 	.hw.init = &(struct clk_init_data) {
2513 		.name = "sd_emmc_a_clk0_div",
2514 		.ops = &clk_regmap_divider_ops,
2515 		.parent_hws = (const struct clk_hw *[]) {
2516 			&g12a_sd_emmc_a_clk0_sel.hw
2517 		},
2518 		.num_parents = 1,
2519 		.flags = CLK_SET_RATE_PARENT,
2520 	},
2521 };
2522 
2523 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2524 	.data = &(struct clk_regmap_gate_data){
2525 		.offset = HHI_SD_EMMC_CLK_CNTL,
2526 		.bit_idx = 7,
2527 	},
2528 	.hw.init = &(struct clk_init_data){
2529 		.name = "sd_emmc_a_clk0",
2530 		.ops = &clk_regmap_gate_ops,
2531 		.parent_hws = (const struct clk_hw *[]) {
2532 			&g12a_sd_emmc_a_clk0_div.hw
2533 		},
2534 		.num_parents = 1,
2535 		.flags = CLK_SET_RATE_PARENT,
2536 	},
2537 };
2538 
2539 /* SDcard clock */
2540 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2541 	.data = &(struct clk_regmap_mux_data){
2542 		.offset = HHI_SD_EMMC_CLK_CNTL,
2543 		.mask = 0x7,
2544 		.shift = 25,
2545 	},
2546 	.hw.init = &(struct clk_init_data) {
2547 		.name = "sd_emmc_b_clk0_sel",
2548 		.ops = &clk_regmap_mux_ops,
2549 		.parent_data = g12a_sd_emmc_clk0_parent_data,
2550 		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2551 		.flags = CLK_SET_RATE_PARENT,
2552 	},
2553 };
2554 
2555 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2556 	.data = &(struct clk_regmap_div_data){
2557 		.offset = HHI_SD_EMMC_CLK_CNTL,
2558 		.shift = 16,
2559 		.width = 7,
2560 	},
2561 	.hw.init = &(struct clk_init_data) {
2562 		.name = "sd_emmc_b_clk0_div",
2563 		.ops = &clk_regmap_divider_ops,
2564 		.parent_hws = (const struct clk_hw *[]) {
2565 			&g12a_sd_emmc_b_clk0_sel.hw
2566 		},
2567 		.num_parents = 1,
2568 		.flags = CLK_SET_RATE_PARENT,
2569 	},
2570 };
2571 
2572 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2573 	.data = &(struct clk_regmap_gate_data){
2574 		.offset = HHI_SD_EMMC_CLK_CNTL,
2575 		.bit_idx = 23,
2576 	},
2577 	.hw.init = &(struct clk_init_data){
2578 		.name = "sd_emmc_b_clk0",
2579 		.ops = &clk_regmap_gate_ops,
2580 		.parent_hws = (const struct clk_hw *[]) {
2581 			&g12a_sd_emmc_b_clk0_div.hw
2582 		},
2583 		.num_parents = 1,
2584 		.flags = CLK_SET_RATE_PARENT,
2585 	},
2586 };
2587 
2588 /* EMMC/NAND clock */
2589 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2590 	.data = &(struct clk_regmap_mux_data){
2591 		.offset = HHI_NAND_CLK_CNTL,
2592 		.mask = 0x7,
2593 		.shift = 9,
2594 	},
2595 	.hw.init = &(struct clk_init_data) {
2596 		.name = "sd_emmc_c_clk0_sel",
2597 		.ops = &clk_regmap_mux_ops,
2598 		.parent_data = g12a_sd_emmc_clk0_parent_data,
2599 		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2600 		.flags = CLK_SET_RATE_PARENT,
2601 	},
2602 };
2603 
2604 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2605 	.data = &(struct clk_regmap_div_data){
2606 		.offset = HHI_NAND_CLK_CNTL,
2607 		.shift = 0,
2608 		.width = 7,
2609 	},
2610 	.hw.init = &(struct clk_init_data) {
2611 		.name = "sd_emmc_c_clk0_div",
2612 		.ops = &clk_regmap_divider_ops,
2613 		.parent_hws = (const struct clk_hw *[]) {
2614 			&g12a_sd_emmc_c_clk0_sel.hw
2615 		},
2616 		.num_parents = 1,
2617 		.flags = CLK_SET_RATE_PARENT,
2618 	},
2619 };
2620 
2621 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2622 	.data = &(struct clk_regmap_gate_data){
2623 		.offset = HHI_NAND_CLK_CNTL,
2624 		.bit_idx = 7,
2625 	},
2626 	.hw.init = &(struct clk_init_data){
2627 		.name = "sd_emmc_c_clk0",
2628 		.ops = &clk_regmap_gate_ops,
2629 		.parent_hws = (const struct clk_hw *[]) {
2630 			&g12a_sd_emmc_c_clk0_div.hw
2631 		},
2632 		.num_parents = 1,
2633 		.flags = CLK_SET_RATE_PARENT,
2634 	},
2635 };
2636 
2637 /* Video Clocks */
2638 
2639 static struct clk_regmap g12a_vid_pll_div = {
2640 	.data = &(struct meson_vid_pll_div_data){
2641 		.val = {
2642 			.reg_off = HHI_VID_PLL_CLK_DIV,
2643 			.shift   = 0,
2644 			.width   = 15,
2645 		},
2646 		.sel = {
2647 			.reg_off = HHI_VID_PLL_CLK_DIV,
2648 			.shift   = 16,
2649 			.width   = 2,
2650 		},
2651 	},
2652 	.hw.init = &(struct clk_init_data) {
2653 		.name = "vid_pll_div",
2654 		.ops = &meson_vid_pll_div_ro_ops,
2655 		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2656 		.num_parents = 1,
2657 		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2658 	},
2659 };
2660 
2661 static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2662 	&g12a_vid_pll_div.hw,
2663 	&g12a_hdmi_pll.hw,
2664 };
2665 
2666 static struct clk_regmap g12a_vid_pll_sel = {
2667 	.data = &(struct clk_regmap_mux_data){
2668 		.offset = HHI_VID_PLL_CLK_DIV,
2669 		.mask = 0x1,
2670 		.shift = 18,
2671 	},
2672 	.hw.init = &(struct clk_init_data){
2673 		.name = "vid_pll_sel",
2674 		.ops = &clk_regmap_mux_ops,
2675 		/*
2676 		 * bit 18 selects from 2 possible parents:
2677 		 * vid_pll_div or hdmi_pll
2678 		 */
2679 		.parent_hws = g12a_vid_pll_parent_hws,
2680 		.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2681 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2682 	},
2683 };
2684 
2685 static struct clk_regmap g12a_vid_pll = {
2686 	.data = &(struct clk_regmap_gate_data){
2687 		.offset = HHI_VID_PLL_CLK_DIV,
2688 		.bit_idx = 19,
2689 	},
2690 	.hw.init = &(struct clk_init_data) {
2691 		.name = "vid_pll",
2692 		.ops = &clk_regmap_gate_ops,
2693 		.parent_hws = (const struct clk_hw *[]) {
2694 			&g12a_vid_pll_sel.hw
2695 		},
2696 		.num_parents = 1,
2697 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2698 	},
2699 };
2700 
2701 /* VPU Clock */
2702 
2703 static const struct clk_hw *g12a_vpu_parent_hws[] = {
2704 	&g12a_fclk_div3.hw,
2705 	&g12a_fclk_div4.hw,
2706 	&g12a_fclk_div5.hw,
2707 	&g12a_fclk_div7.hw,
2708 	&g12a_mpll1.hw,
2709 	&g12a_vid_pll.hw,
2710 	&g12a_hifi_pll.hw,
2711 	&g12a_gp0_pll.hw,
2712 };
2713 
2714 static struct clk_regmap g12a_vpu_0_sel = {
2715 	.data = &(struct clk_regmap_mux_data){
2716 		.offset = HHI_VPU_CLK_CNTL,
2717 		.mask = 0x7,
2718 		.shift = 9,
2719 	},
2720 	.hw.init = &(struct clk_init_data){
2721 		.name = "vpu_0_sel",
2722 		.ops = &clk_regmap_mux_ops,
2723 		.parent_hws = g12a_vpu_parent_hws,
2724 		.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2725 		.flags = CLK_SET_RATE_NO_REPARENT,
2726 	},
2727 };
2728 
2729 static struct clk_regmap g12a_vpu_0_div = {
2730 	.data = &(struct clk_regmap_div_data){
2731 		.offset = HHI_VPU_CLK_CNTL,
2732 		.shift = 0,
2733 		.width = 7,
2734 	},
2735 	.hw.init = &(struct clk_init_data){
2736 		.name = "vpu_0_div",
2737 		.ops = &clk_regmap_divider_ops,
2738 		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2739 		.num_parents = 1,
2740 		.flags = CLK_SET_RATE_PARENT,
2741 	},
2742 };
2743 
2744 static struct clk_regmap g12a_vpu_0 = {
2745 	.data = &(struct clk_regmap_gate_data){
2746 		.offset = HHI_VPU_CLK_CNTL,
2747 		.bit_idx = 8,
2748 	},
2749 	.hw.init = &(struct clk_init_data) {
2750 		.name = "vpu_0",
2751 		.ops = &clk_regmap_gate_ops,
2752 		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2753 		.num_parents = 1,
2754 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2755 	},
2756 };
2757 
2758 static struct clk_regmap g12a_vpu_1_sel = {
2759 	.data = &(struct clk_regmap_mux_data){
2760 		.offset = HHI_VPU_CLK_CNTL,
2761 		.mask = 0x7,
2762 		.shift = 25,
2763 	},
2764 	.hw.init = &(struct clk_init_data){
2765 		.name = "vpu_1_sel",
2766 		.ops = &clk_regmap_mux_ops,
2767 		.parent_hws = g12a_vpu_parent_hws,
2768 		.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2769 		.flags = CLK_SET_RATE_NO_REPARENT,
2770 	},
2771 };
2772 
2773 static struct clk_regmap g12a_vpu_1_div = {
2774 	.data = &(struct clk_regmap_div_data){
2775 		.offset = HHI_VPU_CLK_CNTL,
2776 		.shift = 16,
2777 		.width = 7,
2778 	},
2779 	.hw.init = &(struct clk_init_data){
2780 		.name = "vpu_1_div",
2781 		.ops = &clk_regmap_divider_ops,
2782 		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2783 		.num_parents = 1,
2784 		.flags = CLK_SET_RATE_PARENT,
2785 	},
2786 };
2787 
2788 static struct clk_regmap g12a_vpu_1 = {
2789 	.data = &(struct clk_regmap_gate_data){
2790 		.offset = HHI_VPU_CLK_CNTL,
2791 		.bit_idx = 24,
2792 	},
2793 	.hw.init = &(struct clk_init_data) {
2794 		.name = "vpu_1",
2795 		.ops = &clk_regmap_gate_ops,
2796 		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2797 		.num_parents = 1,
2798 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2799 	},
2800 };
2801 
2802 static struct clk_regmap g12a_vpu = {
2803 	.data = &(struct clk_regmap_mux_data){
2804 		.offset = HHI_VPU_CLK_CNTL,
2805 		.mask = 1,
2806 		.shift = 31,
2807 	},
2808 	.hw.init = &(struct clk_init_data){
2809 		.name = "vpu",
2810 		.ops = &clk_regmap_mux_ops,
2811 		/*
2812 		 * bit 31 selects from 2 possible parents:
2813 		 * vpu_0 or vpu_1
2814 		 */
2815 		.parent_hws = (const struct clk_hw *[]) {
2816 			&g12a_vpu_0.hw,
2817 			&g12a_vpu_1.hw,
2818 		},
2819 		.num_parents = 2,
2820 		.flags = CLK_SET_RATE_NO_REPARENT,
2821 	},
2822 };
2823 
2824 /* VDEC clocks */
2825 
2826 static const struct clk_hw *g12a_vdec_parent_hws[] = {
2827 	&g12a_fclk_div2p5.hw,
2828 	&g12a_fclk_div3.hw,
2829 	&g12a_fclk_div4.hw,
2830 	&g12a_fclk_div5.hw,
2831 	&g12a_fclk_div7.hw,
2832 	&g12a_hifi_pll.hw,
2833 	&g12a_gp0_pll.hw,
2834 };
2835 
2836 static struct clk_regmap g12a_vdec_1_sel = {
2837 	.data = &(struct clk_regmap_mux_data){
2838 		.offset = HHI_VDEC_CLK_CNTL,
2839 		.mask = 0x7,
2840 		.shift = 9,
2841 		.flags = CLK_MUX_ROUND_CLOSEST,
2842 	},
2843 	.hw.init = &(struct clk_init_data){
2844 		.name = "vdec_1_sel",
2845 		.ops = &clk_regmap_mux_ops,
2846 		.parent_hws = g12a_vdec_parent_hws,
2847 		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2848 		.flags = CLK_SET_RATE_PARENT,
2849 	},
2850 };
2851 
2852 static struct clk_regmap g12a_vdec_1_div = {
2853 	.data = &(struct clk_regmap_div_data){
2854 		.offset = HHI_VDEC_CLK_CNTL,
2855 		.shift = 0,
2856 		.width = 7,
2857 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2858 	},
2859 	.hw.init = &(struct clk_init_data){
2860 		.name = "vdec_1_div",
2861 		.ops = &clk_regmap_divider_ops,
2862 		.parent_hws = (const struct clk_hw *[]) {
2863 			&g12a_vdec_1_sel.hw
2864 		},
2865 		.num_parents = 1,
2866 		.flags = CLK_SET_RATE_PARENT,
2867 	},
2868 };
2869 
2870 static struct clk_regmap g12a_vdec_1 = {
2871 	.data = &(struct clk_regmap_gate_data){
2872 		.offset = HHI_VDEC_CLK_CNTL,
2873 		.bit_idx = 8,
2874 	},
2875 	.hw.init = &(struct clk_init_data) {
2876 		.name = "vdec_1",
2877 		.ops = &clk_regmap_gate_ops,
2878 		.parent_hws = (const struct clk_hw *[]) {
2879 			&g12a_vdec_1_div.hw
2880 		},
2881 		.num_parents = 1,
2882 		.flags = CLK_SET_RATE_PARENT,
2883 	},
2884 };
2885 
2886 static struct clk_regmap g12a_vdec_hevcf_sel = {
2887 	.data = &(struct clk_regmap_mux_data){
2888 		.offset = HHI_VDEC2_CLK_CNTL,
2889 		.mask = 0x7,
2890 		.shift = 9,
2891 		.flags = CLK_MUX_ROUND_CLOSEST,
2892 	},
2893 	.hw.init = &(struct clk_init_data){
2894 		.name = "vdec_hevcf_sel",
2895 		.ops = &clk_regmap_mux_ops,
2896 		.parent_hws = g12a_vdec_parent_hws,
2897 		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2898 		.flags = CLK_SET_RATE_PARENT,
2899 	},
2900 };
2901 
2902 static struct clk_regmap g12a_vdec_hevcf_div = {
2903 	.data = &(struct clk_regmap_div_data){
2904 		.offset = HHI_VDEC2_CLK_CNTL,
2905 		.shift = 0,
2906 		.width = 7,
2907 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2908 	},
2909 	.hw.init = &(struct clk_init_data){
2910 		.name = "vdec_hevcf_div",
2911 		.ops = &clk_regmap_divider_ops,
2912 		.parent_hws = (const struct clk_hw *[]) {
2913 			&g12a_vdec_hevcf_sel.hw
2914 		},
2915 		.num_parents = 1,
2916 		.flags = CLK_SET_RATE_PARENT,
2917 	},
2918 };
2919 
2920 static struct clk_regmap g12a_vdec_hevcf = {
2921 	.data = &(struct clk_regmap_gate_data){
2922 		.offset = HHI_VDEC2_CLK_CNTL,
2923 		.bit_idx = 8,
2924 	},
2925 	.hw.init = &(struct clk_init_data) {
2926 		.name = "vdec_hevcf",
2927 		.ops = &clk_regmap_gate_ops,
2928 		.parent_hws = (const struct clk_hw *[]) {
2929 			&g12a_vdec_hevcf_div.hw
2930 		},
2931 		.num_parents = 1,
2932 		.flags = CLK_SET_RATE_PARENT,
2933 	},
2934 };
2935 
2936 static struct clk_regmap g12a_vdec_hevc_sel = {
2937 	.data = &(struct clk_regmap_mux_data){
2938 		.offset = HHI_VDEC2_CLK_CNTL,
2939 		.mask = 0x7,
2940 		.shift = 25,
2941 		.flags = CLK_MUX_ROUND_CLOSEST,
2942 	},
2943 	.hw.init = &(struct clk_init_data){
2944 		.name = "vdec_hevc_sel",
2945 		.ops = &clk_regmap_mux_ops,
2946 		.parent_hws = g12a_vdec_parent_hws,
2947 		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2948 		.flags = CLK_SET_RATE_PARENT,
2949 	},
2950 };
2951 
2952 static struct clk_regmap g12a_vdec_hevc_div = {
2953 	.data = &(struct clk_regmap_div_data){
2954 		.offset = HHI_VDEC2_CLK_CNTL,
2955 		.shift = 16,
2956 		.width = 7,
2957 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2958 	},
2959 	.hw.init = &(struct clk_init_data){
2960 		.name = "vdec_hevc_div",
2961 		.ops = &clk_regmap_divider_ops,
2962 		.parent_hws = (const struct clk_hw *[]) {
2963 			&g12a_vdec_hevc_sel.hw
2964 		},
2965 		.num_parents = 1,
2966 		.flags = CLK_SET_RATE_PARENT,
2967 	},
2968 };
2969 
2970 static struct clk_regmap g12a_vdec_hevc = {
2971 	.data = &(struct clk_regmap_gate_data){
2972 		.offset = HHI_VDEC2_CLK_CNTL,
2973 		.bit_idx = 24,
2974 	},
2975 	.hw.init = &(struct clk_init_data) {
2976 		.name = "vdec_hevc",
2977 		.ops = &clk_regmap_gate_ops,
2978 		.parent_hws = (const struct clk_hw *[]) {
2979 			&g12a_vdec_hevc_div.hw
2980 		},
2981 		.num_parents = 1,
2982 		.flags = CLK_SET_RATE_PARENT,
2983 	},
2984 };
2985 
2986 /* VAPB Clock */
2987 
2988 static const struct clk_hw *g12a_vapb_parent_hws[] = {
2989 	&g12a_fclk_div4.hw,
2990 	&g12a_fclk_div3.hw,
2991 	&g12a_fclk_div5.hw,
2992 	&g12a_fclk_div7.hw,
2993 	&g12a_mpll1.hw,
2994 	&g12a_vid_pll.hw,
2995 	&g12a_mpll2.hw,
2996 	&g12a_fclk_div2p5.hw,
2997 };
2998 
2999 static struct clk_regmap g12a_vapb_0_sel = {
3000 	.data = &(struct clk_regmap_mux_data){
3001 		.offset = HHI_VAPBCLK_CNTL,
3002 		.mask = 0x3,
3003 		.shift = 9,
3004 	},
3005 	.hw.init = &(struct clk_init_data){
3006 		.name = "vapb_0_sel",
3007 		.ops = &clk_regmap_mux_ops,
3008 		.parent_hws = g12a_vapb_parent_hws,
3009 		.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3010 		.flags = CLK_SET_RATE_NO_REPARENT,
3011 	},
3012 };
3013 
3014 static struct clk_regmap g12a_vapb_0_div = {
3015 	.data = &(struct clk_regmap_div_data){
3016 		.offset = HHI_VAPBCLK_CNTL,
3017 		.shift = 0,
3018 		.width = 7,
3019 	},
3020 	.hw.init = &(struct clk_init_data){
3021 		.name = "vapb_0_div",
3022 		.ops = &clk_regmap_divider_ops,
3023 		.parent_hws = (const struct clk_hw *[]) {
3024 			&g12a_vapb_0_sel.hw
3025 		},
3026 		.num_parents = 1,
3027 		.flags = CLK_SET_RATE_PARENT,
3028 	},
3029 };
3030 
3031 static struct clk_regmap g12a_vapb_0 = {
3032 	.data = &(struct clk_regmap_gate_data){
3033 		.offset = HHI_VAPBCLK_CNTL,
3034 		.bit_idx = 8,
3035 	},
3036 	.hw.init = &(struct clk_init_data) {
3037 		.name = "vapb_0",
3038 		.ops = &clk_regmap_gate_ops,
3039 		.parent_hws = (const struct clk_hw *[]) {
3040 			&g12a_vapb_0_div.hw
3041 		},
3042 		.num_parents = 1,
3043 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3044 	},
3045 };
3046 
3047 static struct clk_regmap g12a_vapb_1_sel = {
3048 	.data = &(struct clk_regmap_mux_data){
3049 		.offset = HHI_VAPBCLK_CNTL,
3050 		.mask = 0x3,
3051 		.shift = 25,
3052 	},
3053 	.hw.init = &(struct clk_init_data){
3054 		.name = "vapb_1_sel",
3055 		.ops = &clk_regmap_mux_ops,
3056 		.parent_hws = g12a_vapb_parent_hws,
3057 		.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3058 		.flags = CLK_SET_RATE_NO_REPARENT,
3059 	},
3060 };
3061 
3062 static struct clk_regmap g12a_vapb_1_div = {
3063 	.data = &(struct clk_regmap_div_data){
3064 		.offset = HHI_VAPBCLK_CNTL,
3065 		.shift = 16,
3066 		.width = 7,
3067 	},
3068 	.hw.init = &(struct clk_init_data){
3069 		.name = "vapb_1_div",
3070 		.ops = &clk_regmap_divider_ops,
3071 		.parent_hws = (const struct clk_hw *[]) {
3072 			&g12a_vapb_1_sel.hw
3073 		},
3074 		.num_parents = 1,
3075 		.flags = CLK_SET_RATE_PARENT,
3076 	},
3077 };
3078 
3079 static struct clk_regmap g12a_vapb_1 = {
3080 	.data = &(struct clk_regmap_gate_data){
3081 		.offset = HHI_VAPBCLK_CNTL,
3082 		.bit_idx = 24,
3083 	},
3084 	.hw.init = &(struct clk_init_data) {
3085 		.name = "vapb_1",
3086 		.ops = &clk_regmap_gate_ops,
3087 		.parent_hws = (const struct clk_hw *[]) {
3088 			&g12a_vapb_1_div.hw
3089 		},
3090 		.num_parents = 1,
3091 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3092 	},
3093 };
3094 
3095 static struct clk_regmap g12a_vapb_sel = {
3096 	.data = &(struct clk_regmap_mux_data){
3097 		.offset = HHI_VAPBCLK_CNTL,
3098 		.mask = 1,
3099 		.shift = 31,
3100 	},
3101 	.hw.init = &(struct clk_init_data){
3102 		.name = "vapb_sel",
3103 		.ops = &clk_regmap_mux_ops,
3104 		/*
3105 		 * bit 31 selects from 2 possible parents:
3106 		 * vapb_0 or vapb_1
3107 		 */
3108 		.parent_hws = (const struct clk_hw *[]) {
3109 			&g12a_vapb_0.hw,
3110 			&g12a_vapb_1.hw,
3111 		},
3112 		.num_parents = 2,
3113 		.flags = CLK_SET_RATE_NO_REPARENT,
3114 	},
3115 };
3116 
3117 static struct clk_regmap g12a_vapb = {
3118 	.data = &(struct clk_regmap_gate_data){
3119 		.offset = HHI_VAPBCLK_CNTL,
3120 		.bit_idx = 30,
3121 	},
3122 	.hw.init = &(struct clk_init_data) {
3123 		.name = "vapb",
3124 		.ops = &clk_regmap_gate_ops,
3125 		.parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3126 		.num_parents = 1,
3127 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3128 	},
3129 };
3130 
3131 static const struct clk_hw *g12a_vclk_parent_hws[] = {
3132 	&g12a_vid_pll.hw,
3133 	&g12a_gp0_pll.hw,
3134 	&g12a_hifi_pll.hw,
3135 	&g12a_mpll1.hw,
3136 	&g12a_fclk_div3.hw,
3137 	&g12a_fclk_div4.hw,
3138 	&g12a_fclk_div5.hw,
3139 	&g12a_fclk_div7.hw,
3140 };
3141 
3142 static struct clk_regmap g12a_vclk_sel = {
3143 	.data = &(struct clk_regmap_mux_data){
3144 		.offset = HHI_VID_CLK_CNTL,
3145 		.mask = 0x7,
3146 		.shift = 16,
3147 	},
3148 	.hw.init = &(struct clk_init_data){
3149 		.name = "vclk_sel",
3150 		.ops = &clk_regmap_mux_ops,
3151 		.parent_hws = g12a_vclk_parent_hws,
3152 		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3153 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3154 	},
3155 };
3156 
3157 static struct clk_regmap g12a_vclk2_sel = {
3158 	.data = &(struct clk_regmap_mux_data){
3159 		.offset = HHI_VIID_CLK_CNTL,
3160 		.mask = 0x7,
3161 		.shift = 16,
3162 	},
3163 	.hw.init = &(struct clk_init_data){
3164 		.name = "vclk2_sel",
3165 		.ops = &clk_regmap_mux_ops,
3166 		.parent_hws = g12a_vclk_parent_hws,
3167 		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3168 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3169 	},
3170 };
3171 
3172 static struct clk_regmap g12a_vclk_input = {
3173 	.data = &(struct clk_regmap_gate_data){
3174 		.offset = HHI_VID_CLK_DIV,
3175 		.bit_idx = 16,
3176 	},
3177 	.hw.init = &(struct clk_init_data) {
3178 		.name = "vclk_input",
3179 		.ops = &clk_regmap_gate_ops,
3180 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3181 		.num_parents = 1,
3182 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3183 	},
3184 };
3185 
3186 static struct clk_regmap g12a_vclk2_input = {
3187 	.data = &(struct clk_regmap_gate_data){
3188 		.offset = HHI_VIID_CLK_DIV,
3189 		.bit_idx = 16,
3190 	},
3191 	.hw.init = &(struct clk_init_data) {
3192 		.name = "vclk2_input",
3193 		.ops = &clk_regmap_gate_ops,
3194 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3195 		.num_parents = 1,
3196 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3197 	},
3198 };
3199 
3200 static struct clk_regmap g12a_vclk_div = {
3201 	.data = &(struct clk_regmap_div_data){
3202 		.offset = HHI_VID_CLK_DIV,
3203 		.shift = 0,
3204 		.width = 8,
3205 	},
3206 	.hw.init = &(struct clk_init_data){
3207 		.name = "vclk_div",
3208 		.ops = &clk_regmap_divider_ops,
3209 		.parent_hws = (const struct clk_hw *[]) {
3210 			&g12a_vclk_input.hw
3211 		},
3212 		.num_parents = 1,
3213 		.flags = CLK_GET_RATE_NOCACHE,
3214 	},
3215 };
3216 
3217 static struct clk_regmap g12a_vclk2_div = {
3218 	.data = &(struct clk_regmap_div_data){
3219 		.offset = HHI_VIID_CLK_DIV,
3220 		.shift = 0,
3221 		.width = 8,
3222 	},
3223 	.hw.init = &(struct clk_init_data){
3224 		.name = "vclk2_div",
3225 		.ops = &clk_regmap_divider_ops,
3226 		.parent_hws = (const struct clk_hw *[]) {
3227 			&g12a_vclk2_input.hw
3228 		},
3229 		.num_parents = 1,
3230 		.flags = CLK_GET_RATE_NOCACHE,
3231 	},
3232 };
3233 
3234 static struct clk_regmap g12a_vclk = {
3235 	.data = &(struct clk_regmap_gate_data){
3236 		.offset = HHI_VID_CLK_CNTL,
3237 		.bit_idx = 19,
3238 	},
3239 	.hw.init = &(struct clk_init_data) {
3240 		.name = "vclk",
3241 		.ops = &clk_regmap_gate_ops,
3242 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3243 		.num_parents = 1,
3244 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3245 	},
3246 };
3247 
3248 static struct clk_regmap g12a_vclk2 = {
3249 	.data = &(struct clk_regmap_gate_data){
3250 		.offset = HHI_VIID_CLK_CNTL,
3251 		.bit_idx = 19,
3252 	},
3253 	.hw.init = &(struct clk_init_data) {
3254 		.name = "vclk2",
3255 		.ops = &clk_regmap_gate_ops,
3256 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3257 		.num_parents = 1,
3258 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3259 	},
3260 };
3261 
3262 static struct clk_regmap g12a_vclk_div1 = {
3263 	.data = &(struct clk_regmap_gate_data){
3264 		.offset = HHI_VID_CLK_CNTL,
3265 		.bit_idx = 0,
3266 	},
3267 	.hw.init = &(struct clk_init_data) {
3268 		.name = "vclk_div1",
3269 		.ops = &clk_regmap_gate_ops,
3270 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3271 		.num_parents = 1,
3272 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3273 	},
3274 };
3275 
3276 static struct clk_regmap g12a_vclk_div2_en = {
3277 	.data = &(struct clk_regmap_gate_data){
3278 		.offset = HHI_VID_CLK_CNTL,
3279 		.bit_idx = 1,
3280 	},
3281 	.hw.init = &(struct clk_init_data) {
3282 		.name = "vclk_div2_en",
3283 		.ops = &clk_regmap_gate_ops,
3284 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3285 		.num_parents = 1,
3286 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3287 	},
3288 };
3289 
3290 static struct clk_regmap g12a_vclk_div4_en = {
3291 	.data = &(struct clk_regmap_gate_data){
3292 		.offset = HHI_VID_CLK_CNTL,
3293 		.bit_idx = 2,
3294 	},
3295 	.hw.init = &(struct clk_init_data) {
3296 		.name = "vclk_div4_en",
3297 		.ops = &clk_regmap_gate_ops,
3298 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3299 		.num_parents = 1,
3300 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3301 	},
3302 };
3303 
3304 static struct clk_regmap g12a_vclk_div6_en = {
3305 	.data = &(struct clk_regmap_gate_data){
3306 		.offset = HHI_VID_CLK_CNTL,
3307 		.bit_idx = 3,
3308 	},
3309 	.hw.init = &(struct clk_init_data) {
3310 		.name = "vclk_div6_en",
3311 		.ops = &clk_regmap_gate_ops,
3312 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3313 		.num_parents = 1,
3314 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3315 	},
3316 };
3317 
3318 static struct clk_regmap g12a_vclk_div12_en = {
3319 	.data = &(struct clk_regmap_gate_data){
3320 		.offset = HHI_VID_CLK_CNTL,
3321 		.bit_idx = 4,
3322 	},
3323 	.hw.init = &(struct clk_init_data) {
3324 		.name = "vclk_div12_en",
3325 		.ops = &clk_regmap_gate_ops,
3326 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3327 		.num_parents = 1,
3328 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3329 	},
3330 };
3331 
3332 static struct clk_regmap g12a_vclk2_div1 = {
3333 	.data = &(struct clk_regmap_gate_data){
3334 		.offset = HHI_VIID_CLK_CNTL,
3335 		.bit_idx = 0,
3336 	},
3337 	.hw.init = &(struct clk_init_data) {
3338 		.name = "vclk2_div1",
3339 		.ops = &clk_regmap_gate_ops,
3340 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3341 		.num_parents = 1,
3342 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3343 	},
3344 };
3345 
3346 static struct clk_regmap g12a_vclk2_div2_en = {
3347 	.data = &(struct clk_regmap_gate_data){
3348 		.offset = HHI_VIID_CLK_CNTL,
3349 		.bit_idx = 1,
3350 	},
3351 	.hw.init = &(struct clk_init_data) {
3352 		.name = "vclk2_div2_en",
3353 		.ops = &clk_regmap_gate_ops,
3354 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3355 		.num_parents = 1,
3356 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3357 	},
3358 };
3359 
3360 static struct clk_regmap g12a_vclk2_div4_en = {
3361 	.data = &(struct clk_regmap_gate_data){
3362 		.offset = HHI_VIID_CLK_CNTL,
3363 		.bit_idx = 2,
3364 	},
3365 	.hw.init = &(struct clk_init_data) {
3366 		.name = "vclk2_div4_en",
3367 		.ops = &clk_regmap_gate_ops,
3368 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3369 		.num_parents = 1,
3370 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3371 	},
3372 };
3373 
3374 static struct clk_regmap g12a_vclk2_div6_en = {
3375 	.data = &(struct clk_regmap_gate_data){
3376 		.offset = HHI_VIID_CLK_CNTL,
3377 		.bit_idx = 3,
3378 	},
3379 	.hw.init = &(struct clk_init_data) {
3380 		.name = "vclk2_div6_en",
3381 		.ops = &clk_regmap_gate_ops,
3382 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3383 		.num_parents = 1,
3384 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3385 	},
3386 };
3387 
3388 static struct clk_regmap g12a_vclk2_div12_en = {
3389 	.data = &(struct clk_regmap_gate_data){
3390 		.offset = HHI_VIID_CLK_CNTL,
3391 		.bit_idx = 4,
3392 	},
3393 	.hw.init = &(struct clk_init_data) {
3394 		.name = "vclk2_div12_en",
3395 		.ops = &clk_regmap_gate_ops,
3396 		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3397 		.num_parents = 1,
3398 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3399 	},
3400 };
3401 
3402 static struct clk_fixed_factor g12a_vclk_div2 = {
3403 	.mult = 1,
3404 	.div = 2,
3405 	.hw.init = &(struct clk_init_data){
3406 		.name = "vclk_div2",
3407 		.ops = &clk_fixed_factor_ops,
3408 		.parent_hws = (const struct clk_hw *[]) {
3409 			&g12a_vclk_div2_en.hw
3410 		},
3411 		.num_parents = 1,
3412 	},
3413 };
3414 
3415 static struct clk_fixed_factor g12a_vclk_div4 = {
3416 	.mult = 1,
3417 	.div = 4,
3418 	.hw.init = &(struct clk_init_data){
3419 		.name = "vclk_div4",
3420 		.ops = &clk_fixed_factor_ops,
3421 		.parent_hws = (const struct clk_hw *[]) {
3422 			&g12a_vclk_div4_en.hw
3423 		},
3424 		.num_parents = 1,
3425 	},
3426 };
3427 
3428 static struct clk_fixed_factor g12a_vclk_div6 = {
3429 	.mult = 1,
3430 	.div = 6,
3431 	.hw.init = &(struct clk_init_data){
3432 		.name = "vclk_div6",
3433 		.ops = &clk_fixed_factor_ops,
3434 		.parent_hws = (const struct clk_hw *[]) {
3435 			&g12a_vclk_div6_en.hw
3436 		},
3437 		.num_parents = 1,
3438 	},
3439 };
3440 
3441 static struct clk_fixed_factor g12a_vclk_div12 = {
3442 	.mult = 1,
3443 	.div = 12,
3444 	.hw.init = &(struct clk_init_data){
3445 		.name = "vclk_div12",
3446 		.ops = &clk_fixed_factor_ops,
3447 		.parent_hws = (const struct clk_hw *[]) {
3448 			&g12a_vclk_div12_en.hw
3449 		},
3450 		.num_parents = 1,
3451 	},
3452 };
3453 
3454 static struct clk_fixed_factor g12a_vclk2_div2 = {
3455 	.mult = 1,
3456 	.div = 2,
3457 	.hw.init = &(struct clk_init_data){
3458 		.name = "vclk2_div2",
3459 		.ops = &clk_fixed_factor_ops,
3460 		.parent_hws = (const struct clk_hw *[]) {
3461 			&g12a_vclk2_div2_en.hw
3462 		},
3463 		.num_parents = 1,
3464 	},
3465 };
3466 
3467 static struct clk_fixed_factor g12a_vclk2_div4 = {
3468 	.mult = 1,
3469 	.div = 4,
3470 	.hw.init = &(struct clk_init_data){
3471 		.name = "vclk2_div4",
3472 		.ops = &clk_fixed_factor_ops,
3473 		.parent_hws = (const struct clk_hw *[]) {
3474 			&g12a_vclk2_div4_en.hw
3475 		},
3476 		.num_parents = 1,
3477 	},
3478 };
3479 
3480 static struct clk_fixed_factor g12a_vclk2_div6 = {
3481 	.mult = 1,
3482 	.div = 6,
3483 	.hw.init = &(struct clk_init_data){
3484 		.name = "vclk2_div6",
3485 		.ops = &clk_fixed_factor_ops,
3486 		.parent_hws = (const struct clk_hw *[]) {
3487 			&g12a_vclk2_div6_en.hw
3488 		},
3489 		.num_parents = 1,
3490 	},
3491 };
3492 
3493 static struct clk_fixed_factor g12a_vclk2_div12 = {
3494 	.mult = 1,
3495 	.div = 12,
3496 	.hw.init = &(struct clk_init_data){
3497 		.name = "vclk2_div12",
3498 		.ops = &clk_fixed_factor_ops,
3499 		.parent_hws = (const struct clk_hw *[]) {
3500 			&g12a_vclk2_div12_en.hw
3501 		},
3502 		.num_parents = 1,
3503 	},
3504 };
3505 
3506 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3507 static const struct clk_hw *g12a_cts_parent_hws[] = {
3508 	&g12a_vclk_div1.hw,
3509 	&g12a_vclk_div2.hw,
3510 	&g12a_vclk_div4.hw,
3511 	&g12a_vclk_div6.hw,
3512 	&g12a_vclk_div12.hw,
3513 	&g12a_vclk2_div1.hw,
3514 	&g12a_vclk2_div2.hw,
3515 	&g12a_vclk2_div4.hw,
3516 	&g12a_vclk2_div6.hw,
3517 	&g12a_vclk2_div12.hw,
3518 };
3519 
3520 static struct clk_regmap g12a_cts_enci_sel = {
3521 	.data = &(struct clk_regmap_mux_data){
3522 		.offset = HHI_VID_CLK_DIV,
3523 		.mask = 0xf,
3524 		.shift = 28,
3525 		.table = mux_table_cts_sel,
3526 	},
3527 	.hw.init = &(struct clk_init_data){
3528 		.name = "cts_enci_sel",
3529 		.ops = &clk_regmap_mux_ops,
3530 		.parent_hws = g12a_cts_parent_hws,
3531 		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3532 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3533 	},
3534 };
3535 
3536 static struct clk_regmap g12a_cts_encp_sel = {
3537 	.data = &(struct clk_regmap_mux_data){
3538 		.offset = HHI_VID_CLK_DIV,
3539 		.mask = 0xf,
3540 		.shift = 20,
3541 		.table = mux_table_cts_sel,
3542 	},
3543 	.hw.init = &(struct clk_init_data){
3544 		.name = "cts_encp_sel",
3545 		.ops = &clk_regmap_mux_ops,
3546 		.parent_hws = g12a_cts_parent_hws,
3547 		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3548 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3549 	},
3550 };
3551 
3552 static struct clk_regmap g12a_cts_vdac_sel = {
3553 	.data = &(struct clk_regmap_mux_data){
3554 		.offset = HHI_VIID_CLK_DIV,
3555 		.mask = 0xf,
3556 		.shift = 28,
3557 		.table = mux_table_cts_sel,
3558 	},
3559 	.hw.init = &(struct clk_init_data){
3560 		.name = "cts_vdac_sel",
3561 		.ops = &clk_regmap_mux_ops,
3562 		.parent_hws = g12a_cts_parent_hws,
3563 		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3564 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3565 	},
3566 };
3567 
3568 /* TOFIX: add support for cts_tcon */
3569 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3570 static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3571 	&g12a_vclk_div1.hw,
3572 	&g12a_vclk_div2.hw,
3573 	&g12a_vclk_div4.hw,
3574 	&g12a_vclk_div6.hw,
3575 	&g12a_vclk_div12.hw,
3576 	&g12a_vclk2_div1.hw,
3577 	&g12a_vclk2_div2.hw,
3578 	&g12a_vclk2_div4.hw,
3579 	&g12a_vclk2_div6.hw,
3580 	&g12a_vclk2_div12.hw,
3581 };
3582 
3583 static struct clk_regmap g12a_hdmi_tx_sel = {
3584 	.data = &(struct clk_regmap_mux_data){
3585 		.offset = HHI_HDMI_CLK_CNTL,
3586 		.mask = 0xf,
3587 		.shift = 16,
3588 		.table = mux_table_hdmi_tx_sel,
3589 	},
3590 	.hw.init = &(struct clk_init_data){
3591 		.name = "hdmi_tx_sel",
3592 		.ops = &clk_regmap_mux_ops,
3593 		.parent_hws = g12a_cts_hdmi_tx_parent_hws,
3594 		.num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3595 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3596 	},
3597 };
3598 
3599 static struct clk_regmap g12a_cts_enci = {
3600 	.data = &(struct clk_regmap_gate_data){
3601 		.offset = HHI_VID_CLK_CNTL2,
3602 		.bit_idx = 0,
3603 	},
3604 	.hw.init = &(struct clk_init_data) {
3605 		.name = "cts_enci",
3606 		.ops = &clk_regmap_gate_ops,
3607 		.parent_hws = (const struct clk_hw *[]) {
3608 			&g12a_cts_enci_sel.hw
3609 		},
3610 		.num_parents = 1,
3611 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3612 	},
3613 };
3614 
3615 static struct clk_regmap g12a_cts_encp = {
3616 	.data = &(struct clk_regmap_gate_data){
3617 		.offset = HHI_VID_CLK_CNTL2,
3618 		.bit_idx = 2,
3619 	},
3620 	.hw.init = &(struct clk_init_data) {
3621 		.name = "cts_encp",
3622 		.ops = &clk_regmap_gate_ops,
3623 		.parent_hws = (const struct clk_hw *[]) {
3624 			&g12a_cts_encp_sel.hw
3625 		},
3626 		.num_parents = 1,
3627 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3628 	},
3629 };
3630 
3631 static struct clk_regmap g12a_cts_vdac = {
3632 	.data = &(struct clk_regmap_gate_data){
3633 		.offset = HHI_VID_CLK_CNTL2,
3634 		.bit_idx = 4,
3635 	},
3636 	.hw.init = &(struct clk_init_data) {
3637 		.name = "cts_vdac",
3638 		.ops = &clk_regmap_gate_ops,
3639 		.parent_hws = (const struct clk_hw *[]) {
3640 			&g12a_cts_vdac_sel.hw
3641 		},
3642 		.num_parents = 1,
3643 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3644 	},
3645 };
3646 
3647 static struct clk_regmap g12a_hdmi_tx = {
3648 	.data = &(struct clk_regmap_gate_data){
3649 		.offset = HHI_VID_CLK_CNTL2,
3650 		.bit_idx = 5,
3651 	},
3652 	.hw.init = &(struct clk_init_data) {
3653 		.name = "hdmi_tx",
3654 		.ops = &clk_regmap_gate_ops,
3655 		.parent_hws = (const struct clk_hw *[]) {
3656 			&g12a_hdmi_tx_sel.hw
3657 		},
3658 		.num_parents = 1,
3659 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3660 	},
3661 };
3662 
3663 /* MIPI DSI Host Clocks */
3664 
3665 static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
3666 	&g12a_vid_pll.hw,
3667 	&g12a_gp0_pll.hw,
3668 	&g12a_hifi_pll.hw,
3669 	&g12a_mpll1.hw,
3670 	&g12a_fclk_div2.hw,
3671 	&g12a_fclk_div2p5.hw,
3672 	&g12a_fclk_div3.hw,
3673 	&g12a_fclk_div7.hw,
3674 };
3675 
3676 static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
3677 	.data = &(struct clk_regmap_mux_data){
3678 		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3679 		.mask = 0x7,
3680 		.shift = 12,
3681 		.flags = CLK_MUX_ROUND_CLOSEST,
3682 	},
3683 	.hw.init = &(struct clk_init_data){
3684 		.name = "mipi_dsi_pxclk_sel",
3685 		.ops = &clk_regmap_mux_ops,
3686 		.parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
3687 		.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
3688 		.flags = CLK_SET_RATE_NO_REPARENT,
3689 	},
3690 };
3691 
3692 static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
3693 	.data = &(struct clk_regmap_div_data){
3694 		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3695 		.shift = 0,
3696 		.width = 7,
3697 	},
3698 	.hw.init = &(struct clk_init_data){
3699 		.name = "mipi_dsi_pxclk_div",
3700 		.ops = &clk_regmap_divider_ops,
3701 		.parent_hws = (const struct clk_hw *[]) {
3702 			&g12a_mipi_dsi_pxclk_sel.hw
3703 		},
3704 		.num_parents = 1,
3705 		.flags = CLK_SET_RATE_PARENT,
3706 	},
3707 };
3708 
3709 static struct clk_regmap g12a_mipi_dsi_pxclk = {
3710 	.data = &(struct clk_regmap_gate_data){
3711 		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3712 		.bit_idx = 8,
3713 	},
3714 	.hw.init = &(struct clk_init_data) {
3715 		.name = "mipi_dsi_pxclk",
3716 		.ops = &clk_regmap_gate_ops,
3717 		.parent_hws = (const struct clk_hw *[]) {
3718 			&g12a_mipi_dsi_pxclk_div.hw
3719 		},
3720 		.num_parents = 1,
3721 		.flags = CLK_SET_RATE_PARENT,
3722 	},
3723 };
3724 
3725 /* HDMI Clocks */
3726 
3727 static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3728 	{ .fw_name = "xtal", },
3729 	{ .hw = &g12a_fclk_div4.hw },
3730 	{ .hw = &g12a_fclk_div3.hw },
3731 	{ .hw = &g12a_fclk_div5.hw },
3732 };
3733 
3734 static struct clk_regmap g12a_hdmi_sel = {
3735 	.data = &(struct clk_regmap_mux_data){
3736 		.offset = HHI_HDMI_CLK_CNTL,
3737 		.mask = 0x3,
3738 		.shift = 9,
3739 		.flags = CLK_MUX_ROUND_CLOSEST,
3740 	},
3741 	.hw.init = &(struct clk_init_data){
3742 		.name = "hdmi_sel",
3743 		.ops = &clk_regmap_mux_ops,
3744 		.parent_data = g12a_hdmi_parent_data,
3745 		.num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3746 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3747 	},
3748 };
3749 
3750 static struct clk_regmap g12a_hdmi_div = {
3751 	.data = &(struct clk_regmap_div_data){
3752 		.offset = HHI_HDMI_CLK_CNTL,
3753 		.shift = 0,
3754 		.width = 7,
3755 	},
3756 	.hw.init = &(struct clk_init_data){
3757 		.name = "hdmi_div",
3758 		.ops = &clk_regmap_divider_ops,
3759 		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3760 		.num_parents = 1,
3761 		.flags = CLK_GET_RATE_NOCACHE,
3762 	},
3763 };
3764 
3765 static struct clk_regmap g12a_hdmi = {
3766 	.data = &(struct clk_regmap_gate_data){
3767 		.offset = HHI_HDMI_CLK_CNTL,
3768 		.bit_idx = 8,
3769 	},
3770 	.hw.init = &(struct clk_init_data) {
3771 		.name = "hdmi",
3772 		.ops = &clk_regmap_gate_ops,
3773 		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3774 		.num_parents = 1,
3775 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3776 	},
3777 };
3778 
3779 /*
3780  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3781  * muxed by a glitch-free switch. The CCF can manage this glitch-free
3782  * mux because it does top-to-bottom updates the each clock tree and
3783  * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
3784  */
3785 static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
3786 	{ .fw_name = "xtal", },
3787 	{ .hw = &g12a_gp0_pll.hw },
3788 	{ .hw = &g12a_hifi_pll.hw },
3789 	{ .hw = &g12a_fclk_div2p5.hw },
3790 	{ .hw = &g12a_fclk_div3.hw },
3791 	{ .hw = &g12a_fclk_div4.hw },
3792 	{ .hw = &g12a_fclk_div5.hw },
3793 	{ .hw = &g12a_fclk_div7.hw },
3794 };
3795 
3796 static struct clk_regmap g12a_mali_0_sel = {
3797 	.data = &(struct clk_regmap_mux_data){
3798 		.offset = HHI_MALI_CLK_CNTL,
3799 		.mask = 0x7,
3800 		.shift = 9,
3801 	},
3802 	.hw.init = &(struct clk_init_data){
3803 		.name = "mali_0_sel",
3804 		.ops = &clk_regmap_mux_ops,
3805 		.parent_data = g12a_mali_0_1_parent_data,
3806 		.num_parents = 8,
3807 		/*
3808 		 * Don't request the parent to change the rate because
3809 		 * all GPU frequencies can be derived from the fclk_*
3810 		 * clocks and one special GP0_PLL setting. This is
3811 		 * important because we need the MPLL clocks for audio.
3812 		 */
3813 		.flags = 0,
3814 	},
3815 };
3816 
3817 static struct clk_regmap g12a_mali_0_div = {
3818 	.data = &(struct clk_regmap_div_data){
3819 		.offset = HHI_MALI_CLK_CNTL,
3820 		.shift = 0,
3821 		.width = 7,
3822 	},
3823 	.hw.init = &(struct clk_init_data){
3824 		.name = "mali_0_div",
3825 		.ops = &clk_regmap_divider_ops,
3826 		.parent_hws = (const struct clk_hw *[]) {
3827 			&g12a_mali_0_sel.hw
3828 		},
3829 		.num_parents = 1,
3830 		.flags = CLK_SET_RATE_PARENT,
3831 	},
3832 };
3833 
3834 static struct clk_regmap g12a_mali_0 = {
3835 	.data = &(struct clk_regmap_gate_data){
3836 		.offset = HHI_MALI_CLK_CNTL,
3837 		.bit_idx = 8,
3838 	},
3839 	.hw.init = &(struct clk_init_data){
3840 		.name = "mali_0",
3841 		.ops = &clk_regmap_gate_ops,
3842 		.parent_hws = (const struct clk_hw *[]) {
3843 			&g12a_mali_0_div.hw
3844 		},
3845 		.num_parents = 1,
3846 		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3847 	},
3848 };
3849 
3850 static struct clk_regmap g12a_mali_1_sel = {
3851 	.data = &(struct clk_regmap_mux_data){
3852 		.offset = HHI_MALI_CLK_CNTL,
3853 		.mask = 0x7,
3854 		.shift = 25,
3855 	},
3856 	.hw.init = &(struct clk_init_data){
3857 		.name = "mali_1_sel",
3858 		.ops = &clk_regmap_mux_ops,
3859 		.parent_data = g12a_mali_0_1_parent_data,
3860 		.num_parents = 8,
3861 		/*
3862 		 * Don't request the parent to change the rate because
3863 		 * all GPU frequencies can be derived from the fclk_*
3864 		 * clocks and one special GP0_PLL setting. This is
3865 		 * important because we need the MPLL clocks for audio.
3866 		 */
3867 		.flags = 0,
3868 	},
3869 };
3870 
3871 static struct clk_regmap g12a_mali_1_div = {
3872 	.data = &(struct clk_regmap_div_data){
3873 		.offset = HHI_MALI_CLK_CNTL,
3874 		.shift = 16,
3875 		.width = 7,
3876 	},
3877 	.hw.init = &(struct clk_init_data){
3878 		.name = "mali_1_div",
3879 		.ops = &clk_regmap_divider_ops,
3880 		.parent_hws = (const struct clk_hw *[]) {
3881 			&g12a_mali_1_sel.hw
3882 		},
3883 		.num_parents = 1,
3884 		.flags = CLK_SET_RATE_PARENT,
3885 	},
3886 };
3887 
3888 static struct clk_regmap g12a_mali_1 = {
3889 	.data = &(struct clk_regmap_gate_data){
3890 		.offset = HHI_MALI_CLK_CNTL,
3891 		.bit_idx = 24,
3892 	},
3893 	.hw.init = &(struct clk_init_data){
3894 		.name = "mali_1",
3895 		.ops = &clk_regmap_gate_ops,
3896 		.parent_hws = (const struct clk_hw *[]) {
3897 			&g12a_mali_1_div.hw
3898 		},
3899 		.num_parents = 1,
3900 		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3901 	},
3902 };
3903 
3904 static const struct clk_hw *g12a_mali_parent_hws[] = {
3905 	&g12a_mali_0.hw,
3906 	&g12a_mali_1.hw,
3907 };
3908 
3909 static struct clk_regmap g12a_mali = {
3910 	.data = &(struct clk_regmap_mux_data){
3911 		.offset = HHI_MALI_CLK_CNTL,
3912 		.mask = 1,
3913 		.shift = 31,
3914 	},
3915 	.hw.init = &(struct clk_init_data){
3916 		.name = "mali",
3917 		.ops = &clk_regmap_mux_ops,
3918 		.parent_hws = g12a_mali_parent_hws,
3919 		.num_parents = 2,
3920 		.flags = CLK_SET_RATE_PARENT,
3921 	},
3922 };
3923 
3924 static struct clk_regmap g12a_ts_div = {
3925 	.data = &(struct clk_regmap_div_data){
3926 		.offset = HHI_TS_CLK_CNTL,
3927 		.shift = 0,
3928 		.width = 8,
3929 	},
3930 	.hw.init = &(struct clk_init_data){
3931 		.name = "ts_div",
3932 		.ops = &clk_regmap_divider_ro_ops,
3933 		.parent_data = &(const struct clk_parent_data) {
3934 			.fw_name = "xtal",
3935 		},
3936 		.num_parents = 1,
3937 	},
3938 };
3939 
3940 static struct clk_regmap g12a_ts = {
3941 	.data = &(struct clk_regmap_gate_data){
3942 		.offset = HHI_TS_CLK_CNTL,
3943 		.bit_idx = 8,
3944 	},
3945 	.hw.init = &(struct clk_init_data){
3946 		.name = "ts",
3947 		.ops = &clk_regmap_gate_ops,
3948 		.parent_hws = (const struct clk_hw *[]) {
3949 			&g12a_ts_div.hw
3950 		},
3951 		.num_parents = 1,
3952 	},
3953 };
3954 
3955 /* SPICC SCLK source clock */
3956 
3957 static const struct clk_parent_data spicc_sclk_parent_data[] = {
3958 	{ .fw_name = "xtal", },
3959 	{ .hw = &g12a_clk81.hw },
3960 	{ .hw = &g12a_fclk_div4.hw },
3961 	{ .hw = &g12a_fclk_div3.hw },
3962 	{ .hw = &g12a_fclk_div5.hw },
3963 	{ .hw = &g12a_fclk_div7.hw },
3964 };
3965 
3966 static struct clk_regmap g12a_spicc0_sclk_sel = {
3967 	.data = &(struct clk_regmap_mux_data){
3968 		.offset = HHI_SPICC_CLK_CNTL,
3969 		.mask = 7,
3970 		.shift = 7,
3971 	},
3972 	.hw.init = &(struct clk_init_data){
3973 		.name = "spicc0_sclk_sel",
3974 		.ops = &clk_regmap_mux_ops,
3975 		.parent_data = spicc_sclk_parent_data,
3976 		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
3977 	},
3978 };
3979 
3980 static struct clk_regmap g12a_spicc0_sclk_div = {
3981 	.data = &(struct clk_regmap_div_data){
3982 		.offset = HHI_SPICC_CLK_CNTL,
3983 		.shift = 0,
3984 		.width = 6,
3985 	},
3986 	.hw.init = &(struct clk_init_data){
3987 		.name = "spicc0_sclk_div",
3988 		.ops = &clk_regmap_divider_ops,
3989 		.parent_hws = (const struct clk_hw *[]) {
3990 			&g12a_spicc0_sclk_sel.hw
3991 		},
3992 		.num_parents = 1,
3993 		.flags = CLK_SET_RATE_PARENT,
3994 	},
3995 };
3996 
3997 static struct clk_regmap g12a_spicc0_sclk = {
3998 	.data = &(struct clk_regmap_gate_data){
3999 		.offset = HHI_SPICC_CLK_CNTL,
4000 		.bit_idx = 6,
4001 	},
4002 	.hw.init = &(struct clk_init_data){
4003 		.name = "spicc0_sclk",
4004 		.ops = &clk_regmap_gate_ops,
4005 		.parent_hws = (const struct clk_hw *[]) {
4006 			&g12a_spicc0_sclk_div.hw
4007 		},
4008 		.num_parents = 1,
4009 		.flags = CLK_SET_RATE_PARENT,
4010 	},
4011 };
4012 
4013 static struct clk_regmap g12a_spicc1_sclk_sel = {
4014 	.data = &(struct clk_regmap_mux_data){
4015 		.offset = HHI_SPICC_CLK_CNTL,
4016 		.mask = 7,
4017 		.shift = 23,
4018 	},
4019 	.hw.init = &(struct clk_init_data){
4020 		.name = "spicc1_sclk_sel",
4021 		.ops = &clk_regmap_mux_ops,
4022 		.parent_data = spicc_sclk_parent_data,
4023 		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4024 	},
4025 };
4026 
4027 static struct clk_regmap g12a_spicc1_sclk_div = {
4028 	.data = &(struct clk_regmap_div_data){
4029 		.offset = HHI_SPICC_CLK_CNTL,
4030 		.shift = 16,
4031 		.width = 6,
4032 	},
4033 	.hw.init = &(struct clk_init_data){
4034 		.name = "spicc1_sclk_div",
4035 		.ops = &clk_regmap_divider_ops,
4036 		.parent_hws = (const struct clk_hw *[]) {
4037 			&g12a_spicc1_sclk_sel.hw
4038 		},
4039 		.num_parents = 1,
4040 		.flags = CLK_SET_RATE_PARENT,
4041 	},
4042 };
4043 
4044 static struct clk_regmap g12a_spicc1_sclk = {
4045 	.data = &(struct clk_regmap_gate_data){
4046 		.offset = HHI_SPICC_CLK_CNTL,
4047 		.bit_idx = 22,
4048 	},
4049 	.hw.init = &(struct clk_init_data){
4050 		.name = "spicc1_sclk",
4051 		.ops = &clk_regmap_gate_ops,
4052 		.parent_hws = (const struct clk_hw *[]) {
4053 			&g12a_spicc1_sclk_div.hw
4054 		},
4055 		.num_parents = 1,
4056 		.flags = CLK_SET_RATE_PARENT,
4057 	},
4058 };
4059 
4060 /* Neural Network Accelerator source clock */
4061 
4062 static const struct clk_parent_data nna_clk_parent_data[] = {
4063 	{ .fw_name = "xtal", },
4064 	{ .hw = &g12a_gp0_pll.hw, },
4065 	{ .hw = &g12a_hifi_pll.hw, },
4066 	{ .hw = &g12a_fclk_div2p5.hw, },
4067 	{ .hw = &g12a_fclk_div3.hw, },
4068 	{ .hw = &g12a_fclk_div4.hw, },
4069 	{ .hw = &g12a_fclk_div5.hw, },
4070 	{ .hw = &g12a_fclk_div7.hw },
4071 };
4072 
4073 static struct clk_regmap sm1_nna_axi_clk_sel = {
4074 	.data = &(struct clk_regmap_mux_data){
4075 		.offset = HHI_NNA_CLK_CNTL,
4076 		.mask = 7,
4077 		.shift = 9,
4078 	},
4079 	.hw.init = &(struct clk_init_data){
4080 		.name = "nna_axi_clk_sel",
4081 		.ops = &clk_regmap_mux_ops,
4082 		.parent_data = nna_clk_parent_data,
4083 		.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4084 	},
4085 };
4086 
4087 static struct clk_regmap sm1_nna_axi_clk_div = {
4088 	.data = &(struct clk_regmap_div_data){
4089 		.offset = HHI_NNA_CLK_CNTL,
4090 		.shift = 0,
4091 		.width = 7,
4092 	},
4093 	.hw.init = &(struct clk_init_data){
4094 		.name = "nna_axi_clk_div",
4095 		.ops = &clk_regmap_divider_ops,
4096 		.parent_hws = (const struct clk_hw *[]) {
4097 			&sm1_nna_axi_clk_sel.hw
4098 		},
4099 		.num_parents = 1,
4100 		.flags = CLK_SET_RATE_PARENT,
4101 	},
4102 };
4103 
4104 static struct clk_regmap sm1_nna_axi_clk = {
4105 	.data = &(struct clk_regmap_gate_data){
4106 		.offset = HHI_NNA_CLK_CNTL,
4107 		.bit_idx = 8,
4108 	},
4109 	.hw.init = &(struct clk_init_data){
4110 		.name = "nna_axi_clk",
4111 		.ops = &clk_regmap_gate_ops,
4112 		.parent_hws = (const struct clk_hw *[]) {
4113 			&sm1_nna_axi_clk_div.hw
4114 		},
4115 		.num_parents = 1,
4116 		.flags = CLK_SET_RATE_PARENT,
4117 	},
4118 };
4119 
4120 static struct clk_regmap sm1_nna_core_clk_sel = {
4121 	.data = &(struct clk_regmap_mux_data){
4122 		.offset = HHI_NNA_CLK_CNTL,
4123 		.mask = 7,
4124 		.shift = 25,
4125 	},
4126 	.hw.init = &(struct clk_init_data){
4127 		.name = "nna_core_clk_sel",
4128 		.ops = &clk_regmap_mux_ops,
4129 		.parent_data = nna_clk_parent_data,
4130 		.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4131 	},
4132 };
4133 
4134 static struct clk_regmap sm1_nna_core_clk_div = {
4135 	.data = &(struct clk_regmap_div_data){
4136 		.offset = HHI_NNA_CLK_CNTL,
4137 		.shift = 16,
4138 		.width = 7,
4139 	},
4140 	.hw.init = &(struct clk_init_data){
4141 		.name = "nna_core_clk_div",
4142 		.ops = &clk_regmap_divider_ops,
4143 		.parent_hws = (const struct clk_hw *[]) {
4144 			&sm1_nna_core_clk_sel.hw
4145 		},
4146 		.num_parents = 1,
4147 		.flags = CLK_SET_RATE_PARENT,
4148 	},
4149 };
4150 
4151 static struct clk_regmap sm1_nna_core_clk = {
4152 	.data = &(struct clk_regmap_gate_data){
4153 		.offset = HHI_NNA_CLK_CNTL,
4154 		.bit_idx = 24,
4155 	},
4156 	.hw.init = &(struct clk_init_data){
4157 		.name = "nna_core_clk",
4158 		.ops = &clk_regmap_gate_ops,
4159 		.parent_hws = (const struct clk_hw *[]) {
4160 			&sm1_nna_core_clk_div.hw
4161 		},
4162 		.num_parents = 1,
4163 		.flags = CLK_SET_RATE_PARENT,
4164 	},
4165 };
4166 
4167 #define MESON_GATE(_name, _reg, _bit) \
4168 	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4169 
4170 #define MESON_GATE_RO(_name, _reg, _bit) \
4171 	MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4172 
4173 /* Everything Else (EE) domain gates */
4174 static MESON_GATE(g12a_ddr,			HHI_GCLK_MPEG0,	0);
4175 static MESON_GATE(g12a_dos,			HHI_GCLK_MPEG0,	1);
4176 static MESON_GATE(g12a_audio_locker,		HHI_GCLK_MPEG0,	2);
4177 static MESON_GATE(g12a_mipi_dsi_host,		HHI_GCLK_MPEG0,	3);
4178 static MESON_GATE(g12a_eth_phy,			HHI_GCLK_MPEG0,	4);
4179 static MESON_GATE(g12a_isa,			HHI_GCLK_MPEG0,	5);
4180 static MESON_GATE(g12a_pl301,			HHI_GCLK_MPEG0,	6);
4181 static MESON_GATE(g12a_periphs,			HHI_GCLK_MPEG0,	7);
4182 static MESON_GATE(g12a_spicc_0,			HHI_GCLK_MPEG0,	8);
4183 static MESON_GATE(g12a_i2c,			HHI_GCLK_MPEG0,	9);
4184 static MESON_GATE(g12a_sana,			HHI_GCLK_MPEG0,	10);
4185 static MESON_GATE(g12a_sd,			HHI_GCLK_MPEG0,	11);
4186 static MESON_GATE(g12a_rng0,			HHI_GCLK_MPEG0,	12);
4187 static MESON_GATE(g12a_uart0,			HHI_GCLK_MPEG0,	13);
4188 static MESON_GATE(g12a_spicc_1,			HHI_GCLK_MPEG0,	14);
4189 static MESON_GATE(g12a_hiu_reg,			HHI_GCLK_MPEG0,	19);
4190 static MESON_GATE(g12a_mipi_dsi_phy,		HHI_GCLK_MPEG0,	20);
4191 static MESON_GATE(g12a_assist_misc,		HHI_GCLK_MPEG0,	23);
4192 static MESON_GATE(g12a_emmc_a,			HHI_GCLK_MPEG0,	4);
4193 static MESON_GATE(g12a_emmc_b,			HHI_GCLK_MPEG0,	25);
4194 static MESON_GATE(g12a_emmc_c,			HHI_GCLK_MPEG0,	26);
4195 static MESON_GATE(g12a_audio_codec,		HHI_GCLK_MPEG0,	28);
4196 
4197 static MESON_GATE(g12a_audio,			HHI_GCLK_MPEG1,	0);
4198 static MESON_GATE(g12a_eth_core,		HHI_GCLK_MPEG1,	3);
4199 static MESON_GATE(g12a_demux,			HHI_GCLK_MPEG1,	4);
4200 static MESON_GATE(g12a_audio_ififo,		HHI_GCLK_MPEG1,	11);
4201 static MESON_GATE(g12a_adc,			HHI_GCLK_MPEG1,	13);
4202 static MESON_GATE(g12a_uart1,			HHI_GCLK_MPEG1,	16);
4203 static MESON_GATE(g12a_g2d,			HHI_GCLK_MPEG1,	20);
4204 static MESON_GATE(g12a_reset,			HHI_GCLK_MPEG1,	23);
4205 static MESON_GATE(g12a_pcie_comb,		HHI_GCLK_MPEG1,	24);
4206 static MESON_GATE(g12a_parser,			HHI_GCLK_MPEG1,	25);
4207 static MESON_GATE(g12a_usb_general,		HHI_GCLK_MPEG1,	26);
4208 static MESON_GATE(g12a_pcie_phy,		HHI_GCLK_MPEG1,	27);
4209 static MESON_GATE(g12a_ahb_arb0,		HHI_GCLK_MPEG1,	29);
4210 
4211 static MESON_GATE(g12a_ahb_data_bus,		HHI_GCLK_MPEG2,	1);
4212 static MESON_GATE(g12a_ahb_ctrl_bus,		HHI_GCLK_MPEG2,	2);
4213 static MESON_GATE(g12a_htx_hdcp22,		HHI_GCLK_MPEG2,	3);
4214 static MESON_GATE(g12a_htx_pclk,		HHI_GCLK_MPEG2,	4);
4215 static MESON_GATE(g12a_bt656,			HHI_GCLK_MPEG2,	6);
4216 static MESON_GATE(g12a_usb1_to_ddr,		HHI_GCLK_MPEG2,	8);
4217 static MESON_GATE(g12a_mmc_pclk,		HHI_GCLK_MPEG2,	11);
4218 static MESON_GATE(g12a_uart2,			HHI_GCLK_MPEG2,	15);
4219 static MESON_GATE(g12a_vpu_intr,		HHI_GCLK_MPEG2,	25);
4220 static MESON_GATE(g12a_gic,			HHI_GCLK_MPEG2,	30);
4221 
4222 static MESON_GATE(g12a_vclk2_venci0,		HHI_GCLK_OTHER,	1);
4223 static MESON_GATE(g12a_vclk2_venci1,		HHI_GCLK_OTHER,	2);
4224 static MESON_GATE(g12a_vclk2_vencp0,		HHI_GCLK_OTHER,	3);
4225 static MESON_GATE(g12a_vclk2_vencp1,		HHI_GCLK_OTHER,	4);
4226 static MESON_GATE(g12a_vclk2_venct0,		HHI_GCLK_OTHER,	5);
4227 static MESON_GATE(g12a_vclk2_venct1,		HHI_GCLK_OTHER,	6);
4228 static MESON_GATE(g12a_vclk2_other,		HHI_GCLK_OTHER,	7);
4229 static MESON_GATE(g12a_vclk2_enci,		HHI_GCLK_OTHER,	8);
4230 static MESON_GATE(g12a_vclk2_encp,		HHI_GCLK_OTHER,	9);
4231 static MESON_GATE(g12a_dac_clk,			HHI_GCLK_OTHER,	10);
4232 static MESON_GATE(g12a_aoclk_gate,		HHI_GCLK_OTHER,	14);
4233 static MESON_GATE(g12a_iec958_gate,		HHI_GCLK_OTHER,	16);
4234 static MESON_GATE(g12a_enc480p,			HHI_GCLK_OTHER,	20);
4235 static MESON_GATE(g12a_rng1,			HHI_GCLK_OTHER,	21);
4236 static MESON_GATE(g12a_vclk2_enct,		HHI_GCLK_OTHER,	22);
4237 static MESON_GATE(g12a_vclk2_encl,		HHI_GCLK_OTHER,	23);
4238 static MESON_GATE(g12a_vclk2_venclmmc,		HHI_GCLK_OTHER,	24);
4239 static MESON_GATE(g12a_vclk2_vencl,		HHI_GCLK_OTHER,	25);
4240 static MESON_GATE(g12a_vclk2_other1,		HHI_GCLK_OTHER,	26);
4241 
4242 static MESON_GATE_RO(g12a_dma,			HHI_GCLK_OTHER2, 0);
4243 static MESON_GATE_RO(g12a_efuse,		HHI_GCLK_OTHER2, 1);
4244 static MESON_GATE_RO(g12a_rom_boot,		HHI_GCLK_OTHER2, 2);
4245 static MESON_GATE_RO(g12a_reset_sec,		HHI_GCLK_OTHER2, 3);
4246 static MESON_GATE_RO(g12a_sec_ahb_apb3,		HHI_GCLK_OTHER2, 4);
4247 
4248 /* Array of all clocks provided by this provider */
4249 static struct clk_hw *g12a_hw_clks[] = {
4250 	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4251 	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4252 	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4253 	[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4254 	[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4255 	[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4256 	[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4257 	[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4258 	[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4259 	[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4260 	[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4261 	[CLKID_CLK81]			= &g12a_clk81.hw,
4262 	[CLKID_MPLL0]			= &g12a_mpll0.hw,
4263 	[CLKID_MPLL1]			= &g12a_mpll1.hw,
4264 	[CLKID_MPLL2]			= &g12a_mpll2.hw,
4265 	[CLKID_MPLL3]			= &g12a_mpll3.hw,
4266 	[CLKID_DDR]			= &g12a_ddr.hw,
4267 	[CLKID_DOS]			= &g12a_dos.hw,
4268 	[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4269 	[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4270 	[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4271 	[CLKID_ISA]			= &g12a_isa.hw,
4272 	[CLKID_PL301]			= &g12a_pl301.hw,
4273 	[CLKID_PERIPHS]			= &g12a_periphs.hw,
4274 	[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4275 	[CLKID_I2C]			= &g12a_i2c.hw,
4276 	[CLKID_SANA]			= &g12a_sana.hw,
4277 	[CLKID_SD]			= &g12a_sd.hw,
4278 	[CLKID_RNG0]			= &g12a_rng0.hw,
4279 	[CLKID_UART0]			= &g12a_uart0.hw,
4280 	[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4281 	[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4282 	[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4283 	[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4284 	[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4285 	[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4286 	[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4287 	[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4288 	[CLKID_AUDIO]			= &g12a_audio.hw,
4289 	[CLKID_ETH]			= &g12a_eth_core.hw,
4290 	[CLKID_DEMUX]			= &g12a_demux.hw,
4291 	[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4292 	[CLKID_ADC]			= &g12a_adc.hw,
4293 	[CLKID_UART1]			= &g12a_uart1.hw,
4294 	[CLKID_G2D]			= &g12a_g2d.hw,
4295 	[CLKID_RESET]			= &g12a_reset.hw,
4296 	[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4297 	[CLKID_PARSER]			= &g12a_parser.hw,
4298 	[CLKID_USB]			= &g12a_usb_general.hw,
4299 	[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4300 	[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4301 	[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4302 	[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4303 	[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4304 	[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4305 	[CLKID_BT656]			= &g12a_bt656.hw,
4306 	[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4307 	[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4308 	[CLKID_UART2]			= &g12a_uart2.hw,
4309 	[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4310 	[CLKID_GIC]			= &g12a_gic.hw,
4311 	[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4312 	[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4313 	[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4314 	[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4315 	[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4316 	[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4317 	[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4318 	[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4319 	[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4320 	[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4321 	[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4322 	[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4323 	[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4324 	[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4325 	[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4326 	[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4327 	[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4328 	[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4329 	[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4330 	[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4331 	[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4332 	[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4333 	[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4334 	[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4335 	[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4336 	[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4337 	[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4338 	[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4339 	[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4340 	[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4341 	[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4342 	[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4343 	[CLKID_ENC480P]			= &g12a_enc480p.hw,
4344 	[CLKID_RNG1]			= &g12a_rng1.hw,
4345 	[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4346 	[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4347 	[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4348 	[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4349 	[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4350 	[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4351 	[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4352 	[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4353 	[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4354 	[CLKID_DMA]			= &g12a_dma.hw,
4355 	[CLKID_EFUSE]			= &g12a_efuse.hw,
4356 	[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4357 	[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4358 	[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4359 	[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4360 	[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4361 	[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4362 	[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4363 	[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4364 	[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4365 	[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4366 	[CLKID_VPU]			= &g12a_vpu.hw,
4367 	[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4368 	[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4369 	[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4370 	[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4371 	[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4372 	[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4373 	[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4374 	[CLKID_VAPB]			= &g12a_vapb.hw,
4375 	[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4376 	[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4377 	[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4378 	[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4379 	[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4380 	[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4381 	[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4382 	[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4383 	[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4384 	[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4385 	[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4386 	[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4387 	[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4388 	[CLKID_VCLK]			= &g12a_vclk.hw,
4389 	[CLKID_VCLK2]			= &g12a_vclk2.hw,
4390 	[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4391 	[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4392 	[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4393 	[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4394 	[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4395 	[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4396 	[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4397 	[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4398 	[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4399 	[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4400 	[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4401 	[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4402 	[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4403 	[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4404 	[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4405 	[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4406 	[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4407 	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4408 	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4409 	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4410 	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4411 	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4412 	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4413 	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4414 	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4415 	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4416 	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4417 	[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4418 	[CLKID_HDMI]			= &g12a_hdmi.hw,
4419 	[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4420 	[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4421 	[CLKID_MALI_0]			= &g12a_mali_0.hw,
4422 	[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4423 	[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4424 	[CLKID_MALI_1]			= &g12a_mali_1.hw,
4425 	[CLKID_MALI]			= &g12a_mali.hw,
4426 	[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4427 	[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4428 	[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4429 	[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4430 	[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4431 	[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4432 	[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4433 	[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4434 	[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4435 	[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4436 	[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4437 	[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
4438 	[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4439 	[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4440 	[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4441 	[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4442 	[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4443 	[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4444 	[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4445 	[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4446 	[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4447 	[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4448 	[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4449 	[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4450 	[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4451 	[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4452 	[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4453 	[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4454 	[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4455 	[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4456 	[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4457 	[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4458 	[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4459 	[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4460 	[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4461 	[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4462 	[CLKID_TS]			= &g12a_ts.hw,
4463 	[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4464 	[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4465 	[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4466 	[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4467 	[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4468 	[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4469 	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4470 	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4471 	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4472 };
4473 
4474 static struct clk_hw *g12b_hw_clks[] = {
4475 	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4476 	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4477 	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4478 	[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4479 	[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4480 	[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4481 	[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4482 	[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4483 	[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4484 	[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4485 	[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4486 	[CLKID_CLK81]			= &g12a_clk81.hw,
4487 	[CLKID_MPLL0]			= &g12a_mpll0.hw,
4488 	[CLKID_MPLL1]			= &g12a_mpll1.hw,
4489 	[CLKID_MPLL2]			= &g12a_mpll2.hw,
4490 	[CLKID_MPLL3]			= &g12a_mpll3.hw,
4491 	[CLKID_DDR]			= &g12a_ddr.hw,
4492 	[CLKID_DOS]			= &g12a_dos.hw,
4493 	[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4494 	[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4495 	[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4496 	[CLKID_ISA]			= &g12a_isa.hw,
4497 	[CLKID_PL301]			= &g12a_pl301.hw,
4498 	[CLKID_PERIPHS]			= &g12a_periphs.hw,
4499 	[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4500 	[CLKID_I2C]			= &g12a_i2c.hw,
4501 	[CLKID_SANA]			= &g12a_sana.hw,
4502 	[CLKID_SD]			= &g12a_sd.hw,
4503 	[CLKID_RNG0]			= &g12a_rng0.hw,
4504 	[CLKID_UART0]			= &g12a_uart0.hw,
4505 	[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4506 	[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4507 	[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4508 	[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4509 	[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4510 	[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4511 	[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4512 	[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4513 	[CLKID_AUDIO]			= &g12a_audio.hw,
4514 	[CLKID_ETH]			= &g12a_eth_core.hw,
4515 	[CLKID_DEMUX]			= &g12a_demux.hw,
4516 	[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4517 	[CLKID_ADC]			= &g12a_adc.hw,
4518 	[CLKID_UART1]			= &g12a_uart1.hw,
4519 	[CLKID_G2D]			= &g12a_g2d.hw,
4520 	[CLKID_RESET]			= &g12a_reset.hw,
4521 	[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4522 	[CLKID_PARSER]			= &g12a_parser.hw,
4523 	[CLKID_USB]			= &g12a_usb_general.hw,
4524 	[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4525 	[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4526 	[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4527 	[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4528 	[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4529 	[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4530 	[CLKID_BT656]			= &g12a_bt656.hw,
4531 	[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4532 	[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4533 	[CLKID_UART2]			= &g12a_uart2.hw,
4534 	[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4535 	[CLKID_GIC]			= &g12a_gic.hw,
4536 	[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4537 	[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4538 	[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4539 	[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4540 	[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4541 	[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4542 	[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4543 	[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4544 	[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4545 	[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4546 	[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4547 	[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4548 	[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4549 	[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4550 	[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4551 	[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4552 	[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4553 	[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4554 	[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4555 	[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4556 	[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4557 	[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4558 	[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4559 	[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4560 	[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4561 	[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4562 	[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4563 	[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4564 	[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4565 	[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4566 	[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4567 	[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4568 	[CLKID_ENC480P]			= &g12a_enc480p.hw,
4569 	[CLKID_RNG1]			= &g12a_rng1.hw,
4570 	[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4571 	[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4572 	[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4573 	[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4574 	[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4575 	[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4576 	[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4577 	[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4578 	[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4579 	[CLKID_DMA]			= &g12a_dma.hw,
4580 	[CLKID_EFUSE]			= &g12a_efuse.hw,
4581 	[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4582 	[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4583 	[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4584 	[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4585 	[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4586 	[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4587 	[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4588 	[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4589 	[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4590 	[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4591 	[CLKID_VPU]			= &g12a_vpu.hw,
4592 	[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4593 	[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4594 	[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4595 	[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4596 	[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4597 	[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4598 	[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4599 	[CLKID_VAPB]			= &g12a_vapb.hw,
4600 	[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4601 	[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4602 	[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4603 	[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4604 	[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4605 	[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4606 	[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4607 	[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4608 	[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4609 	[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4610 	[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4611 	[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4612 	[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4613 	[CLKID_VCLK]			= &g12a_vclk.hw,
4614 	[CLKID_VCLK2]			= &g12a_vclk2.hw,
4615 	[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4616 	[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4617 	[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4618 	[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4619 	[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4620 	[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4621 	[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4622 	[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4623 	[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4624 	[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4625 	[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4626 	[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4627 	[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4628 	[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4629 	[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4630 	[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4631 	[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4632 	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4633 	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4634 	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4635 	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4636 	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4637 	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4638 	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4639 	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4640 	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4641 	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4642 	[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4643 	[CLKID_HDMI]			= &g12a_hdmi.hw,
4644 	[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4645 	[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4646 	[CLKID_MALI_0]			= &g12a_mali_0.hw,
4647 	[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4648 	[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4649 	[CLKID_MALI_1]			= &g12a_mali_1.hw,
4650 	[CLKID_MALI]			= &g12a_mali.hw,
4651 	[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4652 	[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4653 	[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4654 	[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4655 	[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4656 	[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4657 	[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4658 	[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4659 	[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4660 	[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4661 	[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4662 	[CLKID_CPU_CLK]			= &g12b_cpu_clk.hw,
4663 	[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4664 	[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4665 	[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4666 	[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4667 	[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4668 	[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4669 	[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4670 	[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4671 	[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4672 	[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4673 	[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4674 	[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4675 	[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4676 	[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4677 	[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4678 	[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4679 	[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4680 	[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4681 	[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4682 	[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4683 	[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4684 	[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4685 	[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4686 	[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4687 	[CLKID_TS]			= &g12a_ts.hw,
4688 	[CLKID_SYS1_PLL_DCO]		= &g12b_sys1_pll_dco.hw,
4689 	[CLKID_SYS1_PLL]		= &g12b_sys1_pll.hw,
4690 	[CLKID_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
4691 	[CLKID_SYS1_PLL_DIV16]		= &g12b_sys1_pll_div16.hw,
4692 	[CLKID_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
4693 	[CLKID_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
4694 	[CLKID_CPUB_CLK_DYN0]		= &g12b_cpub_clk_postmux0.hw,
4695 	[CLKID_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
4696 	[CLKID_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
4697 	[CLKID_CPUB_CLK_DYN1]		= &g12b_cpub_clk_postmux1.hw,
4698 	[CLKID_CPUB_CLK_DYN]		= &g12b_cpub_clk_dyn.hw,
4699 	[CLKID_CPUB_CLK]		= &g12b_cpub_clk.hw,
4700 	[CLKID_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
4701 	[CLKID_CPUB_CLK_DIV16]		= &g12b_cpub_clk_div16.hw,
4702 	[CLKID_CPUB_CLK_DIV2]		= &g12b_cpub_clk_div2.hw,
4703 	[CLKID_CPUB_CLK_DIV3]		= &g12b_cpub_clk_div3.hw,
4704 	[CLKID_CPUB_CLK_DIV4]		= &g12b_cpub_clk_div4.hw,
4705 	[CLKID_CPUB_CLK_DIV5]		= &g12b_cpub_clk_div5.hw,
4706 	[CLKID_CPUB_CLK_DIV6]		= &g12b_cpub_clk_div6.hw,
4707 	[CLKID_CPUB_CLK_DIV7]		= &g12b_cpub_clk_div7.hw,
4708 	[CLKID_CPUB_CLK_DIV8]		= &g12b_cpub_clk_div8.hw,
4709 	[CLKID_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
4710 	[CLKID_CPUB_CLK_APB]		= &g12b_cpub_clk_apb.hw,
4711 	[CLKID_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
4712 	[CLKID_CPUB_CLK_ATB]		= &g12b_cpub_clk_atb.hw,
4713 	[CLKID_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
4714 	[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,
4715 	[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
4716 	[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,
4717 	[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4718 	[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4719 	[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4720 	[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4721 	[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4722 	[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4723 	[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
4724 	[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
4725 	[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
4726 	[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
4727 	[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
4728 	[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
4729 	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4730 	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4731 	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4732 };
4733 
4734 static struct clk_hw *sm1_hw_clks[] = {
4735 	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4736 	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4737 	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4738 	[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4739 	[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4740 	[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4741 	[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4742 	[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4743 	[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4744 	[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4745 	[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4746 	[CLKID_CLK81]			= &g12a_clk81.hw,
4747 	[CLKID_MPLL0]			= &g12a_mpll0.hw,
4748 	[CLKID_MPLL1]			= &g12a_mpll1.hw,
4749 	[CLKID_MPLL2]			= &g12a_mpll2.hw,
4750 	[CLKID_MPLL3]			= &g12a_mpll3.hw,
4751 	[CLKID_DDR]			= &g12a_ddr.hw,
4752 	[CLKID_DOS]			= &g12a_dos.hw,
4753 	[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4754 	[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4755 	[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4756 	[CLKID_ISA]			= &g12a_isa.hw,
4757 	[CLKID_PL301]			= &g12a_pl301.hw,
4758 	[CLKID_PERIPHS]			= &g12a_periphs.hw,
4759 	[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4760 	[CLKID_I2C]			= &g12a_i2c.hw,
4761 	[CLKID_SANA]			= &g12a_sana.hw,
4762 	[CLKID_SD]			= &g12a_sd.hw,
4763 	[CLKID_RNG0]			= &g12a_rng0.hw,
4764 	[CLKID_UART0]			= &g12a_uart0.hw,
4765 	[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4766 	[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4767 	[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4768 	[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4769 	[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4770 	[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4771 	[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4772 	[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4773 	[CLKID_AUDIO]			= &g12a_audio.hw,
4774 	[CLKID_ETH]			= &g12a_eth_core.hw,
4775 	[CLKID_DEMUX]			= &g12a_demux.hw,
4776 	[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4777 	[CLKID_ADC]			= &g12a_adc.hw,
4778 	[CLKID_UART1]			= &g12a_uart1.hw,
4779 	[CLKID_G2D]			= &g12a_g2d.hw,
4780 	[CLKID_RESET]			= &g12a_reset.hw,
4781 	[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4782 	[CLKID_PARSER]			= &g12a_parser.hw,
4783 	[CLKID_USB]			= &g12a_usb_general.hw,
4784 	[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4785 	[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4786 	[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4787 	[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4788 	[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4789 	[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4790 	[CLKID_BT656]			= &g12a_bt656.hw,
4791 	[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4792 	[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4793 	[CLKID_UART2]			= &g12a_uart2.hw,
4794 	[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4795 	[CLKID_GIC]			= &g12a_gic.hw,
4796 	[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4797 	[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4798 	[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4799 	[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4800 	[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4801 	[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4802 	[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4803 	[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4804 	[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4805 	[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4806 	[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4807 	[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4808 	[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4809 	[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4810 	[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4811 	[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4812 	[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4813 	[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4814 	[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4815 	[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4816 	[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4817 	[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4818 	[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4819 	[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4820 	[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4821 	[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4822 	[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4823 	[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4824 	[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4825 	[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4826 	[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4827 	[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4828 	[CLKID_ENC480P]			= &g12a_enc480p.hw,
4829 	[CLKID_RNG1]			= &g12a_rng1.hw,
4830 	[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4831 	[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4832 	[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4833 	[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4834 	[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4835 	[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4836 	[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4837 	[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4838 	[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4839 	[CLKID_DMA]			= &g12a_dma.hw,
4840 	[CLKID_EFUSE]			= &g12a_efuse.hw,
4841 	[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4842 	[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4843 	[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4844 	[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4845 	[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4846 	[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4847 	[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4848 	[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4849 	[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4850 	[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4851 	[CLKID_VPU]			= &g12a_vpu.hw,
4852 	[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4853 	[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4854 	[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4855 	[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4856 	[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4857 	[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4858 	[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4859 	[CLKID_VAPB]			= &g12a_vapb.hw,
4860 	[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4861 	[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4862 	[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4863 	[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4864 	[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4865 	[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4866 	[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4867 	[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4868 	[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4869 	[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4870 	[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4871 	[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4872 	[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4873 	[CLKID_VCLK]			= &g12a_vclk.hw,
4874 	[CLKID_VCLK2]			= &g12a_vclk2.hw,
4875 	[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4876 	[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4877 	[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4878 	[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4879 	[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4880 	[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4881 	[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4882 	[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4883 	[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4884 	[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4885 	[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4886 	[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4887 	[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4888 	[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4889 	[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4890 	[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4891 	[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4892 	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4893 	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4894 	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4895 	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4896 	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4897 	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4898 	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4899 	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4900 	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4901 	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4902 	[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4903 	[CLKID_HDMI]			= &g12a_hdmi.hw,
4904 	[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4905 	[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4906 	[CLKID_MALI_0]			= &g12a_mali_0.hw,
4907 	[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4908 	[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4909 	[CLKID_MALI_1]			= &g12a_mali_1.hw,
4910 	[CLKID_MALI]			= &g12a_mali.hw,
4911 	[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4912 	[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4913 	[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4914 	[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4915 	[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4916 	[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4917 	[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4918 	[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4919 	[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4920 	[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4921 	[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4922 	[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
4923 	[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4924 	[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4925 	[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4926 	[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4927 	[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4928 	[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4929 	[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4930 	[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4931 	[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4932 	[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4933 	[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4934 	[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4935 	[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4936 	[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4937 	[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4938 	[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4939 	[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4940 	[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4941 	[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4942 	[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4943 	[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4944 	[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4945 	[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4946 	[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4947 	[CLKID_TS]			= &g12a_ts.hw,
4948 	[CLKID_GP1_PLL_DCO]		= &sm1_gp1_pll_dco.hw,
4949 	[CLKID_GP1_PLL]			= &sm1_gp1_pll.hw,
4950 	[CLKID_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
4951 	[CLKID_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
4952 	[CLKID_DSU_CLK_DYN0]		= &sm1_dsu_clk_mux0_div.hw,
4953 	[CLKID_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
4954 	[CLKID_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
4955 	[CLKID_DSU_CLK_DYN1]		= &sm1_dsu_clk_postmux1.hw,
4956 	[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,
4957 	[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,
4958 	[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,
4959 	[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,
4960 	[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,
4961 	[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,
4962 	[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4963 	[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4964 	[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4965 	[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4966 	[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4967 	[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4968 	[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
4969 	[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
4970 	[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
4971 	[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
4972 	[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
4973 	[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
4974 	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4975 	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4976 	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4977 };
4978 
4979 /* Convenience table to populate regmap in .probe */
4980 static struct clk_regmap *const g12a_clk_regmaps[] = {
4981 	&g12a_clk81,
4982 	&g12a_dos,
4983 	&g12a_ddr,
4984 	&g12a_audio_locker,
4985 	&g12a_mipi_dsi_host,
4986 	&g12a_eth_phy,
4987 	&g12a_isa,
4988 	&g12a_pl301,
4989 	&g12a_periphs,
4990 	&g12a_spicc_0,
4991 	&g12a_i2c,
4992 	&g12a_sana,
4993 	&g12a_sd,
4994 	&g12a_rng0,
4995 	&g12a_uart0,
4996 	&g12a_spicc_1,
4997 	&g12a_hiu_reg,
4998 	&g12a_mipi_dsi_phy,
4999 	&g12a_assist_misc,
5000 	&g12a_emmc_a,
5001 	&g12a_emmc_b,
5002 	&g12a_emmc_c,
5003 	&g12a_audio_codec,
5004 	&g12a_audio,
5005 	&g12a_eth_core,
5006 	&g12a_demux,
5007 	&g12a_audio_ififo,
5008 	&g12a_adc,
5009 	&g12a_uart1,
5010 	&g12a_g2d,
5011 	&g12a_reset,
5012 	&g12a_pcie_comb,
5013 	&g12a_parser,
5014 	&g12a_usb_general,
5015 	&g12a_pcie_phy,
5016 	&g12a_ahb_arb0,
5017 	&g12a_ahb_data_bus,
5018 	&g12a_ahb_ctrl_bus,
5019 	&g12a_htx_hdcp22,
5020 	&g12a_htx_pclk,
5021 	&g12a_bt656,
5022 	&g12a_usb1_to_ddr,
5023 	&g12a_mmc_pclk,
5024 	&g12a_uart2,
5025 	&g12a_vpu_intr,
5026 	&g12a_gic,
5027 	&g12a_sd_emmc_a_clk0,
5028 	&g12a_sd_emmc_b_clk0,
5029 	&g12a_sd_emmc_c_clk0,
5030 	&g12a_mpeg_clk_div,
5031 	&g12a_sd_emmc_a_clk0_div,
5032 	&g12a_sd_emmc_b_clk0_div,
5033 	&g12a_sd_emmc_c_clk0_div,
5034 	&g12a_mpeg_clk_sel,
5035 	&g12a_sd_emmc_a_clk0_sel,
5036 	&g12a_sd_emmc_b_clk0_sel,
5037 	&g12a_sd_emmc_c_clk0_sel,
5038 	&g12a_mpll0,
5039 	&g12a_mpll1,
5040 	&g12a_mpll2,
5041 	&g12a_mpll3,
5042 	&g12a_mpll0_div,
5043 	&g12a_mpll1_div,
5044 	&g12a_mpll2_div,
5045 	&g12a_mpll3_div,
5046 	&g12a_fixed_pll,
5047 	&g12a_sys_pll,
5048 	&g12a_gp0_pll,
5049 	&g12a_hifi_pll,
5050 	&g12a_vclk2_venci0,
5051 	&g12a_vclk2_venci1,
5052 	&g12a_vclk2_vencp0,
5053 	&g12a_vclk2_vencp1,
5054 	&g12a_vclk2_venct0,
5055 	&g12a_vclk2_venct1,
5056 	&g12a_vclk2_other,
5057 	&g12a_vclk2_enci,
5058 	&g12a_vclk2_encp,
5059 	&g12a_dac_clk,
5060 	&g12a_aoclk_gate,
5061 	&g12a_iec958_gate,
5062 	&g12a_enc480p,
5063 	&g12a_rng1,
5064 	&g12a_vclk2_enct,
5065 	&g12a_vclk2_encl,
5066 	&g12a_vclk2_venclmmc,
5067 	&g12a_vclk2_vencl,
5068 	&g12a_vclk2_other1,
5069 	&g12a_fixed_pll_dco,
5070 	&g12a_sys_pll_dco,
5071 	&g12a_gp0_pll_dco,
5072 	&g12a_hifi_pll_dco,
5073 	&g12a_fclk_div2,
5074 	&g12a_fclk_div3,
5075 	&g12a_fclk_div4,
5076 	&g12a_fclk_div5,
5077 	&g12a_fclk_div7,
5078 	&g12a_fclk_div2p5,
5079 	&g12a_dma,
5080 	&g12a_efuse,
5081 	&g12a_rom_boot,
5082 	&g12a_reset_sec,
5083 	&g12a_sec_ahb_apb3,
5084 	&g12a_vpu_0_sel,
5085 	&g12a_vpu_0_div,
5086 	&g12a_vpu_0,
5087 	&g12a_vpu_1_sel,
5088 	&g12a_vpu_1_div,
5089 	&g12a_vpu_1,
5090 	&g12a_vpu,
5091 	&g12a_vapb_0_sel,
5092 	&g12a_vapb_0_div,
5093 	&g12a_vapb_0,
5094 	&g12a_vapb_1_sel,
5095 	&g12a_vapb_1_div,
5096 	&g12a_vapb_1,
5097 	&g12a_vapb_sel,
5098 	&g12a_vapb,
5099 	&g12a_hdmi_pll_dco,
5100 	&g12a_hdmi_pll_od,
5101 	&g12a_hdmi_pll_od2,
5102 	&g12a_hdmi_pll,
5103 	&g12a_vid_pll_div,
5104 	&g12a_vid_pll_sel,
5105 	&g12a_vid_pll,
5106 	&g12a_vclk_sel,
5107 	&g12a_vclk2_sel,
5108 	&g12a_vclk_input,
5109 	&g12a_vclk2_input,
5110 	&g12a_vclk_div,
5111 	&g12a_vclk2_div,
5112 	&g12a_vclk,
5113 	&g12a_vclk2,
5114 	&g12a_vclk_div1,
5115 	&g12a_vclk_div2_en,
5116 	&g12a_vclk_div4_en,
5117 	&g12a_vclk_div6_en,
5118 	&g12a_vclk_div12_en,
5119 	&g12a_vclk2_div1,
5120 	&g12a_vclk2_div2_en,
5121 	&g12a_vclk2_div4_en,
5122 	&g12a_vclk2_div6_en,
5123 	&g12a_vclk2_div12_en,
5124 	&g12a_cts_enci_sel,
5125 	&g12a_cts_encp_sel,
5126 	&g12a_cts_vdac_sel,
5127 	&g12a_hdmi_tx_sel,
5128 	&g12a_cts_enci,
5129 	&g12a_cts_encp,
5130 	&g12a_cts_vdac,
5131 	&g12a_hdmi_tx,
5132 	&g12a_hdmi_sel,
5133 	&g12a_hdmi_div,
5134 	&g12a_hdmi,
5135 	&g12a_mali_0_sel,
5136 	&g12a_mali_0_div,
5137 	&g12a_mali_0,
5138 	&g12a_mali_1_sel,
5139 	&g12a_mali_1_div,
5140 	&g12a_mali_1,
5141 	&g12a_mali,
5142 	&g12a_mpll_50m,
5143 	&g12a_sys_pll_div16_en,
5144 	&g12a_cpu_clk_premux0,
5145 	&g12a_cpu_clk_mux0_div,
5146 	&g12a_cpu_clk_postmux0,
5147 	&g12a_cpu_clk_premux1,
5148 	&g12a_cpu_clk_mux1_div,
5149 	&g12a_cpu_clk_postmux1,
5150 	&g12a_cpu_clk_dyn,
5151 	&g12a_cpu_clk,
5152 	&g12a_cpu_clk_div16_en,
5153 	&g12a_cpu_clk_apb_div,
5154 	&g12a_cpu_clk_apb,
5155 	&g12a_cpu_clk_atb_div,
5156 	&g12a_cpu_clk_atb,
5157 	&g12a_cpu_clk_axi_div,
5158 	&g12a_cpu_clk_axi,
5159 	&g12a_cpu_clk_trace_div,
5160 	&g12a_cpu_clk_trace,
5161 	&g12a_pcie_pll_od,
5162 	&g12a_pcie_pll_dco,
5163 	&g12a_vdec_1_sel,
5164 	&g12a_vdec_1_div,
5165 	&g12a_vdec_1,
5166 	&g12a_vdec_hevc_sel,
5167 	&g12a_vdec_hevc_div,
5168 	&g12a_vdec_hevc,
5169 	&g12a_vdec_hevcf_sel,
5170 	&g12a_vdec_hevcf_div,
5171 	&g12a_vdec_hevcf,
5172 	&g12a_ts_div,
5173 	&g12a_ts,
5174 	&g12b_cpu_clk,
5175 	&g12b_sys1_pll_dco,
5176 	&g12b_sys1_pll,
5177 	&g12b_sys1_pll_div16_en,
5178 	&g12b_cpub_clk_premux0,
5179 	&g12b_cpub_clk_mux0_div,
5180 	&g12b_cpub_clk_postmux0,
5181 	&g12b_cpub_clk_premux1,
5182 	&g12b_cpub_clk_mux1_div,
5183 	&g12b_cpub_clk_postmux1,
5184 	&g12b_cpub_clk_dyn,
5185 	&g12b_cpub_clk,
5186 	&g12b_cpub_clk_div16_en,
5187 	&g12b_cpub_clk_apb_sel,
5188 	&g12b_cpub_clk_apb,
5189 	&g12b_cpub_clk_atb_sel,
5190 	&g12b_cpub_clk_atb,
5191 	&g12b_cpub_clk_axi_sel,
5192 	&g12b_cpub_clk_axi,
5193 	&g12b_cpub_clk_trace_sel,
5194 	&g12b_cpub_clk_trace,
5195 	&sm1_gp1_pll_dco,
5196 	&sm1_gp1_pll,
5197 	&sm1_dsu_clk_premux0,
5198 	&sm1_dsu_clk_premux1,
5199 	&sm1_dsu_clk_mux0_div,
5200 	&sm1_dsu_clk_postmux0,
5201 	&sm1_dsu_clk_mux1_div,
5202 	&sm1_dsu_clk_postmux1,
5203 	&sm1_dsu_clk_dyn,
5204 	&sm1_dsu_final_clk,
5205 	&sm1_dsu_clk,
5206 	&sm1_cpu1_clk,
5207 	&sm1_cpu2_clk,
5208 	&sm1_cpu3_clk,
5209 	&g12a_spicc0_sclk_sel,
5210 	&g12a_spicc0_sclk_div,
5211 	&g12a_spicc0_sclk,
5212 	&g12a_spicc1_sclk_sel,
5213 	&g12a_spicc1_sclk_div,
5214 	&g12a_spicc1_sclk,
5215 	&sm1_nna_axi_clk_sel,
5216 	&sm1_nna_axi_clk_div,
5217 	&sm1_nna_axi_clk,
5218 	&sm1_nna_core_clk_sel,
5219 	&sm1_nna_core_clk_div,
5220 	&sm1_nna_core_clk,
5221 	&g12a_mipi_dsi_pxclk_sel,
5222 	&g12a_mipi_dsi_pxclk_div,
5223 	&g12a_mipi_dsi_pxclk,
5224 };
5225 
5226 static const struct reg_sequence g12a_init_regs[] = {
5227 	{ .reg = HHI_MPLL_CNTL0,	.def = 0x00000543 },
5228 };
5229 
5230 #define DVFS_CON_ID "dvfs"
5231 
meson_g12a_dvfs_setup_common(struct device * dev,struct clk_hw ** hws)5232 static int meson_g12a_dvfs_setup_common(struct device *dev,
5233 					struct clk_hw **hws)
5234 {
5235 	struct clk *notifier_clk;
5236 	struct clk_hw *xtal;
5237 	int ret;
5238 
5239 	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5240 
5241 	/* Setup clock notifier for cpu_clk_postmux0 */
5242 	g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
5243 	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,
5244 					   DVFS_CON_ID);
5245 	ret = devm_clk_notifier_register(dev, notifier_clk,
5246 					 &g12a_cpu_clk_postmux0_nb_data.nb);
5247 	if (ret) {
5248 		dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n");
5249 		return ret;
5250 	}
5251 
5252 	/* Setup clock notifier for cpu_clk_dyn mux */
5253 	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,
5254 					   DVFS_CON_ID);
5255 	ret = devm_clk_notifier_register(dev, notifier_clk,
5256 					 &g12a_cpu_clk_mux_nb);
5257 	if (ret) {
5258 		dev_err(dev, "failed to register the cpu_clk_dyn notifier\n");
5259 		return ret;
5260 	}
5261 
5262 	return 0;
5263 }
5264 
meson_g12b_dvfs_setup(struct platform_device * pdev)5265 static int meson_g12b_dvfs_setup(struct platform_device *pdev)
5266 {
5267 	struct clk_hw **hws = g12b_hw_clks;
5268 	struct device *dev = &pdev->dev;
5269 	struct clk *notifier_clk;
5270 	struct clk_hw *xtal;
5271 	int ret;
5272 
5273 	ret = meson_g12a_dvfs_setup_common(dev, hws);
5274 	if (ret)
5275 		return ret;
5276 
5277 	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5278 
5279 	/* Setup clock notifier for cpu_clk mux */
5280 	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
5281 					   DVFS_CON_ID);
5282 	ret = devm_clk_notifier_register(dev, notifier_clk,
5283 					 &g12a_cpu_clk_mux_nb);
5284 	if (ret) {
5285 		dev_err(dev, "failed to register the cpu_clk notifier\n");
5286 		return ret;
5287 	}
5288 
5289 	/* Setup clock notifier for sys1_pll */
5290 	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,
5291 					   DVFS_CON_ID);
5292 	ret = devm_clk_notifier_register(dev, notifier_clk,
5293 					 &g12b_cpu_clk_sys1_pll_nb_data.nb);
5294 	if (ret) {
5295 		dev_err(dev, "failed to register the sys1_pll notifier\n");
5296 		return ret;
5297 	}
5298 
5299 	/* Add notifiers for the second CPU cluster */
5300 
5301 	/* Setup clock notifier for cpub_clk_postmux0 */
5302 	g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
5303 	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,
5304 					   DVFS_CON_ID);
5305 	ret = devm_clk_notifier_register(dev, notifier_clk,
5306 					 &g12b_cpub_clk_postmux0_nb_data.nb);
5307 	if (ret) {
5308 		dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n");
5309 		return ret;
5310 	}
5311 
5312 	/* Setup clock notifier for cpub_clk_dyn mux */
5313 	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");
5314 	ret = devm_clk_notifier_register(dev, notifier_clk,
5315 					 &g12a_cpu_clk_mux_nb);
5316 	if (ret) {
5317 		dev_err(dev, "failed to register the cpub_clk_dyn notifier\n");
5318 		return ret;
5319 	}
5320 
5321 	/* Setup clock notifier for cpub_clk mux */
5322 	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);
5323 	ret = devm_clk_notifier_register(dev, notifier_clk,
5324 					 &g12a_cpu_clk_mux_nb);
5325 	if (ret) {
5326 		dev_err(dev, "failed to register the cpub_clk notifier\n");
5327 		return ret;
5328 	}
5329 
5330 	/* Setup clock notifier for sys_pll */
5331 	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5332 	ret = devm_clk_notifier_register(dev, notifier_clk,
5333 					 &g12b_cpub_clk_sys_pll_nb_data.nb);
5334 	if (ret) {
5335 		dev_err(dev, "failed to register the sys_pll notifier\n");
5336 		return ret;
5337 	}
5338 
5339 	return 0;
5340 }
5341 
meson_g12a_dvfs_setup(struct platform_device * pdev)5342 static int meson_g12a_dvfs_setup(struct platform_device *pdev)
5343 {
5344 	struct clk_hw **hws = g12a_hw_clks;
5345 	struct device *dev = &pdev->dev;
5346 	struct clk *notifier_clk;
5347 	int ret;
5348 
5349 	ret = meson_g12a_dvfs_setup_common(dev, hws);
5350 	if (ret)
5351 		return ret;
5352 
5353 	/* Setup clock notifier for cpu_clk mux */
5354 	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);
5355 	ret = devm_clk_notifier_register(dev, notifier_clk,
5356 				    &g12a_cpu_clk_mux_nb);
5357 	if (ret) {
5358 		dev_err(dev, "failed to register the cpu_clk notifier\n");
5359 		return ret;
5360 	}
5361 
5362 	/* Setup clock notifier for sys_pll */
5363 	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5364 	ret = devm_clk_notifier_register(dev, notifier_clk,
5365 					 &g12a_sys_pll_nb_data.nb);
5366 	if (ret) {
5367 		dev_err(dev, "failed to register the sys_pll notifier\n");
5368 		return ret;
5369 	}
5370 
5371 	return 0;
5372 }
5373 
5374 struct meson_g12a_data {
5375 	const struct meson_eeclkc_data eeclkc_data;
5376 	int (*dvfs_setup)(struct platform_device *pdev);
5377 };
5378 
meson_g12a_probe(struct platform_device * pdev)5379 static int meson_g12a_probe(struct platform_device *pdev)
5380 {
5381 	const struct meson_eeclkc_data *eeclkc_data;
5382 	const struct meson_g12a_data *g12a_data;
5383 	int ret;
5384 
5385 	eeclkc_data = of_device_get_match_data(&pdev->dev);
5386 	if (!eeclkc_data)
5387 		return -EINVAL;
5388 
5389 	ret = meson_eeclkc_probe(pdev);
5390 	if (ret)
5391 		return ret;
5392 
5393 	g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5394 				 eeclkc_data);
5395 
5396 	if (g12a_data->dvfs_setup)
5397 		return g12a_data->dvfs_setup(pdev);
5398 
5399 	return 0;
5400 }
5401 
5402 static const struct meson_g12a_data g12a_clkc_data = {
5403 	.eeclkc_data = {
5404 		.regmap_clks = g12a_clk_regmaps,
5405 		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5406 		.hw_clks = {
5407 			.hws = g12a_hw_clks,
5408 			.num = ARRAY_SIZE(g12a_hw_clks),
5409 		},
5410 		.init_regs = g12a_init_regs,
5411 		.init_count = ARRAY_SIZE(g12a_init_regs),
5412 	},
5413 	.dvfs_setup = meson_g12a_dvfs_setup,
5414 };
5415 
5416 static const struct meson_g12a_data g12b_clkc_data = {
5417 	.eeclkc_data = {
5418 		.regmap_clks = g12a_clk_regmaps,
5419 		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5420 		.hw_clks = {
5421 			.hws = g12b_hw_clks,
5422 			.num = ARRAY_SIZE(g12b_hw_clks),
5423 		},
5424 	},
5425 	.dvfs_setup = meson_g12b_dvfs_setup,
5426 };
5427 
5428 static const struct meson_g12a_data sm1_clkc_data = {
5429 	.eeclkc_data = {
5430 		.regmap_clks = g12a_clk_regmaps,
5431 		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5432 		.hw_clks = {
5433 			.hws = sm1_hw_clks,
5434 			.num = ARRAY_SIZE(sm1_hw_clks),
5435 		},
5436 	},
5437 	.dvfs_setup = meson_g12a_dvfs_setup,
5438 };
5439 
5440 static const struct of_device_id clkc_match_table[] = {
5441 	{
5442 		.compatible = "amlogic,g12a-clkc",
5443 		.data = &g12a_clkc_data.eeclkc_data
5444 	},
5445 	{
5446 		.compatible = "amlogic,g12b-clkc",
5447 		.data = &g12b_clkc_data.eeclkc_data
5448 	},
5449 	{
5450 		.compatible = "amlogic,sm1-clkc",
5451 		.data = &sm1_clkc_data.eeclkc_data
5452 	},
5453 	{}
5454 };
5455 MODULE_DEVICE_TABLE(of, clkc_match_table);
5456 
5457 static struct platform_driver g12a_driver = {
5458 	.probe		= meson_g12a_probe,
5459 	.driver		= {
5460 		.name	= "g12a-clkc",
5461 		.of_match_table = clkc_match_table,
5462 	},
5463 };
5464 
5465 module_platform_driver(g12a_driver);
5466 MODULE_LICENSE("GPL v2");
5467