1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2012 Samsung Electronics. 4 * Abhilash Kesavan <a.kesavan@samsung.com> 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <asm/gpio.h> 10 #include <asm/arch/pinmux.h> 11 #include <asm/arch/sromc.h> 12 exynos5_uart_config(int peripheral)13 static void exynos5_uart_config(int peripheral) 14 { 15 int i, start, count; 16 17 switch (peripheral) { 18 case PERIPH_ID_UART0: 19 start = EXYNOS5_GPIO_A00; 20 count = 4; 21 break; 22 case PERIPH_ID_UART1: 23 start = EXYNOS5_GPIO_D00; 24 count = 4; 25 break; 26 case PERIPH_ID_UART2: 27 start = EXYNOS5_GPIO_A10; 28 count = 4; 29 break; 30 case PERIPH_ID_UART3: 31 start = EXYNOS5_GPIO_A14; 32 count = 2; 33 break; 34 default: 35 debug("%s: invalid peripheral %d", __func__, peripheral); 36 return; 37 } 38 for (i = start; i < start + count; i++) { 39 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 40 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 41 } 42 } 43 exynos5420_uart_config(int peripheral)44 static void exynos5420_uart_config(int peripheral) 45 { 46 int i, start, count; 47 48 switch (peripheral) { 49 case PERIPH_ID_UART0: 50 start = EXYNOS5420_GPIO_A00; 51 count = 4; 52 break; 53 case PERIPH_ID_UART1: 54 start = EXYNOS5420_GPIO_A04; 55 count = 4; 56 break; 57 case PERIPH_ID_UART2: 58 start = EXYNOS5420_GPIO_A10; 59 count = 4; 60 break; 61 case PERIPH_ID_UART3: 62 start = EXYNOS5420_GPIO_A14; 63 count = 2; 64 break; 65 default: 66 debug("%s: invalid peripheral %d", __func__, peripheral); 67 return; 68 } 69 70 for (i = start; i < start + count; i++) { 71 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 72 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 73 } 74 } 75 exynos5_mmc_config(int peripheral,int flags)76 static int exynos5_mmc_config(int peripheral, int flags) 77 { 78 int i, start, start_ext, gpio_func = 0; 79 80 switch (peripheral) { 81 case PERIPH_ID_SDMMC0: 82 start = EXYNOS5_GPIO_C00; 83 start_ext = EXYNOS5_GPIO_C10; 84 gpio_func = S5P_GPIO_FUNC(0x2); 85 break; 86 case PERIPH_ID_SDMMC1: 87 start = EXYNOS5_GPIO_C20; 88 start_ext = 0; 89 break; 90 case PERIPH_ID_SDMMC2: 91 start = EXYNOS5_GPIO_C30; 92 start_ext = EXYNOS5_GPIO_C43; 93 gpio_func = S5P_GPIO_FUNC(0x3); 94 break; 95 case PERIPH_ID_SDMMC3: 96 start = EXYNOS5_GPIO_C40; 97 start_ext = 0; 98 break; 99 default: 100 debug("%s: invalid peripheral %d", __func__, peripheral); 101 return -1; 102 } 103 if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { 104 debug("SDMMC device %d does not support 8bit mode", 105 peripheral); 106 return -1; 107 } 108 if (flags & PINMUX_FLAG_8BIT_MODE) { 109 for (i = start_ext; i <= (start_ext + 3); i++) { 110 gpio_cfg_pin(i, gpio_func); 111 gpio_set_pull(i, S5P_GPIO_PULL_UP); 112 gpio_set_drv(i, S5P_GPIO_DRV_4X); 113 } 114 } 115 for (i = start; i < (start + 2); i++) { 116 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 117 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 118 gpio_set_drv(i, S5P_GPIO_DRV_4X); 119 } 120 for (i = (start + 3); i <= (start + 6); i++) { 121 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 122 gpio_set_pull(i, S5P_GPIO_PULL_UP); 123 gpio_set_drv(i, S5P_GPIO_DRV_4X); 124 } 125 126 return 0; 127 } 128 exynos5420_mmc_config(int peripheral,int flags)129 static int exynos5420_mmc_config(int peripheral, int flags) 130 { 131 int i, start = 0, start_ext = 0; 132 133 switch (peripheral) { 134 case PERIPH_ID_SDMMC0: 135 start = EXYNOS5420_GPIO_C00; 136 start_ext = EXYNOS5420_GPIO_C30; 137 break; 138 case PERIPH_ID_SDMMC1: 139 start = EXYNOS5420_GPIO_C10; 140 start_ext = EXYNOS5420_GPIO_D14; 141 break; 142 case PERIPH_ID_SDMMC2: 143 start = EXYNOS5420_GPIO_C20; 144 start_ext = 0; 145 break; 146 default: 147 start = 0; 148 debug("%s: invalid peripheral %d", __func__, peripheral); 149 return -1; 150 } 151 152 if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { 153 debug("SDMMC device %d does not support 8bit mode", 154 peripheral); 155 return -1; 156 } 157 158 if (flags & PINMUX_FLAG_8BIT_MODE) { 159 for (i = start_ext; i <= (start_ext + 3); i++) { 160 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 161 gpio_set_pull(i, S5P_GPIO_PULL_UP); 162 gpio_set_drv(i, S5P_GPIO_DRV_4X); 163 } 164 } 165 166 for (i = start; i < (start + 3); i++) { 167 /* 168 * MMC0 is intended to be used for eMMC. The 169 * card detect pin is used as a VDDEN signal to 170 * power on the eMMC. The 5420 iROM makes 171 * this same assumption. 172 */ 173 if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { 174 #ifndef CONFIG_SPL_BUILD 175 gpio_request(i, "sdmmc0_vdden"); 176 #endif 177 gpio_set_value(i, 1); 178 gpio_cfg_pin(i, S5P_GPIO_OUTPUT); 179 } else { 180 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 181 } 182 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 183 gpio_set_drv(i, S5P_GPIO_DRV_4X); 184 } 185 186 for (i = (start + 3); i <= (start + 6); i++) { 187 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 188 gpio_set_pull(i, S5P_GPIO_PULL_UP); 189 gpio_set_drv(i, S5P_GPIO_DRV_4X); 190 } 191 192 return 0; 193 } 194 exynos5_sromc_config(int flags)195 static void exynos5_sromc_config(int flags) 196 { 197 int i; 198 199 /* 200 * SROM:CS1 and EBI 201 * 202 * GPY0[0] SROM_CSn[0] 203 * GPY0[1] SROM_CSn[1](2) 204 * GPY0[2] SROM_CSn[2] 205 * GPY0[3] SROM_CSn[3] 206 * GPY0[4] EBI_OEn(2) 207 * GPY0[5] EBI_EEn(2) 208 * 209 * GPY1[0] EBI_BEn[0](2) 210 * GPY1[1] EBI_BEn[1](2) 211 * GPY1[2] SROM_WAIT(2) 212 * GPY1[3] EBI_DATA_RDn(2) 213 */ 214 gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK), 215 S5P_GPIO_FUNC(2)); 216 gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2)); 217 gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2)); 218 219 for (i = 0; i < 4; i++) 220 gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2)); 221 222 /* 223 * EBI: 8 Addrss Lines 224 * 225 * GPY3[0] EBI_ADDR[0](2) 226 * GPY3[1] EBI_ADDR[1](2) 227 * GPY3[2] EBI_ADDR[2](2) 228 * GPY3[3] EBI_ADDR[3](2) 229 * GPY3[4] EBI_ADDR[4](2) 230 * GPY3[5] EBI_ADDR[5](2) 231 * GPY3[6] EBI_ADDR[6](2) 232 * GPY3[7] EBI_ADDR[7](2) 233 * 234 * EBI: 16 Data Lines 235 * 236 * GPY5[0] EBI_DATA[0](2) 237 * GPY5[1] EBI_DATA[1](2) 238 * GPY5[2] EBI_DATA[2](2) 239 * GPY5[3] EBI_DATA[3](2) 240 * GPY5[4] EBI_DATA[4](2) 241 * GPY5[5] EBI_DATA[5](2) 242 * GPY5[6] EBI_DATA[6](2) 243 * GPY5[7] EBI_DATA[7](2) 244 * 245 * GPY6[0] EBI_DATA[8](2) 246 * GPY6[1] EBI_DATA[9](2) 247 * GPY6[2] EBI_DATA[10](2) 248 * GPY6[3] EBI_DATA[11](2) 249 * GPY6[4] EBI_DATA[12](2) 250 * GPY6[5] EBI_DATA[13](2) 251 * GPY6[6] EBI_DATA[14](2) 252 * GPY6[7] EBI_DATA[15](2) 253 */ 254 for (i = 0; i < 8; i++) { 255 gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2)); 256 gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP); 257 258 gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2)); 259 gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP); 260 261 gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2)); 262 gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP); 263 } 264 } 265 exynos5_i2c_config(int peripheral,int flags)266 static void exynos5_i2c_config(int peripheral, int flags) 267 { 268 int func01, func23; 269 270 /* High-Speed I2C */ 271 if (flags & PINMUX_FLAG_HS_MODE) { 272 func01 = 4; 273 func23 = 4; 274 } else { 275 func01 = 2; 276 func23 = 3; 277 } 278 279 switch (peripheral) { 280 case PERIPH_ID_I2C0: 281 gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01)); 282 gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01)); 283 break; 284 case PERIPH_ID_I2C1: 285 gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01)); 286 gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01)); 287 break; 288 case PERIPH_ID_I2C2: 289 gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23)); 290 gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23)); 291 break; 292 case PERIPH_ID_I2C3: 293 gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23)); 294 gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23)); 295 break; 296 case PERIPH_ID_I2C4: 297 gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3)); 298 gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3)); 299 break; 300 case PERIPH_ID_I2C5: 301 gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3)); 302 gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3)); 303 break; 304 case PERIPH_ID_I2C6: 305 gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4)); 306 gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4)); 307 break; 308 case PERIPH_ID_I2C7: 309 gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3)); 310 gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3)); 311 break; 312 } 313 } 314 exynos5420_i2c_config(int peripheral)315 static void exynos5420_i2c_config(int peripheral) 316 { 317 switch (peripheral) { 318 case PERIPH_ID_I2C0: 319 gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2)); 320 gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2)); 321 break; 322 case PERIPH_ID_I2C1: 323 gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2)); 324 gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2)); 325 break; 326 case PERIPH_ID_I2C2: 327 gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3)); 328 gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3)); 329 break; 330 case PERIPH_ID_I2C3: 331 gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3)); 332 gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3)); 333 break; 334 case PERIPH_ID_I2C4: 335 gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3)); 336 gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3)); 337 break; 338 case PERIPH_ID_I2C5: 339 gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3)); 340 gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3)); 341 break; 342 case PERIPH_ID_I2C6: 343 gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4)); 344 gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4)); 345 break; 346 case PERIPH_ID_I2C7: 347 gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3)); 348 gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3)); 349 break; 350 case PERIPH_ID_I2C8: 351 gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2)); 352 gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2)); 353 break; 354 case PERIPH_ID_I2C9: 355 gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2)); 356 gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2)); 357 break; 358 case PERIPH_ID_I2C10: 359 gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2)); 360 gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2)); 361 break; 362 } 363 } 364 exynos5_i2s_config(int peripheral)365 static void exynos5_i2s_config(int peripheral) 366 { 367 int i; 368 369 switch (peripheral) { 370 case PERIPH_ID_I2S0: 371 for (i = 0; i < 5; i++) 372 gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02)); 373 break; 374 case PERIPH_ID_I2S1: 375 for (i = 0; i < 5; i++) 376 gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02)); 377 break; 378 } 379 } 380 exynos5420_i2s_config(int peripheral)381 static void exynos5420_i2s_config(int peripheral) 382 { 383 int i; 384 385 switch (peripheral) { 386 case PERIPH_ID_I2S0: 387 for (i = 0; i < 5; i++) 388 gpio_cfg_pin(EXYNOS5420_GPIO_Z0 + i, 389 S5P_GPIO_FUNC(0x02)); 390 break; 391 } 392 } 393 394 exynos5_spi_config(int peripheral)395 void exynos5_spi_config(int peripheral) 396 { 397 int cfg = 0, pin = 0, i; 398 399 switch (peripheral) { 400 case PERIPH_ID_SPI0: 401 cfg = S5P_GPIO_FUNC(0x2); 402 pin = EXYNOS5_GPIO_A20; 403 break; 404 case PERIPH_ID_SPI1: 405 cfg = S5P_GPIO_FUNC(0x2); 406 pin = EXYNOS5_GPIO_A24; 407 break; 408 case PERIPH_ID_SPI2: 409 cfg = S5P_GPIO_FUNC(0x5); 410 pin = EXYNOS5_GPIO_B11; 411 break; 412 case PERIPH_ID_SPI3: 413 cfg = S5P_GPIO_FUNC(0x2); 414 pin = EXYNOS5_GPIO_F10; 415 break; 416 case PERIPH_ID_SPI4: 417 for (i = 0; i < 2; i++) { 418 gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); 419 gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); 420 } 421 break; 422 } 423 if (peripheral != PERIPH_ID_SPI4) { 424 for (i = pin; i < pin + 4; i++) 425 gpio_cfg_pin(i, cfg); 426 } 427 } 428 exynos5420_spi_config(int peripheral)429 void exynos5420_spi_config(int peripheral) 430 { 431 int cfg, pin, i; 432 433 switch (peripheral) { 434 case PERIPH_ID_SPI0: 435 pin = EXYNOS5420_GPIO_A20; 436 cfg = S5P_GPIO_FUNC(0x2); 437 break; 438 case PERIPH_ID_SPI1: 439 pin = EXYNOS5420_GPIO_A24; 440 cfg = S5P_GPIO_FUNC(0x2); 441 break; 442 case PERIPH_ID_SPI2: 443 pin = EXYNOS5420_GPIO_B11; 444 cfg = S5P_GPIO_FUNC(0x5); 445 break; 446 case PERIPH_ID_SPI3: 447 pin = EXYNOS5420_GPIO_F10; 448 cfg = S5P_GPIO_FUNC(0x2); 449 break; 450 case PERIPH_ID_SPI4: 451 cfg = 0; 452 pin = 0; 453 break; 454 default: 455 cfg = 0; 456 pin = 0; 457 debug("%s: invalid peripheral %d", __func__, peripheral); 458 return; 459 } 460 461 if (peripheral != PERIPH_ID_SPI4) { 462 for (i = pin; i < pin + 4; i++) 463 gpio_cfg_pin(i, cfg); 464 } else { 465 for (i = 0; i < 2; i++) { 466 gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i, 467 S5P_GPIO_FUNC(0x4)); 468 gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i, 469 S5P_GPIO_FUNC(0x4)); 470 } 471 } 472 } 473 exynos5_pinmux_config(int peripheral,int flags)474 static int exynos5_pinmux_config(int peripheral, int flags) 475 { 476 switch (peripheral) { 477 case PERIPH_ID_UART0: 478 case PERIPH_ID_UART1: 479 case PERIPH_ID_UART2: 480 case PERIPH_ID_UART3: 481 exynos5_uart_config(peripheral); 482 break; 483 case PERIPH_ID_SDMMC0: 484 case PERIPH_ID_SDMMC1: 485 case PERIPH_ID_SDMMC2: 486 case PERIPH_ID_SDMMC3: 487 return exynos5_mmc_config(peripheral, flags); 488 case PERIPH_ID_SROMC: 489 exynos5_sromc_config(flags); 490 break; 491 case PERIPH_ID_I2C0: 492 case PERIPH_ID_I2C1: 493 case PERIPH_ID_I2C2: 494 case PERIPH_ID_I2C3: 495 case PERIPH_ID_I2C4: 496 case PERIPH_ID_I2C5: 497 case PERIPH_ID_I2C6: 498 case PERIPH_ID_I2C7: 499 exynos5_i2c_config(peripheral, flags); 500 break; 501 case PERIPH_ID_I2S0: 502 case PERIPH_ID_I2S1: 503 exynos5_i2s_config(peripheral); 504 break; 505 case PERIPH_ID_SPI0: 506 case PERIPH_ID_SPI1: 507 case PERIPH_ID_SPI2: 508 case PERIPH_ID_SPI3: 509 case PERIPH_ID_SPI4: 510 exynos5_spi_config(peripheral); 511 break; 512 case PERIPH_ID_DPHPD: 513 /* Set Hotplug detect for DP */ 514 gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); 515 516 /* 517 * Hotplug detect should have an external pullup; disable the 518 * internal pulldown so they don't fight. 519 */ 520 gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE); 521 break; 522 case PERIPH_ID_PWM0: 523 gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2)); 524 break; 525 default: 526 debug("%s: invalid peripheral %d", __func__, peripheral); 527 return -1; 528 } 529 530 return 0; 531 } 532 exynos5420_pinmux_config(int peripheral,int flags)533 static int exynos5420_pinmux_config(int peripheral, int flags) 534 { 535 switch (peripheral) { 536 case PERIPH_ID_UART0: 537 case PERIPH_ID_UART1: 538 case PERIPH_ID_UART2: 539 case PERIPH_ID_UART3: 540 exynos5420_uart_config(peripheral); 541 break; 542 case PERIPH_ID_SDMMC0: 543 case PERIPH_ID_SDMMC1: 544 case PERIPH_ID_SDMMC2: 545 case PERIPH_ID_SDMMC3: 546 return exynos5420_mmc_config(peripheral, flags); 547 case PERIPH_ID_SPI0: 548 case PERIPH_ID_SPI1: 549 case PERIPH_ID_SPI2: 550 case PERIPH_ID_SPI3: 551 case PERIPH_ID_SPI4: 552 exynos5420_spi_config(peripheral); 553 break; 554 case PERIPH_ID_I2C0: 555 case PERIPH_ID_I2C1: 556 case PERIPH_ID_I2C2: 557 case PERIPH_ID_I2C3: 558 case PERIPH_ID_I2C4: 559 case PERIPH_ID_I2C5: 560 case PERIPH_ID_I2C6: 561 case PERIPH_ID_I2C7: 562 case PERIPH_ID_I2C8: 563 case PERIPH_ID_I2C9: 564 case PERIPH_ID_I2C10: 565 exynos5420_i2c_config(peripheral); 566 break; 567 case PERIPH_ID_I2S0: 568 exynos5420_i2s_config(peripheral); 569 break; 570 case PERIPH_ID_PWM0: 571 gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2)); 572 break; 573 default: 574 debug("%s: invalid peripheral %d", __func__, peripheral); 575 return -1; 576 } 577 578 return 0; 579 } 580 exynos4_i2c_config(int peripheral,int flags)581 static void exynos4_i2c_config(int peripheral, int flags) 582 { 583 switch (peripheral) { 584 case PERIPH_ID_I2C0: 585 gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2)); 586 gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2)); 587 break; 588 case PERIPH_ID_I2C1: 589 gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2)); 590 gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2)); 591 break; 592 case PERIPH_ID_I2C2: 593 gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3)); 594 gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3)); 595 break; 596 case PERIPH_ID_I2C3: 597 gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3)); 598 gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3)); 599 break; 600 case PERIPH_ID_I2C4: 601 gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3)); 602 gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3)); 603 break; 604 case PERIPH_ID_I2C5: 605 gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3)); 606 gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3)); 607 break; 608 case PERIPH_ID_I2C6: 609 gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4)); 610 gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4)); 611 break; 612 case PERIPH_ID_I2C7: 613 gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3)); 614 gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3)); 615 break; 616 } 617 } 618 exynos4_mmc_config(int peripheral,int flags)619 static int exynos4_mmc_config(int peripheral, int flags) 620 { 621 int i, start = 0, start_ext = 0; 622 unsigned int func, ext_func; 623 624 switch (peripheral) { 625 case PERIPH_ID_SDMMC0: 626 start = EXYNOS4_GPIO_K00; 627 start_ext = EXYNOS4_GPIO_K13; 628 func = S5P_GPIO_FUNC(0x2); 629 ext_func = S5P_GPIO_FUNC(0x3); 630 break; 631 case PERIPH_ID_SDMMC2: 632 start = EXYNOS4_GPIO_K20; 633 start_ext = EXYNOS4_GPIO_K33; 634 func = S5P_GPIO_FUNC(0x2); 635 ext_func = S5P_GPIO_FUNC(0x3); 636 break; 637 case PERIPH_ID_SDMMC4: 638 start = EXYNOS4_GPIO_K00; 639 start_ext = EXYNOS4_GPIO_K13; 640 func = S5P_GPIO_FUNC(0x3); 641 ext_func = S5P_GPIO_FUNC(0x4); 642 break; 643 default: 644 return -1; 645 } 646 for (i = start; i < (start + 7); i++) { 647 if (i == (start + 2)) 648 continue; 649 gpio_cfg_pin(i, func); 650 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 651 gpio_set_drv(i, S5P_GPIO_DRV_4X); 652 } 653 /* SDMMC2 do not use 8bit mode at exynos4 */ 654 if (flags & PINMUX_FLAG_8BIT_MODE) { 655 for (i = start_ext; i < (start_ext + 4); i++) { 656 gpio_cfg_pin(i, ext_func); 657 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 658 gpio_set_drv(i, S5P_GPIO_DRV_4X); 659 } 660 } 661 662 return 0; 663 } 664 exynos4_uart_config(int peripheral)665 static void exynos4_uart_config(int peripheral) 666 { 667 int i, start, count; 668 669 switch (peripheral) { 670 case PERIPH_ID_UART0: 671 start = EXYNOS4_GPIO_A00; 672 count = 4; 673 break; 674 case PERIPH_ID_UART1: 675 start = EXYNOS4_GPIO_A04; 676 count = 4; 677 break; 678 case PERIPH_ID_UART2: 679 start = EXYNOS4_GPIO_A10; 680 count = 4; 681 break; 682 case PERIPH_ID_UART3: 683 start = EXYNOS4_GPIO_A14; 684 count = 2; 685 break; 686 default: 687 debug("%s: invalid peripheral %d", __func__, peripheral); 688 return; 689 } 690 for (i = start; i < (start + count); i++) { 691 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 692 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 693 } 694 } 695 exynos4x12_i2c_config(int peripheral,int flags)696 static void exynos4x12_i2c_config(int peripheral, int flags) 697 { 698 switch (peripheral) { 699 case PERIPH_ID_I2C0: 700 gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2)); 701 gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2)); 702 break; 703 case PERIPH_ID_I2C1: 704 gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2)); 705 gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2)); 706 break; 707 case PERIPH_ID_I2C2: 708 gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3)); 709 gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3)); 710 break; 711 case PERIPH_ID_I2C3: 712 gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3)); 713 gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3)); 714 break; 715 case PERIPH_ID_I2C4: 716 gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3)); 717 gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3)); 718 break; 719 case PERIPH_ID_I2C5: 720 gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3)); 721 gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3)); 722 break; 723 case PERIPH_ID_I2C6: 724 gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4)); 725 gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4)); 726 break; 727 case PERIPH_ID_I2C7: 728 gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3)); 729 gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3)); 730 break; 731 } 732 } 733 exynos4x12_mmc_config(int peripheral,int flags)734 static int exynos4x12_mmc_config(int peripheral, int flags) 735 { 736 int i, start = 0, start_ext = 0; 737 unsigned int func, ext_func; 738 739 switch (peripheral) { 740 case PERIPH_ID_SDMMC0: 741 start = EXYNOS4X12_GPIO_K00; 742 start_ext = EXYNOS4X12_GPIO_K13; 743 func = S5P_GPIO_FUNC(0x2); 744 ext_func = S5P_GPIO_FUNC(0x3); 745 break; 746 case PERIPH_ID_SDMMC2: 747 start = EXYNOS4X12_GPIO_K20; 748 start_ext = EXYNOS4X12_GPIO_K33; 749 func = S5P_GPIO_FUNC(0x2); 750 ext_func = S5P_GPIO_FUNC(0x3); 751 break; 752 case PERIPH_ID_SDMMC4: 753 start = EXYNOS4X12_GPIO_K00; 754 start_ext = EXYNOS4X12_GPIO_K13; 755 func = S5P_GPIO_FUNC(0x3); 756 ext_func = S5P_GPIO_FUNC(0x4); 757 break; 758 default: 759 return -1; 760 } 761 for (i = start; i < (start + 7); i++) { 762 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 763 if (i == (start + 2)) 764 continue; 765 gpio_cfg_pin(i, func); 766 gpio_set_drv(i, S5P_GPIO_DRV_4X); 767 } 768 if (flags & PINMUX_FLAG_8BIT_MODE) { 769 for (i = start_ext; i < (start_ext + 4); i++) { 770 gpio_cfg_pin(i, ext_func); 771 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 772 gpio_set_drv(i, S5P_GPIO_DRV_4X); 773 } 774 } 775 776 return 0; 777 } 778 exynos4x12_uart_config(int peripheral)779 static void exynos4x12_uart_config(int peripheral) 780 { 781 int i, start, count; 782 783 switch (peripheral) { 784 case PERIPH_ID_UART0: 785 start = EXYNOS4X12_GPIO_A00; 786 count = 4; 787 break; 788 case PERIPH_ID_UART1: 789 start = EXYNOS4X12_GPIO_A04; 790 count = 4; 791 break; 792 case PERIPH_ID_UART2: 793 start = EXYNOS4X12_GPIO_A10; 794 count = 4; 795 break; 796 case PERIPH_ID_UART3: 797 start = EXYNOS4X12_GPIO_A14; 798 count = 2; 799 break; 800 default: 801 debug("%s: invalid peripheral %d", __func__, peripheral); 802 return; 803 } 804 for (i = start; i < (start + count); i++) { 805 gpio_set_pull(i, S5P_GPIO_PULL_NONE); 806 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 807 } 808 } 809 exynos4_pinmux_config(int peripheral,int flags)810 static int exynos4_pinmux_config(int peripheral, int flags) 811 { 812 switch (peripheral) { 813 case PERIPH_ID_UART0: 814 case PERIPH_ID_UART1: 815 case PERIPH_ID_UART2: 816 case PERIPH_ID_UART3: 817 exynos4_uart_config(peripheral); 818 break; 819 case PERIPH_ID_I2C0: 820 case PERIPH_ID_I2C1: 821 case PERIPH_ID_I2C2: 822 case PERIPH_ID_I2C3: 823 case PERIPH_ID_I2C4: 824 case PERIPH_ID_I2C5: 825 case PERIPH_ID_I2C6: 826 case PERIPH_ID_I2C7: 827 exynos4_i2c_config(peripheral, flags); 828 break; 829 case PERIPH_ID_SDMMC0: 830 case PERIPH_ID_SDMMC2: 831 case PERIPH_ID_SDMMC4: 832 return exynos4_mmc_config(peripheral, flags); 833 case PERIPH_ID_SDMMC1: 834 case PERIPH_ID_SDMMC3: 835 debug("SDMMC device %d not implemented\n", peripheral); 836 return -1; 837 default: 838 debug("%s: invalid peripheral %d", __func__, peripheral); 839 return -1; 840 } 841 842 return 0; 843 } 844 exynos4x12_pinmux_config(int peripheral,int flags)845 static int exynos4x12_pinmux_config(int peripheral, int flags) 846 { 847 switch (peripheral) { 848 case PERIPH_ID_UART0: 849 case PERIPH_ID_UART1: 850 case PERIPH_ID_UART2: 851 case PERIPH_ID_UART3: 852 exynos4x12_uart_config(peripheral); 853 break; 854 case PERIPH_ID_I2C0: 855 case PERIPH_ID_I2C1: 856 case PERIPH_ID_I2C2: 857 case PERIPH_ID_I2C3: 858 case PERIPH_ID_I2C4: 859 case PERIPH_ID_I2C5: 860 case PERIPH_ID_I2C6: 861 case PERIPH_ID_I2C7: 862 exynos4x12_i2c_config(peripheral, flags); 863 break; 864 case PERIPH_ID_SDMMC0: 865 case PERIPH_ID_SDMMC2: 866 case PERIPH_ID_SDMMC4: 867 return exynos4x12_mmc_config(peripheral, flags); 868 case PERIPH_ID_SDMMC1: 869 case PERIPH_ID_SDMMC3: 870 debug("SDMMC device %d not implemented\n", peripheral); 871 return -1; 872 default: 873 debug("%s: invalid peripheral %d", __func__, peripheral); 874 return -1; 875 } 876 877 return 0; 878 } 879 exynos_pinmux_config(int peripheral,int flags)880 int exynos_pinmux_config(int peripheral, int flags) 881 { 882 if (cpu_is_exynos5()) { 883 if (proid_is_exynos542x()) 884 return exynos5420_pinmux_config(peripheral, flags); 885 else if (proid_is_exynos5250()) 886 return exynos5_pinmux_config(peripheral, flags); 887 } else if (cpu_is_exynos4()) { 888 if (proid_is_exynos4412()) 889 return exynos4x12_pinmux_config(peripheral, flags); 890 else 891 return exynos4_pinmux_config(peripheral, flags); 892 } 893 894 debug("pinmux functionality not supported\n"); 895 896 return -1; 897 } 898 899 #if CONFIG_IS_ENABLED(OF_CONTROL) exynos4_pinmux_decode_periph_id(const void * blob,int node)900 static int exynos4_pinmux_decode_periph_id(const void *blob, int node) 901 { 902 int err; 903 u32 cell[3]; 904 905 err = fdtdec_get_int_array(blob, node, "interrupts", cell, 906 ARRAY_SIZE(cell)); 907 if (err) { 908 debug(" invalid peripheral id\n"); 909 return PERIPH_ID_NONE; 910 } 911 912 return cell[1]; 913 } 914 exynos5_pinmux_decode_periph_id(const void * blob,int node)915 static int exynos5_pinmux_decode_periph_id(const void *blob, int node) 916 { 917 int err; 918 u32 cell[3]; 919 920 err = fdtdec_get_int_array(blob, node, "interrupts", cell, 921 ARRAY_SIZE(cell)); 922 if (err) 923 return PERIPH_ID_NONE; 924 925 return cell[1]; 926 } 927 pinmux_decode_periph_id(const void * blob,int node)928 int pinmux_decode_periph_id(const void *blob, int node) 929 { 930 if (cpu_is_exynos5()) 931 return exynos5_pinmux_decode_periph_id(blob, node); 932 else if (cpu_is_exynos4()) 933 return exynos4_pinmux_decode_periph_id(blob, node); 934 935 return PERIPH_ID_NONE; 936 } 937 #endif 938