1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020, Linaro Ltd.
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
13
14 #include "common.h"
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-pll.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "gdsc.h"
21 #include "reset.h"
22
23 enum {
24 P_BI_TCXO,
25 P_GPLL0_OUT_EVEN,
26 P_GPLL0_OUT_MAIN,
27 P_GPLL4_OUT_EVEN,
28 P_GPLL5_OUT_MAIN,
29 P_SLEEP_CLK,
30 };
31
32 static const struct pll_vco lucid_vco[] = {
33 { 249600000, 2000000000, 0 },
34 };
35
36 static struct clk_alpha_pll gpll0 = {
37 .offset = 0x0,
38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
39 .vco_table = lucid_vco,
40 .num_vco = ARRAY_SIZE(lucid_vco),
41 .clkr = {
42 .enable_reg = 0x6d000,
43 .enable_mask = BIT(0),
44 .hw.init = &(struct clk_init_data){
45 .name = "gpll0",
46 .parent_data = &(const struct clk_parent_data){
47 .fw_name = "bi_tcxo",
48 },
49 .num_parents = 1,
50 .ops = &clk_alpha_pll_fixed_lucid_ops,
51 },
52 },
53 };
54
55 static const struct clk_div_table post_div_table_lucid_even[] = {
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
60 { }
61 };
62
63 static struct clk_alpha_pll_postdiv gpll0_out_even = {
64 .offset = 0x0,
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
66 .post_div_shift = 8,
67 .post_div_table = post_div_table_lucid_even,
68 .num_post_div = ARRAY_SIZE(post_div_table_lucid_even),
69 .width = 4,
70 .clkr.hw.init = &(struct clk_init_data){
71 .name = "gpll0_out_even",
72 .parent_hws = (const struct clk_hw*[]){
73 &gpll0.clkr.hw,
74 },
75 .num_parents = 1,
76 .ops = &clk_alpha_pll_postdiv_lucid_ops,
77 },
78 };
79
80 static struct clk_alpha_pll gpll4 = {
81 .offset = 0x76000,
82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
83 .vco_table = lucid_vco,
84 .num_vco = ARRAY_SIZE(lucid_vco),
85 .clkr = {
86 .enable_reg = 0x6d000,
87 .enable_mask = BIT(4),
88 .hw.init = &(struct clk_init_data){
89 .name = "gpll4",
90 .parent_data = &(const struct clk_parent_data){
91 .fw_name = "bi_tcxo",
92 },
93 .num_parents = 1,
94 .ops = &clk_alpha_pll_fixed_lucid_ops,
95 },
96 },
97 };
98
99 static struct clk_alpha_pll_postdiv gpll4_out_even = {
100 .offset = 0x76000,
101 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
102 .post_div_shift = 8,
103 .post_div_table = post_div_table_lucid_even,
104 .num_post_div = ARRAY_SIZE(post_div_table_lucid_even),
105 .width = 4,
106 .clkr.hw.init = &(struct clk_init_data){
107 .name = "gpll4_out_even",
108 .parent_hws = (const struct clk_hw*[]){
109 &gpll4.clkr.hw,
110 },
111 .num_parents = 1,
112 .ops = &clk_alpha_pll_postdiv_lucid_ops,
113 },
114 };
115
116 static struct clk_alpha_pll gpll5 = {
117 .offset = 0x74000,
118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
119 .vco_table = lucid_vco,
120 .num_vco = ARRAY_SIZE(lucid_vco),
121 .clkr = {
122 .enable_reg = 0x6d000,
123 .enable_mask = BIT(5),
124 .hw.init = &(struct clk_init_data){
125 .name = "gpll5",
126 .parent_data = &(const struct clk_parent_data){
127 .fw_name = "bi_tcxo",
128 },
129 .num_parents = 1,
130 .ops = &clk_alpha_pll_fixed_lucid_ops,
131 },
132 },
133 };
134
135 static const struct parent_map gcc_parent_map_0[] = {
136 { P_BI_TCXO, 0 },
137 { P_GPLL0_OUT_MAIN, 1 },
138 { P_GPLL0_OUT_EVEN, 6 },
139 };
140
141 static const struct clk_parent_data gcc_parents_0[] = {
142 { .fw_name = "bi_tcxo" },
143 { .hw = &gpll0.clkr.hw },
144 { .hw = &gpll0_out_even.clkr.hw },
145 };
146
147 static const struct clk_parent_data gcc_parents_0_ao[] = {
148 { .fw_name = "bi_tcxo_ao" },
149 { .hw = &gpll0.clkr.hw },
150 { .hw = &gpll0_out_even.clkr.hw },
151 };
152
153 static const struct parent_map gcc_parent_map_2[] = {
154 { P_BI_TCXO, 0 },
155 { P_GPLL0_OUT_MAIN, 1 },
156 { P_GPLL4_OUT_EVEN, 2 },
157 { P_GPLL5_OUT_MAIN, 5 },
158 { P_GPLL0_OUT_EVEN, 6 },
159 };
160
161 static const struct clk_parent_data gcc_parents_2[] = {
162 { .fw_name = "bi_tcxo" },
163 { .hw = &gpll0.clkr.hw },
164 { .hw = &gpll4_out_even.clkr.hw },
165 { .hw = &gpll5.clkr.hw },
166 { .hw = &gpll0_out_even.clkr.hw },
167 };
168
169 static const struct parent_map gcc_parent_map_3[] = {
170 { P_BI_TCXO, 0 },
171 { P_GPLL0_OUT_MAIN, 1 },
172 { P_SLEEP_CLK, 5 },
173 { P_GPLL0_OUT_EVEN, 6 },
174 };
175
176 static const struct clk_parent_data gcc_parents_3[] = {
177 { .fw_name = "bi_tcxo" },
178 { .hw = &gpll0.clkr.hw },
179 { .fw_name = "sleep_clk", .name = "sleep_clk" },
180 { .hw = &gpll0_out_even.clkr.hw },
181 };
182
183 static const struct parent_map gcc_parent_map_4[] = {
184 { P_BI_TCXO, 0 },
185 { P_SLEEP_CLK, 5 },
186 };
187
188 static const struct clk_parent_data gcc_parents_4[] = {
189 { .fw_name = "bi_tcxo" },
190 { .fw_name = "sleep_clk", .name = "sleep_clk" },
191 };
192
193 static const struct parent_map gcc_parent_map_5[] = {
194 { P_BI_TCXO, 0 },
195 { P_GPLL0_OUT_MAIN, 1 },
196 { P_GPLL4_OUT_EVEN, 2 },
197 { P_GPLL0_OUT_EVEN, 6 },
198 };
199
200 static const struct clk_parent_data gcc_parents_5[] = {
201 { .fw_name = "bi_tcxo" },
202 { .hw = &gpll0.clkr.hw },
203 { .hw = &gpll4_out_even.clkr.hw },
204 { .hw = &gpll0_out_even.clkr.hw },
205 };
206
207 static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
208 F(9600000, P_BI_TCXO, 2, 0, 0),
209 F(19200000, P_BI_TCXO, 1, 0, 0),
210 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
211 { }
212 };
213
214 static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
215 .cmd_rcgr = 0x11024,
216 .mnd_width = 8,
217 .hid_width = 5,
218 .parent_map = gcc_parent_map_0,
219 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
220 .clkr.hw.init = &(struct clk_init_data){
221 .name = "gcc_blsp1_qup1_i2c_apps_clk_src",
222 .parent_data = gcc_parents_0,
223 .num_parents = ARRAY_SIZE(gcc_parents_0),
224 .ops = &clk_rcg2_ops,
225 },
226 };
227
228 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
229 F(960000, P_BI_TCXO, 10, 1, 2),
230 F(4800000, P_BI_TCXO, 4, 0, 0),
231 F(9600000, P_BI_TCXO, 2, 0, 0),
232 F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4),
233 F(19200000, P_BI_TCXO, 1, 0, 0),
234 F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2),
235 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
236 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
237 { }
238 };
239
240 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
241 .cmd_rcgr = 0x1100c,
242 .mnd_width = 8,
243 .hid_width = 5,
244 .parent_map = gcc_parent_map_0,
245 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
246 .clkr.hw.init = &(struct clk_init_data){
247 .name = "gcc_blsp1_qup1_spi_apps_clk_src",
248 .parent_data = gcc_parents_0,
249 .num_parents = ARRAY_SIZE(gcc_parents_0),
250 .ops = &clk_rcg2_ops,
251 },
252 };
253
254 static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
255 .cmd_rcgr = 0x13024,
256 .mnd_width = 8,
257 .hid_width = 5,
258 .parent_map = gcc_parent_map_0,
259 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
260 .clkr.hw.init = &(struct clk_init_data){
261 .name = "gcc_blsp1_qup2_i2c_apps_clk_src",
262 .parent_data = gcc_parents_0,
263 .num_parents = ARRAY_SIZE(gcc_parents_0),
264 .ops = &clk_rcg2_ops,
265 },
266 };
267
268 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
269 .cmd_rcgr = 0x1300c,
270 .mnd_width = 8,
271 .hid_width = 5,
272 .parent_map = gcc_parent_map_0,
273 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
274 .clkr.hw.init = &(struct clk_init_data){
275 .name = "gcc_blsp1_qup2_spi_apps_clk_src",
276 .parent_data = gcc_parents_0,
277 .num_parents = ARRAY_SIZE(gcc_parents_0),
278 .ops = &clk_rcg2_ops,
279 },
280 };
281
282 static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
283 .cmd_rcgr = 0x15024,
284 .mnd_width = 8,
285 .hid_width = 5,
286 .parent_map = gcc_parent_map_0,
287 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
288 .clkr.hw.init = &(struct clk_init_data){
289 .name = "gcc_blsp1_qup3_i2c_apps_clk_src",
290 .parent_data = gcc_parents_0,
291 .num_parents = ARRAY_SIZE(gcc_parents_0),
292 .ops = &clk_rcg2_ops,
293 },
294 };
295
296 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
297 .cmd_rcgr = 0x1500c,
298 .mnd_width = 8,
299 .hid_width = 5,
300 .parent_map = gcc_parent_map_0,
301 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
302 .clkr.hw.init = &(struct clk_init_data){
303 .name = "gcc_blsp1_qup3_spi_apps_clk_src",
304 .parent_data = gcc_parents_0,
305 .num_parents = ARRAY_SIZE(gcc_parents_0),
306 .ops = &clk_rcg2_ops,
307 },
308 };
309
310 static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
311 .cmd_rcgr = 0x17024,
312 .mnd_width = 8,
313 .hid_width = 5,
314 .parent_map = gcc_parent_map_0,
315 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
316 .clkr.hw.init = &(struct clk_init_data){
317 .name = "gcc_blsp1_qup4_i2c_apps_clk_src",
318 .parent_data = gcc_parents_0,
319 .num_parents = ARRAY_SIZE(gcc_parents_0),
320 .ops = &clk_rcg2_ops,
321 },
322 };
323
324 static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
325 .cmd_rcgr = 0x1700c,
326 .mnd_width = 8,
327 .hid_width = 5,
328 .parent_map = gcc_parent_map_0,
329 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
330 .clkr.hw.init = &(struct clk_init_data){
331 .name = "gcc_blsp1_qup4_spi_apps_clk_src",
332 .parent_data = gcc_parents_0,
333 .num_parents = ARRAY_SIZE(gcc_parents_0),
334 .ops = &clk_rcg2_ops,
335 },
336 };
337
338 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
339 F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625),
340 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
341 F(9600000, P_BI_TCXO, 2, 0, 0),
342 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
343 F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75),
344 F(19200000, P_BI_TCXO, 1, 0, 0),
345 F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2),
346 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
347 F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2),
348 F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2),
349 F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2),
350 F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2),
351 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
352 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
353 F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2),
354 F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2),
355 F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2),
356 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
357 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
358 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
359 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
360 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
361 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
362 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
363 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
364 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
365 { }
366 };
367
368 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
369 .cmd_rcgr = 0x1200c,
370 .mnd_width = 16,
371 .hid_width = 5,
372 .parent_map = gcc_parent_map_0,
373 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "gcc_blsp1_uart1_apps_clk_src",
376 .parent_data = gcc_parents_0,
377 .num_parents = ARRAY_SIZE(gcc_parents_0),
378 .ops = &clk_rcg2_ops,
379 },
380 };
381
382 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
383 .cmd_rcgr = 0x1400c,
384 .mnd_width = 16,
385 .hid_width = 5,
386 .parent_map = gcc_parent_map_0,
387 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
388 .clkr.hw.init = &(struct clk_init_data){
389 .name = "gcc_blsp1_uart2_apps_clk_src",
390 .parent_data = gcc_parents_0,
391 .num_parents = ARRAY_SIZE(gcc_parents_0),
392 .ops = &clk_rcg2_ops,
393 },
394 };
395
396 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
397 .cmd_rcgr = 0x1600c,
398 .mnd_width = 16,
399 .hid_width = 5,
400 .parent_map = gcc_parent_map_0,
401 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
402 .clkr.hw.init = &(struct clk_init_data){
403 .name = "gcc_blsp1_uart3_apps_clk_src",
404 .parent_data = gcc_parents_0,
405 .num_parents = ARRAY_SIZE(gcc_parents_0),
406 .ops = &clk_rcg2_ops,
407 },
408 };
409
410 static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
411 .cmd_rcgr = 0x1800c,
412 .mnd_width = 16,
413 .hid_width = 5,
414 .parent_map = gcc_parent_map_0,
415 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
416 .clkr.hw.init = &(struct clk_init_data){
417 .name = "gcc_blsp1_uart4_apps_clk_src",
418 .parent_data = gcc_parents_0,
419 .num_parents = ARRAY_SIZE(gcc_parents_0),
420 .ops = &clk_rcg2_ops,
421 },
422 };
423
424 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
425 F(19200000, P_BI_TCXO, 1, 0, 0),
426 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
427 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
428 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
429 { }
430 };
431
432 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
433 .cmd_rcgr = 0x24010,
434 .mnd_width = 0,
435 .hid_width = 5,
436 .parent_map = gcc_parent_map_0,
437 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
438 .clkr.hw.init = &(struct clk_init_data){
439 .name = "gcc_cpuss_ahb_clk_src",
440 .parent_data = gcc_parents_0_ao,
441 .num_parents = ARRAY_SIZE(gcc_parents_0_ao),
442 .ops = &clk_rcg2_ops,
443 },
444 };
445
446 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
447 F(19200000, P_BI_TCXO, 1, 0, 0),
448 { }
449 };
450
451 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
452 .cmd_rcgr = 0x2402c,
453 .mnd_width = 0,
454 .hid_width = 5,
455 .parent_map = gcc_parent_map_0,
456 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
457 .clkr.hw.init = &(struct clk_init_data){
458 .name = "gcc_cpuss_rbcpr_clk_src",
459 .parent_data = gcc_parents_0_ao,
460 .num_parents = ARRAY_SIZE(gcc_parents_0_ao),
461 .ops = &clk_rcg2_ops,
462 },
463 };
464
465 static const struct freq_tbl ftbl_gcc_emac_clk_src[] = {
466 F(2500000, P_BI_TCXO, 1, 25, 192),
467 F(5000000, P_BI_TCXO, 1, 25, 96),
468 F(19200000, P_BI_TCXO, 1, 0, 0),
469 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
470 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
471 F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0),
472 { }
473 };
474
475 static struct clk_rcg2 gcc_emac_clk_src = {
476 .cmd_rcgr = 0x47020,
477 .mnd_width = 8,
478 .hid_width = 5,
479 .parent_map = gcc_parent_map_5,
480 .freq_tbl = ftbl_gcc_emac_clk_src,
481 .clkr.hw.init = &(struct clk_init_data){
482 .name = "gcc_emac_clk_src",
483 .parent_data = gcc_parents_5,
484 .num_parents = ARRAY_SIZE(gcc_parents_5),
485 .ops = &clk_rcg2_ops,
486 },
487 };
488
489 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
490 F(19200000, P_BI_TCXO, 1, 0, 0),
491 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
492 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
493 { }
494 };
495
496 static struct clk_rcg2 gcc_emac_ptp_clk_src = {
497 .cmd_rcgr = 0x47038,
498 .mnd_width = 0,
499 .hid_width = 5,
500 .parent_map = gcc_parent_map_2,
501 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
502 .clkr.hw.init = &(struct clk_init_data){
503 .name = "gcc_emac_ptp_clk_src",
504 .parent_data = gcc_parents_2,
505 .num_parents = ARRAY_SIZE(gcc_parents_2),
506 .ops = &clk_rcg2_ops,
507 },
508 };
509
510 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
511 F(19200000, P_BI_TCXO, 1, 0, 0),
512 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
513 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
514 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
515 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
516 { }
517 };
518
519 static struct clk_rcg2 gcc_gp1_clk_src = {
520 .cmd_rcgr = 0x2b004,
521 .mnd_width = 8,
522 .hid_width = 5,
523 .parent_map = gcc_parent_map_3,
524 .freq_tbl = ftbl_gcc_gp1_clk_src,
525 .clkr.hw.init = &(struct clk_init_data){
526 .name = "gcc_gp1_clk_src",
527 .parent_data = gcc_parents_3,
528 .num_parents = ARRAY_SIZE(gcc_parents_3),
529 .ops = &clk_rcg2_ops,
530 },
531 };
532
533 static struct clk_rcg2 gcc_gp2_clk_src = {
534 .cmd_rcgr = 0x2c004,
535 .mnd_width = 8,
536 .hid_width = 5,
537 .parent_map = gcc_parent_map_3,
538 .freq_tbl = ftbl_gcc_gp1_clk_src,
539 .clkr.hw.init = &(struct clk_init_data){
540 .name = "gcc_gp2_clk_src",
541 .parent_data = gcc_parents_3,
542 .num_parents = ARRAY_SIZE(gcc_parents_3),
543 .ops = &clk_rcg2_ops,
544 },
545 };
546
547 static struct clk_rcg2 gcc_gp3_clk_src = {
548 .cmd_rcgr = 0x2d004,
549 .mnd_width = 8,
550 .hid_width = 5,
551 .parent_map = gcc_parent_map_3,
552 .freq_tbl = ftbl_gcc_gp1_clk_src,
553 .clkr.hw.init = &(struct clk_init_data){
554 .name = "gcc_gp3_clk_src",
555 .parent_data = gcc_parents_3,
556 .num_parents = ARRAY_SIZE(gcc_parents_3),
557 .ops = &clk_rcg2_ops,
558 },
559 };
560
561 static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
562 .cmd_rcgr = 0x37034,
563 .mnd_width = 16,
564 .hid_width = 5,
565 .parent_map = gcc_parent_map_4,
566 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "gcc_pcie_aux_phy_clk_src",
569 .parent_data = gcc_parents_4,
570 .num_parents = ARRAY_SIZE(gcc_parents_4),
571 .ops = &clk_rcg2_ops,
572 },
573 };
574
575 static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = {
576 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
577 { }
578 };
579
580 static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
581 .cmd_rcgr = 0x37050,
582 .mnd_width = 0,
583 .hid_width = 5,
584 .parent_map = gcc_parent_map_3,
585 .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src,
586 .clkr.hw.init = &(struct clk_init_data){
587 .name = "gcc_pcie_rchng_phy_clk_src",
588 .parent_data = gcc_parents_3,
589 .num_parents = ARRAY_SIZE(gcc_parents_3),
590 .ops = &clk_rcg2_ops,
591 },
592 };
593
594 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
595 F(9600000, P_BI_TCXO, 2, 0, 0),
596 F(19200000, P_BI_TCXO, 1, 0, 0),
597 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
598 { }
599 };
600
601 static struct clk_rcg2 gcc_pdm2_clk_src = {
602 .cmd_rcgr = 0x19010,
603 .mnd_width = 0,
604 .hid_width = 5,
605 .parent_map = gcc_parent_map_0,
606 .freq_tbl = ftbl_gcc_pdm2_clk_src,
607 .clkr.hw.init = &(struct clk_init_data){
608 .name = "gcc_pdm2_clk_src",
609 .parent_data = gcc_parents_0,
610 .num_parents = ARRAY_SIZE(gcc_parents_0),
611 .ops = &clk_rcg2_ops,
612 },
613 };
614
615 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
616 .cmd_rcgr = 0xf00c,
617 .mnd_width = 8,
618 .hid_width = 5,
619 .parent_map = gcc_parent_map_0,
620 .freq_tbl = ftbl_gcc_gp1_clk_src,
621 .clkr.hw.init = &(struct clk_init_data){
622 .name = "gcc_sdcc1_apps_clk_src",
623 .parent_data = gcc_parents_0,
624 .num_parents = ARRAY_SIZE(gcc_parents_0),
625 .ops = &clk_rcg2_ops,
626 },
627 };
628
629 static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
630 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
631 { }
632 };
633
634 static struct clk_rcg2 gcc_usb30_master_clk_src = {
635 .cmd_rcgr = 0xb024,
636 .mnd_width = 8,
637 .hid_width = 5,
638 .parent_map = gcc_parent_map_0,
639 .freq_tbl = ftbl_gcc_usb30_master_clk_src,
640 .clkr.hw.init = &(struct clk_init_data){
641 .name = "gcc_usb30_master_clk_src",
642 .parent_data = gcc_parents_0,
643 .num_parents = ARRAY_SIZE(gcc_parents_0),
644 .ops = &clk_rcg2_ops,
645 },
646 };
647
648 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
649 F(19200000, P_BI_TCXO, 1, 0, 0),
650 { }
651 };
652
653 static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
654 .cmd_rcgr = 0xb03c,
655 .mnd_width = 0,
656 .hid_width = 5,
657 .parent_map = gcc_parent_map_0,
658 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
659 .clkr.hw.init = &(struct clk_init_data){
660 .name = "gcc_usb30_mock_utmi_clk_src",
661 .parent_data = gcc_parents_0,
662 .num_parents = ARRAY_SIZE(gcc_parents_0),
663 .ops = &clk_rcg2_ops,
664 },
665 };
666
667 static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
668 F(1000000, P_BI_TCXO, 1, 5, 96),
669 F(19200000, P_BI_TCXO, 1, 0, 0),
670 { }
671 };
672
673 static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
674 .cmd_rcgr = 0xb064,
675 .mnd_width = 16,
676 .hid_width = 5,
677 .parent_map = gcc_parent_map_4,
678 .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
679 .clkr.hw.init = &(struct clk_init_data){
680 .name = "gcc_usb3_phy_aux_clk_src",
681 .parent_data = gcc_parents_4,
682 .num_parents = ARRAY_SIZE(gcc_parents_4),
683 .ops = &clk_rcg2_ops,
684 },
685 };
686
687 static struct clk_branch gcc_ahb_pcie_link_clk = {
688 .halt_reg = 0x22004,
689 .halt_check = BRANCH_HALT,
690 .clkr = {
691 .enable_reg = 0x22004,
692 .enable_mask = BIT(0),
693 .hw.init = &(struct clk_init_data){
694 .name = "gcc_ahb_pcie_link_clk",
695 .ops = &clk_branch2_ops,
696 },
697 },
698 };
699
700 static struct clk_branch gcc_blsp1_ahb_clk = {
701 .halt_reg = 0x10004,
702 .halt_check = BRANCH_HALT_VOTED,
703 .clkr = {
704 .enable_reg = 0x6d008,
705 .enable_mask = BIT(14),
706 .hw.init = &(struct clk_init_data){
707 .name = "gcc_blsp1_ahb_clk",
708 .ops = &clk_branch2_ops,
709 },
710 },
711 };
712
713 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
714 .halt_reg = 0x11008,
715 .halt_check = BRANCH_HALT,
716 .clkr = {
717 .enable_reg = 0x11008,
718 .enable_mask = BIT(0),
719 .hw.init = &(struct clk_init_data){
720 .name = "gcc_blsp1_qup1_i2c_apps_clk",
721 .parent_hws = (const struct clk_hw *[]){
722 &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw },
723 .num_parents = 1,
724 .flags = CLK_SET_RATE_PARENT,
725 .ops = &clk_branch2_ops,
726 },
727 },
728 };
729
730 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
731 .halt_reg = 0x11004,
732 .halt_check = BRANCH_HALT,
733 .clkr = {
734 .enable_reg = 0x11004,
735 .enable_mask = BIT(0),
736 .hw.init = &(struct clk_init_data){
737 .name = "gcc_blsp1_qup1_spi_apps_clk",
738 .parent_hws = (const struct clk_hw *[]){
739 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw },
740 .num_parents = 1,
741 .flags = CLK_SET_RATE_PARENT,
742 .ops = &clk_branch2_ops,
743 },
744 },
745 };
746
747 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
748 .halt_reg = 0x13008,
749 .halt_check = BRANCH_HALT,
750 .clkr = {
751 .enable_reg = 0x13008,
752 .enable_mask = BIT(0),
753 .hw.init = &(struct clk_init_data){
754 .name = "gcc_blsp1_qup2_i2c_apps_clk",
755 .parent_hws = (const struct clk_hw *[]){
756 &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw },
757 .num_parents = 1,
758 .flags = CLK_SET_RATE_PARENT,
759 .ops = &clk_branch2_ops,
760 },
761 },
762 };
763
764 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
765 .halt_reg = 0x13004,
766 .halt_check = BRANCH_HALT,
767 .clkr = {
768 .enable_reg = 0x13004,
769 .enable_mask = BIT(0),
770 .hw.init = &(struct clk_init_data){
771 .name = "gcc_blsp1_qup2_spi_apps_clk",
772 .parent_hws = (const struct clk_hw *[]){
773 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw },
774 .num_parents = 1,
775 .flags = CLK_SET_RATE_PARENT,
776 .ops = &clk_branch2_ops,
777 },
778 },
779 };
780
781 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
782 .halt_reg = 0x15008,
783 .halt_check = BRANCH_HALT,
784 .clkr = {
785 .enable_reg = 0x15008,
786 .enable_mask = BIT(0),
787 .hw.init = &(struct clk_init_data){
788 .name = "gcc_blsp1_qup3_i2c_apps_clk",
789 .parent_hws = (const struct clk_hw *[]){
790 &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw },
791 .num_parents = 1,
792 .flags = CLK_SET_RATE_PARENT,
793 .ops = &clk_branch2_ops,
794 },
795 },
796 };
797
798 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
799 .halt_reg = 0x15004,
800 .halt_check = BRANCH_HALT,
801 .clkr = {
802 .enable_reg = 0x15004,
803 .enable_mask = BIT(0),
804 .hw.init = &(struct clk_init_data){
805 .name = "gcc_blsp1_qup3_spi_apps_clk",
806 .parent_hws = (const struct clk_hw *[]){
807 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw },
808 .num_parents = 1,
809 .flags = CLK_SET_RATE_PARENT,
810 .ops = &clk_branch2_ops,
811 },
812 },
813 };
814
815 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
816 .halt_reg = 0x17008,
817 .halt_check = BRANCH_HALT,
818 .clkr = {
819 .enable_reg = 0x17008,
820 .enable_mask = BIT(0),
821 .hw.init = &(struct clk_init_data){
822 .name = "gcc_blsp1_qup4_i2c_apps_clk",
823 .parent_hws = (const struct clk_hw *[]){
824 &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw },
825 .num_parents = 1,
826 .flags = CLK_SET_RATE_PARENT,
827 .ops = &clk_branch2_ops,
828 },
829 },
830 };
831
832 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
833 .halt_reg = 0x17004,
834 .halt_check = BRANCH_HALT,
835 .clkr = {
836 .enable_reg = 0x17004,
837 .enable_mask = BIT(0),
838 .hw.init = &(struct clk_init_data){
839 .name = "gcc_blsp1_qup4_spi_apps_clk",
840 .parent_hws = (const struct clk_hw *[]){
841 &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw },
842 .num_parents = 1,
843 .flags = CLK_SET_RATE_PARENT,
844 .ops = &clk_branch2_ops,
845 },
846 },
847 };
848
849 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
850 .halt_reg = 0x12004,
851 .halt_check = BRANCH_HALT,
852 .clkr = {
853 .enable_reg = 0x12004,
854 .enable_mask = BIT(0),
855 .hw.init = &(struct clk_init_data){
856 .name = "gcc_blsp1_uart1_apps_clk",
857 .parent_hws = (const struct clk_hw *[]){
858 &gcc_blsp1_uart1_apps_clk_src.clkr.hw },
859 .num_parents = 1,
860 .flags = CLK_SET_RATE_PARENT,
861 .ops = &clk_branch2_ops,
862 },
863 },
864 };
865
866 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
867 .halt_reg = 0x14004,
868 .halt_check = BRANCH_HALT,
869 .clkr = {
870 .enable_reg = 0x14004,
871 .enable_mask = BIT(0),
872 .hw.init = &(struct clk_init_data){
873 .name = "gcc_blsp1_uart2_apps_clk",
874 .parent_hws = (const struct clk_hw *[]){
875 &gcc_blsp1_uart2_apps_clk_src.clkr.hw },
876 .num_parents = 1,
877 .flags = CLK_SET_RATE_PARENT,
878 .ops = &clk_branch2_ops,
879 },
880 },
881 };
882
883 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
884 .halt_reg = 0x16004,
885 .halt_check = BRANCH_HALT,
886 .clkr = {
887 .enable_reg = 0x16004,
888 .enable_mask = BIT(0),
889 .hw.init = &(struct clk_init_data){
890 .name = "gcc_blsp1_uart3_apps_clk",
891 .parent_hws = (const struct clk_hw *[]){
892 &gcc_blsp1_uart3_apps_clk_src.clkr.hw },
893 .num_parents = 1,
894 .flags = CLK_SET_RATE_PARENT,
895 .ops = &clk_branch2_ops,
896 },
897 },
898 };
899
900 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
901 .halt_reg = 0x18004,
902 .halt_check = BRANCH_HALT,
903 .clkr = {
904 .enable_reg = 0x18004,
905 .enable_mask = BIT(0),
906 .hw.init = &(struct clk_init_data){
907 .name = "gcc_blsp1_uart4_apps_clk",
908 .parent_hws = (const struct clk_hw *[]){
909 &gcc_blsp1_uart4_apps_clk_src.clkr.hw },
910 .num_parents = 1,
911 .flags = CLK_SET_RATE_PARENT,
912 .ops = &clk_branch2_ops,
913 },
914 },
915 };
916
917 static struct clk_branch gcc_boot_rom_ahb_clk = {
918 .halt_reg = 0x1c004,
919 .halt_check = BRANCH_HALT_VOTED,
920 .hwcg_reg = 0x1c004,
921 .hwcg_bit = 1,
922 .clkr = {
923 .enable_reg = 0x6d008,
924 .enable_mask = BIT(10),
925 .hw.init = &(struct clk_init_data){
926 .name = "gcc_boot_rom_ahb_clk",
927 .ops = &clk_branch2_ops,
928 },
929 },
930 };
931
932 static struct clk_branch gcc_ce1_ahb_clk = {
933 .halt_reg = 0x2100c,
934 .halt_check = BRANCH_HALT_VOTED,
935 .hwcg_reg = 0x2100c,
936 .hwcg_bit = 1,
937 .clkr = {
938 .enable_reg = 0x6d008,
939 .enable_mask = BIT(3),
940 .hw.init = &(struct clk_init_data){
941 .name = "gcc_ce1_ahb_clk",
942 .ops = &clk_branch2_ops,
943 },
944 },
945 };
946
947 static struct clk_branch gcc_ce1_axi_clk = {
948 .halt_reg = 0x21008,
949 .halt_check = BRANCH_HALT_VOTED,
950 .clkr = {
951 .enable_reg = 0x6d008,
952 .enable_mask = BIT(4),
953 .hw.init = &(struct clk_init_data){
954 .name = "gcc_ce1_axi_clk",
955 .ops = &clk_branch2_ops,
956 },
957 },
958 };
959
960 static struct clk_branch gcc_ce1_clk = {
961 .halt_reg = 0x21004,
962 .halt_check = BRANCH_HALT_VOTED,
963 .clkr = {
964 .enable_reg = 0x6d008,
965 .enable_mask = BIT(5),
966 .hw.init = &(struct clk_init_data){
967 .name = "gcc_ce1_clk",
968 .ops = &clk_branch2_ops,
969 },
970 },
971 };
972
973 static struct clk_branch gcc_cpuss_rbcpr_clk = {
974 .halt_reg = 0x24008,
975 .halt_check = BRANCH_HALT,
976 .clkr = {
977 .enable_reg = 0x24008,
978 .enable_mask = BIT(0),
979 .hw.init = &(struct clk_init_data){
980 .name = "gcc_cpuss_rbcpr_clk",
981 .parent_hws = (const struct clk_hw *[]){
982 &gcc_cpuss_rbcpr_clk_src.clkr.hw },
983 .num_parents = 1,
984 .flags = CLK_SET_RATE_PARENT,
985 .ops = &clk_branch2_ops,
986 },
987 },
988 };
989
990 static struct clk_branch gcc_eth_axi_clk = {
991 .halt_reg = 0x4701c,
992 .halt_check = BRANCH_HALT,
993 .clkr = {
994 .enable_reg = 0x4701c,
995 .enable_mask = BIT(0),
996 .hw.init = &(struct clk_init_data){
997 .name = "gcc_eth_axi_clk",
998 .ops = &clk_branch2_ops,
999 },
1000 },
1001 };
1002
1003 static struct clk_branch gcc_eth_ptp_clk = {
1004 .halt_reg = 0x47018,
1005 .halt_check = BRANCH_HALT,
1006 .clkr = {
1007 .enable_reg = 0x47018,
1008 .enable_mask = BIT(0),
1009 .hw.init = &(struct clk_init_data){
1010 .name = "gcc_eth_ptp_clk",
1011 .parent_hws = (const struct clk_hw *[]){
1012 &gcc_emac_ptp_clk_src.clkr.hw },
1013 .num_parents = 1,
1014 .flags = CLK_SET_RATE_PARENT,
1015 .ops = &clk_branch2_ops,
1016 },
1017 },
1018 };
1019
1020 static struct clk_branch gcc_eth_rgmii_clk = {
1021 .halt_reg = 0x47010,
1022 .halt_check = BRANCH_HALT,
1023 .clkr = {
1024 .enable_reg = 0x47010,
1025 .enable_mask = BIT(0),
1026 .hw.init = &(struct clk_init_data){
1027 .name = "gcc_eth_rgmii_clk",
1028 .parent_hws = (const struct clk_hw *[]){
1029 &gcc_emac_clk_src.clkr.hw },
1030 .num_parents = 1,
1031 .flags = CLK_SET_RATE_PARENT,
1032 .ops = &clk_branch2_ops,
1033 },
1034 },
1035 };
1036
1037 static struct clk_branch gcc_eth_slave_ahb_clk = {
1038 .halt_reg = 0x47014,
1039 .halt_check = BRANCH_HALT,
1040 .clkr = {
1041 .enable_reg = 0x47014,
1042 .enable_mask = BIT(0),
1043 .hw.init = &(struct clk_init_data){
1044 .name = "gcc_eth_slave_ahb_clk",
1045 .ops = &clk_branch2_ops,
1046 },
1047 },
1048 };
1049
1050 static struct clk_branch gcc_gp1_clk = {
1051 .halt_reg = 0x2b000,
1052 .halt_check = BRANCH_HALT,
1053 .clkr = {
1054 .enable_reg = 0x2b000,
1055 .enable_mask = BIT(0),
1056 .hw.init = &(struct clk_init_data){
1057 .name = "gcc_gp1_clk",
1058 .parent_hws = (const struct clk_hw *[]){
1059 &gcc_gp1_clk_src.clkr.hw },
1060 .num_parents = 1,
1061 .flags = CLK_SET_RATE_PARENT,
1062 .ops = &clk_branch2_ops,
1063 },
1064 },
1065 };
1066
1067 static struct clk_branch gcc_gp2_clk = {
1068 .halt_reg = 0x2c000,
1069 .halt_check = BRANCH_HALT,
1070 .clkr = {
1071 .enable_reg = 0x2c000,
1072 .enable_mask = BIT(0),
1073 .hw.init = &(struct clk_init_data){
1074 .name = "gcc_gp2_clk",
1075 .parent_hws = (const struct clk_hw *[]){
1076 &gcc_gp2_clk_src.clkr.hw },
1077 .num_parents = 1,
1078 .flags = CLK_SET_RATE_PARENT,
1079 .ops = &clk_branch2_ops,
1080 },
1081 },
1082 };
1083
1084 static struct clk_branch gcc_gp3_clk = {
1085 .halt_reg = 0x2d000,
1086 .halt_check = BRANCH_HALT,
1087 .clkr = {
1088 .enable_reg = 0x2d000,
1089 .enable_mask = BIT(0),
1090 .hw.init = &(struct clk_init_data){
1091 .name = "gcc_gp3_clk",
1092 .parent_hws = (const struct clk_hw *[]){
1093 &gcc_gp3_clk_src.clkr.hw },
1094 .num_parents = 1,
1095 .flags = CLK_SET_RATE_PARENT,
1096 .ops = &clk_branch2_ops,
1097 },
1098 },
1099 };
1100
1101 static struct clk_branch gcc_pcie_0_clkref_clk = {
1102 .halt_reg = 0x88004,
1103 .halt_check = BRANCH_HALT_DELAY,
1104 .clkr = {
1105 .enable_reg = 0x88004,
1106 .enable_mask = BIT(0),
1107 .hw.init = &(struct clk_init_data){
1108 .name = "gcc_pcie_0_clkref_clk",
1109 .ops = &clk_branch2_ops,
1110 },
1111 },
1112 };
1113
1114 static struct clk_branch gcc_pcie_aux_clk = {
1115 .halt_reg = 0x37024,
1116 .halt_check = BRANCH_HALT_DELAY,
1117 .clkr = {
1118 .enable_reg = 0x6d010,
1119 .enable_mask = BIT(3),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "gcc_pcie_aux_clk",
1122 .ops = &clk_branch2_ops,
1123 },
1124 },
1125 };
1126
1127 static struct clk_branch gcc_pcie_cfg_ahb_clk = {
1128 .halt_reg = 0x3701c,
1129 .halt_check = BRANCH_HALT_VOTED,
1130 .clkr = {
1131 .enable_reg = 0x6d010,
1132 .enable_mask = BIT(2),
1133 .hw.init = &(struct clk_init_data){
1134 .name = "gcc_pcie_cfg_ahb_clk",
1135 .ops = &clk_branch2_ops,
1136 },
1137 },
1138 };
1139
1140 static struct clk_branch gcc_pcie_mstr_axi_clk = {
1141 .halt_reg = 0x37018,
1142 .halt_check = BRANCH_HALT_VOTED,
1143 .clkr = {
1144 .enable_reg = 0x6d010,
1145 .enable_mask = BIT(1),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "gcc_pcie_mstr_axi_clk",
1148 .ops = &clk_branch2_ops,
1149 },
1150 },
1151 };
1152
1153 static struct clk_branch gcc_pcie_pipe_clk = {
1154 .halt_reg = 0x3702c,
1155 .halt_check = BRANCH_HALT_DELAY,
1156 .clkr = {
1157 .enable_reg = 0x6d010,
1158 .enable_mask = BIT(4),
1159 .hw.init = &(struct clk_init_data){
1160 .name = "gcc_pcie_pipe_clk",
1161 .ops = &clk_branch2_ops,
1162 },
1163 },
1164 };
1165
1166 static struct clk_branch gcc_pcie_rchng_phy_clk = {
1167 .halt_reg = 0x37020,
1168 .halt_check = BRANCH_HALT_VOTED,
1169 .clkr = {
1170 .enable_reg = 0x6d010,
1171 .enable_mask = BIT(7),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "gcc_pcie_rchng_phy_clk",
1174 .parent_hws = (const struct clk_hw *[]){
1175 &gcc_pcie_rchng_phy_clk_src.clkr.hw },
1176 .num_parents = 1,
1177 .flags = CLK_SET_RATE_PARENT,
1178 .ops = &clk_branch2_ops,
1179 },
1180 },
1181 };
1182
1183 static struct clk_branch gcc_pcie_sleep_clk = {
1184 .halt_reg = 0x37028,
1185 .halt_check = BRANCH_HALT_VOTED,
1186 .clkr = {
1187 .enable_reg = 0x6d010,
1188 .enable_mask = BIT(6),
1189 .hw.init = &(struct clk_init_data){
1190 .name = "gcc_pcie_sleep_clk",
1191 .parent_hws = (const struct clk_hw *[]){
1192 &gcc_pcie_aux_phy_clk_src.clkr.hw },
1193 .num_parents = 1,
1194 .flags = CLK_SET_RATE_PARENT,
1195 .ops = &clk_branch2_ops,
1196 },
1197 },
1198 };
1199
1200 static struct clk_branch gcc_pcie_slv_axi_clk = {
1201 .halt_reg = 0x37014,
1202 .halt_check = BRANCH_HALT_VOTED,
1203 .hwcg_reg = 0x37014,
1204 .hwcg_bit = 1,
1205 .clkr = {
1206 .enable_reg = 0x6d010,
1207 .enable_mask = BIT(0),
1208 .hw.init = &(struct clk_init_data){
1209 .name = "gcc_pcie_slv_axi_clk",
1210 .ops = &clk_branch2_ops,
1211 },
1212 },
1213 };
1214
1215 static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
1216 .halt_reg = 0x37010,
1217 .halt_check = BRANCH_HALT_VOTED,
1218 .clkr = {
1219 .enable_reg = 0x6d010,
1220 .enable_mask = BIT(5),
1221 .hw.init = &(struct clk_init_data){
1222 .name = "gcc_pcie_slv_q2a_axi_clk",
1223 .ops = &clk_branch2_ops,
1224 },
1225 },
1226 };
1227
1228 static struct clk_branch gcc_pdm2_clk = {
1229 .halt_reg = 0x1900c,
1230 .halt_check = BRANCH_HALT,
1231 .clkr = {
1232 .enable_reg = 0x1900c,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data){
1235 .name = "gcc_pdm2_clk",
1236 .parent_hws = (const struct clk_hw *[]){
1237 &gcc_pdm2_clk_src.clkr.hw },
1238 .num_parents = 1,
1239 .flags = CLK_SET_RATE_PARENT,
1240 .ops = &clk_branch2_ops,
1241 },
1242 },
1243 };
1244
1245 static struct clk_branch gcc_pdm_ahb_clk = {
1246 .halt_reg = 0x19004,
1247 .halt_check = BRANCH_HALT,
1248 .hwcg_reg = 0x19004,
1249 .hwcg_bit = 1,
1250 .clkr = {
1251 .enable_reg = 0x19004,
1252 .enable_mask = BIT(0),
1253 .hw.init = &(struct clk_init_data){
1254 .name = "gcc_pdm_ahb_clk",
1255 .ops = &clk_branch2_ops,
1256 },
1257 },
1258 };
1259
1260 static struct clk_branch gcc_pdm_xo4_clk = {
1261 .halt_reg = 0x19008,
1262 .halt_check = BRANCH_HALT,
1263 .clkr = {
1264 .enable_reg = 0x19008,
1265 .enable_mask = BIT(0),
1266 .hw.init = &(struct clk_init_data){
1267 .name = "gcc_pdm_xo4_clk",
1268 .ops = &clk_branch2_ops,
1269 },
1270 },
1271 };
1272
1273 static struct clk_branch gcc_sdcc1_ahb_clk = {
1274 .halt_reg = 0xf008,
1275 .halt_check = BRANCH_HALT,
1276 .clkr = {
1277 .enable_reg = 0xf008,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gcc_sdcc1_ahb_clk",
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch gcc_sdcc1_apps_clk = {
1287 .halt_reg = 0xf004,
1288 .halt_check = BRANCH_HALT,
1289 .clkr = {
1290 .enable_reg = 0xf004,
1291 .enable_mask = BIT(0),
1292 .hw.init = &(struct clk_init_data){
1293 .name = "gcc_sdcc1_apps_clk",
1294 .parent_hws = (const struct clk_hw *[]){
1295 &gcc_sdcc1_apps_clk_src.clkr.hw },
1296 .num_parents = 1,
1297 .flags = CLK_SET_RATE_PARENT,
1298 .ops = &clk_branch2_ops,
1299 },
1300 },
1301 };
1302
1303 static struct clk_branch gcc_usb30_master_clk = {
1304 .halt_reg = 0xb010,
1305 .halt_check = BRANCH_HALT,
1306 .clkr = {
1307 .enable_reg = 0xb010,
1308 .enable_mask = BIT(0),
1309 .hw.init = &(struct clk_init_data){
1310 .name = "gcc_usb30_master_clk",
1311 .parent_hws = (const struct clk_hw *[]){
1312 &gcc_usb30_master_clk_src.clkr.hw },
1313 .num_parents = 1,
1314 .flags = CLK_SET_RATE_PARENT,
1315 .ops = &clk_branch2_ops,
1316 },
1317 },
1318 };
1319
1320 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1321 .halt_reg = 0xb020,
1322 .halt_check = BRANCH_HALT,
1323 .clkr = {
1324 .enable_reg = 0xb020,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "gcc_usb30_mock_utmi_clk",
1328 .parent_hws = (const struct clk_hw *[]){
1329 &gcc_usb30_mock_utmi_clk_src.clkr.hw },
1330 .num_parents = 1,
1331 .flags = CLK_SET_RATE_PARENT,
1332 .ops = &clk_branch2_ops,
1333 },
1334 },
1335 };
1336
1337 static struct clk_branch gcc_usb30_mstr_axi_clk = {
1338 .halt_reg = 0xb014,
1339 .halt_check = BRANCH_HALT,
1340 .clkr = {
1341 .enable_reg = 0xb014,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "gcc_usb30_mstr_axi_clk",
1345 .ops = &clk_branch2_ops,
1346 },
1347 },
1348 };
1349
1350 static struct clk_branch gcc_usb30_sleep_clk = {
1351 .halt_reg = 0xb01c,
1352 .halt_check = BRANCH_HALT,
1353 .clkr = {
1354 .enable_reg = 0xb01c,
1355 .enable_mask = BIT(0),
1356 .hw.init = &(struct clk_init_data){
1357 .name = "gcc_usb30_sleep_clk",
1358 .ops = &clk_branch2_ops,
1359 },
1360 },
1361 };
1362
1363 static struct clk_branch gcc_usb30_slv_ahb_clk = {
1364 .halt_reg = 0xb018,
1365 .halt_check = BRANCH_HALT,
1366 .clkr = {
1367 .enable_reg = 0xb018,
1368 .enable_mask = BIT(0),
1369 .hw.init = &(struct clk_init_data){
1370 .name = "gcc_usb30_slv_ahb_clk",
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374 };
1375
1376 static struct clk_branch gcc_usb3_phy_aux_clk = {
1377 .halt_reg = 0xb058,
1378 .halt_check = BRANCH_HALT,
1379 .clkr = {
1380 .enable_reg = 0xb058,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "gcc_usb3_phy_aux_clk",
1384 .parent_hws = (const struct clk_hw *[]){
1385 &gcc_usb3_phy_aux_clk_src.clkr.hw },
1386 .num_parents = 1,
1387 .flags = CLK_SET_RATE_PARENT,
1388 .ops = &clk_branch2_ops,
1389 },
1390 },
1391 };
1392
1393 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1394 .halt_reg = 0xb05c,
1395 .halt_check = BRANCH_HALT_DELAY,
1396 .clkr = {
1397 .enable_reg = 0xb05c,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "gcc_usb3_phy_pipe_clk",
1401 .ops = &clk_branch2_ops,
1402 },
1403 },
1404 };
1405
1406 static struct clk_branch gcc_usb3_prim_clkref_clk = {
1407 .halt_reg = 0x88000,
1408 .halt_check = BRANCH_HALT_DELAY,
1409 .clkr = {
1410 .enable_reg = 0x88000,
1411 .enable_mask = BIT(0),
1412 .hw.init = &(struct clk_init_data){
1413 .name = "gcc_usb3_prim_clkref_clk",
1414 .ops = &clk_branch2_ops,
1415 },
1416 },
1417 };
1418
1419 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1420 .halt_reg = 0xe004,
1421 .halt_check = BRANCH_HALT,
1422 .hwcg_reg = 0xe004,
1423 .hwcg_bit = 1,
1424 .clkr = {
1425 .enable_reg = 0xe004,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1429 .ops = &clk_branch2_ops,
1430 },
1431 },
1432 };
1433
1434 static struct clk_branch gcc_xo_pcie_link_clk = {
1435 .halt_reg = 0x22008,
1436 .halt_check = BRANCH_HALT,
1437 .clkr = {
1438 .enable_reg = 0x22008,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "gcc_xo_pcie_link_clk",
1442 .ops = &clk_branch2_ops,
1443 },
1444 },
1445 };
1446
1447 static struct gdsc usb30_gdsc = {
1448 .gdscr = 0x0b004,
1449 .pd = {
1450 .name = "usb30_gdsc",
1451 },
1452 .pwrsts = PWRSTS_OFF_ON,
1453 };
1454
1455 static struct gdsc pcie_gdsc = {
1456 .gdscr = 0x37004,
1457 .pd = {
1458 .name = "pcie_gdsc",
1459 },
1460 .pwrsts = PWRSTS_OFF_ON,
1461 };
1462
1463 static struct gdsc emac_gdsc = {
1464 .gdscr = 0x47004,
1465 .pd = {
1466 .name = "emac_gdsc",
1467 },
1468 .pwrsts = PWRSTS_OFF_ON,
1469 };
1470
1471 static struct clk_regmap *gcc_sdx55_clocks[] = {
1472 [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
1473 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1474 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1475 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] =
1476 &gcc_blsp1_qup1_i2c_apps_clk_src.clkr,
1477 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1478 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] =
1479 &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
1480 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1481 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] =
1482 &gcc_blsp1_qup2_i2c_apps_clk_src.clkr,
1483 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1484 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] =
1485 &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
1486 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
1487 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] =
1488 &gcc_blsp1_qup3_i2c_apps_clk_src.clkr,
1489 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
1490 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] =
1491 &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
1492 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
1493 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] =
1494 &gcc_blsp1_qup4_i2c_apps_clk_src.clkr,
1495 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
1496 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] =
1497 &gcc_blsp1_qup4_spi_apps_clk_src.clkr,
1498 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1499 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
1500 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1501 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
1502 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
1503 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
1504 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
1505 [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr,
1506 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1507 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
1508 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
1509 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
1510 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
1511 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
1512 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
1513 [GCC_EMAC_CLK_SRC] = &gcc_emac_clk_src.clkr,
1514 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
1515 [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
1516 [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
1517 [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
1518 [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
1519 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1520 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
1521 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1522 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
1523 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1524 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
1525 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
1526 [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
1527 [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
1528 [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
1529 [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
1530 [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
1531 [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
1532 [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
1533 [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
1534 [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
1535 [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
1536 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1537 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
1538 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1539 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
1540 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1541 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1542 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
1543 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
1544 [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
1545 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
1546 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
1547 [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
1548 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
1549 [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
1550 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
1551 [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
1552 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
1553 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
1554 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
1555 [GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr,
1556 [GPLL0] = &gpll0.clkr,
1557 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
1558 [GPLL4] = &gpll4.clkr,
1559 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
1560 [GPLL5] = &gpll5.clkr,
1561 };
1562
1563 static const struct qcom_reset_map gcc_sdx55_resets[] = {
1564 [GCC_EMAC_BCR] = { 0x47000 },
1565 [GCC_PCIE_BCR] = { 0x37000 },
1566 [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1567 [GCC_PCIE_PHY_BCR] = { 0x39000 },
1568 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1569 [GCC_QUSB2PHY_BCR] = { 0xd000 },
1570 [GCC_USB30_BCR] = { 0xb000 },
1571 [GCC_USB3_PHY_BCR] = { 0xc000 },
1572 [GCC_USB3PHY_PHY_BCR] = { 0xc004 },
1573 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
1574 };
1575
1576 static struct gdsc *gcc_sdx55_gdscs[] = {
1577 [USB30_GDSC] = &usb30_gdsc,
1578 [PCIE_GDSC] = &pcie_gdsc,
1579 [EMAC_GDSC] = &emac_gdsc,
1580 };
1581
1582 static const struct regmap_config gcc_sdx55_regmap_config = {
1583 .reg_bits = 32,
1584 .reg_stride = 4,
1585 .val_bits = 32,
1586 .max_register = 0x9b040,
1587 .fast_io = true,
1588 };
1589
1590 static const struct qcom_cc_desc gcc_sdx55_desc = {
1591 .config = &gcc_sdx55_regmap_config,
1592 .clks = gcc_sdx55_clocks,
1593 .num_clks = ARRAY_SIZE(gcc_sdx55_clocks),
1594 .resets = gcc_sdx55_resets,
1595 .num_resets = ARRAY_SIZE(gcc_sdx55_resets),
1596 .gdscs = gcc_sdx55_gdscs,
1597 .num_gdscs = ARRAY_SIZE(gcc_sdx55_gdscs),
1598 };
1599
1600 static const struct of_device_id gcc_sdx55_match_table[] = {
1601 { .compatible = "qcom,gcc-sdx55" },
1602 { }
1603 };
1604 MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table);
1605
gcc_sdx55_probe(struct platform_device * pdev)1606 static int gcc_sdx55_probe(struct platform_device *pdev)
1607 {
1608 struct regmap *regmap;
1609
1610 regmap = qcom_cc_map(pdev, &gcc_sdx55_desc);
1611 if (IS_ERR(regmap))
1612 return PTR_ERR(regmap);
1613
1614 /*
1615 * Keep the clocks always-ON as they are critical to the functioning
1616 * of the system:
1617 * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK
1618 */
1619 regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
1620 regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
1621 regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
1622
1623 return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap);
1624 }
1625
1626 static struct platform_driver gcc_sdx55_driver = {
1627 .probe = gcc_sdx55_probe,
1628 .driver = {
1629 .name = "gcc-sdx55",
1630 .of_match_table = gcc_sdx55_match_table,
1631 },
1632 };
1633
gcc_sdx55_init(void)1634 static int __init gcc_sdx55_init(void)
1635 {
1636 return platform_driver_register(&gcc_sdx55_driver);
1637 }
1638 subsys_initcall(gcc_sdx55_init);
1639
gcc_sdx55_exit(void)1640 static void __exit gcc_sdx55_exit(void)
1641 {
1642 platform_driver_unregister(&gcc_sdx55_driver);
1643 }
1644 module_exit(gcc_sdx55_exit);
1645
1646 MODULE_DESCRIPTION("QTI GCC SDX55 Driver");
1647 MODULE_LICENSE("GPL v2");
1648