1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
4  * All rights reserved.
5  *
6  * Author: Li Yang <leoli@freescale.com>
7  *         Jiang Bo <tanya.jiang@freescale.com>
8  *
9  * Description:
10  * Freescale high-speed USB SOC DR module device controller driver.
11  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
12  * The driver is previously named as mpc_udc.  Based on bare board
13  * code from Dave Liu and Shlomi Gridish.
14  */
15 
16 #undef VERBOSE
17 
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/interrupt.h>
28 #include <linux/proc_fs.h>
29 #include <linux/mm.h>
30 #include <linux/moduleparam.h>
31 #include <linux/device.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_device.h>
37 #include <linux/fsl_devices.h>
38 #include <linux/dmapool.h>
39 
40 #include <asm/byteorder.h>
41 #include <asm/io.h>
42 #include <asm/unaligned.h>
43 #include <asm/dma.h>
44 
45 #include "fsl_usb2_udc.h"
46 
47 #define	DRIVER_DESC	"Freescale High-Speed USB SOC Device Controller driver"
48 #define	DRIVER_AUTHOR	"Li Yang/Jiang Bo"
49 #define	DRIVER_VERSION	"Apr 20, 2007"
50 
51 #define	DMA_ADDR_INVALID	(~(dma_addr_t)0)
52 
53 static const char driver_name[] = "fsl-usb2-udc";
54 
55 static struct usb_dr_device __iomem *dr_regs;
56 
57 static struct usb_sys_interface __iomem *usb_sys_regs;
58 
59 /* it is initialized in probe()  */
60 static struct fsl_udc *udc_controller = NULL;
61 
62 static const struct usb_endpoint_descriptor
63 fsl_ep0_desc = {
64 	.bLength =		USB_DT_ENDPOINT_SIZE,
65 	.bDescriptorType =	USB_DT_ENDPOINT,
66 	.bEndpointAddress =	0,
67 	.bmAttributes =		USB_ENDPOINT_XFER_CONTROL,
68 	.wMaxPacketSize =	USB_MAX_CTRL_PAYLOAD,
69 };
70 
71 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
72 
73 #ifdef CONFIG_PPC32
74 /*
75  * On some SoCs, the USB controller registers can be big or little endian,
76  * depending on the version of the chip. In order to be able to run the
77  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
78  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
79  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
80  * call through those pointers. Platform code for SoCs that have BE USB
81  * registers should set pdata->big_endian_mmio flag.
82  *
83  * This also applies to controller-to-cpu accessors for the USB descriptors,
84  * since their endianness is also SoC dependant. Platform code for SoCs that
85  * have BE USB descriptors should set pdata->big_endian_desc flag.
86  */
_fsl_readl_be(const unsigned __iomem * p)87 static u32 _fsl_readl_be(const unsigned __iomem *p)
88 {
89 	return in_be32(p);
90 }
91 
_fsl_readl_le(const unsigned __iomem * p)92 static u32 _fsl_readl_le(const unsigned __iomem *p)
93 {
94 	return in_le32(p);
95 }
96 
_fsl_writel_be(u32 v,unsigned __iomem * p)97 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
98 {
99 	out_be32(p, v);
100 }
101 
_fsl_writel_le(u32 v,unsigned __iomem * p)102 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
103 {
104 	out_le32(p, v);
105 }
106 
107 static u32 (*_fsl_readl)(const unsigned __iomem *p);
108 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
109 
110 #define fsl_readl(p)		(*_fsl_readl)((p))
111 #define fsl_writel(v, p)	(*_fsl_writel)((v), (p))
112 
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)113 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
114 {
115 	if (pdata->big_endian_mmio) {
116 		_fsl_readl = _fsl_readl_be;
117 		_fsl_writel = _fsl_writel_be;
118 	} else {
119 		_fsl_readl = _fsl_readl_le;
120 		_fsl_writel = _fsl_writel_le;
121 	}
122 }
123 
cpu_to_hc32(const u32 x)124 static inline u32 cpu_to_hc32(const u32 x)
125 {
126 	return udc_controller->pdata->big_endian_desc
127 		? (__force u32)cpu_to_be32(x)
128 		: (__force u32)cpu_to_le32(x);
129 }
130 
hc32_to_cpu(const u32 x)131 static inline u32 hc32_to_cpu(const u32 x)
132 {
133 	return udc_controller->pdata->big_endian_desc
134 		? be32_to_cpu((__force __be32)x)
135 		: le32_to_cpu((__force __le32)x);
136 }
137 #else /* !CONFIG_PPC32 */
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)138 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
139 
140 #define fsl_readl(addr)		readl(addr)
141 #define fsl_writel(val32, addr) writel(val32, addr)
142 #define cpu_to_hc32(x)		cpu_to_le32(x)
143 #define hc32_to_cpu(x)		le32_to_cpu(x)
144 #endif /* CONFIG_PPC32 */
145 
146 /********************************************************************
147  *	Internal Used Function
148 ********************************************************************/
149 /*-----------------------------------------------------------------
150  * done() - retire a request; caller blocked irqs
151  * @status : request status to be set, only works when
152  *	request is still in progress.
153  *--------------------------------------------------------------*/
done(struct fsl_ep * ep,struct fsl_req * req,int status)154 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
155 __releases(ep->udc->lock)
156 __acquires(ep->udc->lock)
157 {
158 	struct fsl_udc *udc = NULL;
159 	unsigned char stopped = ep->stopped;
160 	struct ep_td_struct *curr_td, *next_td;
161 	int j;
162 
163 	udc = (struct fsl_udc *)ep->udc;
164 	/* Removed the req from fsl_ep->queue */
165 	list_del_init(&req->queue);
166 
167 	/* req.status should be set as -EINPROGRESS in ep_queue() */
168 	if (req->req.status == -EINPROGRESS)
169 		req->req.status = status;
170 	else
171 		status = req->req.status;
172 
173 	/* Free dtd for the request */
174 	next_td = req->head;
175 	for (j = 0; j < req->dtd_count; j++) {
176 		curr_td = next_td;
177 		if (j != req->dtd_count - 1) {
178 			next_td = curr_td->next_td_virt;
179 		}
180 		dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
181 	}
182 
183 	usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
184 
185 	if (status && (status != -ESHUTDOWN))
186 		VDBG("complete %s req %p stat %d len %u/%u",
187 			ep->ep.name, &req->req, status,
188 			req->req.actual, req->req.length);
189 
190 	ep->stopped = 1;
191 
192 	spin_unlock(&ep->udc->lock);
193 
194 	usb_gadget_giveback_request(&ep->ep, &req->req);
195 
196 	spin_lock(&ep->udc->lock);
197 	ep->stopped = stopped;
198 }
199 
200 /*-----------------------------------------------------------------
201  * nuke(): delete all requests related to this ep
202  * called with spinlock held
203  *--------------------------------------------------------------*/
nuke(struct fsl_ep * ep,int status)204 static void nuke(struct fsl_ep *ep, int status)
205 {
206 	ep->stopped = 1;
207 
208 	/* Flush fifo */
209 	fsl_ep_fifo_flush(&ep->ep);
210 
211 	/* Whether this eq has request linked */
212 	while (!list_empty(&ep->queue)) {
213 		struct fsl_req *req = NULL;
214 
215 		req = list_entry(ep->queue.next, struct fsl_req, queue);
216 		done(ep, req, status);
217 	}
218 }
219 
220 /*------------------------------------------------------------------
221 	Internal Hardware related function
222  ------------------------------------------------------------------*/
223 
dr_controller_setup(struct fsl_udc * udc)224 static int dr_controller_setup(struct fsl_udc *udc)
225 {
226 	unsigned int tmp, portctrl, ep_num;
227 	unsigned int max_no_of_ep;
228 	unsigned int ctrl;
229 	unsigned long timeout;
230 
231 #define FSL_UDC_RESET_TIMEOUT 1000
232 
233 	/* Config PHY interface */
234 	portctrl = fsl_readl(&dr_regs->portsc1);
235 	portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
236 	switch (udc->phy_mode) {
237 	case FSL_USB2_PHY_ULPI:
238 		if (udc->pdata->have_sysif_regs) {
239 			if (udc->pdata->controller_ver) {
240 				/* controller version 1.6 or above */
241 				ctrl = __raw_readl(&usb_sys_regs->control);
242 				ctrl &= ~USB_CTRL_UTMI_PHY_EN;
243 				ctrl |= USB_CTRL_USB_EN;
244 				__raw_writel(ctrl, &usb_sys_regs->control);
245 			}
246 		}
247 		portctrl |= PORTSCX_PTS_ULPI;
248 		break;
249 	case FSL_USB2_PHY_UTMI_WIDE:
250 		portctrl |= PORTSCX_PTW_16BIT;
251 		fallthrough;
252 	case FSL_USB2_PHY_UTMI:
253 	case FSL_USB2_PHY_UTMI_DUAL:
254 		if (udc->pdata->have_sysif_regs) {
255 			if (udc->pdata->controller_ver) {
256 				/* controller version 1.6 or above */
257 				ctrl = __raw_readl(&usb_sys_regs->control);
258 				ctrl |= (USB_CTRL_UTMI_PHY_EN |
259 					USB_CTRL_USB_EN);
260 				__raw_writel(ctrl, &usb_sys_regs->control);
261 				mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
262 					PHY CLK to become stable - 10ms*/
263 			}
264 		}
265 		portctrl |= PORTSCX_PTS_UTMI;
266 		break;
267 	case FSL_USB2_PHY_SERIAL:
268 		portctrl |= PORTSCX_PTS_FSLS;
269 		break;
270 	default:
271 		return -EINVAL;
272 	}
273 	fsl_writel(portctrl, &dr_regs->portsc1);
274 
275 	/* Stop and reset the usb controller */
276 	tmp = fsl_readl(&dr_regs->usbcmd);
277 	tmp &= ~USB_CMD_RUN_STOP;
278 	fsl_writel(tmp, &dr_regs->usbcmd);
279 
280 	tmp = fsl_readl(&dr_regs->usbcmd);
281 	tmp |= USB_CMD_CTRL_RESET;
282 	fsl_writel(tmp, &dr_regs->usbcmd);
283 
284 	/* Wait for reset to complete */
285 	timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
286 	while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
287 		if (time_after(jiffies, timeout)) {
288 			ERR("udc reset timeout!\n");
289 			return -ETIMEDOUT;
290 		}
291 		cpu_relax();
292 	}
293 
294 	/* Set the controller as device mode */
295 	tmp = fsl_readl(&dr_regs->usbmode);
296 	tmp &= ~USB_MODE_CTRL_MODE_MASK;	/* clear mode bits */
297 	tmp |= USB_MODE_CTRL_MODE_DEVICE;
298 	/* Disable Setup Lockout */
299 	tmp |= USB_MODE_SETUP_LOCK_OFF;
300 	if (udc->pdata->es)
301 		tmp |= USB_MODE_ES;
302 	fsl_writel(tmp, &dr_regs->usbmode);
303 
304 	/* Clear the setup status */
305 	fsl_writel(0, &dr_regs->usbsts);
306 
307 	tmp = udc->ep_qh_dma;
308 	tmp &= USB_EP_LIST_ADDRESS_MASK;
309 	fsl_writel(tmp, &dr_regs->endpointlistaddr);
310 
311 	VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
312 		udc->ep_qh, (int)tmp,
313 		fsl_readl(&dr_regs->endpointlistaddr));
314 
315 	max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
316 	for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
317 		tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
318 		tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
319 		tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
320 		| (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
321 		fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
322 	}
323 	/* Config control enable i/o output, cpu endian register */
324 	if (udc->pdata->have_sysif_regs) {
325 		ctrl = __raw_readl(&usb_sys_regs->control);
326 		ctrl |= USB_CTRL_IOENB;
327 		__raw_writel(ctrl, &usb_sys_regs->control);
328 	}
329 
330 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
331 	/* Turn on cache snooping hardware, since some PowerPC platforms
332 	 * wholly rely on hardware to deal with cache coherent. */
333 
334 	if (udc->pdata->have_sysif_regs) {
335 		/* Setup Snooping for all the 4GB space */
336 		tmp = SNOOP_SIZE_2GB;	/* starts from 0x0, size 2G */
337 		__raw_writel(tmp, &usb_sys_regs->snoop1);
338 		tmp |= 0x80000000;	/* starts from 0x8000000, size 2G */
339 		__raw_writel(tmp, &usb_sys_regs->snoop2);
340 	}
341 #endif
342 
343 	return 0;
344 }
345 
346 /* Enable DR irq and set controller to run state */
dr_controller_run(struct fsl_udc * udc)347 static void dr_controller_run(struct fsl_udc *udc)
348 {
349 	u32 temp;
350 
351 	/* Enable DR irq reg */
352 	temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
353 		| USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
354 		| USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
355 
356 	fsl_writel(temp, &dr_regs->usbintr);
357 
358 	/* Clear stopped bit */
359 	udc->stopped = 0;
360 
361 	/* Set the controller as device mode */
362 	temp = fsl_readl(&dr_regs->usbmode);
363 	temp |= USB_MODE_CTRL_MODE_DEVICE;
364 	fsl_writel(temp, &dr_regs->usbmode);
365 
366 	/* Set controller to Run */
367 	temp = fsl_readl(&dr_regs->usbcmd);
368 	temp |= USB_CMD_RUN_STOP;
369 	fsl_writel(temp, &dr_regs->usbcmd);
370 }
371 
dr_controller_stop(struct fsl_udc * udc)372 static void dr_controller_stop(struct fsl_udc *udc)
373 {
374 	unsigned int tmp;
375 
376 	pr_debug("%s\n", __func__);
377 
378 	/* if we're in OTG mode, and the Host is currently using the port,
379 	 * stop now and don't rip the controller out from under the
380 	 * ehci driver
381 	 */
382 	if (udc->gadget.is_otg) {
383 		if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
384 			pr_debug("udc: Leaving early\n");
385 			return;
386 		}
387 	}
388 
389 	/* disable all INTR */
390 	fsl_writel(0, &dr_regs->usbintr);
391 
392 	/* Set stopped bit for isr */
393 	udc->stopped = 1;
394 
395 	/* disable IO output */
396 /*	usb_sys_regs->control = 0; */
397 
398 	/* set controller to Stop */
399 	tmp = fsl_readl(&dr_regs->usbcmd);
400 	tmp &= ~USB_CMD_RUN_STOP;
401 	fsl_writel(tmp, &dr_regs->usbcmd);
402 }
403 
dr_ep_setup(unsigned char ep_num,unsigned char dir,unsigned char ep_type)404 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
405 			unsigned char ep_type)
406 {
407 	unsigned int tmp_epctrl = 0;
408 
409 	tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
410 	if (dir) {
411 		if (ep_num)
412 			tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
413 		tmp_epctrl |= EPCTRL_TX_ENABLE;
414 		tmp_epctrl &= ~EPCTRL_TX_TYPE;
415 		tmp_epctrl |= ((unsigned int)(ep_type)
416 				<< EPCTRL_TX_EP_TYPE_SHIFT);
417 	} else {
418 		if (ep_num)
419 			tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
420 		tmp_epctrl |= EPCTRL_RX_ENABLE;
421 		tmp_epctrl &= ~EPCTRL_RX_TYPE;
422 		tmp_epctrl |= ((unsigned int)(ep_type)
423 				<< EPCTRL_RX_EP_TYPE_SHIFT);
424 	}
425 
426 	fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
427 }
428 
429 static void
dr_ep_change_stall(unsigned char ep_num,unsigned char dir,int value)430 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
431 {
432 	u32 tmp_epctrl = 0;
433 
434 	tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
435 
436 	if (value) {
437 		/* set the stall bit */
438 		if (dir)
439 			tmp_epctrl |= EPCTRL_TX_EP_STALL;
440 		else
441 			tmp_epctrl |= EPCTRL_RX_EP_STALL;
442 	} else {
443 		/* clear the stall bit and reset data toggle */
444 		if (dir) {
445 			tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
446 			tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
447 		} else {
448 			tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
449 			tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
450 		}
451 	}
452 	fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
453 }
454 
455 /* Get stall status of a specific ep
456    Return: 0: not stalled; 1:stalled */
dr_ep_get_stall(unsigned char ep_num,unsigned char dir)457 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
458 {
459 	u32 epctrl;
460 
461 	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
462 	if (dir)
463 		return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
464 	else
465 		return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
466 }
467 
468 /********************************************************************
469 	Internal Structure Build up functions
470 ********************************************************************/
471 
472 /*------------------------------------------------------------------
473 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
474  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
475  * @mult: Mult field
476  ------------------------------------------------------------------*/
struct_ep_qh_setup(struct fsl_udc * udc,unsigned char ep_num,unsigned char dir,unsigned char ep_type,unsigned int max_pkt_len,unsigned int zlt,unsigned char mult)477 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
478 		unsigned char dir, unsigned char ep_type,
479 		unsigned int max_pkt_len,
480 		unsigned int zlt, unsigned char mult)
481 {
482 	struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
483 	unsigned int tmp = 0;
484 
485 	/* set the Endpoint Capabilites in QH */
486 	switch (ep_type) {
487 	case USB_ENDPOINT_XFER_CONTROL:
488 		/* Interrupt On Setup (IOS). for control ep  */
489 		tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
490 			| EP_QUEUE_HEAD_IOS;
491 		break;
492 	case USB_ENDPOINT_XFER_ISOC:
493 		tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
494 			| (mult << EP_QUEUE_HEAD_MULT_POS);
495 		break;
496 	case USB_ENDPOINT_XFER_BULK:
497 	case USB_ENDPOINT_XFER_INT:
498 		tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
499 		break;
500 	default:
501 		VDBG("error ep type is %d", ep_type);
502 		return;
503 	}
504 	if (zlt)
505 		tmp |= EP_QUEUE_HEAD_ZLT_SEL;
506 
507 	p_QH->max_pkt_length = cpu_to_hc32(tmp);
508 	p_QH->next_dtd_ptr = 1;
509 	p_QH->size_ioc_int_sts = 0;
510 }
511 
512 /* Setup qh structure and ep register for ep0. */
ep0_setup(struct fsl_udc * udc)513 static void ep0_setup(struct fsl_udc *udc)
514 {
515 	/* the initialization of an ep includes: fields in QH, Regs,
516 	 * fsl_ep struct */
517 	struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
518 			USB_MAX_CTRL_PAYLOAD, 0, 0);
519 	struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
520 			USB_MAX_CTRL_PAYLOAD, 0, 0);
521 	dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
522 	dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
523 
524 	return;
525 
526 }
527 
528 /***********************************************************************
529 		Endpoint Management Functions
530 ***********************************************************************/
531 
532 /*-------------------------------------------------------------------------
533  * when configurations are set, or when interface settings change
534  * for example the do_set_interface() in gadget layer,
535  * the driver will enable or disable the relevant endpoints
536  * ep0 doesn't use this routine. It is always enabled.
537 -------------------------------------------------------------------------*/
fsl_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)538 static int fsl_ep_enable(struct usb_ep *_ep,
539 		const struct usb_endpoint_descriptor *desc)
540 {
541 	struct fsl_udc *udc = NULL;
542 	struct fsl_ep *ep = NULL;
543 	unsigned short max = 0;
544 	unsigned char mult = 0, zlt;
545 	int retval = -EINVAL;
546 	unsigned long flags;
547 
548 	ep = container_of(_ep, struct fsl_ep, ep);
549 
550 	/* catch various bogus parameters */
551 	if (!_ep || !desc
552 			|| (desc->bDescriptorType != USB_DT_ENDPOINT))
553 		return -EINVAL;
554 
555 	udc = ep->udc;
556 
557 	if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
558 		return -ESHUTDOWN;
559 
560 	max = usb_endpoint_maxp(desc);
561 
562 	/* Disable automatic zlp generation.  Driver is responsible to indicate
563 	 * explicitly through req->req.zero.  This is needed to enable multi-td
564 	 * request. */
565 	zlt = 1;
566 
567 	/* Assume the max packet size from gadget is always correct */
568 	switch (desc->bmAttributes & 0x03) {
569 	case USB_ENDPOINT_XFER_CONTROL:
570 	case USB_ENDPOINT_XFER_BULK:
571 	case USB_ENDPOINT_XFER_INT:
572 		/* mult = 0.  Execute N Transactions as demonstrated by
573 		 * the USB variable length packet protocol where N is
574 		 * computed using the Maximum Packet Length (dQH) and
575 		 * the Total Bytes field (dTD) */
576 		mult = 0;
577 		break;
578 	case USB_ENDPOINT_XFER_ISOC:
579 		/* Calculate transactions needed for high bandwidth iso */
580 		mult = usb_endpoint_maxp_mult(desc);
581 		/* 3 transactions at most */
582 		if (mult > 3)
583 			goto en_done;
584 		break;
585 	default:
586 		goto en_done;
587 	}
588 
589 	spin_lock_irqsave(&udc->lock, flags);
590 	ep->ep.maxpacket = max;
591 	ep->ep.desc = desc;
592 	ep->stopped = 0;
593 
594 	/* Controller related setup */
595 	/* Init EPx Queue Head (Ep Capabilites field in QH
596 	 * according to max, zlt, mult) */
597 	struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
598 			(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
599 					?  USB_SEND : USB_RECV),
600 			(unsigned char) (desc->bmAttributes
601 					& USB_ENDPOINT_XFERTYPE_MASK),
602 			max, zlt, mult);
603 
604 	/* Init endpoint ctrl register */
605 	dr_ep_setup((unsigned char) ep_index(ep),
606 			(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
607 					? USB_SEND : USB_RECV),
608 			(unsigned char) (desc->bmAttributes
609 					& USB_ENDPOINT_XFERTYPE_MASK));
610 
611 	spin_unlock_irqrestore(&udc->lock, flags);
612 	retval = 0;
613 
614 	VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
615 			ep->ep.desc->bEndpointAddress & 0x0f,
616 			(desc->bEndpointAddress & USB_DIR_IN)
617 				? "in" : "out", max);
618 en_done:
619 	return retval;
620 }
621 
622 /*---------------------------------------------------------------------
623  * @ep : the ep being unconfigured. May not be ep0
624  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
625 *---------------------------------------------------------------------*/
fsl_ep_disable(struct usb_ep * _ep)626 static int fsl_ep_disable(struct usb_ep *_ep)
627 {
628 	struct fsl_udc *udc = NULL;
629 	struct fsl_ep *ep = NULL;
630 	unsigned long flags;
631 	u32 epctrl;
632 	int ep_num;
633 
634 	ep = container_of(_ep, struct fsl_ep, ep);
635 	if (!_ep || !ep->ep.desc) {
636 		VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
637 		return -EINVAL;
638 	}
639 
640 	/* disable ep on controller */
641 	ep_num = ep_index(ep);
642 	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
643 	if (ep_is_in(ep)) {
644 		epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
645 		epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
646 	} else {
647 		epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
648 		epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
649 	}
650 	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
651 
652 	udc = (struct fsl_udc *)ep->udc;
653 	spin_lock_irqsave(&udc->lock, flags);
654 
655 	/* nuke all pending requests (does flush) */
656 	nuke(ep, -ESHUTDOWN);
657 
658 	ep->ep.desc = NULL;
659 	ep->stopped = 1;
660 	spin_unlock_irqrestore(&udc->lock, flags);
661 
662 	VDBG("disabled %s OK", _ep->name);
663 	return 0;
664 }
665 
666 /*---------------------------------------------------------------------
667  * allocate a request object used by this endpoint
668  * the main operation is to insert the req->queue to the eq->queue
669  * Returns the request, or null if one could not be allocated
670 *---------------------------------------------------------------------*/
671 static struct usb_request *
fsl_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)672 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
673 {
674 	struct fsl_req *req;
675 
676 	req = kzalloc(sizeof *req, gfp_flags);
677 	if (!req)
678 		return NULL;
679 
680 	req->req.dma = DMA_ADDR_INVALID;
681 	INIT_LIST_HEAD(&req->queue);
682 
683 	return &req->req;
684 }
685 
fsl_free_request(struct usb_ep * _ep,struct usb_request * _req)686 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
687 {
688 	struct fsl_req *req = NULL;
689 
690 	req = container_of(_req, struct fsl_req, req);
691 
692 	if (_req)
693 		kfree(req);
694 }
695 
696 /* Actually add a dTD chain to an empty dQH and let go */
fsl_prime_ep(struct fsl_ep * ep,struct ep_td_struct * td)697 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
698 {
699 	struct ep_queue_head *qh = get_qh_by_ep(ep);
700 
701 	/* Write dQH next pointer and terminate bit to 0 */
702 	qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
703 			& EP_QUEUE_HEAD_NEXT_POINTER_MASK);
704 
705 	/* Clear active and halt bit */
706 	qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
707 					| EP_QUEUE_HEAD_STATUS_HALT));
708 
709 	/* Ensure that updates to the QH will occur before priming. */
710 	wmb();
711 
712 	/* Prime endpoint by writing correct bit to ENDPTPRIME */
713 	fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
714 			: (1 << (ep_index(ep))), &dr_regs->endpointprime);
715 }
716 
717 /* Add dTD chain to the dQH of an EP */
fsl_queue_td(struct fsl_ep * ep,struct fsl_req * req)718 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
719 {
720 	u32 temp, bitmask, tmp_stat;
721 
722 	/* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
723 	VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
724 
725 	bitmask = ep_is_in(ep)
726 		? (1 << (ep_index(ep) + 16))
727 		: (1 << (ep_index(ep)));
728 
729 	/* check if the pipe is empty */
730 	if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
731 		/* Add td to the end */
732 		struct fsl_req *lastreq;
733 		lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
734 		lastreq->tail->next_td_ptr =
735 			cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
736 		/* Ensure dTD's next dtd pointer to be updated */
737 		wmb();
738 		/* Read prime bit, if 1 goto done */
739 		if (fsl_readl(&dr_regs->endpointprime) & bitmask)
740 			return;
741 
742 		do {
743 			/* Set ATDTW bit in USBCMD */
744 			temp = fsl_readl(&dr_regs->usbcmd);
745 			fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
746 
747 			/* Read correct status bit */
748 			tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
749 
750 		} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
751 
752 		/* Write ATDTW bit to 0 */
753 		temp = fsl_readl(&dr_regs->usbcmd);
754 		fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
755 
756 		if (tmp_stat)
757 			return;
758 	}
759 
760 	fsl_prime_ep(ep, req->head);
761 }
762 
763 /* Fill in the dTD structure
764  * @req: request that the transfer belongs to
765  * @length: return actually data length of the dTD
766  * @dma: return dma address of the dTD
767  * @is_last: return flag if it is the last dTD of the request
768  * return: pointer to the built dTD */
fsl_build_dtd(struct fsl_req * req,unsigned * length,dma_addr_t * dma,int * is_last,gfp_t gfp_flags)769 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
770 		dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
771 {
772 	u32 swap_temp;
773 	struct ep_td_struct *dtd;
774 
775 	/* how big will this transfer be? */
776 	*length = min(req->req.length - req->req.actual,
777 			(unsigned)EP_MAX_LENGTH_TRANSFER);
778 
779 	dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
780 	if (dtd == NULL)
781 		return dtd;
782 
783 	dtd->td_dma = *dma;
784 	/* Clear reserved field */
785 	swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
786 	swap_temp &= ~DTD_RESERVED_FIELDS;
787 	dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
788 
789 	/* Init all of buffer page pointers */
790 	swap_temp = (u32) (req->req.dma + req->req.actual);
791 	dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
792 	dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
793 	dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
794 	dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
795 	dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
796 
797 	req->req.actual += *length;
798 
799 	/* zlp is needed if req->req.zero is set */
800 	if (req->req.zero) {
801 		if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
802 			*is_last = 1;
803 		else
804 			*is_last = 0;
805 	} else if (req->req.length == req->req.actual)
806 		*is_last = 1;
807 	else
808 		*is_last = 0;
809 
810 	if ((*is_last) == 0)
811 		VDBG("multi-dtd request!");
812 	/* Fill in the transfer size; set active bit */
813 	swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
814 
815 	/* Enable interrupt for the last dtd of a request */
816 	if (*is_last && !req->req.no_interrupt)
817 		swap_temp |= DTD_IOC;
818 
819 	dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
820 
821 	mb();
822 
823 	VDBG("length = %d address= 0x%x", *length, (int)*dma);
824 
825 	return dtd;
826 }
827 
828 /* Generate dtd chain for a request */
fsl_req_to_dtd(struct fsl_req * req,gfp_t gfp_flags)829 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
830 {
831 	unsigned	count;
832 	int		is_last;
833 	int		is_first =1;
834 	struct ep_td_struct	*last_dtd = NULL, *dtd;
835 	dma_addr_t dma;
836 
837 	do {
838 		dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
839 		if (dtd == NULL)
840 			return -ENOMEM;
841 
842 		if (is_first) {
843 			is_first = 0;
844 			req->head = dtd;
845 		} else {
846 			last_dtd->next_td_ptr = cpu_to_hc32(dma);
847 			last_dtd->next_td_virt = dtd;
848 		}
849 		last_dtd = dtd;
850 
851 		req->dtd_count++;
852 	} while (!is_last);
853 
854 	dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
855 
856 	req->tail = dtd;
857 
858 	return 0;
859 }
860 
861 /* queues (submits) an I/O request to an endpoint */
862 static int
fsl_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)863 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
864 {
865 	struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
866 	struct fsl_req *req = container_of(_req, struct fsl_req, req);
867 	struct fsl_udc *udc;
868 	unsigned long flags;
869 	int ret;
870 
871 	/* catch various bogus parameters */
872 	if (!_req || !req->req.complete || !req->req.buf
873 			|| !list_empty(&req->queue)) {
874 		VDBG("%s, bad params", __func__);
875 		return -EINVAL;
876 	}
877 	if (unlikely(!_ep || !ep->ep.desc)) {
878 		VDBG("%s, bad ep", __func__);
879 		return -EINVAL;
880 	}
881 	if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
882 		if (req->req.length > ep->ep.maxpacket)
883 			return -EMSGSIZE;
884 	}
885 
886 	udc = ep->udc;
887 	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
888 		return -ESHUTDOWN;
889 
890 	req->ep = ep;
891 
892 	ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
893 	if (ret)
894 		return ret;
895 
896 	req->req.status = -EINPROGRESS;
897 	req->req.actual = 0;
898 	req->dtd_count = 0;
899 
900 	/* build dtds and push them to device queue */
901 	if (!fsl_req_to_dtd(req, gfp_flags)) {
902 		spin_lock_irqsave(&udc->lock, flags);
903 		fsl_queue_td(ep, req);
904 	} else {
905 		return -ENOMEM;
906 	}
907 
908 	/* irq handler advances the queue */
909 	if (req != NULL)
910 		list_add_tail(&req->queue, &ep->queue);
911 	spin_unlock_irqrestore(&udc->lock, flags);
912 
913 	return 0;
914 }
915 
916 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
fsl_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)917 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
918 {
919 	struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
920 	struct fsl_req *req = NULL;
921 	struct fsl_req *iter;
922 	unsigned long flags;
923 	int ep_num, stopped, ret = 0;
924 	u32 epctrl;
925 
926 	if (!_ep || !_req)
927 		return -EINVAL;
928 
929 	spin_lock_irqsave(&ep->udc->lock, flags);
930 	stopped = ep->stopped;
931 
932 	/* Stop the ep before we deal with the queue */
933 	ep->stopped = 1;
934 	ep_num = ep_index(ep);
935 	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
936 	if (ep_is_in(ep))
937 		epctrl &= ~EPCTRL_TX_ENABLE;
938 	else
939 		epctrl &= ~EPCTRL_RX_ENABLE;
940 	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
941 
942 	/* make sure it's actually queued on this endpoint */
943 	list_for_each_entry(iter, &ep->queue, queue) {
944 		if (&iter->req != _req)
945 			continue;
946 		req = iter;
947 		break;
948 	}
949 	if (!req) {
950 		ret = -EINVAL;
951 		goto out;
952 	}
953 
954 	/* The request is in progress, or completed but not dequeued */
955 	if (ep->queue.next == &req->queue) {
956 		_req->status = -ECONNRESET;
957 		fsl_ep_fifo_flush(_ep);	/* flush current transfer */
958 
959 		/* The request isn't the last request in this ep queue */
960 		if (req->queue.next != &ep->queue) {
961 			struct fsl_req *next_req;
962 
963 			next_req = list_entry(req->queue.next, struct fsl_req,
964 					queue);
965 
966 			/* prime with dTD of next request */
967 			fsl_prime_ep(ep, next_req->head);
968 		}
969 	/* The request hasn't been processed, patch up the TD chain */
970 	} else {
971 		struct fsl_req *prev_req;
972 
973 		prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
974 		prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
975 	}
976 
977 	done(ep, req, -ECONNRESET);
978 
979 	/* Enable EP */
980 out:	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
981 	if (ep_is_in(ep))
982 		epctrl |= EPCTRL_TX_ENABLE;
983 	else
984 		epctrl |= EPCTRL_RX_ENABLE;
985 	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
986 	ep->stopped = stopped;
987 
988 	spin_unlock_irqrestore(&ep->udc->lock, flags);
989 	return ret;
990 }
991 
992 /*-------------------------------------------------------------------------*/
993 
994 /*-----------------------------------------------------------------
995  * modify the endpoint halt feature
996  * @ep: the non-isochronous endpoint being stalled
997  * @value: 1--set halt  0--clear halt
998  * Returns zero, or a negative error code.
999 *----------------------------------------------------------------*/
fsl_ep_set_halt(struct usb_ep * _ep,int value)1000 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1001 {
1002 	struct fsl_ep *ep = NULL;
1003 	unsigned long flags;
1004 	int status = -EOPNOTSUPP;	/* operation not supported */
1005 	unsigned char ep_dir = 0, ep_num = 0;
1006 	struct fsl_udc *udc = NULL;
1007 
1008 	ep = container_of(_ep, struct fsl_ep, ep);
1009 	udc = ep->udc;
1010 	if (!_ep || !ep->ep.desc) {
1011 		status = -EINVAL;
1012 		goto out;
1013 	}
1014 
1015 	if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1016 		status = -EOPNOTSUPP;
1017 		goto out;
1018 	}
1019 
1020 	/* Attempt to halt IN ep will fail if any transfer requests
1021 	 * are still queue */
1022 	if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1023 		status = -EAGAIN;
1024 		goto out;
1025 	}
1026 
1027 	status = 0;
1028 	ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1029 	ep_num = (unsigned char)(ep_index(ep));
1030 	spin_lock_irqsave(&ep->udc->lock, flags);
1031 	dr_ep_change_stall(ep_num, ep_dir, value);
1032 	spin_unlock_irqrestore(&ep->udc->lock, flags);
1033 
1034 	if (ep_index(ep) == 0) {
1035 		udc->ep0_state = WAIT_FOR_SETUP;
1036 		udc->ep0_dir = 0;
1037 	}
1038 out:
1039 	VDBG(" %s %s halt stat %d", ep->ep.name,
1040 			value ?  "set" : "clear", status);
1041 
1042 	return status;
1043 }
1044 
fsl_ep_fifo_status(struct usb_ep * _ep)1045 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1046 {
1047 	struct fsl_ep *ep;
1048 	struct fsl_udc *udc;
1049 	int size = 0;
1050 	u32 bitmask;
1051 	struct ep_queue_head *qh;
1052 
1053 	if (!_ep || !_ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1054 		return -ENODEV;
1055 
1056 	ep = container_of(_ep, struct fsl_ep, ep);
1057 
1058 	udc = (struct fsl_udc *)ep->udc;
1059 
1060 	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1061 		return -ESHUTDOWN;
1062 
1063 	qh = get_qh_by_ep(ep);
1064 
1065 	bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1066 	    (1 << (ep_index(ep)));
1067 
1068 	if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1069 		size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1070 		    >> DTD_LENGTH_BIT_POS;
1071 
1072 	pr_debug("%s %u\n", __func__, size);
1073 	return size;
1074 }
1075 
fsl_ep_fifo_flush(struct usb_ep * _ep)1076 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1077 {
1078 	struct fsl_ep *ep;
1079 	int ep_num, ep_dir;
1080 	u32 bits;
1081 	unsigned long timeout;
1082 #define FSL_UDC_FLUSH_TIMEOUT 1000
1083 
1084 	if (!_ep) {
1085 		return;
1086 	} else {
1087 		ep = container_of(_ep, struct fsl_ep, ep);
1088 		if (!ep->ep.desc)
1089 			return;
1090 	}
1091 	ep_num = ep_index(ep);
1092 	ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1093 
1094 	if (ep_num == 0)
1095 		bits = (1 << 16) | 1;
1096 	else if (ep_dir == USB_SEND)
1097 		bits = 1 << (16 + ep_num);
1098 	else
1099 		bits = 1 << ep_num;
1100 
1101 	timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1102 	do {
1103 		fsl_writel(bits, &dr_regs->endptflush);
1104 
1105 		/* Wait until flush complete */
1106 		while (fsl_readl(&dr_regs->endptflush)) {
1107 			if (time_after(jiffies, timeout)) {
1108 				ERR("ep flush timeout\n");
1109 				return;
1110 			}
1111 			cpu_relax();
1112 		}
1113 		/* See if we need to flush again */
1114 	} while (fsl_readl(&dr_regs->endptstatus) & bits);
1115 }
1116 
1117 static const struct usb_ep_ops fsl_ep_ops = {
1118 	.enable = fsl_ep_enable,
1119 	.disable = fsl_ep_disable,
1120 
1121 	.alloc_request = fsl_alloc_request,
1122 	.free_request = fsl_free_request,
1123 
1124 	.queue = fsl_ep_queue,
1125 	.dequeue = fsl_ep_dequeue,
1126 
1127 	.set_halt = fsl_ep_set_halt,
1128 	.fifo_status = fsl_ep_fifo_status,
1129 	.fifo_flush = fsl_ep_fifo_flush,	/* flush fifo */
1130 };
1131 
1132 /*-------------------------------------------------------------------------
1133 		Gadget Driver Layer Operations
1134 -------------------------------------------------------------------------*/
1135 
1136 /*----------------------------------------------------------------------
1137  * Get the current frame number (from DR frame_index Reg )
1138  *----------------------------------------------------------------------*/
fsl_get_frame(struct usb_gadget * gadget)1139 static int fsl_get_frame(struct usb_gadget *gadget)
1140 {
1141 	return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1142 }
1143 
1144 /*-----------------------------------------------------------------------
1145  * Tries to wake up the host connected to this gadget
1146  -----------------------------------------------------------------------*/
fsl_wakeup(struct usb_gadget * gadget)1147 static int fsl_wakeup(struct usb_gadget *gadget)
1148 {
1149 	struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1150 	u32 portsc;
1151 
1152 	/* Remote wakeup feature not enabled by host */
1153 	if (!udc->remote_wakeup)
1154 		return -ENOTSUPP;
1155 
1156 	portsc = fsl_readl(&dr_regs->portsc1);
1157 	/* not suspended? */
1158 	if (!(portsc & PORTSCX_PORT_SUSPEND))
1159 		return 0;
1160 	/* trigger force resume */
1161 	portsc |= PORTSCX_PORT_FORCE_RESUME;
1162 	fsl_writel(portsc, &dr_regs->portsc1);
1163 	return 0;
1164 }
1165 
can_pullup(struct fsl_udc * udc)1166 static int can_pullup(struct fsl_udc *udc)
1167 {
1168 	return udc->driver && udc->softconnect && udc->vbus_active;
1169 }
1170 
1171 /* Notify controller that VBUS is powered, Called by whatever
1172    detects VBUS sessions */
fsl_vbus_session(struct usb_gadget * gadget,int is_active)1173 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1174 {
1175 	struct fsl_udc	*udc;
1176 	unsigned long	flags;
1177 
1178 	udc = container_of(gadget, struct fsl_udc, gadget);
1179 	spin_lock_irqsave(&udc->lock, flags);
1180 	VDBG("VBUS %s", is_active ? "on" : "off");
1181 	udc->vbus_active = (is_active != 0);
1182 	if (can_pullup(udc))
1183 		fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1184 				&dr_regs->usbcmd);
1185 	else
1186 		fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1187 				&dr_regs->usbcmd);
1188 	spin_unlock_irqrestore(&udc->lock, flags);
1189 	return 0;
1190 }
1191 
1192 /* constrain controller's VBUS power usage
1193  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1194  * reporting how much power the device may consume.  For example, this
1195  * could affect how quickly batteries are recharged.
1196  *
1197  * Returns zero on success, else negative errno.
1198  */
fsl_vbus_draw(struct usb_gadget * gadget,unsigned mA)1199 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1200 {
1201 	struct fsl_udc *udc;
1202 
1203 	udc = container_of(gadget, struct fsl_udc, gadget);
1204 	if (!IS_ERR_OR_NULL(udc->transceiver))
1205 		return usb_phy_set_power(udc->transceiver, mA);
1206 	return -ENOTSUPP;
1207 }
1208 
1209 /* Change Data+ pullup status
1210  * this func is used by usb_gadget_connect/disconnect
1211  */
fsl_pullup(struct usb_gadget * gadget,int is_on)1212 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1213 {
1214 	struct fsl_udc *udc;
1215 
1216 	udc = container_of(gadget, struct fsl_udc, gadget);
1217 
1218 	if (!udc->vbus_active)
1219 		return -EOPNOTSUPP;
1220 
1221 	udc->softconnect = (is_on != 0);
1222 	if (can_pullup(udc))
1223 		fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1224 				&dr_regs->usbcmd);
1225 	else
1226 		fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1227 				&dr_regs->usbcmd);
1228 
1229 	return 0;
1230 }
1231 
1232 static int fsl_udc_start(struct usb_gadget *g,
1233 		struct usb_gadget_driver *driver);
1234 static int fsl_udc_stop(struct usb_gadget *g);
1235 
1236 static const struct usb_gadget_ops fsl_gadget_ops = {
1237 	.get_frame = fsl_get_frame,
1238 	.wakeup = fsl_wakeup,
1239 /*	.set_selfpowered = fsl_set_selfpowered,	*/ /* Always selfpowered */
1240 	.vbus_session = fsl_vbus_session,
1241 	.vbus_draw = fsl_vbus_draw,
1242 	.pullup = fsl_pullup,
1243 	.udc_start = fsl_udc_start,
1244 	.udc_stop = fsl_udc_stop,
1245 };
1246 
1247 /*
1248  * Empty complete function used by this driver to fill in the req->complete
1249  * field when creating a request since the complete field is mandatory.
1250  */
fsl_noop_complete(struct usb_ep * ep,struct usb_request * req)1251 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1252 
1253 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1254    on new transaction */
ep0stall(struct fsl_udc * udc)1255 static void ep0stall(struct fsl_udc *udc)
1256 {
1257 	u32 tmp;
1258 
1259 	/* must set tx and rx to stall at the same time */
1260 	tmp = fsl_readl(&dr_regs->endptctrl[0]);
1261 	tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1262 	fsl_writel(tmp, &dr_regs->endptctrl[0]);
1263 	udc->ep0_state = WAIT_FOR_SETUP;
1264 	udc->ep0_dir = 0;
1265 }
1266 
1267 /* Prime a status phase for ep0 */
ep0_prime_status(struct fsl_udc * udc,int direction)1268 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1269 {
1270 	struct fsl_req *req = udc->status_req;
1271 	struct fsl_ep *ep;
1272 	int ret;
1273 
1274 	if (direction == EP_DIR_IN)
1275 		udc->ep0_dir = USB_DIR_IN;
1276 	else
1277 		udc->ep0_dir = USB_DIR_OUT;
1278 
1279 	ep = &udc->eps[0];
1280 	if (udc->ep0_state != DATA_STATE_XMIT)
1281 		udc->ep0_state = WAIT_FOR_OUT_STATUS;
1282 
1283 	req->ep = ep;
1284 	req->req.length = 0;
1285 	req->req.status = -EINPROGRESS;
1286 	req->req.actual = 0;
1287 	req->req.complete = fsl_noop_complete;
1288 	req->dtd_count = 0;
1289 
1290 	ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1291 	if (ret)
1292 		return ret;
1293 
1294 	if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1295 		fsl_queue_td(ep, req);
1296 	else
1297 		return -ENOMEM;
1298 
1299 	list_add_tail(&req->queue, &ep->queue);
1300 
1301 	return 0;
1302 }
1303 
udc_reset_ep_queue(struct fsl_udc * udc,u8 pipe)1304 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1305 {
1306 	struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1307 
1308 	if (ep->ep.name)
1309 		nuke(ep, -ESHUTDOWN);
1310 }
1311 
1312 /*
1313  * ch9 Set address
1314  */
ch9setaddress(struct fsl_udc * udc,u16 value,u16 index,u16 length)1315 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1316 {
1317 	/* Save the new address to device struct */
1318 	udc->device_address = (u8) value;
1319 	/* Update usb state */
1320 	udc->usb_state = USB_STATE_ADDRESS;
1321 	/* Status phase */
1322 	if (ep0_prime_status(udc, EP_DIR_IN))
1323 		ep0stall(udc);
1324 }
1325 
1326 /*
1327  * ch9 Get status
1328  */
ch9getstatus(struct fsl_udc * udc,u8 request_type,u16 value,u16 index,u16 length)1329 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1330 		u16 index, u16 length)
1331 {
1332 	u16 tmp = 0;		/* Status, cpu endian */
1333 	struct fsl_req *req;
1334 	struct fsl_ep *ep;
1335 	int ret;
1336 
1337 	ep = &udc->eps[0];
1338 
1339 	if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1340 		/* Get device status */
1341 		tmp = udc->gadget.is_selfpowered;
1342 		tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1343 	} else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1344 		/* Get interface status */
1345 		/* We don't have interface information in udc driver */
1346 		tmp = 0;
1347 	} else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1348 		/* Get endpoint status */
1349 		struct fsl_ep *target_ep;
1350 
1351 		target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1352 
1353 		/* stall if endpoint doesn't exist */
1354 		if (!target_ep->ep.desc)
1355 			goto stall;
1356 		tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1357 				<< USB_ENDPOINT_HALT;
1358 	}
1359 
1360 	udc->ep0_dir = USB_DIR_IN;
1361 	/* Borrow the per device status_req */
1362 	req = udc->status_req;
1363 	/* Fill in the reqest structure */
1364 	*((u16 *) req->req.buf) = cpu_to_le16(tmp);
1365 
1366 	req->ep = ep;
1367 	req->req.length = 2;
1368 	req->req.status = -EINPROGRESS;
1369 	req->req.actual = 0;
1370 	req->req.complete = fsl_noop_complete;
1371 	req->dtd_count = 0;
1372 
1373 	ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1374 	if (ret)
1375 		goto stall;
1376 
1377 	/* prime the data phase */
1378 	if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1379 		fsl_queue_td(ep, req);
1380 	else			/* no mem */
1381 		goto stall;
1382 
1383 	list_add_tail(&req->queue, &ep->queue);
1384 	udc->ep0_state = DATA_STATE_XMIT;
1385 	if (ep0_prime_status(udc, EP_DIR_OUT))
1386 		ep0stall(udc);
1387 
1388 	return;
1389 stall:
1390 	ep0stall(udc);
1391 }
1392 
setup_received_irq(struct fsl_udc * udc,struct usb_ctrlrequest * setup)1393 static void setup_received_irq(struct fsl_udc *udc,
1394 		struct usb_ctrlrequest *setup)
1395 __releases(udc->lock)
1396 __acquires(udc->lock)
1397 {
1398 	u16 wValue = le16_to_cpu(setup->wValue);
1399 	u16 wIndex = le16_to_cpu(setup->wIndex);
1400 	u16 wLength = le16_to_cpu(setup->wLength);
1401 
1402 	udc_reset_ep_queue(udc, 0);
1403 
1404 	/* We process some stardard setup requests here */
1405 	switch (setup->bRequest) {
1406 	case USB_REQ_GET_STATUS:
1407 		/* Data+Status phase from udc */
1408 		if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1409 					!= (USB_DIR_IN | USB_TYPE_STANDARD))
1410 			break;
1411 		ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1412 		return;
1413 
1414 	case USB_REQ_SET_ADDRESS:
1415 		/* Status phase from udc */
1416 		if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1417 						| USB_RECIP_DEVICE))
1418 			break;
1419 		ch9setaddress(udc, wValue, wIndex, wLength);
1420 		return;
1421 
1422 	case USB_REQ_CLEAR_FEATURE:
1423 	case USB_REQ_SET_FEATURE:
1424 		/* Status phase from udc */
1425 	{
1426 		int rc = -EOPNOTSUPP;
1427 		u16 ptc = 0;
1428 
1429 		if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1430 				== (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1431 			int pipe = get_pipe_by_windex(wIndex);
1432 			struct fsl_ep *ep;
1433 
1434 			if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1435 				break;
1436 			ep = get_ep_by_pipe(udc, pipe);
1437 
1438 			spin_unlock(&udc->lock);
1439 			rc = fsl_ep_set_halt(&ep->ep,
1440 					(setup->bRequest == USB_REQ_SET_FEATURE)
1441 						? 1 : 0);
1442 			spin_lock(&udc->lock);
1443 
1444 		} else if ((setup->bRequestType & (USB_RECIP_MASK
1445 				| USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1446 				| USB_TYPE_STANDARD)) {
1447 			/* Note: The driver has not include OTG support yet.
1448 			 * This will be set when OTG support is added */
1449 			if (wValue == USB_DEVICE_TEST_MODE)
1450 				ptc = wIndex >> 8;
1451 			else if (gadget_is_otg(&udc->gadget)) {
1452 				if (setup->bRequest ==
1453 				    USB_DEVICE_B_HNP_ENABLE)
1454 					udc->gadget.b_hnp_enable = 1;
1455 				else if (setup->bRequest ==
1456 					 USB_DEVICE_A_HNP_SUPPORT)
1457 					udc->gadget.a_hnp_support = 1;
1458 				else if (setup->bRequest ==
1459 					 USB_DEVICE_A_ALT_HNP_SUPPORT)
1460 					udc->gadget.a_alt_hnp_support = 1;
1461 			}
1462 			rc = 0;
1463 		} else
1464 			break;
1465 
1466 		if (rc == 0) {
1467 			if (ep0_prime_status(udc, EP_DIR_IN))
1468 				ep0stall(udc);
1469 		}
1470 		if (ptc) {
1471 			u32 tmp;
1472 
1473 			mdelay(10);
1474 			tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1475 			fsl_writel(tmp, &dr_regs->portsc1);
1476 			printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1477 		}
1478 
1479 		return;
1480 	}
1481 
1482 	default:
1483 		break;
1484 	}
1485 
1486 	/* Requests handled by gadget */
1487 	if (wLength) {
1488 		/* Data phase from gadget, status phase from udc */
1489 		udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1490 				?  USB_DIR_IN : USB_DIR_OUT;
1491 		spin_unlock(&udc->lock);
1492 		if (udc->driver->setup(&udc->gadget,
1493 				&udc->local_setup_buff) < 0)
1494 			ep0stall(udc);
1495 		spin_lock(&udc->lock);
1496 		udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1497 				?  DATA_STATE_XMIT : DATA_STATE_RECV;
1498 		/*
1499 		 * If the data stage is IN, send status prime immediately.
1500 		 * See 2.0 Spec chapter 8.5.3.3 for detail.
1501 		 */
1502 		if (udc->ep0_state == DATA_STATE_XMIT)
1503 			if (ep0_prime_status(udc, EP_DIR_OUT))
1504 				ep0stall(udc);
1505 
1506 	} else {
1507 		/* No data phase, IN status from gadget */
1508 		udc->ep0_dir = USB_DIR_IN;
1509 		spin_unlock(&udc->lock);
1510 		if (udc->driver->setup(&udc->gadget,
1511 				&udc->local_setup_buff) < 0)
1512 			ep0stall(udc);
1513 		spin_lock(&udc->lock);
1514 		udc->ep0_state = WAIT_FOR_OUT_STATUS;
1515 	}
1516 }
1517 
1518 /* Process request for Data or Status phase of ep0
1519  * prime status phase if needed */
ep0_req_complete(struct fsl_udc * udc,struct fsl_ep * ep0,struct fsl_req * req)1520 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1521 		struct fsl_req *req)
1522 {
1523 	if (udc->usb_state == USB_STATE_ADDRESS) {
1524 		/* Set the new address */
1525 		u32 new_address = (u32) udc->device_address;
1526 		fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1527 				&dr_regs->deviceaddr);
1528 	}
1529 
1530 	done(ep0, req, 0);
1531 
1532 	switch (udc->ep0_state) {
1533 	case DATA_STATE_XMIT:
1534 		/* already primed at setup_received_irq */
1535 		udc->ep0_state = WAIT_FOR_OUT_STATUS;
1536 		break;
1537 	case DATA_STATE_RECV:
1538 		/* send status phase */
1539 		if (ep0_prime_status(udc, EP_DIR_IN))
1540 			ep0stall(udc);
1541 		break;
1542 	case WAIT_FOR_OUT_STATUS:
1543 		udc->ep0_state = WAIT_FOR_SETUP;
1544 		break;
1545 	case WAIT_FOR_SETUP:
1546 		ERR("Unexpected ep0 packets\n");
1547 		break;
1548 	default:
1549 		ep0stall(udc);
1550 		break;
1551 	}
1552 }
1553 
1554 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1555  * being corrupted by another incoming setup packet */
tripwire_handler(struct fsl_udc * udc,u8 ep_num,u8 * buffer_ptr)1556 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1557 {
1558 	u32 temp;
1559 	struct ep_queue_head *qh;
1560 	struct fsl_usb2_platform_data *pdata = udc->pdata;
1561 
1562 	qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1563 
1564 	/* Clear bit in ENDPTSETUPSTAT */
1565 	temp = fsl_readl(&dr_regs->endptsetupstat);
1566 	fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1567 
1568 	/* while a hazard exists when setup package arrives */
1569 	do {
1570 		/* Set Setup Tripwire */
1571 		temp = fsl_readl(&dr_regs->usbcmd);
1572 		fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1573 
1574 		/* Copy the setup packet to local buffer */
1575 		if (pdata->le_setup_buf) {
1576 			u32 *p = (u32 *)buffer_ptr;
1577 			u32 *s = (u32 *)qh->setup_buffer;
1578 
1579 			/* Convert little endian setup buffer to CPU endian */
1580 			*p++ = le32_to_cpu(*s++);
1581 			*p = le32_to_cpu(*s);
1582 		} else {
1583 			memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1584 		}
1585 	} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1586 
1587 	/* Clear Setup Tripwire */
1588 	temp = fsl_readl(&dr_regs->usbcmd);
1589 	fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1590 }
1591 
1592 /* process-ep_req(): free the completed Tds for this req */
process_ep_req(struct fsl_udc * udc,int pipe,struct fsl_req * curr_req)1593 static int process_ep_req(struct fsl_udc *udc, int pipe,
1594 		struct fsl_req *curr_req)
1595 {
1596 	struct ep_td_struct *curr_td;
1597 	int	actual, remaining_length, j, tmp;
1598 	int	status = 0;
1599 	int	errors = 0;
1600 	struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1601 	int direction = pipe % 2;
1602 
1603 	curr_td = curr_req->head;
1604 	actual = curr_req->req.length;
1605 
1606 	for (j = 0; j < curr_req->dtd_count; j++) {
1607 		remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1608 					& DTD_PACKET_SIZE)
1609 				>> DTD_LENGTH_BIT_POS;
1610 		actual -= remaining_length;
1611 
1612 		errors = hc32_to_cpu(curr_td->size_ioc_sts);
1613 		if (errors & DTD_ERROR_MASK) {
1614 			if (errors & DTD_STATUS_HALTED) {
1615 				ERR("dTD error %08x QH=%d\n", errors, pipe);
1616 				/* Clear the errors and Halt condition */
1617 				tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1618 				tmp &= ~errors;
1619 				curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1620 				status = -EPIPE;
1621 				/* FIXME: continue with next queued TD? */
1622 
1623 				break;
1624 			}
1625 			if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1626 				VDBG("Transfer overflow");
1627 				status = -EPROTO;
1628 				break;
1629 			} else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1630 				VDBG("ISO error");
1631 				status = -EILSEQ;
1632 				break;
1633 			} else
1634 				ERR("Unknown error has occurred (0x%x)!\n",
1635 					errors);
1636 
1637 		} else if (hc32_to_cpu(curr_td->size_ioc_sts)
1638 				& DTD_STATUS_ACTIVE) {
1639 			VDBG("Request not complete");
1640 			status = REQ_UNCOMPLETE;
1641 			return status;
1642 		} else if (remaining_length) {
1643 			if (direction) {
1644 				VDBG("Transmit dTD remaining length not zero");
1645 				status = -EPROTO;
1646 				break;
1647 			} else {
1648 				break;
1649 			}
1650 		} else {
1651 			VDBG("dTD transmitted successful");
1652 		}
1653 
1654 		if (j != curr_req->dtd_count - 1)
1655 			curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1656 	}
1657 
1658 	if (status)
1659 		return status;
1660 
1661 	curr_req->req.actual = actual;
1662 
1663 	return 0;
1664 }
1665 
1666 /* Process a DTD completion interrupt */
dtd_complete_irq(struct fsl_udc * udc)1667 static void dtd_complete_irq(struct fsl_udc *udc)
1668 {
1669 	u32 bit_pos;
1670 	int i, ep_num, direction, bit_mask, status;
1671 	struct fsl_ep *curr_ep;
1672 	struct fsl_req *curr_req, *temp_req;
1673 
1674 	/* Clear the bits in the register */
1675 	bit_pos = fsl_readl(&dr_regs->endptcomplete);
1676 	fsl_writel(bit_pos, &dr_regs->endptcomplete);
1677 
1678 	if (!bit_pos)
1679 		return;
1680 
1681 	for (i = 0; i < udc->max_ep; i++) {
1682 		ep_num = i >> 1;
1683 		direction = i % 2;
1684 
1685 		bit_mask = 1 << (ep_num + 16 * direction);
1686 
1687 		if (!(bit_pos & bit_mask))
1688 			continue;
1689 
1690 		curr_ep = get_ep_by_pipe(udc, i);
1691 
1692 		/* If the ep is configured */
1693 		if (!curr_ep->ep.name) {
1694 			WARNING("Invalid EP?");
1695 			continue;
1696 		}
1697 
1698 		/* process the req queue until an uncomplete request */
1699 		list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1700 				queue) {
1701 			status = process_ep_req(udc, i, curr_req);
1702 
1703 			VDBG("status of process_ep_req= %d, ep = %d",
1704 					status, ep_num);
1705 			if (status == REQ_UNCOMPLETE)
1706 				break;
1707 			/* write back status to req */
1708 			curr_req->req.status = status;
1709 
1710 			if (ep_num == 0) {
1711 				ep0_req_complete(udc, curr_ep, curr_req);
1712 				break;
1713 			} else
1714 				done(curr_ep, curr_req, status);
1715 		}
1716 	}
1717 }
1718 
portscx_device_speed(u32 reg)1719 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1720 {
1721 	switch (reg & PORTSCX_PORT_SPEED_MASK) {
1722 	case PORTSCX_PORT_SPEED_HIGH:
1723 		return USB_SPEED_HIGH;
1724 	case PORTSCX_PORT_SPEED_FULL:
1725 		return USB_SPEED_FULL;
1726 	case PORTSCX_PORT_SPEED_LOW:
1727 		return USB_SPEED_LOW;
1728 	default:
1729 		return USB_SPEED_UNKNOWN;
1730 	}
1731 }
1732 
1733 /* Process a port change interrupt */
port_change_irq(struct fsl_udc * udc)1734 static void port_change_irq(struct fsl_udc *udc)
1735 {
1736 	if (udc->bus_reset)
1737 		udc->bus_reset = 0;
1738 
1739 	/* Bus resetting is finished */
1740 	if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1741 		/* Get the speed */
1742 		udc->gadget.speed =
1743 			portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1744 
1745 	/* Update USB state */
1746 	if (!udc->resume_state)
1747 		udc->usb_state = USB_STATE_DEFAULT;
1748 }
1749 
1750 /* Process suspend interrupt */
suspend_irq(struct fsl_udc * udc)1751 static void suspend_irq(struct fsl_udc *udc)
1752 {
1753 	udc->resume_state = udc->usb_state;
1754 	udc->usb_state = USB_STATE_SUSPENDED;
1755 
1756 	/* report suspend to the driver, serial.c does not support this */
1757 	if (udc->driver->suspend)
1758 		udc->driver->suspend(&udc->gadget);
1759 }
1760 
bus_resume(struct fsl_udc * udc)1761 static void bus_resume(struct fsl_udc *udc)
1762 {
1763 	udc->usb_state = udc->resume_state;
1764 	udc->resume_state = 0;
1765 
1766 	/* report resume to the driver, serial.c does not support this */
1767 	if (udc->driver->resume)
1768 		udc->driver->resume(&udc->gadget);
1769 }
1770 
1771 /* Clear up all ep queues */
reset_queues(struct fsl_udc * udc,bool bus_reset)1772 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1773 {
1774 	u8 pipe;
1775 
1776 	for (pipe = 0; pipe < udc->max_pipes; pipe++)
1777 		udc_reset_ep_queue(udc, pipe);
1778 
1779 	/* report disconnect; the driver is already quiesced */
1780 	spin_unlock(&udc->lock);
1781 	if (bus_reset)
1782 		usb_gadget_udc_reset(&udc->gadget, udc->driver);
1783 	else
1784 		udc->driver->disconnect(&udc->gadget);
1785 	spin_lock(&udc->lock);
1786 
1787 	return 0;
1788 }
1789 
1790 /* Process reset interrupt */
reset_irq(struct fsl_udc * udc)1791 static void reset_irq(struct fsl_udc *udc)
1792 {
1793 	u32 temp;
1794 	unsigned long timeout;
1795 
1796 	/* Clear the device address */
1797 	temp = fsl_readl(&dr_regs->deviceaddr);
1798 	fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1799 
1800 	udc->device_address = 0;
1801 
1802 	/* Clear usb state */
1803 	udc->resume_state = 0;
1804 	udc->ep0_dir = 0;
1805 	udc->ep0_state = WAIT_FOR_SETUP;
1806 	udc->remote_wakeup = 0;	/* default to 0 on reset */
1807 	udc->gadget.b_hnp_enable = 0;
1808 	udc->gadget.a_hnp_support = 0;
1809 	udc->gadget.a_alt_hnp_support = 0;
1810 
1811 	/* Clear all the setup token semaphores */
1812 	temp = fsl_readl(&dr_regs->endptsetupstat);
1813 	fsl_writel(temp, &dr_regs->endptsetupstat);
1814 
1815 	/* Clear all the endpoint complete status bits */
1816 	temp = fsl_readl(&dr_regs->endptcomplete);
1817 	fsl_writel(temp, &dr_regs->endptcomplete);
1818 
1819 	timeout = jiffies + 100;
1820 	while (fsl_readl(&dr_regs->endpointprime)) {
1821 		/* Wait until all endptprime bits cleared */
1822 		if (time_after(jiffies, timeout)) {
1823 			ERR("Timeout for reset\n");
1824 			break;
1825 		}
1826 		cpu_relax();
1827 	}
1828 
1829 	/* Write 1s to the flush register */
1830 	fsl_writel(0xffffffff, &dr_regs->endptflush);
1831 
1832 	if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1833 		VDBG("Bus reset");
1834 		/* Bus is reseting */
1835 		udc->bus_reset = 1;
1836 		/* Reset all the queues, include XD, dTD, EP queue
1837 		 * head and TR Queue */
1838 		reset_queues(udc, true);
1839 		udc->usb_state = USB_STATE_DEFAULT;
1840 	} else {
1841 		VDBG("Controller reset");
1842 		/* initialize usb hw reg except for regs for EP, not
1843 		 * touch usbintr reg */
1844 		dr_controller_setup(udc);
1845 
1846 		/* Reset all internal used Queues */
1847 		reset_queues(udc, false);
1848 
1849 		ep0_setup(udc);
1850 
1851 		/* Enable DR IRQ reg, Set Run bit, change udc state */
1852 		dr_controller_run(udc);
1853 		udc->usb_state = USB_STATE_ATTACHED;
1854 	}
1855 }
1856 
1857 /*
1858  * USB device controller interrupt handler
1859  */
fsl_udc_irq(int irq,void * _udc)1860 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1861 {
1862 	struct fsl_udc *udc = _udc;
1863 	u32 irq_src;
1864 	irqreturn_t status = IRQ_NONE;
1865 	unsigned long flags;
1866 
1867 	/* Disable ISR for OTG host mode */
1868 	if (udc->stopped)
1869 		return IRQ_NONE;
1870 	spin_lock_irqsave(&udc->lock, flags);
1871 	irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1872 	/* Clear notification bits */
1873 	fsl_writel(irq_src, &dr_regs->usbsts);
1874 
1875 	/* VDBG("irq_src [0x%8x]", irq_src); */
1876 
1877 	/* Need to resume? */
1878 	if (udc->usb_state == USB_STATE_SUSPENDED)
1879 		if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1880 			bus_resume(udc);
1881 
1882 	/* USB Interrupt */
1883 	if (irq_src & USB_STS_INT) {
1884 		VDBG("Packet int");
1885 		/* Setup package, we only support ep0 as control ep */
1886 		if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1887 			tripwire_handler(udc, 0,
1888 					(u8 *) (&udc->local_setup_buff));
1889 			setup_received_irq(udc, &udc->local_setup_buff);
1890 			status = IRQ_HANDLED;
1891 		}
1892 
1893 		/* completion of dtd */
1894 		if (fsl_readl(&dr_regs->endptcomplete)) {
1895 			dtd_complete_irq(udc);
1896 			status = IRQ_HANDLED;
1897 		}
1898 	}
1899 
1900 	/* SOF (for ISO transfer) */
1901 	if (irq_src & USB_STS_SOF) {
1902 		status = IRQ_HANDLED;
1903 	}
1904 
1905 	/* Port Change */
1906 	if (irq_src & USB_STS_PORT_CHANGE) {
1907 		port_change_irq(udc);
1908 		status = IRQ_HANDLED;
1909 	}
1910 
1911 	/* Reset Received */
1912 	if (irq_src & USB_STS_RESET) {
1913 		VDBG("reset int");
1914 		reset_irq(udc);
1915 		status = IRQ_HANDLED;
1916 	}
1917 
1918 	/* Sleep Enable (Suspend) */
1919 	if (irq_src & USB_STS_SUSPEND) {
1920 		suspend_irq(udc);
1921 		status = IRQ_HANDLED;
1922 	}
1923 
1924 	if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1925 		VDBG("Error IRQ %x", irq_src);
1926 	}
1927 
1928 	spin_unlock_irqrestore(&udc->lock, flags);
1929 	return status;
1930 }
1931 
1932 /*----------------------------------------------------------------*
1933  * Hook to gadget drivers
1934  * Called by initialization code of gadget drivers
1935 *----------------------------------------------------------------*/
fsl_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)1936 static int fsl_udc_start(struct usb_gadget *g,
1937 		struct usb_gadget_driver *driver)
1938 {
1939 	int retval = 0;
1940 	unsigned long flags;
1941 
1942 	/* lock is needed but whether should use this lock or another */
1943 	spin_lock_irqsave(&udc_controller->lock, flags);
1944 
1945 	/* hook up the driver */
1946 	udc_controller->driver = driver;
1947 	spin_unlock_irqrestore(&udc_controller->lock, flags);
1948 	g->is_selfpowered = 1;
1949 
1950 	if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1951 		/* Suspend the controller until OTG enable it */
1952 		udc_controller->stopped = 1;
1953 		printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1954 
1955 		/* connect to bus through transceiver */
1956 		if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1957 			retval = otg_set_peripheral(
1958 					udc_controller->transceiver->otg,
1959 						    &udc_controller->gadget);
1960 			if (retval < 0) {
1961 				ERR("can't bind to transceiver\n");
1962 				udc_controller->driver = NULL;
1963 				return retval;
1964 			}
1965 		}
1966 	} else {
1967 		/* Enable DR IRQ reg and set USBCMD reg Run bit */
1968 		dr_controller_run(udc_controller);
1969 		udc_controller->usb_state = USB_STATE_ATTACHED;
1970 		udc_controller->ep0_state = WAIT_FOR_SETUP;
1971 		udc_controller->ep0_dir = 0;
1972 	}
1973 
1974 	return retval;
1975 }
1976 
1977 /* Disconnect from gadget driver */
fsl_udc_stop(struct usb_gadget * g)1978 static int fsl_udc_stop(struct usb_gadget *g)
1979 {
1980 	struct fsl_ep *loop_ep;
1981 	unsigned long flags;
1982 
1983 	if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1984 		otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1985 
1986 	/* stop DR, disable intr */
1987 	dr_controller_stop(udc_controller);
1988 
1989 	/* in fact, no needed */
1990 	udc_controller->usb_state = USB_STATE_ATTACHED;
1991 	udc_controller->ep0_state = WAIT_FOR_SETUP;
1992 	udc_controller->ep0_dir = 0;
1993 
1994 	/* stand operation */
1995 	spin_lock_irqsave(&udc_controller->lock, flags);
1996 	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1997 	nuke(&udc_controller->eps[0], -ESHUTDOWN);
1998 	list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
1999 			ep.ep_list)
2000 		nuke(loop_ep, -ESHUTDOWN);
2001 	spin_unlock_irqrestore(&udc_controller->lock, flags);
2002 
2003 	udc_controller->driver = NULL;
2004 
2005 	return 0;
2006 }
2007 
2008 /*-------------------------------------------------------------------------
2009 		PROC File System Support
2010 -------------------------------------------------------------------------*/
2011 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2012 
2013 #include <linux/seq_file.h>
2014 
2015 static const char proc_filename[] = "driver/fsl_usb2_udc";
2016 
fsl_proc_read(struct seq_file * m,void * v)2017 static int fsl_proc_read(struct seq_file *m, void *v)
2018 {
2019 	unsigned long flags;
2020 	int i;
2021 	u32 tmp_reg;
2022 	struct fsl_ep *ep = NULL;
2023 	struct fsl_req *req;
2024 
2025 	struct fsl_udc *udc = udc_controller;
2026 
2027 	spin_lock_irqsave(&udc->lock, flags);
2028 
2029 	/* ------basic driver information ---- */
2030 	seq_printf(m,
2031 			DRIVER_DESC "\n"
2032 			"%s version: %s\n"
2033 			"Gadget driver: %s\n\n",
2034 			driver_name, DRIVER_VERSION,
2035 			udc->driver ? udc->driver->driver.name : "(none)");
2036 
2037 	/* ------ DR Registers ----- */
2038 	tmp_reg = fsl_readl(&dr_regs->usbcmd);
2039 	seq_printf(m,
2040 			"USBCMD reg:\n"
2041 			"SetupTW: %d\n"
2042 			"Run/Stop: %s\n\n",
2043 			(tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2044 			(tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2045 
2046 	tmp_reg = fsl_readl(&dr_regs->usbsts);
2047 	seq_printf(m,
2048 			"USB Status Reg:\n"
2049 			"Dr Suspend: %d Reset Received: %d System Error: %s "
2050 			"USB Error Interrupt: %s\n\n",
2051 			(tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2052 			(tmp_reg & USB_STS_RESET) ? 1 : 0,
2053 			(tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2054 			(tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2055 
2056 	tmp_reg = fsl_readl(&dr_regs->usbintr);
2057 	seq_printf(m,
2058 			"USB Interrupt Enable Reg:\n"
2059 			"Sleep Enable: %d SOF Received Enable: %d "
2060 			"Reset Enable: %d\n"
2061 			"System Error Enable: %d "
2062 			"Port Change Detected Enable: %d\n"
2063 			"USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2064 			(tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2065 			(tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2066 			(tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2067 			(tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2068 			(tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2069 			(tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2070 			(tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2071 
2072 	tmp_reg = fsl_readl(&dr_regs->frindex);
2073 	seq_printf(m,
2074 			"USB Frame Index Reg: Frame Number is 0x%x\n\n",
2075 			(tmp_reg & USB_FRINDEX_MASKS));
2076 
2077 	tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2078 	seq_printf(m,
2079 			"USB Device Address Reg: Device Addr is 0x%x\n\n",
2080 			(tmp_reg & USB_DEVICE_ADDRESS_MASK));
2081 
2082 	tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2083 	seq_printf(m,
2084 			"USB Endpoint List Address Reg: "
2085 			"Device Addr is 0x%x\n\n",
2086 			(tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2087 
2088 	tmp_reg = fsl_readl(&dr_regs->portsc1);
2089 	seq_printf(m,
2090 		"USB Port Status&Control Reg:\n"
2091 		"Port Transceiver Type : %s Port Speed: %s\n"
2092 		"PHY Low Power Suspend: %s Port Reset: %s "
2093 		"Port Suspend Mode: %s\n"
2094 		"Over-current Change: %s "
2095 		"Port Enable/Disable Change: %s\n"
2096 		"Port Enabled/Disabled: %s "
2097 		"Current Connect Status: %s\n\n", ( {
2098 			const char *s;
2099 			switch (tmp_reg & PORTSCX_PTS_FSLS) {
2100 			case PORTSCX_PTS_UTMI:
2101 				s = "UTMI"; break;
2102 			case PORTSCX_PTS_ULPI:
2103 				s = "ULPI "; break;
2104 			case PORTSCX_PTS_FSLS:
2105 				s = "FS/LS Serial"; break;
2106 			default:
2107 				s = "None"; break;
2108 			}
2109 			s;} ),
2110 		usb_speed_string(portscx_device_speed(tmp_reg)),
2111 		(tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2112 		"Normal PHY mode" : "Low power mode",
2113 		(tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2114 		"Not in Reset",
2115 		(tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2116 		(tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2117 		"No",
2118 		(tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2119 		"Not change",
2120 		(tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2121 		"Not correct",
2122 		(tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2123 		"Attached" : "Not-Att");
2124 
2125 	tmp_reg = fsl_readl(&dr_regs->usbmode);
2126 	seq_printf(m,
2127 			"USB Mode Reg: Controller Mode is: %s\n\n", ( {
2128 				const char *s;
2129 				switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2130 				case USB_MODE_CTRL_MODE_IDLE:
2131 					s = "Idle"; break;
2132 				case USB_MODE_CTRL_MODE_DEVICE:
2133 					s = "Device Controller"; break;
2134 				case USB_MODE_CTRL_MODE_HOST:
2135 					s = "Host Controller"; break;
2136 				default:
2137 					s = "None"; break;
2138 				}
2139 				s;
2140 			} ));
2141 
2142 	tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2143 	seq_printf(m,
2144 			"Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2145 			(tmp_reg & EP_SETUP_STATUS_MASK));
2146 
2147 	for (i = 0; i < udc->max_ep / 2; i++) {
2148 		tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2149 		seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2150 	}
2151 	tmp_reg = fsl_readl(&dr_regs->endpointprime);
2152 	seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2153 
2154 	if (udc->pdata->have_sysif_regs) {
2155 		tmp_reg = usb_sys_regs->snoop1;
2156 		seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2157 
2158 		tmp_reg = usb_sys_regs->control;
2159 		seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2160 	}
2161 
2162 	/* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2163 	ep = &udc->eps[0];
2164 	seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2165 			ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2166 
2167 	if (list_empty(&ep->queue)) {
2168 		seq_puts(m, "its req queue is empty\n\n");
2169 	} else {
2170 		list_for_each_entry(req, &ep->queue, queue) {
2171 			seq_printf(m,
2172 				"req %p actual 0x%x length 0x%x buf %p\n",
2173 				&req->req, req->req.actual,
2174 				req->req.length, req->req.buf);
2175 		}
2176 	}
2177 	/* other gadget->eplist ep */
2178 	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2179 		if (ep->ep.desc) {
2180 			seq_printf(m,
2181 					"\nFor %s Maxpkt is 0x%x "
2182 					"index is 0x%x\n",
2183 					ep->ep.name, ep_maxpacket(ep),
2184 					ep_index(ep));
2185 
2186 			if (list_empty(&ep->queue)) {
2187 				seq_puts(m, "its req queue is empty\n\n");
2188 			} else {
2189 				list_for_each_entry(req, &ep->queue, queue) {
2190 					seq_printf(m,
2191 						"req %p actual 0x%x length "
2192 						"0x%x  buf %p\n",
2193 						&req->req, req->req.actual,
2194 						req->req.length, req->req.buf);
2195 				}	/* end for each_entry of ep req */
2196 			}	/* end for else */
2197 		}	/* end for if(ep->queue) */
2198 	}	/* end (ep->desc) */
2199 
2200 	spin_unlock_irqrestore(&udc->lock, flags);
2201 	return 0;
2202 }
2203 
2204 #define create_proc_file() \
2205 	proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2206 #define remove_proc_file()	remove_proc_entry(proc_filename, NULL)
2207 
2208 #else				/* !CONFIG_USB_GADGET_DEBUG_FILES */
2209 
2210 #define create_proc_file()	do {} while (0)
2211 #define remove_proc_file()	do {} while (0)
2212 
2213 #endif				/* CONFIG_USB_GADGET_DEBUG_FILES */
2214 
2215 /*-------------------------------------------------------------------------*/
2216 
2217 /* Release udc structures */
fsl_udc_release(struct device * dev)2218 static void fsl_udc_release(struct device *dev)
2219 {
2220 	complete(udc_controller->done);
2221 	dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2222 			udc_controller->ep_qh, udc_controller->ep_qh_dma);
2223 	kfree(udc_controller);
2224 }
2225 
2226 /******************************************************************
2227 	Internal structure setup functions
2228 *******************************************************************/
2229 /*------------------------------------------------------------------
2230  * init resource for global controller called by fsl_udc_probe()
2231  * On success the udc handle is initialized, on failure it is
2232  * unchanged (reset).
2233  * Return 0 on success and -1 on allocation failure
2234  ------------------------------------------------------------------*/
struct_udc_setup(struct fsl_udc * udc,struct platform_device * pdev)2235 static int struct_udc_setup(struct fsl_udc *udc,
2236 		struct platform_device *pdev)
2237 {
2238 	struct fsl_usb2_platform_data *pdata;
2239 	size_t size;
2240 
2241 	pdata = dev_get_platdata(&pdev->dev);
2242 	udc->phy_mode = pdata->phy_mode;
2243 
2244 	udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2245 	if (!udc->eps) {
2246 		ERR("kmalloc udc endpoint status failed\n");
2247 		goto eps_alloc_failed;
2248 	}
2249 
2250 	/* initialized QHs, take care of alignment */
2251 	size = udc->max_ep * sizeof(struct ep_queue_head);
2252 	if (size < QH_ALIGNMENT)
2253 		size = QH_ALIGNMENT;
2254 	else if ((size % QH_ALIGNMENT) != 0) {
2255 		size += QH_ALIGNMENT + 1;
2256 		size &= ~(QH_ALIGNMENT - 1);
2257 	}
2258 	udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2259 					&udc->ep_qh_dma, GFP_KERNEL);
2260 	if (!udc->ep_qh) {
2261 		ERR("malloc QHs for udc failed\n");
2262 		goto ep_queue_alloc_failed;
2263 	}
2264 
2265 	udc->ep_qh_size = size;
2266 
2267 	/* Initialize ep0 status request structure */
2268 	/* FIXME: fsl_alloc_request() ignores ep argument */
2269 	udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2270 			struct fsl_req, req);
2271 	if (!udc->status_req) {
2272 		ERR("kzalloc for udc status request failed\n");
2273 		goto udc_status_alloc_failed;
2274 	}
2275 
2276 	/* allocate a small amount of memory to get valid address */
2277 	udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2278 	if (!udc->status_req->req.buf) {
2279 		ERR("kzalloc for udc request buffer failed\n");
2280 		goto udc_req_buf_alloc_failed;
2281 	}
2282 
2283 	udc->resume_state = USB_STATE_NOTATTACHED;
2284 	udc->usb_state = USB_STATE_POWERED;
2285 	udc->ep0_dir = 0;
2286 	udc->remote_wakeup = 0;	/* default to 0 on reset */
2287 
2288 	return 0;
2289 
2290 udc_req_buf_alloc_failed:
2291 	kfree(udc->status_req);
2292 udc_status_alloc_failed:
2293 	kfree(udc->ep_qh);
2294 	udc->ep_qh_size = 0;
2295 ep_queue_alloc_failed:
2296 	kfree(udc->eps);
2297 eps_alloc_failed:
2298 	udc->phy_mode = 0;
2299 	return -1;
2300 
2301 }
2302 
2303 /*----------------------------------------------------------------
2304  * Setup the fsl_ep struct for eps
2305  * Link fsl_ep->ep to gadget->ep_list
2306  * ep0out is not used so do nothing here
2307  * ep0in should be taken care
2308  *--------------------------------------------------------------*/
struct_ep_setup(struct fsl_udc * udc,unsigned char index,char * name,int link)2309 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2310 		char *name, int link)
2311 {
2312 	struct fsl_ep *ep = &udc->eps[index];
2313 
2314 	ep->udc = udc;
2315 	strcpy(ep->name, name);
2316 	ep->ep.name = ep->name;
2317 
2318 	ep->ep.ops = &fsl_ep_ops;
2319 	ep->stopped = 0;
2320 
2321 	if (index == 0) {
2322 		ep->ep.caps.type_control = true;
2323 	} else {
2324 		ep->ep.caps.type_iso = true;
2325 		ep->ep.caps.type_bulk = true;
2326 		ep->ep.caps.type_int = true;
2327 	}
2328 
2329 	if (index & 1)
2330 		ep->ep.caps.dir_in = true;
2331 	else
2332 		ep->ep.caps.dir_out = true;
2333 
2334 	/* for ep0: maxP defined in desc
2335 	 * for other eps, maxP is set by epautoconfig() called by gadget layer
2336 	 */
2337 	usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2338 
2339 	/* the queue lists any req for this ep */
2340 	INIT_LIST_HEAD(&ep->queue);
2341 
2342 	/* gagdet.ep_list used for ep_autoconfig so no ep0 */
2343 	if (link)
2344 		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2345 	ep->gadget = &udc->gadget;
2346 	ep->qh = &udc->ep_qh[index];
2347 
2348 	return 0;
2349 }
2350 
2351 /* Driver probe function
2352  * all initialization operations implemented here except enabling usb_intr reg
2353  * board setup should have been done in the platform code
2354  */
fsl_udc_probe(struct platform_device * pdev)2355 static int fsl_udc_probe(struct platform_device *pdev)
2356 {
2357 	struct fsl_usb2_platform_data *pdata;
2358 	struct resource *res;
2359 	int ret = -ENODEV;
2360 	unsigned int i;
2361 	u32 dccparams;
2362 
2363 	udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2364 	if (udc_controller == NULL)
2365 		return -ENOMEM;
2366 
2367 	pdata = dev_get_platdata(&pdev->dev);
2368 	udc_controller->pdata = pdata;
2369 	spin_lock_init(&udc_controller->lock);
2370 	udc_controller->stopped = 1;
2371 
2372 #ifdef CONFIG_USB_OTG
2373 	if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2374 		udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2375 		if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2376 			ERR("Can't find OTG driver!\n");
2377 			ret = -ENODEV;
2378 			goto err_kfree;
2379 		}
2380 	}
2381 #endif
2382 
2383 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2384 	if (!res) {
2385 		ret = -ENXIO;
2386 		goto err_kfree;
2387 	}
2388 
2389 	if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2390 		if (!request_mem_region(res->start, resource_size(res),
2391 					driver_name)) {
2392 			ERR("request mem region for %s failed\n", pdev->name);
2393 			ret = -EBUSY;
2394 			goto err_kfree;
2395 		}
2396 	}
2397 
2398 	dr_regs = ioremap(res->start, resource_size(res));
2399 	if (!dr_regs) {
2400 		ret = -ENOMEM;
2401 		goto err_release_mem_region;
2402 	}
2403 
2404 	pdata->regs = (void __iomem *)dr_regs;
2405 
2406 	/*
2407 	 * do platform specific init: check the clock, grab/config pins, etc.
2408 	 */
2409 	if (pdata->init && pdata->init(pdev)) {
2410 		ret = -ENODEV;
2411 		goto err_iounmap;
2412 	}
2413 
2414 	/* Set accessors only after pdata->init() ! */
2415 	fsl_set_accessors(pdata);
2416 
2417 	if (pdata->have_sysif_regs)
2418 		usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2419 
2420 	/* Read Device Controller Capability Parameters register */
2421 	dccparams = fsl_readl(&dr_regs->dccparams);
2422 	if (!(dccparams & DCCPARAMS_DC)) {
2423 		ERR("This SOC doesn't support device role\n");
2424 		ret = -ENODEV;
2425 		goto err_exit;
2426 	}
2427 	/* Get max device endpoints */
2428 	/* DEN is bidirectional ep number, max_ep doubles the number */
2429 	udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2430 
2431 	ret = platform_get_irq(pdev, 0);
2432 	if (ret <= 0) {
2433 		ret = ret ? : -ENODEV;
2434 		goto err_exit;
2435 	}
2436 	udc_controller->irq = ret;
2437 
2438 	ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2439 			driver_name, udc_controller);
2440 	if (ret != 0) {
2441 		ERR("cannot request irq %d err %d\n",
2442 				udc_controller->irq, ret);
2443 		goto err_exit;
2444 	}
2445 
2446 	/* Initialize the udc structure including QH member and other member */
2447 	if (struct_udc_setup(udc_controller, pdev)) {
2448 		ERR("Can't initialize udc data structure\n");
2449 		ret = -ENOMEM;
2450 		goto err_free_irq;
2451 	}
2452 
2453 	if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2454 		/* initialize usb hw reg except for regs for EP,
2455 		 * leave usbintr reg untouched */
2456 		dr_controller_setup(udc_controller);
2457 	}
2458 
2459 	/* Setup gadget structure */
2460 	udc_controller->gadget.ops = &fsl_gadget_ops;
2461 	udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2462 	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2463 	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2464 	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2465 	udc_controller->gadget.name = driver_name;
2466 
2467 	/* Setup gadget.dev and register with kernel */
2468 	dev_set_name(&udc_controller->gadget.dev, "gadget");
2469 	udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2470 
2471 	if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2472 		udc_controller->gadget.is_otg = 1;
2473 
2474 	/* setup QH and epctrl for ep0 */
2475 	ep0_setup(udc_controller);
2476 
2477 	/* setup udc->eps[] for ep0 */
2478 	struct_ep_setup(udc_controller, 0, "ep0", 0);
2479 	/* for ep0: the desc defined here;
2480 	 * for other eps, gadget layer called ep_enable with defined desc
2481 	 */
2482 	udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2483 	usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2484 				   USB_MAX_CTRL_PAYLOAD);
2485 
2486 	/* setup the udc->eps[] for non-control endpoints and link
2487 	 * to gadget.ep_list */
2488 	for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2489 		char name[16];
2490 
2491 		sprintf(name, "ep%dout", i);
2492 		struct_ep_setup(udc_controller, i * 2, name, 1);
2493 		sprintf(name, "ep%din", i);
2494 		struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2495 	}
2496 
2497 	/* use dma_pool for TD management */
2498 	udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2499 			sizeof(struct ep_td_struct),
2500 			DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2501 	if (udc_controller->td_pool == NULL) {
2502 		ret = -ENOMEM;
2503 		goto err_free_irq;
2504 	}
2505 
2506 	ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2507 			fsl_udc_release);
2508 	if (ret)
2509 		goto err_del_udc;
2510 
2511 	create_proc_file();
2512 	return 0;
2513 
2514 err_del_udc:
2515 	dma_pool_destroy(udc_controller->td_pool);
2516 err_free_irq:
2517 	free_irq(udc_controller->irq, udc_controller);
2518 err_exit:
2519 	if (pdata->exit)
2520 		pdata->exit(pdev);
2521 err_iounmap:
2522 	iounmap(dr_regs);
2523 err_release_mem_region:
2524 	if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2525 		release_mem_region(res->start, resource_size(res));
2526 err_kfree:
2527 	kfree(udc_controller);
2528 	udc_controller = NULL;
2529 	return ret;
2530 }
2531 
2532 /* Driver removal function
2533  * Free resources and finish pending transactions
2534  */
fsl_udc_remove(struct platform_device * pdev)2535 static int fsl_udc_remove(struct platform_device *pdev)
2536 {
2537 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2538 	struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2539 
2540 	DECLARE_COMPLETION_ONSTACK(done);
2541 
2542 	if (!udc_controller)
2543 		return -ENODEV;
2544 
2545 	udc_controller->done = &done;
2546 	usb_del_gadget_udc(&udc_controller->gadget);
2547 
2548 	/* DR has been stopped in usb_gadget_unregister_driver() */
2549 	remove_proc_file();
2550 
2551 	/* Free allocated memory */
2552 	kfree(udc_controller->status_req->req.buf);
2553 	kfree(udc_controller->status_req);
2554 	kfree(udc_controller->eps);
2555 
2556 	dma_pool_destroy(udc_controller->td_pool);
2557 	free_irq(udc_controller->irq, udc_controller);
2558 	iounmap(dr_regs);
2559 	if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2560 		release_mem_region(res->start, resource_size(res));
2561 
2562 	/* free udc --wait for the release() finished */
2563 	wait_for_completion(&done);
2564 
2565 	/*
2566 	 * do platform specific un-initialization:
2567 	 * release iomux pins, etc.
2568 	 */
2569 	if (pdata->exit)
2570 		pdata->exit(pdev);
2571 
2572 	return 0;
2573 }
2574 
2575 /*-----------------------------------------------------------------
2576  * Modify Power management attributes
2577  * Used by OTG statemachine to disable gadget temporarily
2578  -----------------------------------------------------------------*/
fsl_udc_suspend(struct platform_device * pdev,pm_message_t state)2579 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2580 {
2581 	dr_controller_stop(udc_controller);
2582 	return 0;
2583 }
2584 
2585 /*-----------------------------------------------------------------
2586  * Invoked on USB resume. May be called in_interrupt.
2587  * Here we start the DR controller and enable the irq
2588  *-----------------------------------------------------------------*/
fsl_udc_resume(struct platform_device * pdev)2589 static int fsl_udc_resume(struct platform_device *pdev)
2590 {
2591 	/* Enable DR irq reg and set controller Run */
2592 	if (udc_controller->stopped) {
2593 		dr_controller_setup(udc_controller);
2594 		dr_controller_run(udc_controller);
2595 	}
2596 	udc_controller->usb_state = USB_STATE_ATTACHED;
2597 	udc_controller->ep0_state = WAIT_FOR_SETUP;
2598 	udc_controller->ep0_dir = 0;
2599 	return 0;
2600 }
2601 
fsl_udc_otg_suspend(struct device * dev,pm_message_t state)2602 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2603 {
2604 	struct fsl_udc *udc = udc_controller;
2605 	u32 mode, usbcmd;
2606 
2607 	mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2608 
2609 	pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2610 
2611 	/*
2612 	 * If the controller is already stopped, then this must be a
2613 	 * PM suspend.  Remember this fact, so that we will leave the
2614 	 * controller stopped at PM resume time.
2615 	 */
2616 	if (udc->stopped) {
2617 		pr_debug("gadget already stopped, leaving early\n");
2618 		udc->already_stopped = 1;
2619 		return 0;
2620 	}
2621 
2622 	if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2623 		pr_debug("gadget not in device mode, leaving early\n");
2624 		return 0;
2625 	}
2626 
2627 	/* stop the controller */
2628 	usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2629 	fsl_writel(usbcmd, &dr_regs->usbcmd);
2630 
2631 	udc->stopped = 1;
2632 
2633 	pr_info("USB Gadget suspended\n");
2634 
2635 	return 0;
2636 }
2637 
fsl_udc_otg_resume(struct device * dev)2638 static int fsl_udc_otg_resume(struct device *dev)
2639 {
2640 	pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2641 		 udc_controller->stopped, udc_controller->already_stopped);
2642 
2643 	/*
2644 	 * If the controller was stopped at suspend time, then
2645 	 * don't resume it now.
2646 	 */
2647 	if (udc_controller->already_stopped) {
2648 		udc_controller->already_stopped = 0;
2649 		pr_debug("gadget was already stopped, leaving early\n");
2650 		return 0;
2651 	}
2652 
2653 	pr_info("USB Gadget resume\n");
2654 
2655 	return fsl_udc_resume(NULL);
2656 }
2657 /*-------------------------------------------------------------------------
2658 	Register entry point for the peripheral controller driver
2659 --------------------------------------------------------------------------*/
2660 static const struct platform_device_id fsl_udc_devtype[] = {
2661 	{
2662 		.name = "fsl-usb2-udc",
2663 	}, {
2664 		/* sentinel */
2665 	}
2666 };
2667 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2668 static struct platform_driver udc_driver = {
2669 	.remove		= fsl_udc_remove,
2670 	.id_table	= fsl_udc_devtype,
2671 	/* these suspend and resume are not usb suspend and resume */
2672 	.suspend	= fsl_udc_suspend,
2673 	.resume		= fsl_udc_resume,
2674 	.driver		= {
2675 			.name = driver_name,
2676 			/* udc suspend/resume called from OTG driver */
2677 			.suspend = fsl_udc_otg_suspend,
2678 			.resume  = fsl_udc_otg_resume,
2679 	},
2680 };
2681 
2682 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2683 
2684 MODULE_DESCRIPTION(DRIVER_DESC);
2685 MODULE_AUTHOR(DRIVER_AUTHOR);
2686 MODULE_LICENSE("GPL");
2687 MODULE_ALIAS("platform:fsl-usb2-udc");
2688