1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017 Intel Corporation <www.intel.com>
4 */
5
6 #include <asm/io.h>
7 #include <asm/arch/fpga_manager.h>
8 #include <asm/arch/reset_manager.h>
9 #include <asm/arch/system_manager.h>
10 #include <asm/arch/sdram.h>
11 #include <asm/arch/misc.h>
12 #include <altera.h>
13 #include <common.h>
14 #include <errno.h>
15 #include <wait_bit.h>
16 #include <watchdog.h>
17
18 #define CFGWDTH_32 1
19 #define MIN_BITSTREAM_SIZECHECK 230
20 #define ENCRYPTION_OFFSET 69
21 #define COMPRESSION_OFFSET 229
22 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
23 #define FPGA_TIMEOUT_CNT 0x1000000
24
25 static const struct socfpga_fpga_manager *fpga_manager_base =
26 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
27
28 static const struct socfpga_system_manager *system_manager_base =
29 (void *)SOCFPGA_SYSMGR_ADDRESS;
30
31 static void fpgamgr_set_cd_ratio(unsigned long ratio);
32
fpgamgr_get_msel(void)33 static uint32_t fpgamgr_get_msel(void)
34 {
35 u32 reg;
36
37 reg = readl(&fpga_manager_base->imgcfg_stat);
38 reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
39 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
40
41 return reg;
42 }
43
fpgamgr_set_cfgwdth(int width)44 static void fpgamgr_set_cfgwdth(int width)
45 {
46 if (width)
47 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
48 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
49 else
50 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
51 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
52 }
53
is_fpgamgr_user_mode(void)54 int is_fpgamgr_user_mode(void)
55 {
56 return (readl(&fpga_manager_base->imgcfg_stat) &
57 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
58 }
59
wait_for_user_mode(void)60 static int wait_for_user_mode(void)
61 {
62 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
63 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
64 1, FPGA_TIMEOUT_MSEC, false);
65 }
66
is_fpgamgr_early_user_mode(void)67 static int is_fpgamgr_early_user_mode(void)
68 {
69 return (readl(&fpga_manager_base->imgcfg_stat) &
70 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
71 }
72
fpgamgr_wait_early_user_mode(void)73 int fpgamgr_wait_early_user_mode(void)
74 {
75 u32 sync_data = 0xffffffff;
76 u32 i = 0;
77 unsigned start = get_timer(0);
78 unsigned long cd_ratio;
79
80 /* Getting existing CDRATIO */
81 cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
82 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
83 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
84
85 /* Using CDRATIO_X1 for better compatibility */
86 fpgamgr_set_cd_ratio(CDRATIO_x1);
87
88 while (!is_fpgamgr_early_user_mode()) {
89 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
90 return -ETIMEDOUT;
91 fpgamgr_program_write((const long unsigned int *)&sync_data,
92 sizeof(sync_data));
93 udelay(FPGA_TIMEOUT_MSEC);
94 i++;
95 }
96
97 debug("Additional %i sync word needed\n", i);
98
99 /* restoring original CDRATIO */
100 fpgamgr_set_cd_ratio(cd_ratio);
101
102 return 0;
103 }
104
105 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
wait_for_nconfig_pin_and_nstatus_pin(void)106 static int wait_for_nconfig_pin_and_nstatus_pin(void)
107 {
108 unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
109 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
110
111 /*
112 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
113 * de-asserted, timeout at 1000ms
114 */
115 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
116 true, FPGA_TIMEOUT_MSEC, false);
117 }
118
wait_for_f2s_nstatus_pin(unsigned long value)119 static int wait_for_f2s_nstatus_pin(unsigned long value)
120 {
121 /* Poll until f2s to specific value, timeout at 1000ms */
122 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
123 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
124 value, FPGA_TIMEOUT_MSEC, false);
125 }
126
127 /* set CD ratio */
fpgamgr_set_cd_ratio(unsigned long ratio)128 static void fpgamgr_set_cd_ratio(unsigned long ratio)
129 {
130 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
131 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
132
133 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
134 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
135 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
136 }
137
138 /* get the MSEL value, verify we are set for FPP configuration mode */
fpgamgr_verify_msel(void)139 static int fpgamgr_verify_msel(void)
140 {
141 u32 msel = fpgamgr_get_msel();
142
143 if (msel & ~BIT(0)) {
144 printf("Fail: read msel=%d\n", msel);
145 return -EPERM;
146 }
147
148 return 0;
149 }
150
151 /*
152 * Write cdratio and cdwidth based on whether the bitstream is compressed
153 * and/or encoded
154 */
fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width,u32 * rbf_data,size_t rbf_size)155 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
156 size_t rbf_size)
157 {
158 unsigned int cd_ratio;
159 bool encrypt, compress;
160
161 /*
162 * According to the bitstream specification,
163 * both encryption and compression status are
164 * in location before offset 230 of the buffer.
165 */
166 if (rbf_size < MIN_BITSTREAM_SIZECHECK)
167 return -EINVAL;
168
169 encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
170 encrypt = encrypt != 0;
171
172 compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
173 compress = !compress;
174
175 debug("header word %d = %08x\n", 69, rbf_data[69]);
176 debug("header word %d = %08x\n", 229, rbf_data[229]);
177 debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
178
179 /*
180 * from the register map description of cdratio in imgcfg_ctrl_02:
181 * Normal Configuration : 32bit Passive Parallel
182 * Partial Reconfiguration : 16bit Passive Parallel
183 */
184
185 /*
186 * cd ratio is dependent on cfg width and whether the bitstream
187 * is encrypted and/or compressed.
188 *
189 * | width | encr. | compr. | cd ratio |
190 * | 16 | 0 | 0 | 1 |
191 * | 16 | 0 | 1 | 4 |
192 * | 16 | 1 | 0 | 2 |
193 * | 16 | 1 | 1 | 4 |
194 * | 32 | 0 | 0 | 1 |
195 * | 32 | 0 | 1 | 8 |
196 * | 32 | 1 | 0 | 4 |
197 * | 32 | 1 | 1 | 8 |
198 */
199 if (!compress && !encrypt) {
200 cd_ratio = CDRATIO_x1;
201 } else {
202 if (compress)
203 cd_ratio = CDRATIO_x4;
204 else
205 cd_ratio = CDRATIO_x2;
206
207 /* if 32 bit, double the cd ratio (so register
208 field setting is incremented) */
209 if (cfg_width == CFGWDTH_32)
210 cd_ratio += 1;
211 }
212
213 fpgamgr_set_cfgwdth(cfg_width);
214 fpgamgr_set_cd_ratio(cd_ratio);
215
216 return 0;
217 }
218
fpgamgr_reset(void)219 static int fpgamgr_reset(void)
220 {
221 unsigned long reg;
222
223 /* S2F_NCONFIG = 0 */
224 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
225 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
226
227 /* Wait for f2s_nstatus == 0 */
228 if (wait_for_f2s_nstatus_pin(0))
229 return -ETIME;
230
231 /* S2F_NCONFIG = 1 */
232 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
233 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
234
235 /* Wait for f2s_nstatus == 1 */
236 if (wait_for_f2s_nstatus_pin(1))
237 return -ETIME;
238
239 /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
240 reg = readl(&fpga_manager_base->imgcfg_stat);
241 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
242 return -EPERM;
243
244 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
245 return -EPERM;
246
247 return 0;
248 }
249
250 /* Start the FPGA programming by initialize the FPGA Manager */
fpgamgr_program_init(u32 * rbf_data,size_t rbf_size)251 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
252 {
253 int ret;
254
255 /* Step 1 */
256 if (fpgamgr_verify_msel())
257 return -EPERM;
258
259 /* Step 2 */
260 if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
261 return -EPERM;
262
263 /*
264 * Step 3:
265 * Make sure no other external devices are trying to interfere with
266 * programming:
267 */
268 if (wait_for_nconfig_pin_and_nstatus_pin())
269 return -ETIME;
270
271 /*
272 * Step 4:
273 * Deassert the signal drives from HPS
274 *
275 * S2F_NCE = 1
276 * S2F_PR_REQUEST = 0
277 * EN_CFG_CTRL = 0
278 * EN_CFG_DATA = 0
279 * S2F_NCONFIG = 1
280 * S2F_NSTATUS_OE = 0
281 * S2F_CONDONE_OE = 0
282 */
283 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
284 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
285
286 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
287 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
288
289 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
290 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
291 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
292
293 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
294 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
295
296 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
297 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
298 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
299
300 /*
301 * Step 5:
302 * Enable overrides
303 * S2F_NENABLE_CONFIG = 0
304 * S2F_NENABLE_NCONFIG = 0
305 */
306 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
307 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
308 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
309 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
310
311 /*
312 * Disable driving signals that HPS doesn't need to drive.
313 * S2F_NENABLE_NSTATUS = 1
314 * S2F_NENABLE_CONDONE = 1
315 */
316 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
317 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
318 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
319
320 /*
321 * Step 6:
322 * Drive chip select S2F_NCE = 0
323 */
324 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
325 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
326
327 /* Step 7 */
328 if (wait_for_nconfig_pin_and_nstatus_pin())
329 return -ETIME;
330
331 /* Step 8 */
332 ret = fpgamgr_reset();
333
334 if (ret)
335 return ret;
336
337 /*
338 * Step 9:
339 * EN_CFG_CTRL and EN_CFG_DATA = 1
340 */
341 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
342 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
343 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
344
345 return 0;
346 }
347
348 /* Ensure the FPGA entering config done */
fpgamgr_program_poll_cd(void)349 static int fpgamgr_program_poll_cd(void)
350 {
351 unsigned long reg, i;
352
353 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
354 reg = readl(&fpga_manager_base->imgcfg_stat);
355 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
356 return 0;
357
358 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
359 printf("nstatus == 0 while waiting for condone\n");
360 return -EPERM;
361 }
362 }
363
364 if (i == FPGA_TIMEOUT_CNT)
365 return -ETIME;
366
367 return 0;
368 }
369
370 /* Ensure the FPGA entering user mode */
fpgamgr_program_poll_usermode(void)371 static int fpgamgr_program_poll_usermode(void)
372 {
373 unsigned long reg;
374 int ret = 0;
375
376 if (fpgamgr_dclkcnt_set(0xf))
377 return -ETIME;
378
379 ret = wait_for_user_mode();
380 if (ret < 0) {
381 printf("%s: Failed to enter user mode with ", __func__);
382 printf("error code %d\n", ret);
383 return ret;
384 }
385
386 /*
387 * Step 14:
388 * Stop DATA path and Dclk
389 * EN_CFG_CTRL and EN_CFG_DATA = 0
390 */
391 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
392 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
393 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
394
395 /*
396 * Step 15:
397 * Disable overrides
398 * S2F_NENABLE_CONFIG = 1
399 * S2F_NENABLE_NCONFIG = 1
400 */
401 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
402 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
403 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
404 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
405
406 /* Disable chip select S2F_NCE = 1 */
407 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
408 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
409
410 /*
411 * Step 16:
412 * Final check
413 */
414 reg = readl(&fpga_manager_base->imgcfg_stat);
415 if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
416 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
417 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
418 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
419 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
420 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
421 return -EPERM;
422
423 return 0;
424 }
425
fpgamgr_program_finish(void)426 int fpgamgr_program_finish(void)
427 {
428 /* Ensure the FPGA entering config done */
429 int status = fpgamgr_program_poll_cd();
430
431 if (status) {
432 printf("FPGA: Poll CD failed with error code %d\n", status);
433 return -EPERM;
434 }
435 WATCHDOG_RESET();
436
437 /* Ensure the FPGA entering user mode */
438 status = fpgamgr_program_poll_usermode();
439 if (status) {
440 printf("FPGA: Poll usermode failed with error code %d\n",
441 status);
442 return -EPERM;
443 }
444
445 printf("Full Configuration Succeeded.\n");
446
447 return 0;
448 }
449
450 /*
451 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
452 * Return 0 for sucess, non-zero for error.
453 */
socfpga_load(Altera_desc * desc,const void * rbf_data,size_t rbf_size)454 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
455 {
456 int status;
457
458 /* disable all signals from hps peripheral controller to fpga */
459 writel(0, &system_manager_base->fpgaintf_en_global);
460
461 /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
462 socfpga_bridges_reset();
463
464 /* Initialize the FPGA Manager */
465 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
466 if (status)
467 return status;
468
469 /* Write the RBF data to FPGA Manager */
470 fpgamgr_program_write(rbf_data, rbf_size);
471
472 return fpgamgr_program_finish();
473 }
474