1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _SYSTEM_MANAGER_GEN5_H_ 7 #define _SYSTEM_MANAGER_GEN5_H_ 8 9 #ifndef __ASSEMBLY__ 10 11 void sysmgr_pinmux_init(void); 12 void sysmgr_config_warmrstcfgio(int enable); 13 14 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); 15 16 struct socfpga_system_manager { 17 /* System Manager Module */ 18 u32 siliconid1; /* 0x00 */ 19 u32 siliconid2; 20 u32 _pad_0x8_0xf[2]; 21 u32 wddbg; /* 0x10 */ 22 u32 bootinfo; 23 u32 hpsinfo; 24 u32 parityinj; 25 /* FPGA Interface Group */ 26 u32 fpgaintfgrp_gbl; /* 0x20 */ 27 u32 fpgaintfgrp_indiv; 28 u32 fpgaintfgrp_module; 29 u32 _pad_0x2c_0x2f; 30 /* Scan Manager Group */ 31 u32 scanmgrgrp_ctrl; /* 0x30 */ 32 u32 _pad_0x34_0x3f[3]; 33 /* Freeze Control Group */ 34 u32 frzctrl_vioctrl; /* 0x40 */ 35 u32 _pad_0x44_0x4f[3]; 36 u32 frzctrl_hioctrl; /* 0x50 */ 37 u32 frzctrl_src; 38 u32 frzctrl_hwctrl; 39 u32 _pad_0x5c_0x5f; 40 /* EMAC Group */ 41 u32 emacgrp_ctrl; /* 0x60 */ 42 u32 emacgrp_l3master; 43 u32 _pad_0x68_0x6f[2]; 44 /* DMA Controller Group */ 45 u32 dmagrp_ctrl; /* 0x70 */ 46 u32 dmagrp_persecurity; 47 u32 _pad_0x78_0x7f[2]; 48 /* Preloader (initial software) Group */ 49 u32 iswgrp_handoff[8]; /* 0x80 */ 50 u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ 51 /* Boot ROM Code Register Group */ 52 u32 romcodegrp_ctrl; /* 0xc0 */ 53 u32 romcodegrp_cpu1startaddr; 54 u32 romcodegrp_initswstate; 55 u32 romcodegrp_initswlastld; 56 u32 romcodegrp_bootromswstate; /* 0xd0 */ 57 u32 __pad_0xd4_0xdf[3]; 58 /* Warm Boot from On-Chip RAM Group */ 59 u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ 60 u32 romcodegrp_warmramgrp_datastart; 61 u32 romcodegrp_warmramgrp_length; 62 u32 romcodegrp_warmramgrp_execution; 63 u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ 64 u32 __pad_0xf4_0xff[3]; 65 /* Boot ROM Hardware Register Group */ 66 u32 romhwgrp_ctrl; /* 0x100 */ 67 u32 _pad_0x104_0x107; 68 /* SDMMC Controller Group */ 69 u32 sdmmcgrp_ctrl; 70 u32 sdmmcgrp_l3master; 71 /* NAND Flash Controller Register Group */ 72 u32 nandgrp_bootstrap; /* 0x110 */ 73 u32 nandgrp_l3master; 74 /* USB Controller Group */ 75 u32 usbgrp_l3master; 76 u32 _pad_0x11c_0x13f[9]; 77 /* ECC Management Register Group */ 78 u32 eccgrp_l2; /* 0x140 */ 79 u32 eccgrp_ocram; 80 u32 eccgrp_usb0; 81 u32 eccgrp_usb1; 82 u32 eccgrp_emac0; /* 0x150 */ 83 u32 eccgrp_emac1; 84 u32 eccgrp_dma; 85 u32 eccgrp_can0; 86 u32 eccgrp_can1; /* 0x160 */ 87 u32 eccgrp_nand; 88 u32 eccgrp_qspi; 89 u32 eccgrp_sdmmc; 90 u32 _pad_0x170_0x3ff[164]; 91 /* Pin Mux Control Group */ 92 u32 emacio[20]; /* 0x400 */ 93 u32 flashio[12]; /* 0x450 */ 94 u32 generalio[28]; /* 0x480 */ 95 u32 _pad_0x4f0_0x4ff[4]; 96 u32 mixed1io[22]; /* 0x500 */ 97 u32 mixed2io[8]; /* 0x558 */ 98 u32 gplinmux[23]; /* 0x578 */ 99 u32 gplmux[71]; /* 0x5d4 */ 100 u32 nandusefpga; /* 0x6f0 */ 101 u32 _pad_0x6f4; 102 u32 rgmii1usefpga; /* 0x6f8 */ 103 u32 _pad_0x6fc_0x700[2]; 104 u32 i2c0usefpga; /* 0x704 */ 105 u32 sdmmcusefpga; /* 0x708 */ 106 u32 _pad_0x70c_0x710[2]; 107 u32 rgmii0usefpga; /* 0x714 */ 108 u32 _pad_0x718_0x720[3]; 109 u32 i2c3usefpga; /* 0x724 */ 110 u32 i2c2usefpga; /* 0x728 */ 111 u32 i2c1usefpga; /* 0x72c */ 112 u32 spim1usefpga; /* 0x730 */ 113 u32 _pad_0x734; 114 u32 spim0usefpga; /* 0x738 */ 115 }; 116 #endif 117 118 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 119 #define SYSMGR_BOOTINFO_BSEL_SHIFT 0 120 121 #endif /* _SYSTEM_MANAGER_GEN5_H_ */ 122