1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002-2013
4 * Eric Jarrige <eric.jarrige@armadeus.org>
5 *
6 * based on the files by
7 * Rich Ireland, Enterasys Networks, rireland@enterasys.com
8 * and
9 * Keith Outwater, keith_outwater@mvis.com
10 */
11 #include <common.h>
12
13 #include <asm/arch/imx-regs.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <command.h>
17 #include <config.h>
18 #include "fpga.h"
19 #include <spartan3.h>
20 #include "apf27.h"
21
22 /*
23 * Note that these are pointers to code that is in Flash. They will be
24 * relocated at runtime.
25 * Spartan2 code is used to download our Spartan 3 :) code is compatible.
26 * Just take care about the file size
27 */
28 xilinx_spartan3_slave_parallel_fns fpga_fns = {
29 fpga_pre_fn,
30 fpga_pgm_fn,
31 fpga_init_fn,
32 NULL,
33 fpga_done_fn,
34 fpga_clk_fn,
35 fpga_cs_fn,
36 fpga_wr_fn,
37 fpga_rdata_fn,
38 fpga_wdata_fn,
39 fpga_busy_fn,
40 fpga_abort_fn,
41 fpga_post_fn,
42 };
43
44 xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
45 {xilinx_spartan3,
46 slave_parallel,
47 1196128l/8,
48 (void *)&fpga_fns,
49 0,
50 &spartan3_op,
51 "3s200aft256"}
52 };
53
54 /*
55 * Initialize GPIO port B before download
56 */
fpga_pre_fn(int cookie)57 int fpga_pre_fn(int cookie)
58 {
59 /* Initialize GPIO pins */
60 gpio_set_value(ACFG_FPGA_PWR, 1);
61 imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
62 imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
63 imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
64 imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
65 imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
66 imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
67 imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
68 gpio_set_value(ACFG_FPGA_RESET, 1);
69 imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
70 imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
71 gpio_set_value(ACFG_FPGA_PRG, 1);
72 gpio_set_value(ACFG_FPGA_CLK, 1);
73 gpio_set_value(ACFG_FPGA_RW, 1);
74 gpio_set_value(ACFG_FPGA_CS, 1);
75 gpio_set_value(ACFG_FPGA_SUSPEND, 0);
76 gpio_set_value(ACFG_FPGA_PWR, 0);
77 udelay(30000); /*wait until supply started*/
78
79 return cookie;
80 }
81
82 /*
83 * Set the FPGA's active-low program line to the specified level
84 */
fpga_pgm_fn(int assert,int flush,int cookie)85 int fpga_pgm_fn(int assert, int flush, int cookie)
86 {
87 debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
88 assert ? "high" : "low");
89 gpio_set_value(ACFG_FPGA_PRG, !assert);
90 return assert;
91 }
92
93 /*
94 * Set the FPGA's active-high clock line to the specified level
95 */
fpga_clk_fn(int assert_clk,int flush,int cookie)96 int fpga_clk_fn(int assert_clk, int flush, int cookie)
97 {
98 debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
99 assert_clk ? "high" : "low");
100 gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
101 return assert_clk;
102 }
103
104 /*
105 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
106 * asserted (low).
107 */
fpga_init_fn(int cookie)108 int fpga_init_fn(int cookie)
109 {
110 int value;
111 debug("%s:%d: INIT check... ", __func__, __LINE__);
112 value = gpio_get_value(ACFG_FPGA_INIT);
113 /* printf("init value read %x",value); */
114 #ifdef CONFIG_SYS_FPGA_IS_PROTO
115 return value;
116 #else
117 return !value;
118 #endif
119 }
120
121 /*
122 * Test the state of the active-high FPGA DONE pin
123 */
fpga_done_fn(int cookie)124 int fpga_done_fn(int cookie)
125 {
126 debug("%s:%d: DONE check... %s", __func__, __LINE__,
127 gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
128 return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
129 }
130
131 /*
132 * Set the FPGA's wr line to the specified level
133 */
fpga_wr_fn(int assert_write,int flush,int cookie)134 int fpga_wr_fn(int assert_write, int flush, int cookie)
135 {
136 debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
137 assert_write ? "high" : "low");
138 gpio_set_value(ACFG_FPGA_RW, !assert_write);
139 return assert_write;
140 }
141
fpga_cs_fn(int assert_cs,int flush,int cookie)142 int fpga_cs_fn(int assert_cs, int flush, int cookie)
143 {
144 debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
145 assert_cs ? "high" : "low");
146 gpio_set_value(ACFG_FPGA_CS, !assert_cs);
147 return assert_cs;
148 }
149
fpga_rdata_fn(unsigned char * data,int cookie)150 int fpga_rdata_fn(unsigned char *data, int cookie)
151 {
152 debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
153 *((char *)ACFG_FPGA_RDATA));
154 *data = (unsigned char)
155 ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
156 return *data;
157 }
158
fpga_wdata_fn(unsigned char data,int flush,int cookie)159 int fpga_wdata_fn(unsigned char data, int flush, int cookie)
160 {
161 debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
162 data);
163 *((unsigned short *)ACFG_FPGA_WDATA) = data;
164 return data;
165 }
166
fpga_abort_fn(int cookie)167 int fpga_abort_fn(int cookie)
168 {
169 return fpga_post_fn(cookie);
170 }
171
172
fpga_busy_fn(int cookie)173 int fpga_busy_fn(int cookie)
174 {
175 return 1;
176 }
177
fpga_post_fn(int cookie)178 int fpga_post_fn(int cookie)
179 {
180 debug("%s:%d: FPGA POST ", __func__, __LINE__);
181
182 imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
183 imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
184 imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
185 gpio_set_value(ACFG_FPGA_PRG, 1);
186 gpio_set_value(ACFG_FPGA_RESET, 0);
187 imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
188 return cookie;
189 }
190
apf27_fpga_setup(void)191 void apf27_fpga_setup(void)
192 {
193 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
194 struct system_control_regs *system =
195 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
196
197 /* Configure FPGA CLKO */
198 writel(ACFG_CCSR_VAL, &pll->ccsr);
199
200 /* Configure strentgh for FPGA */
201 writel(ACFG_DSCR10_VAL, &system->dscr10);
202 writel(ACFG_DSCR3_VAL, &system->dscr3);
203 writel(ACFG_DSCR7_VAL, &system->dscr7);
204 writel(ACFG_DSCR2_VAL, &system->dscr2);
205 }
206
207 /*
208 * Initialize the fpga. Return 1 on success, 0 on failure.
209 */
APF27_init_fpga(void)210 void APF27_init_fpga(void)
211 {
212 int i;
213
214 apf27_fpga_setup();
215
216 fpga_init();
217
218 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
219 debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
220 fpga_add(fpga_xilinx, &fpga[i]);
221 }
222
223 return;
224 }
225