1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Pinctrl driver for STMicroelectronics STi SoCs
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
7 */
8
9 #include <common.h>
10 #include <bitfield.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <regmap.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <dm/pinctrl.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define MAX_STI_PINCONF_ENTRIES 7
21 /* Output enable */
22 #define OE (1 << 27)
23 /* Pull Up */
24 #define PU (1 << 26)
25 /* Open Drain */
26 #define OD (1 << 25)
27
28 /* User-frendly defines for Pin Direction */
29 /* oe = 0, pu = 0, od = 0 */
30 #define IN (0)
31 /* oe = 0, pu = 1, od = 0 */
32 #define IN_PU (PU)
33 /* oe = 1, pu = 0, od = 0 */
34 #define OUT (OE)
35 /* oe = 1, pu = 1, od = 0 */
36 #define OUT_PU (OE | PU)
37 /* oe = 1, pu = 0, od = 1 */
38 #define BIDIR (OE | OD)
39 /* oe = 1, pu = 1, od = 1 */
40 #define BIDIR_PU (OE | PU | OD)
41
42 struct sti_pinctrl_platdata {
43 struct regmap *regmap;
44 };
45
46 struct sti_pin_desc {
47 unsigned char bank;
48 unsigned char pin;
49 unsigned char alt;
50 int dir;
51 };
52
53 /*
54 * PIO alternative Function selector
55 */
sti_alternate_select(struct udevice * dev,struct sti_pin_desc * pin_desc)56 void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
57 {
58 struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
59 unsigned long sysconf, *sysconfreg;
60 int alt = pin_desc->alt;
61 int bank = pin_desc->bank;
62 int pin = pin_desc->pin;
63
64 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start;
65
66 switch (bank) {
67 case 0 ... 5: /* in "SBC Bank" */
68 sysconfreg += bank;
69 break;
70 case 10 ... 20: /* in "FRONT Bank" */
71 sysconfreg += bank - 10;
72 break;
73 case 30 ... 35: /* in "REAR Bank" */
74 sysconfreg += bank - 30;
75 break;
76 case 40 ... 42: /* in "FLASH Bank" */
77 sysconfreg += bank - 40;
78 break;
79 default:
80 BUG();
81 return;
82 }
83
84 sysconf = readl(sysconfreg);
85 sysconf = bitfield_replace(sysconf, pin * 4, 3, alt);
86 writel(sysconf, sysconfreg);
87 }
88
89 /* pin configuration */
sti_pin_configure(struct udevice * dev,struct sti_pin_desc * pin_desc)90 void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
91 {
92 struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
93 int bit;
94 int oe = 0, pu = 0, od = 0;
95 unsigned long *sysconfreg;
96 int bank = pin_desc->bank;
97
98 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start + 40;
99
100 /*
101 * NOTE: The PIO configuration for the PIO pins in the
102 * "FLASH Bank" are different from all the other banks!
103 * Specifically, the output-enable pin control register
104 * (SYS_CFG_3040) and the pull-up pin control register
105 * (SYS_CFG_3050), are both classed as being "reserved".
106 * Hence, we do not write to these registers to configure
107 * the OE and PU features for PIOs in this bank. However,
108 * the open-drain pin control register (SYS_CFG_3060)
109 * follows the style of the other banks, and so we can
110 * treat that register normally.
111 *
112 * Being pedantic, we should configure the PU and PD features
113 * in the "FLASH Bank" explicitly instead using the four
114 * SYS_CFG registers: 3080, 3081, 3085, and 3086. However, this
115 * would necessitate passing in the alternate function number
116 * to this function, and adding some horrible complexity here.
117 * Alternatively, we could just perform 4 32-bit "pokes" to
118 * these four SYS_CFG registers early in the initialization.
119 * In practice, these four SYS_CFG registers are correct
120 * after a reset, and U-Boot does not need to change them, so
121 * we (cheat and) rely on these registers being correct.
122 * WARNING: Please be aware of this (pragmatic) behaviour!
123 */
124 int flashss = 0; /* bool: PIO in the Flash Sub-System ? */
125
126 switch (pin_desc->dir) {
127 case IN:
128 oe = 0; pu = 0; od = 0;
129 break;
130 case IN_PU:
131 oe = 0; pu = 1; od = 0;
132 break;
133 case OUT:
134 oe = 1; pu = 0; od = 0;
135 break;
136 case BIDIR:
137 oe = 1; pu = 0; od = 1;
138 break;
139 case BIDIR_PU:
140 oe = 1; pu = 1; od = 1;
141 break;
142
143 default:
144 pr_err("%s invalid direction value: 0x%x\n",
145 __func__, pin_desc->dir);
146 BUG();
147 break;
148 }
149
150 switch (bank) {
151 case 0 ... 5: /* in "SBC Bank" */
152 sysconfreg += bank / 4;
153 break;
154 case 10 ... 20: /* in "FRONT Bank" */
155 bank -= 10;
156 sysconfreg += bank / 4;
157 break;
158 case 30 ... 35: /* in "REAR Bank" */
159 bank -= 30;
160 sysconfreg += bank / 4;
161 break;
162 case 40 ... 42: /* in "FLASH Bank" */
163 bank -= 40;
164 sysconfreg += bank / 4;
165 flashss = 1; /* pin is in the Flash Sub-System */
166 break;
167 default:
168 BUG();
169 return;
170 }
171
172 bit = ((bank * 8) + pin_desc->pin) % 32;
173
174 /*
175 * set the "Output Enable" pin control
176 * but, do nothing if in the flashSS
177 */
178 if (!flashss) {
179 if (oe)
180 generic_set_bit(bit, sysconfreg);
181 else
182 generic_clear_bit(bit, sysconfreg);
183 }
184
185 sysconfreg += 10; /* skip to next set of syscfg registers */
186
187 /*
188 * set the "Pull Up" pin control
189 * but, do nothing if in the FlashSS
190 */
191
192 if (!flashss) {
193 if (pu)
194 generic_set_bit(bit, sysconfreg);
195 else
196 generic_clear_bit(bit, sysconfreg);
197 }
198
199 sysconfreg += 10; /* skip to next set of syscfg registers */
200
201 /* set the "Open Drain Enable" pin control */
202 if (od)
203 generic_set_bit(bit, sysconfreg);
204 else
205 generic_clear_bit(bit, sysconfreg);
206 }
207
208
sti_pinctrl_set_state(struct udevice * dev,struct udevice * config)209 static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
210 {
211 struct fdtdec_phandle_args args;
212 const void *blob = gd->fdt_blob;
213 const char *prop_name;
214 int node = dev_of_offset(config);
215 int property_offset, prop_len;
216 int pinconf_node, ret, count;
217 const char *bank_name;
218 u32 cells[MAX_STI_PINCONF_ENTRIES];
219
220 struct sti_pin_desc pin_desc;
221
222 /* go to next node "st,pins" which contains the pins configuration */
223 pinconf_node = fdt_subnode_offset(blob, node, "st,pins");
224
225 /*
226 * parse each pins configuration which looks like :
227 * pin_name = <bank_phandle pin_nb alt dir rt_type rt_delay rt_clk>
228 */
229
230 fdt_for_each_property_offset(property_offset, blob, pinconf_node) {
231 fdt_getprop_by_offset(blob, property_offset, &prop_name,
232 &prop_len);
233
234 /* extract the bank of the pin description */
235 ret = fdtdec_parse_phandle_with_args(blob, pinconf_node,
236 prop_name, "#gpio-cells",
237 0, 0, &args);
238 if (ret < 0) {
239 pr_err("Can't get the gpio bank phandle: %d\n", ret);
240 return ret;
241 }
242
243 bank_name = fdt_getprop(blob, args.node, "st,bank-name",
244 &count);
245 if (count < 0) {
246 pr_err("Can't find bank-name property %d\n", count);
247 return -EINVAL;
248 }
249
250 pin_desc.bank = trailing_strtoln(bank_name, NULL);
251
252 count = fdtdec_get_int_array_count(blob, pinconf_node,
253 prop_name, cells,
254 ARRAY_SIZE(cells));
255 if (count < 0) {
256 pr_err("Bad pin configuration array %d\n", count);
257 return -EINVAL;
258 }
259
260 if (count > MAX_STI_PINCONF_ENTRIES) {
261 pr_err("Unsupported pinconf array count %d\n", count);
262 return -EINVAL;
263 }
264
265 pin_desc.pin = cells[1];
266 pin_desc.alt = cells[2];
267 pin_desc.dir = cells[3];
268
269 sti_alternate_select(dev, &pin_desc);
270 sti_pin_configure(dev, &pin_desc);
271 };
272
273 return 0;
274 }
275
sti_pinctrl_probe(struct udevice * dev)276 static int sti_pinctrl_probe(struct udevice *dev)
277 {
278 struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
279 struct udevice *syscon;
280 int err;
281
282 /* get corresponding syscon phandle */
283 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
284 "st,syscfg", &syscon);
285 if (err) {
286 pr_err("unable to find syscon device\n");
287 return err;
288 }
289
290 plat->regmap = syscon_get_regmap(syscon);
291 if (!plat->regmap) {
292 pr_err("unable to find regmap\n");
293 return -ENODEV;
294 }
295
296 return 0;
297 }
298
299 static const struct udevice_id sti_pinctrl_ids[] = {
300 { .compatible = "st,stih407-sbc-pinctrl" },
301 { .compatible = "st,stih407-front-pinctrl" },
302 { .compatible = "st,stih407-rear-pinctrl" },
303 { .compatible = "st,stih407-flash-pinctrl" },
304 { }
305 };
306
307 const struct pinctrl_ops sti_pinctrl_ops = {
308 .set_state = sti_pinctrl_set_state,
309 };
310
311 U_BOOT_DRIVER(pinctrl_sti) = {
312 .name = "pinctrl_sti",
313 .id = UCLASS_PINCTRL,
314 .of_match = sti_pinctrl_ids,
315 .ops = &sti_pinctrl_ops,
316 .probe = sti_pinctrl_probe,
317 .platdata_auto_alloc_size = sizeof(struct sti_pinctrl_platdata),
318 .ops = &sti_pinctrl_ops,
319 };
320