1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 *
10 * (C) Copyright 2003
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
13 *
14 * (C) Copyright 2004
15 * ARM Ltd.
16 * Philippe Robin, <philippe.robin@arm.com>
17 */
18 #include <common.h>
19 #include <malloc.h>
20 #include <errno.h>
21 #include <netdev.h>
22 #include <asm/io.h>
23 #include <asm/mach-types.h>
24 #include <asm/arch/systimer.h>
25 #include <asm/arch/sysctrl.h>
26 #include <asm/arch/wdt.h>
27 #include "../drivers/mmc/arm_pl180_mmci.h"
28
29 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
30 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
31
32 static void flash__init(void);
33 static void vexpress_timer_init(void);
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)37 void show_boot_progress(int progress)
38 {
39 printf("Boot reached stage %d\n", progress);
40 }
41 #endif
42
delay(ulong loops)43 static inline void delay(ulong loops)
44 {
45 __asm__ volatile ("1:\n"
46 "subs %0, %1, #1\n"
47 "bne 1b" : "=r" (loops) : "0" (loops));
48 }
49
board_init(void)50 int board_init(void)
51 {
52 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
53 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
54 gd->flags = 0;
55
56 icache_enable();
57 flash__init();
58 vexpress_timer_init();
59
60 return 0;
61 }
62
board_eth_init(bd_t * bis)63 int board_eth_init(bd_t *bis)
64 {
65 int rc = 0;
66 #ifdef CONFIG_SMC911X
67 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
68 #endif
69 return rc;
70 }
71
cpu_mmc_init(bd_t * bis)72 int cpu_mmc_init(bd_t *bis)
73 {
74 int rc = 0;
75 (void) bis;
76 #ifdef CONFIG_ARM_PL180_MMCI
77 struct pl180_mmc_host *host;
78 struct mmc *mmc;
79
80 host = malloc(sizeof(struct pl180_mmc_host));
81 if (!host)
82 return -ENOMEM;
83 memset(host, 0, sizeof(*host));
84
85 strcpy(host->name, "MMC");
86 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
87 host->pwr_init = INIT_PWR;
88 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
89 host->voltages = VOLTAGE_WINDOW_MMC;
90 host->caps = 0;
91 host->clock_in = ARM_MCLK;
92 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
93 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
94 rc = arm_pl180_mmci_init(host, &mmc);
95 #endif
96 return rc;
97 }
98
flash__init(void)99 static void flash__init(void)
100 {
101 /* Setup the sytem control register to allow writing to flash */
102 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
103 &sysctrl_base->scflashctrl);
104 }
105
dram_init(void)106 int dram_init(void)
107 {
108 gd->ram_size =
109 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
110 return 0;
111 }
112
dram_init_banksize(void)113 int dram_init_banksize(void)
114 {
115 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
116 gd->bd->bi_dram[0].size =
117 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
118 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
119 gd->bd->bi_dram[1].size =
120 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
121
122 return 0;
123 }
124
125 /*
126 * Start timer:
127 * Setup a 32 bit timer, running at 1KHz
128 * Versatile Express Motherboard provides 1 MHz timer
129 */
vexpress_timer_init(void)130 static void vexpress_timer_init(void)
131 {
132 /*
133 * Set clock frequency in system controller:
134 * VEXPRESS_REFCLK is 32KHz
135 * VEXPRESS_TIMCLK is 1MHz
136 */
137 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
138 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
139 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
140
141 /*
142 * Set Timer0 to be:
143 * Enabled, free running, no interrupt, 32-bit, wrapping
144 */
145 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
146 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
147 writel(SYSTIMER_EN | SYSTIMER_32BIT |
148 readl(&systimer_base->timer0control),
149 &systimer_base->timer0control);
150 }
151
v2m_cfg_write(u32 devfn,u32 data)152 int v2m_cfg_write(u32 devfn, u32 data)
153 {
154 /* Configuration interface broken? */
155 u32 val;
156
157 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
158
159 val = readl(V2M_SYS_CFGSTAT);
160 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
161
162 writel(data, V2M_SYS_CFGDATA);
163 writel(devfn, V2M_SYS_CFGCTRL);
164
165 do {
166 val = readl(V2M_SYS_CFGSTAT);
167 } while (val == 0);
168
169 return !!(val & SYS_CFG_ERR);
170 }
171
172 /* Use the ARM Watchdog System to cause reset */
reset_cpu(ulong addr)173 void reset_cpu(ulong addr)
174 {
175 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
176 printf("Unable to reboot\n");
177 }
178
lowlevel_init(void)179 void lowlevel_init(void)
180 {
181 }
182
get_board_rev(void)183 ulong get_board_rev(void){
184 return readl((u32 *)SYS_ID);
185 }
186
187 #ifdef CONFIG_ARMV7_NONSEC
188 /* Setting the address at which secondary cores start from.
189 * Versatile Express uses one address for all cores, so ignore corenr
190 */
smp_set_core_boot_addr(unsigned long addr,int corenr)191 void smp_set_core_boot_addr(unsigned long addr, int corenr)
192 {
193 /* The SYSFLAGS register on VExpress needs to be cleared first
194 * by writing to the next address, since any writes to the address
195 * at offset 0 will only be ORed in
196 */
197 writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
198 writel(addr, CONFIG_SYSFLAGS_ADDR);
199 }
200 #endif
201