1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Author: Huang Rui <ray.huang@amd.com>
23  *
24  */
25 #include "pp_debug.h"
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gfp.h>
31 
32 #include "smumgr.h"
33 #include "iceland_smumgr.h"
34 
35 #include "ppsmc.h"
36 
37 #include "cgs_common.h"
38 
39 #include "smu7_dyn_defaults.h"
40 #include "smu7_hwmgr.h"
41 #include "hardwaremanager.h"
42 #include "ppatomctrl.h"
43 #include "atombios.h"
44 #include "pppcielanes.h"
45 #include "pp_endian.h"
46 #include "processpptables.h"
47 
48 
49 #include "smu/smu_7_1_1_d.h"
50 #include "smu/smu_7_1_1_sh_mask.h"
51 #include "smu71_discrete.h"
52 
53 #include "smu_ucode_xfer_vi.h"
54 #include "gmc/gmc_8_1_d.h"
55 #include "gmc/gmc_8_1_sh_mask.h"
56 #include "bif/bif_5_0_d.h"
57 #include "bif/bif_5_0_sh_mask.h"
58 #include "dce/dce_10_0_d.h"
59 #include "dce/dce_10_0_sh_mask.h"
60 
61 
62 #define ICELAND_SMC_SIZE               0x20000
63 
64 #define POWERTUNE_DEFAULT_SET_MAX    1
65 #define MC_CG_ARB_FREQ_F1           0x0b
66 #define VDDC_VDDCI_DELTA            200
67 
68 #define DEVICE_ID_VI_ICELAND_M_6900	0x6900
69 #define DEVICE_ID_VI_ICELAND_M_6901	0x6901
70 #define DEVICE_ID_VI_ICELAND_M_6902	0x6902
71 #define DEVICE_ID_VI_ICELAND_M_6903	0x6903
72 
73 static const struct iceland_pt_defaults defaults_iceland = {
74 	/*
75 	 * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
76 	 * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
77 	 */
78 	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
79 	{ 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
80 	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
81 };
82 
83 /* 35W - XT, XTL */
84 static const struct iceland_pt_defaults defaults_icelandxt = {
85 	/*
86 	 * sviLoadLIneEn, SviLoadLineVddC,
87 	 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
88 	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
89 	 * BAPM_TEMP_GRADIENT
90 	 */
91 	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
92 	{ 0xA7,  0x0, 0x0, 0xB5,  0x0, 0x0, 0x9F,  0x0, 0x0, 0xD6,  0x0, 0x0, 0xD7,  0x0, 0x0},
93 	{ 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
94 };
95 
96 /* 25W - PRO, LE */
97 static const struct iceland_pt_defaults defaults_icelandpro = {
98 	/*
99 	 * sviLoadLIneEn, SviLoadLineVddC,
100 	 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
101 	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
102 	 * BAPM_TEMP_GRADIENT
103 	 */
104 	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
105 	{ 0xB7,  0x0, 0x0, 0xC3,  0x0, 0x0, 0xB5,  0x0, 0x0, 0xEA,  0x0, 0x0, 0xE6,  0x0, 0x0},
106 	{ 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
107 };
108 
iceland_start_smc(struct pp_hwmgr * hwmgr)109 static int iceland_start_smc(struct pp_hwmgr *hwmgr)
110 {
111 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
112 				  SMC_SYSCON_RESET_CNTL, rst_reg, 0);
113 
114 	return 0;
115 }
116 
iceland_reset_smc(struct pp_hwmgr * hwmgr)117 static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
118 {
119 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
120 				  SMC_SYSCON_RESET_CNTL,
121 				  rst_reg, 1);
122 }
123 
124 
iceland_stop_smc_clock(struct pp_hwmgr * hwmgr)125 static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
126 {
127 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
128 				  SMC_SYSCON_CLOCK_CNTL_0,
129 				  ck_disable, 1);
130 }
131 
iceland_start_smc_clock(struct pp_hwmgr * hwmgr)132 static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
133 {
134 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
135 				  SMC_SYSCON_CLOCK_CNTL_0,
136 				  ck_disable, 0);
137 }
138 
iceland_smu_start_smc(struct pp_hwmgr * hwmgr)139 static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
140 {
141 	/* set smc instruct start point at 0x0 */
142 	smu7_program_jump_on_start(hwmgr);
143 
144 	/* enable smc clock */
145 	iceland_start_smc_clock(hwmgr);
146 
147 	/* de-assert reset */
148 	iceland_start_smc(hwmgr);
149 
150 	PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
151 				 INTERRUPTS_ENABLED, 1);
152 
153 	return 0;
154 }
155 
156 
iceland_upload_smc_firmware_data(struct pp_hwmgr * hwmgr,uint32_t length,const uint8_t * src,uint32_t limit,uint32_t start_addr)157 static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
158 					uint32_t length, const uint8_t *src,
159 					uint32_t limit, uint32_t start_addr)
160 {
161 	uint32_t byte_count = length;
162 	uint32_t data;
163 
164 	PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
165 
166 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
167 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
168 
169 	while (byte_count >= 4) {
170 		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
171 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
172 		src += 4;
173 		byte_count -= 4;
174 	}
175 
176 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
177 
178 	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
179 
180 	return 0;
181 }
182 
183 
iceland_smu_upload_firmware_image(struct pp_hwmgr * hwmgr)184 static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
185 {
186 	uint32_t val;
187 	struct cgs_firmware_info info = {0};
188 
189 	if (hwmgr == NULL || hwmgr->device == NULL)
190 		return -EINVAL;
191 
192 	/* load SMC firmware */
193 	cgs_get_firmware_info(hwmgr->device,
194 		smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
195 
196 	if (info.image_size & 3) {
197 		pr_err("[ powerplay ] SMC ucode is not 4 bytes aligned\n");
198 		return -EINVAL;
199 	}
200 
201 	if (info.image_size > ICELAND_SMC_SIZE) {
202 		pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
203 		return -EINVAL;
204 	}
205 	hwmgr->smu_version = info.version;
206 	/* wait for smc boot up */
207 	PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
208 					 RCU_UC_EVENTS, boot_seq_done, 0);
209 
210 	/* clear firmware interrupt enable flag */
211 	val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
212 				    ixSMC_SYSCON_MISC_CNTL);
213 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
214 			       ixSMC_SYSCON_MISC_CNTL, val | 1);
215 
216 	/* stop smc clock */
217 	iceland_stop_smc_clock(hwmgr);
218 
219 	/* reset smc */
220 	iceland_reset_smc(hwmgr);
221 	iceland_upload_smc_firmware_data(hwmgr, info.image_size,
222 				(uint8_t *)info.kptr, ICELAND_SMC_SIZE,
223 				info.ucode_start_address);
224 
225 	return 0;
226 }
227 
iceland_request_smu_load_specific_fw(struct pp_hwmgr * hwmgr,uint32_t firmwareType)228 static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
229 						uint32_t firmwareType)
230 {
231 	return 0;
232 }
233 
iceland_start_smu(struct pp_hwmgr * hwmgr)234 static int iceland_start_smu(struct pp_hwmgr *hwmgr)
235 {
236 	struct iceland_smumgr *priv = hwmgr->smu_backend;
237 	int result;
238 
239 	if (!smu7_is_smc_ram_running(hwmgr)) {
240 		result = iceland_smu_upload_firmware_image(hwmgr);
241 		if (result)
242 			return result;
243 
244 		iceland_smu_start_smc(hwmgr);
245 	}
246 
247 	/* Setup SoftRegsStart here to visit the register UcodeLoadStatus
248 	 * to check fw loading state
249 	 */
250 	smu7_read_smc_sram_dword(hwmgr,
251 			SMU71_FIRMWARE_HEADER_LOCATION +
252 			offsetof(SMU71_Firmware_Header, SoftRegisters),
253 			&(priv->smu7_data.soft_regs_start), 0x40000);
254 
255 	result = smu7_request_smu_load_fw(hwmgr);
256 
257 	return result;
258 }
259 
iceland_smu_init(struct pp_hwmgr * hwmgr)260 static int iceland_smu_init(struct pp_hwmgr *hwmgr)
261 {
262 	struct iceland_smumgr *iceland_priv;
263 
264 	iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
265 
266 	if (iceland_priv == NULL)
267 		return -ENOMEM;
268 
269 	hwmgr->smu_backend = iceland_priv;
270 
271 	if (smu7_init(hwmgr)) {
272 		kfree(iceland_priv);
273 		return -EINVAL;
274 	}
275 
276 	return 0;
277 }
278 
279 
iceland_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)280 static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
281 {
282 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
283 	struct amdgpu_device *adev = hwmgr->adev;
284 	uint32_t dev_id;
285 
286 	dev_id = adev->pdev->device;
287 
288 	switch (dev_id) {
289 	case DEVICE_ID_VI_ICELAND_M_6900:
290 	case DEVICE_ID_VI_ICELAND_M_6903:
291 		smu_data->power_tune_defaults = &defaults_icelandxt;
292 		break;
293 
294 	case DEVICE_ID_VI_ICELAND_M_6901:
295 	case DEVICE_ID_VI_ICELAND_M_6902:
296 		smu_data->power_tune_defaults = &defaults_icelandpro;
297 		break;
298 	default:
299 		smu_data->power_tune_defaults = &defaults_iceland;
300 		pr_warn("Unknown V.I. Device ID.\n");
301 		break;
302 	}
303 	return;
304 }
305 
iceland_populate_svi_load_line(struct pp_hwmgr * hwmgr)306 static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
307 {
308 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
309 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
310 
311 	smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
312 	smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
313 	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
314 	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
315 
316 	return 0;
317 }
318 
iceland_populate_tdc_limit(struct pp_hwmgr * hwmgr)319 static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
320 {
321 	uint16_t tdc_limit;
322 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
323 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
324 
325 	tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
326 	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
327 			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
328 	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
329 			defaults->tdc_vddc_throttle_release_limit_perc;
330 	smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
331 
332 	return 0;
333 }
334 
iceland_populate_dw8(struct pp_hwmgr * hwmgr,uint32_t fuse_table_offset)335 static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
336 {
337 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
338 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
339 	uint32_t temp;
340 
341 	if (smu7_read_smc_sram_dword(hwmgr,
342 			fuse_table_offset +
343 			offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
344 			(uint32_t *)&temp, SMC_RAM_END))
345 		PP_ASSERT_WITH_CODE(false,
346 				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
347 				return -EINVAL);
348 	else
349 		smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
350 
351 	return 0;
352 }
353 
iceland_populate_temperature_scaler(struct pp_hwmgr * hwmgr)354 static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
355 {
356 	return 0;
357 }
358 
iceland_populate_gnb_lpml(struct pp_hwmgr * hwmgr)359 static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
360 {
361 	int i;
362 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
363 
364 	/* Currently not used. Set all to zero. */
365 	for (i = 0; i < 8; i++)
366 		smu_data->power_tune_table.GnbLPML[i] = 0;
367 
368 	return 0;
369 }
370 
iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr * hwmgr)371 static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
372 {
373 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
374 	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
375 	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
376 	struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
377 
378 	HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
379 	LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
380 
381 	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
382 			CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
383 	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
384 			CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
385 
386 	return 0;
387 }
388 
iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr * hwmgr)389 static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
390 {
391 	int i;
392 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
393 	uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
394 	uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
395 
396 	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
397 			    "The CAC Leakage table does not exist!", return -EINVAL);
398 	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
399 			    "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
400 	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
401 			    "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
402 
403 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
404 		for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
405 			lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
406 			hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
407 		}
408 	} else {
409 		PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
410 	}
411 
412 	return 0;
413 }
414 
iceland_populate_vddc_vid(struct pp_hwmgr * hwmgr)415 static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
416 {
417 	int i;
418 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
419 	uint8_t *vid = smu_data->power_tune_table.VddCVid;
420 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
421 
422 	PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
423 		"There should never be more than 8 entries for VddcVid!!!",
424 		return -EINVAL);
425 
426 	for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
427 		vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
428 	}
429 
430 	return 0;
431 }
432 
433 
434 
iceland_populate_pm_fuses(struct pp_hwmgr * hwmgr)435 static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
436 {
437 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
438 	uint32_t pm_fuse_table_offset;
439 
440 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
441 			PHM_PlatformCaps_PowerContainment)) {
442 		if (smu7_read_smc_sram_dword(hwmgr,
443 				SMU71_FIRMWARE_HEADER_LOCATION +
444 				offsetof(SMU71_Firmware_Header, PmFuseTable),
445 				&pm_fuse_table_offset, SMC_RAM_END))
446 			PP_ASSERT_WITH_CODE(false,
447 					"Attempt to get pm_fuse_table_offset Failed!",
448 					return -EINVAL);
449 
450 		/* DW0 - DW3 */
451 		if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
452 			PP_ASSERT_WITH_CODE(false,
453 					"Attempt to populate bapm vddc vid Failed!",
454 					return -EINVAL);
455 
456 		/* DW4 - DW5 */
457 		if (iceland_populate_vddc_vid(hwmgr))
458 			PP_ASSERT_WITH_CODE(false,
459 					"Attempt to populate vddc vid Failed!",
460 					return -EINVAL);
461 
462 		/* DW6 */
463 		if (iceland_populate_svi_load_line(hwmgr))
464 			PP_ASSERT_WITH_CODE(false,
465 					"Attempt to populate SviLoadLine Failed!",
466 					return -EINVAL);
467 		/* DW7 */
468 		if (iceland_populate_tdc_limit(hwmgr))
469 			PP_ASSERT_WITH_CODE(false,
470 					"Attempt to populate TDCLimit Failed!", return -EINVAL);
471 		/* DW8 */
472 		if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
473 			PP_ASSERT_WITH_CODE(false,
474 					"Attempt to populate TdcWaterfallCtl, "
475 					"LPMLTemperature Min and Max Failed!",
476 					return -EINVAL);
477 
478 		/* DW9-DW12 */
479 		if (0 != iceland_populate_temperature_scaler(hwmgr))
480 			PP_ASSERT_WITH_CODE(false,
481 					"Attempt to populate LPMLTemperatureScaler Failed!",
482 					return -EINVAL);
483 
484 		/* DW13-DW16 */
485 		if (iceland_populate_gnb_lpml(hwmgr))
486 			PP_ASSERT_WITH_CODE(false,
487 					"Attempt to populate GnbLPML Failed!",
488 					return -EINVAL);
489 
490 		/* DW18 */
491 		if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
492 			PP_ASSERT_WITH_CODE(false,
493 					"Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
494 					return -EINVAL);
495 
496 		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
497 				(uint8_t *)&smu_data->power_tune_table,
498 				sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
499 			PP_ASSERT_WITH_CODE(false,
500 					"Attempt to download PmFuseTable Failed!",
501 					return -EINVAL);
502 	}
503 	return 0;
504 }
505 
iceland_get_dependency_volt_by_clk(struct pp_hwmgr * hwmgr,struct phm_clock_voltage_dependency_table * allowed_clock_voltage_table,uint32_t clock,uint32_t * vol)506 static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
507 	struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
508 	uint32_t clock, uint32_t *vol)
509 {
510 	uint32_t i = 0;
511 
512 	/* clock - voltage dependency table is empty table */
513 	if (allowed_clock_voltage_table->count == 0)
514 		return -EINVAL;
515 
516 	for (i = 0; i < allowed_clock_voltage_table->count; i++) {
517 		/* find first sclk bigger than request */
518 		if (allowed_clock_voltage_table->entries[i].clk >= clock) {
519 			*vol = allowed_clock_voltage_table->entries[i].v;
520 			return 0;
521 		}
522 	}
523 
524 	/* sclk is bigger than max sclk in the dependence table */
525 	*vol = allowed_clock_voltage_table->entries[i - 1].v;
526 
527 	return 0;
528 }
529 
iceland_get_std_voltage_value_sidd(struct pp_hwmgr * hwmgr,pp_atomctrl_voltage_table_entry * tab,uint16_t * hi,uint16_t * lo)530 static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
531 		pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
532 		uint16_t *lo)
533 {
534 	uint16_t v_index;
535 	bool vol_found = false;
536 	*hi = tab->value * VOLTAGE_SCALE;
537 	*lo = tab->value * VOLTAGE_SCALE;
538 
539 	/* SCLK/VDDC Dependency Table has to exist. */
540 	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
541 			"The SCLK/VDDC Dependency Table does not exist.",
542 			return -EINVAL);
543 
544 	if (NULL == hwmgr->dyn_state.cac_leakage_table) {
545 		pr_warn("CAC Leakage Table does not exist, using vddc.\n");
546 		return 0;
547 	}
548 
549 	/*
550 	 * Since voltage in the sclk/vddc dependency table is not
551 	 * necessarily in ascending order because of ELB voltage
552 	 * patching, loop through entire list to find exact voltage.
553 	 */
554 	for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
555 		if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
556 			vol_found = true;
557 			if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
558 				*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
559 				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
560 			} else {
561 				pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
562 				*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
563 				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
564 			}
565 			break;
566 		}
567 	}
568 
569 	/*
570 	 * If voltage is not found in the first pass, loop again to
571 	 * find the best match, equal or higher value.
572 	 */
573 	if (!vol_found) {
574 		for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
575 			if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
576 				vol_found = true;
577 				if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
578 					*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
579 					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
580 				} else {
581 					pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
582 					*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
583 					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
584 				}
585 				break;
586 			}
587 		}
588 
589 		if (!vol_found)
590 			pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
591 	}
592 
593 	return 0;
594 }
595 
iceland_populate_smc_voltage_table(struct pp_hwmgr * hwmgr,pp_atomctrl_voltage_table_entry * tab,SMU71_Discrete_VoltageLevel * smc_voltage_tab)596 static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
597 		pp_atomctrl_voltage_table_entry *tab,
598 		SMU71_Discrete_VoltageLevel *smc_voltage_tab)
599 {
600 	int result;
601 
602 	result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
603 			&smc_voltage_tab->StdVoltageHiSidd,
604 			&smc_voltage_tab->StdVoltageLoSidd);
605 	if (0 != result) {
606 		smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
607 		smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
608 	}
609 
610 	smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
611 	CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
612 	CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
613 
614 	return 0;
615 }
616 
iceland_populate_smc_vddc_table(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)617 static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
618 			SMU71_Discrete_DpmTable *table)
619 {
620 	unsigned int count;
621 	int result;
622 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
623 
624 	table->VddcLevelCount = data->vddc_voltage_table.count;
625 	for (count = 0; count < table->VddcLevelCount; count++) {
626 		result = iceland_populate_smc_voltage_table(hwmgr,
627 				&(data->vddc_voltage_table.entries[count]),
628 				&(table->VddcLevel[count]));
629 		PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
630 
631 		/* GPIO voltage control */
632 		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
633 			table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
634 		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
635 			table->VddcLevel[count].Smio = 0;
636 	}
637 
638 	CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
639 
640 	return 0;
641 }
642 
iceland_populate_smc_vdd_ci_table(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)643 static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
644 			SMU71_Discrete_DpmTable *table)
645 {
646 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
647 	uint32_t count;
648 	int result;
649 
650 	table->VddciLevelCount = data->vddci_voltage_table.count;
651 
652 	for (count = 0; count < table->VddciLevelCount; count++) {
653 		result = iceland_populate_smc_voltage_table(hwmgr,
654 				&(data->vddci_voltage_table.entries[count]),
655 				&(table->VddciLevel[count]));
656 		PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
657 		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
658 			table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
659 		else
660 			table->VddciLevel[count].Smio |= 0;
661 	}
662 
663 	CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
664 
665 	return 0;
666 }
667 
iceland_populate_smc_mvdd_table(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)668 static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
669 			SMU71_Discrete_DpmTable *table)
670 {
671 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
672 	uint32_t count;
673 	int result;
674 
675 	table->MvddLevelCount = data->mvdd_voltage_table.count;
676 
677 	for (count = 0; count < table->VddciLevelCount; count++) {
678 		result = iceland_populate_smc_voltage_table(hwmgr,
679 				&(data->mvdd_voltage_table.entries[count]),
680 				&table->MvddLevel[count]);
681 		PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
682 		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
683 			table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
684 		else
685 			table->MvddLevel[count].Smio |= 0;
686 	}
687 
688 	CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
689 
690 	return 0;
691 }
692 
693 
iceland_populate_smc_voltage_tables(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)694 static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
695 	SMU71_Discrete_DpmTable *table)
696 {
697 	int result;
698 
699 	result = iceland_populate_smc_vddc_table(hwmgr, table);
700 	PP_ASSERT_WITH_CODE(0 == result,
701 			"can not populate VDDC voltage table to SMC", return -EINVAL);
702 
703 	result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
704 	PP_ASSERT_WITH_CODE(0 == result,
705 			"can not populate VDDCI voltage table to SMC", return -EINVAL);
706 
707 	result = iceland_populate_smc_mvdd_table(hwmgr, table);
708 	PP_ASSERT_WITH_CODE(0 == result,
709 			"can not populate MVDD voltage table to SMC", return -EINVAL);
710 
711 	return 0;
712 }
713 
iceland_populate_ulv_level(struct pp_hwmgr * hwmgr,struct SMU71_Discrete_Ulv * state)714 static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
715 		struct SMU71_Discrete_Ulv *state)
716 {
717 	uint32_t voltage_response_time, ulv_voltage;
718 	int result;
719 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
720 
721 	state->CcPwrDynRm = 0;
722 	state->CcPwrDynRm1 = 0;
723 
724 	result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
725 	PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
726 
727 	if (ulv_voltage == 0) {
728 		data->ulv_supported = false;
729 		return 0;
730 	}
731 
732 	if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
733 		/* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
734 		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
735 			state->VddcOffset = 0;
736 		else
737 			/* used in SMIO Mode. not implemented for now. this is backup only for CI. */
738 			state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
739 	} else {
740 		/* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
741 		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
742 			state->VddcOffsetVid = 0;
743 		else  /* used in SVI2 Mode */
744 			state->VddcOffsetVid = (uint8_t)(
745 					(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
746 						* VOLTAGE_VID_OFFSET_SCALE2
747 						/ VOLTAGE_VID_OFFSET_SCALE1);
748 	}
749 	state->VddcPhase = 1;
750 
751 	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
752 	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
753 	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
754 
755 	return 0;
756 }
757 
iceland_populate_ulv_state(struct pp_hwmgr * hwmgr,SMU71_Discrete_Ulv * ulv_level)758 static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
759 		 SMU71_Discrete_Ulv *ulv_level)
760 {
761 	return iceland_populate_ulv_level(hwmgr, ulv_level);
762 }
763 
iceland_populate_smc_link_level(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)764 static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
765 {
766 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
767 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
768 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
769 	uint32_t i;
770 
771 	/* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
772 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
773 		table->LinkLevel[i].PcieGenSpeed  =
774 			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
775 		table->LinkLevel[i].PcieLaneCount =
776 			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
777 		table->LinkLevel[i].EnabledForActivity =
778 			1;
779 		table->LinkLevel[i].SPC =
780 			(uint8_t)(data->pcie_spc_cap & 0xff);
781 		table->LinkLevel[i].DownThreshold =
782 			PP_HOST_TO_SMC_UL(5);
783 		table->LinkLevel[i].UpThreshold =
784 			PP_HOST_TO_SMC_UL(30);
785 	}
786 
787 	smu_data->smc_state_table.LinkLevelCount =
788 		(uint8_t)dpm_table->pcie_speed_table.count;
789 	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
790 		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
791 
792 	return 0;
793 }
794 
iceland_calculate_sclk_params(struct pp_hwmgr * hwmgr,uint32_t engine_clock,SMU71_Discrete_GraphicsLevel * sclk)795 static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
796 		uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
797 {
798 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
799 	pp_atomctrl_clock_dividers_vi dividers;
800 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
801 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
802 	uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
803 	uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
804 	uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
805 	uint32_t    reference_clock;
806 	uint32_t reference_divider;
807 	uint32_t fbdiv;
808 	int result;
809 
810 	/* get the engine clock dividers for this clock value*/
811 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
812 
813 	PP_ASSERT_WITH_CODE(result == 0,
814 		"Error retrieving Engine Clock dividers from VBIOS.", return result);
815 
816 	/* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
817 	reference_clock = atomctrl_get_reference_clock(hwmgr);
818 
819 	reference_divider = 1 + dividers.uc_pll_ref_div;
820 
821 	/* low 14 bits is fraction and high 12 bits is divider*/
822 	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
823 
824 	/* SPLL_FUNC_CNTL setup*/
825 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
826 		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
827 	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
828 		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
829 
830 	/* SPLL_FUNC_CNTL_3 setup*/
831 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
832 		CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
833 
834 	/* set to use fractional accumulation*/
835 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
836 		CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
837 
838 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
839 			PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
840 		pp_atomctrl_internal_ss_info ss_info;
841 
842 		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
843 		if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
844 			/*
845 			* ss_info.speed_spectrum_percentage -- in unit of 0.01%
846 			* ss_info.speed_spectrum_rate -- in unit of khz
847 			*/
848 			/* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
849 			uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
850 
851 			/* clkv = 2 * D * fbdiv / NS */
852 			uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
853 
854 			cg_spll_spread_spectrum =
855 				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
856 			cg_spll_spread_spectrum =
857 				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
858 			cg_spll_spread_spectrum_2 =
859 				PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
860 		}
861 	}
862 
863 	sclk->SclkFrequency        = engine_clock;
864 	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
865 	sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
866 	sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
867 	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
868 	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
869 
870 	return 0;
871 }
872 
iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr * hwmgr,const struct phm_phase_shedding_limits_table * pl,uint32_t sclk,uint32_t * p_shed)873 static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
874 				const struct phm_phase_shedding_limits_table *pl,
875 					uint32_t sclk, uint32_t *p_shed)
876 {
877 	unsigned int i;
878 
879 	/* use the minimum phase shedding */
880 	*p_shed = 1;
881 
882 	for (i = 0; i < pl->count; i++) {
883 		if (sclk < pl->entries[i].Sclk) {
884 			*p_shed = i;
885 			break;
886 		}
887 	}
888 	return 0;
889 }
890 
iceland_populate_single_graphic_level(struct pp_hwmgr * hwmgr,uint32_t engine_clock,SMU71_Discrete_GraphicsLevel * graphic_level)891 static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
892 						uint32_t engine_clock,
893 				SMU71_Discrete_GraphicsLevel *graphic_level)
894 {
895 	int result;
896 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
897 
898 	result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
899 
900 	/* populate graphics levels*/
901 	result = iceland_get_dependency_volt_by_clk(hwmgr,
902 		hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
903 		&graphic_level->MinVddc);
904 	PP_ASSERT_WITH_CODE((0 == result),
905 		"can not find VDDC voltage value for VDDC engine clock dependency table", return result);
906 
907 	/* SCLK frequency in units of 10KHz*/
908 	graphic_level->SclkFrequency = engine_clock;
909 	graphic_level->MinVddcPhases = 1;
910 
911 	if (data->vddc_phase_shed_control)
912 		iceland_populate_phase_value_based_on_sclk(hwmgr,
913 				hwmgr->dyn_state.vddc_phase_shed_limits_table,
914 				engine_clock,
915 				&graphic_level->MinVddcPhases);
916 
917 	/* Indicates maximum activity level for this performance level. 50% for now*/
918 	graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity;
919 
920 	graphic_level->CcPwrDynRm = 0;
921 	graphic_level->CcPwrDynRm1 = 0;
922 	/* this level can be used if activity is high enough.*/
923 	graphic_level->EnabledForActivity = 0;
924 	/* this level can be used for throttling.*/
925 	graphic_level->EnabledForThrottle = 1;
926 	graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst;
927 	graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst;
928 	graphic_level->VoltageDownHyst = 0;
929 	graphic_level->PowerThrottle = 0;
930 
931 	data->display_timing.min_clock_in_sr =
932 			hwmgr->display_config->min_core_set_clock_in_sr;
933 
934 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
935 			PHM_PlatformCaps_SclkDeepSleep))
936 		graphic_level->DeepSleepDivId =
937 				smu7_get_sleep_divider_id_from_clock(engine_clock,
938 						data->display_timing.min_clock_in_sr);
939 
940 	/* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
941 	graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
942 
943 	if (0 == result) {
944 		graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
945 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
946 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
947 		CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
948 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
949 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
950 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
951 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
952 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
953 		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
954 	}
955 
956 	return result;
957 }
958 
iceland_populate_all_graphic_levels(struct pp_hwmgr * hwmgr)959 static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
960 {
961 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
962 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
963 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
964 	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
965 				offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
966 
967 	uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *
968 						SMU71_MAX_LEVELS_GRAPHICS;
969 
970 	SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
971 
972 	uint32_t i;
973 	uint8_t highest_pcie_level_enabled = 0;
974 	uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
975 	uint8_t count = 0;
976 	int result = 0;
977 
978 	memset(levels, 0x00, level_array_size);
979 
980 	for (i = 0; i < dpm_table->sclk_table.count; i++) {
981 		result = iceland_populate_single_graphic_level(hwmgr,
982 					dpm_table->sclk_table.dpm_levels[i].value,
983 					&(smu_data->smc_state_table.GraphicsLevel[i]));
984 		if (result != 0)
985 			return result;
986 
987 		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
988 		if (i > 1)
989 			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
990 	}
991 
992 	/* Only enable level 0 for now. */
993 	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
994 
995 	/* set highest level watermark to high */
996 	if (dpm_table->sclk_table.count > 1)
997 		smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
998 			PPSMC_DISPLAY_WATERMARK_HIGH;
999 
1000 	smu_data->smc_state_table.GraphicsDpmLevelCount =
1001 		(uint8_t)dpm_table->sclk_table.count;
1002 	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1003 		phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1004 
1005 	while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1006 				(1 << (highest_pcie_level_enabled + 1))) != 0) {
1007 		highest_pcie_level_enabled++;
1008 	}
1009 
1010 	while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1011 		(1 << lowest_pcie_level_enabled)) == 0) {
1012 		lowest_pcie_level_enabled++;
1013 	}
1014 
1015 	while ((count < highest_pcie_level_enabled) &&
1016 			((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1017 				(1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
1018 		count++;
1019 	}
1020 
1021 	mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
1022 		(lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
1023 
1024 
1025 	/* set pcieDpmLevel to highest_pcie_level_enabled*/
1026 	for (i = 2; i < dpm_table->sclk_table.count; i++) {
1027 		smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1028 	}
1029 
1030 	/* set pcieDpmLevel to lowest_pcie_level_enabled*/
1031 	smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1032 
1033 	/* set pcieDpmLevel to mid_pcie_level_enabled*/
1034 	smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
1035 
1036 	/* level count will send to smc once at init smc table and never change*/
1037 	result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
1038 				(uint8_t *)levels, (uint32_t)level_array_size,
1039 								SMC_RAM_END);
1040 
1041 	return result;
1042 }
1043 
iceland_calculate_mclk_params(struct pp_hwmgr * hwmgr,uint32_t memory_clock,SMU71_Discrete_MemoryLevel * mclk,bool strobe_mode,bool dllStateOn)1044 static int iceland_calculate_mclk_params(
1045 		struct pp_hwmgr *hwmgr,
1046 		uint32_t memory_clock,
1047 		SMU71_Discrete_MemoryLevel *mclk,
1048 		bool strobe_mode,
1049 		bool dllStateOn
1050 		)
1051 {
1052 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1053 
1054 	uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
1055 	uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1056 	uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1057 	uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1058 	uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1059 	uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1060 	uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1061 	uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
1062 	uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
1063 
1064 	pp_atomctrl_memory_clock_param mpll_param;
1065 	int result;
1066 
1067 	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1068 				memory_clock, &mpll_param, strobe_mode);
1069 	PP_ASSERT_WITH_CODE(0 == result,
1070 		"Error retrieving Memory Clock Parameters from VBIOS.", return result);
1071 
1072 	/* MPLL_FUNC_CNTL setup*/
1073 	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1074 
1075 	/* MPLL_FUNC_CNTL_1 setup*/
1076 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1077 							MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1078 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1079 							MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1080 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1081 							MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1082 
1083 	/* MPLL_AD_FUNC_CNTL setup*/
1084 	mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1085 							MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1086 
1087 	if (data->is_memory_gddr5) {
1088 		/* MPLL_DQ_FUNC_CNTL setup*/
1089 		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1090 								MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1091 		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1092 								MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1093 	}
1094 
1095 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1096 			PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1097 		/*
1098 		 ************************************
1099 		 Fref = Reference Frequency
1100 		 NF = Feedback divider ratio
1101 		 NR = Reference divider ratio
1102 		 Fnom = Nominal VCO output frequency = Fref * NF / NR
1103 		 Fs = Spreading Rate
1104 		 D = Percentage down-spread / 2
1105 		 Fint = Reference input frequency to PFD = Fref / NR
1106 		 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1107 		 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1108 		 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1109 		 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1110 		 *************************************
1111 		 */
1112 		pp_atomctrl_internal_ss_info ss_info;
1113 		uint32_t freq_nom;
1114 		uint32_t tmp;
1115 		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1116 
1117 		/* for GDDR5 for all modes and DDR3 */
1118 		if (1 == mpll_param.qdr)
1119 			freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1120 		else
1121 			freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1122 
1123 		/* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
1124 		tmp = (freq_nom / reference_clock);
1125 		tmp = tmp * tmp;
1126 
1127 		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1128 			/* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1129 			/* ss.Info.speed_spectrum_rate -- in unit of khz */
1130 			/* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1131 			/*     = reference_clock * 5 / speed_spectrum_rate */
1132 			uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1133 
1134 			/* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1135 			/*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1136 			uint32_t clkv =
1137 				(uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1138 							ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1139 
1140 			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1141 			mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1142 		}
1143 	}
1144 
1145 	/* MCLK_PWRMGT_CNTL setup */
1146 	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1147 		MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1148 	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1149 		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1150 	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1151 		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1152 
1153 
1154 	/* Save the result data to outpupt memory level structure */
1155 	mclk->MclkFrequency   = memory_clock;
1156 	mclk->MpllFuncCntl    = mpll_func_cntl;
1157 	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
1158 	mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
1159 	mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
1160 	mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
1161 	mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
1162 	mclk->DllCntl         = dll_cntl;
1163 	mclk->MpllSs1         = mpll_ss1;
1164 	mclk->MpllSs2         = mpll_ss2;
1165 
1166 	return 0;
1167 }
1168 
iceland_get_mclk_frequency_ratio(uint32_t memory_clock,bool strobe_mode)1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
1170 		bool strobe_mode)
1171 {
1172 	uint8_t mc_para_index;
1173 
1174 	if (strobe_mode) {
1175 		if (memory_clock < 12500) {
1176 			mc_para_index = 0x00;
1177 		} else if (memory_clock > 47500) {
1178 			mc_para_index = 0x0f;
1179 		} else {
1180 			mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1181 		}
1182 	} else {
1183 		if (memory_clock < 65000) {
1184 			mc_para_index = 0x00;
1185 		} else if (memory_clock > 135000) {
1186 			mc_para_index = 0x0f;
1187 		} else {
1188 			mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1189 		}
1190 	}
1191 
1192 	return mc_para_index;
1193 }
1194 
iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)1195 static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1196 {
1197 	uint8_t mc_para_index;
1198 
1199 	if (memory_clock < 10000) {
1200 		mc_para_index = 0;
1201 	} else if (memory_clock >= 80000) {
1202 		mc_para_index = 0x0f;
1203 	} else {
1204 		mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1205 	}
1206 
1207 	return mc_para_index;
1208 }
1209 
iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr * hwmgr,const struct phm_phase_shedding_limits_table * pl,uint32_t memory_clock,uint32_t * p_shed)1210 static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
1211 					uint32_t memory_clock, uint32_t *p_shed)
1212 {
1213 	unsigned int i;
1214 
1215 	*p_shed = 1;
1216 
1217 	for (i = 0; i < pl->count; i++) {
1218 		if (memory_clock < pl->entries[i].Mclk) {
1219 			*p_shed = i;
1220 			break;
1221 		}
1222 	}
1223 
1224 	return 0;
1225 }
1226 
iceland_populate_single_memory_level(struct pp_hwmgr * hwmgr,uint32_t memory_clock,SMU71_Discrete_MemoryLevel * memory_level)1227 static int iceland_populate_single_memory_level(
1228 		struct pp_hwmgr *hwmgr,
1229 		uint32_t memory_clock,
1230 		SMU71_Discrete_MemoryLevel *memory_level
1231 		)
1232 {
1233 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1234 	int result = 0;
1235 	bool dll_state_on;
1236 	uint32_t mclk_edc_wr_enable_threshold = 40000;
1237 	uint32_t mclk_edc_enable_threshold = 40000;
1238 	uint32_t mclk_strobe_mode_threshold = 40000;
1239 
1240 	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
1241 		result = iceland_get_dependency_volt_by_clk(hwmgr,
1242 			hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
1243 		PP_ASSERT_WITH_CODE((0 == result),
1244 			"can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1245 	}
1246 
1247 	if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
1248 		memory_level->MinVddci = memory_level->MinVddc;
1249 	} else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
1250 		result = iceland_get_dependency_volt_by_clk(hwmgr,
1251 				hwmgr->dyn_state.vddci_dependency_on_mclk,
1252 				memory_clock,
1253 				&memory_level->MinVddci);
1254 		PP_ASSERT_WITH_CODE((0 == result),
1255 			"can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
1256 	}
1257 
1258 	memory_level->MinVddcPhases = 1;
1259 
1260 	if (data->vddc_phase_shed_control) {
1261 		iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
1262 				memory_clock, &memory_level->MinVddcPhases);
1263 	}
1264 
1265 	memory_level->EnabledForThrottle = 1;
1266 	memory_level->EnabledForActivity = 0;
1267 	memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1268 	memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1269 	memory_level->VoltageDownHyst = 0;
1270 
1271 	/* Indicates maximum activity level for this performance level.*/
1272 	memory_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1273 	memory_level->StutterEnable = 0;
1274 	memory_level->StrobeEnable = 0;
1275 	memory_level->EdcReadEnable = 0;
1276 	memory_level->EdcWriteEnable = 0;
1277 	memory_level->RttEnable = 0;
1278 
1279 	/* default set to low watermark. Highest level will be set to high later.*/
1280 	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1281 
1282 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1283 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1284 
1285 	/* stutter mode not support on iceland */
1286 
1287 	/* decide strobe mode*/
1288 	memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
1289 		(memory_clock <= mclk_strobe_mode_threshold);
1290 
1291 	/* decide EDC mode and memory clock ratio*/
1292 	if (data->is_memory_gddr5) {
1293 		memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
1294 					memory_level->StrobeEnable);
1295 
1296 		if ((mclk_edc_enable_threshold != 0) &&
1297 				(memory_clock > mclk_edc_enable_threshold)) {
1298 			memory_level->EdcReadEnable = 1;
1299 		}
1300 
1301 		if ((mclk_edc_wr_enable_threshold != 0) &&
1302 				(memory_clock > mclk_edc_wr_enable_threshold)) {
1303 			memory_level->EdcWriteEnable = 1;
1304 		}
1305 
1306 		if (memory_level->StrobeEnable) {
1307 			if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
1308 					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
1309 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1310 			else
1311 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1312 		} else
1313 			dll_state_on = data->dll_default_on;
1314 	} else {
1315 		memory_level->StrobeRatio =
1316 			iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
1317 		dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1318 	}
1319 
1320 	result = iceland_calculate_mclk_params(hwmgr,
1321 		memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
1322 
1323 	if (0 == result) {
1324 		memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1325 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
1326 		memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1327 		memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1328 		/* MCLK frequency in units of 10KHz*/
1329 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
1330 		/* Indicates maximum activity level for this performance level.*/
1331 		CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
1332 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
1333 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
1334 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
1335 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
1336 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
1337 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
1338 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
1339 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
1340 		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
1341 	}
1342 
1343 	return result;
1344 }
1345 
iceland_populate_all_memory_levels(struct pp_hwmgr * hwmgr)1346 static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1347 {
1348 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1349 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1350 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
1351 	int result;
1352 
1353 	/* populate MCLK dpm table to SMU7 */
1354 	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
1355 	uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
1356 	SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1357 	uint32_t i;
1358 
1359 	memset(levels, 0x00, level_array_size);
1360 
1361 	for (i = 0; i < dpm_table->mclk_table.count; i++) {
1362 		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1363 			"can not populate memory level as memory clock is zero", return -EINVAL);
1364 		result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
1365 			&(smu_data->smc_state_table.MemoryLevel[i]));
1366 		if (0 != result) {
1367 			return result;
1368 		}
1369 	}
1370 
1371 	/* Only enable level 0 for now.*/
1372 	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1373 
1374 	/*
1375 	* in order to prevent MC activity from stutter mode to push DPM up.
1376 	* the UVD change complements this by putting the MCLK in a higher state
1377 	* by default such that we are not effected by up threshold or and MCLK DPM latency.
1378 	*/
1379 	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1380 	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1381 
1382 	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1383 	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1384 	/* set highest level watermark to high*/
1385 	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1386 
1387 	/* level count will send to smc once at init smc table and never change*/
1388 	result = smu7_copy_bytes_to_smc(hwmgr,
1389 		level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
1390 		SMC_RAM_END);
1391 
1392 	return result;
1393 }
1394 
iceland_populate_mvdd_value(struct pp_hwmgr * hwmgr,uint32_t mclk,SMU71_Discrete_VoltageLevel * voltage)1395 static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
1396 					SMU71_Discrete_VoltageLevel *voltage)
1397 {
1398 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1399 
1400 	uint32_t i = 0;
1401 
1402 	if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1403 		/* find mvdd value which clock is more than request */
1404 		for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
1405 			if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
1406 				/* Always round to higher voltage. */
1407 				voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
1408 				break;
1409 			}
1410 		}
1411 
1412 		PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
1413 			"MVDD Voltage is outside the supported range.", return -EINVAL);
1414 
1415 	} else {
1416 		return -EINVAL;
1417 	}
1418 
1419 	return 0;
1420 }
1421 
iceland_populate_smc_acpi_level(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)1422 static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1423 	SMU71_Discrete_DpmTable *table)
1424 {
1425 	int result = 0;
1426 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1427 	struct pp_atomctrl_clock_dividers_vi dividers;
1428 	uint32_t vddc_phase_shed_control = 0;
1429 
1430 	SMU71_Discrete_VoltageLevel voltage_level;
1431 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1432 	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1433 	uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
1434 	uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
1435 
1436 
1437 	/* The ACPI state should not do DPM on DC (or ever).*/
1438 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1439 
1440 	if (data->acpi_vddc)
1441 		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1442 	else
1443 		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1444 
1445 	table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
1446 	/* assign zero for now*/
1447 	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1448 
1449 	/* get the engine clock dividers for this clock value*/
1450 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1451 		table->ACPILevel.SclkFrequency,  &dividers);
1452 
1453 	PP_ASSERT_WITH_CODE(result == 0,
1454 		"Error retrieving Engine Clock dividers from VBIOS.", return result);
1455 
1456 	/* divider ID for required SCLK*/
1457 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1458 	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1459 	table->ACPILevel.DeepSleepDivId = 0;
1460 
1461 	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
1462 							CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
1463 	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
1464 							CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
1465 	spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
1466 							CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
1467 
1468 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1469 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1470 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1471 	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1472 	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1473 	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1474 	table->ACPILevel.CcPwrDynRm = 0;
1475 	table->ACPILevel.CcPwrDynRm1 = 0;
1476 
1477 
1478 	/* For various features to be enabled/disabled while this level is active.*/
1479 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1480 	/* SCLK frequency in units of 10KHz*/
1481 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1482 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1483 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1484 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1485 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1486 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1487 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1488 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1489 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1490 
1491 	/* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1492 	table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
1493 	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
1494 
1495 	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1496 		table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
1497 	else {
1498 		if (data->acpi_vddci != 0)
1499 			table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
1500 		else
1501 			table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
1502 	}
1503 
1504 	if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
1505 		table->MemoryACPILevel.MinMvdd =
1506 			PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1507 	else
1508 		table->MemoryACPILevel.MinMvdd = 0;
1509 
1510 	/* Force reset on DLL*/
1511 	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1512 		MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1513 	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1514 		MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1515 
1516 	/* Disable DLL in ACPIState*/
1517 	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1518 		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1519 	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1520 		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
1521 
1522 	/* Enable DLL bypass signal*/
1523 	dll_cntl            = PHM_SET_FIELD(dll_cntl,
1524 		DLL_CNTL, MRDCK0_BYPASS, 0);
1525 	dll_cntl            = PHM_SET_FIELD(dll_cntl,
1526 		DLL_CNTL, MRDCK1_BYPASS, 0);
1527 
1528 	table->MemoryACPILevel.DllCntl            =
1529 		PP_HOST_TO_SMC_UL(dll_cntl);
1530 	table->MemoryACPILevel.MclkPwrmgtCntl     =
1531 		PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1532 	table->MemoryACPILevel.MpllAdFuncCntl     =
1533 		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1534 	table->MemoryACPILevel.MpllDqFuncCntl     =
1535 		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1536 	table->MemoryACPILevel.MpllFuncCntl       =
1537 		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1538 	table->MemoryACPILevel.MpllFuncCntl_1     =
1539 		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1540 	table->MemoryACPILevel.MpllFuncCntl_2     =
1541 		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
1542 	table->MemoryACPILevel.MpllSs1            =
1543 		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
1544 	table->MemoryACPILevel.MpllSs2            =
1545 		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
1546 
1547 	table->MemoryACPILevel.EnabledForThrottle = 0;
1548 	table->MemoryACPILevel.EnabledForActivity = 0;
1549 	table->MemoryACPILevel.UpHyst = 0;
1550 	table->MemoryACPILevel.DownHyst = 100;
1551 	table->MemoryACPILevel.VoltageDownHyst = 0;
1552 	/* Indicates maximum activity level for this performance level.*/
1553 	table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1554 
1555 	table->MemoryACPILevel.StutterEnable = 0;
1556 	table->MemoryACPILevel.StrobeEnable = 0;
1557 	table->MemoryACPILevel.EdcReadEnable = 0;
1558 	table->MemoryACPILevel.EdcWriteEnable = 0;
1559 	table->MemoryACPILevel.RttEnable = 0;
1560 
1561 	return result;
1562 }
1563 
iceland_populate_smc_uvd_level(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)1564 static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1565 					SMU71_Discrete_DpmTable *table)
1566 {
1567 	return 0;
1568 }
1569 
iceland_populate_smc_vce_level(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)1570 static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1571 		SMU71_Discrete_DpmTable *table)
1572 {
1573 	return 0;
1574 }
1575 
iceland_populate_smc_acp_level(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)1576 static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1577 		SMU71_Discrete_DpmTable *table)
1578 {
1579 	return 0;
1580 }
1581 
iceland_populate_memory_timing_parameters(struct pp_hwmgr * hwmgr,uint32_t engine_clock,uint32_t memory_clock,struct SMU71_Discrete_MCArbDramTimingTableEntry * arb_regs)1582 static int iceland_populate_memory_timing_parameters(
1583 		struct pp_hwmgr *hwmgr,
1584 		uint32_t engine_clock,
1585 		uint32_t memory_clock,
1586 		struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
1587 		)
1588 {
1589 	uint32_t dramTiming;
1590 	uint32_t dramTiming2;
1591 	uint32_t burstTime;
1592 	int result;
1593 
1594 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1595 				engine_clock, memory_clock);
1596 
1597 	PP_ASSERT_WITH_CODE(result == 0,
1598 		"Error calling VBIOS to set DRAM_TIMING.", return result);
1599 
1600 	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1601 	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1602 	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1603 
1604 	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
1605 	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1606 	arb_regs->McArbBurstTime = (uint8_t)burstTime;
1607 
1608 	return 0;
1609 }
1610 
iceland_program_memory_timing_parameters(struct pp_hwmgr * hwmgr)1611 static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1612 {
1613 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1614 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1615 	int result = 0;
1616 	SMU71_Discrete_MCArbDramTimingTable  arb_regs;
1617 	uint32_t i, j;
1618 
1619 	memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
1620 
1621 	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1622 		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1623 			result = iceland_populate_memory_timing_parameters
1624 				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1625 				 data->dpm_table.mclk_table.dpm_levels[j].value,
1626 				 &arb_regs.entries[i][j]);
1627 
1628 			if (0 != result) {
1629 				break;
1630 			}
1631 		}
1632 	}
1633 
1634 	if (0 == result) {
1635 		result = smu7_copy_bytes_to_smc(
1636 				hwmgr,
1637 				smu_data->smu7_data.arb_table_start,
1638 				(uint8_t *)&arb_regs,
1639 				sizeof(SMU71_Discrete_MCArbDramTimingTable),
1640 				SMC_RAM_END
1641 				);
1642 	}
1643 
1644 	return result;
1645 }
1646 
iceland_populate_smc_boot_level(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * table)1647 static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1648 			SMU71_Discrete_DpmTable *table)
1649 {
1650 	int result = 0;
1651 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1652 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1653 	table->GraphicsBootLevel = 0;
1654 	table->MemoryBootLevel = 0;
1655 
1656 	/* find boot level from dpm table*/
1657 	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1658 			data->vbios_boot_state.sclk_bootup_value,
1659 			(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1660 
1661 	if (0 != result) {
1662 		smu_data->smc_state_table.GraphicsBootLevel = 0;
1663 		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
1664 		result = 0;
1665 	}
1666 
1667 	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1668 		data->vbios_boot_state.mclk_bootup_value,
1669 		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1670 
1671 	if (0 != result) {
1672 		smu_data->smc_state_table.MemoryBootLevel = 0;
1673 		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
1674 		result = 0;
1675 	}
1676 
1677 	table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
1678 	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1679 		table->BootVddci = table->BootVddc;
1680 	else
1681 		table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
1682 
1683 	table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1684 
1685 	return result;
1686 }
1687 
iceland_populate_mc_reg_address(struct pp_hwmgr * hwmgr,SMU71_Discrete_MCRegisters * mc_reg_table)1688 static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1689 				 SMU71_Discrete_MCRegisters *mc_reg_table)
1690 {
1691 	const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
1692 
1693 	uint32_t i, j;
1694 
1695 	for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
1696 		if (smu_data->mc_reg_table.validflag & 1<<j) {
1697 			PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
1698 				"Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
1699 			mc_reg_table->address[i].s0 =
1700 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1701 			mc_reg_table->address[i].s1 =
1702 				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
1703 			i++;
1704 		}
1705 	}
1706 
1707 	mc_reg_table->last = (uint8_t)i;
1708 
1709 	return 0;
1710 }
1711 
1712 /*convert register values from driver to SMC format */
iceland_convert_mc_registers(const struct iceland_mc_reg_entry * entry,SMU71_Discrete_MCRegisterSet * data,uint32_t num_entries,uint32_t valid_flag)1713 static void iceland_convert_mc_registers(
1714 	const struct iceland_mc_reg_entry *entry,
1715 	SMU71_Discrete_MCRegisterSet *data,
1716 	uint32_t num_entries, uint32_t valid_flag)
1717 {
1718 	uint32_t i, j;
1719 
1720 	for (i = 0, j = 0; j < num_entries; j++) {
1721 		if (valid_flag & 1<<j) {
1722 			data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
1723 			i++;
1724 		}
1725 	}
1726 }
1727 
iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr * hwmgr,const uint32_t memory_clock,SMU71_Discrete_MCRegisterSet * mc_reg_table_data)1728 static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
1729 		const uint32_t memory_clock,
1730 		SMU71_Discrete_MCRegisterSet *mc_reg_table_data
1731 		)
1732 {
1733 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1734 	uint32_t i = 0;
1735 
1736 	for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
1737 		if (memory_clock <=
1738 			smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
1739 			break;
1740 		}
1741 	}
1742 
1743 	if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
1744 		--i;
1745 
1746 	iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
1747 				mc_reg_table_data, smu_data->mc_reg_table.last,
1748 				smu_data->mc_reg_table.validflag);
1749 
1750 	return 0;
1751 }
1752 
iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr * hwmgr,SMU71_Discrete_MCRegisters * mc_regs)1753 static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1754 		SMU71_Discrete_MCRegisters *mc_regs)
1755 {
1756 	int result = 0;
1757 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1758 	int res;
1759 	uint32_t i;
1760 
1761 	for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1762 		res = iceland_convert_mc_reg_table_entry_to_smc(
1763 				hwmgr,
1764 				data->dpm_table.mclk_table.dpm_levels[i].value,
1765 				&mc_regs->data[i]
1766 				);
1767 
1768 		if (0 != res)
1769 			result = res;
1770 	}
1771 
1772 	return result;
1773 }
1774 
iceland_update_and_upload_mc_reg_table(struct pp_hwmgr * hwmgr)1775 static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1776 {
1777 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1778 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1779 	uint32_t address;
1780 	int32_t result;
1781 
1782 	if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
1783 		return 0;
1784 
1785 
1786 	memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
1787 
1788 	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
1789 
1790 	if (result != 0)
1791 		return result;
1792 
1793 
1794 	address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
1795 
1796 	return  smu7_copy_bytes_to_smc(hwmgr, address,
1797 				 (uint8_t *)&smu_data->mc_regs.data[0],
1798 				sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
1799 				SMC_RAM_END);
1800 }
1801 
iceland_populate_initial_mc_reg_table(struct pp_hwmgr * hwmgr)1802 static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1803 {
1804 	int result;
1805 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1806 
1807 	memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
1808 	result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
1809 	PP_ASSERT_WITH_CODE(0 == result,
1810 		"Failed to initialize MCRegTable for the MC register addresses!", return result;);
1811 
1812 	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
1813 	PP_ASSERT_WITH_CODE(0 == result,
1814 		"Failed to initialize MCRegTable for driver state!", return result;);
1815 
1816 	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
1817 			(uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
1818 }
1819 
iceland_populate_smc_initial_state(struct pp_hwmgr * hwmgr)1820 static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1821 {
1822 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1823 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1824 	uint8_t count, level;
1825 
1826 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
1827 
1828 	for (level = 0; level < count; level++) {
1829 		if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
1830 			 >= data->vbios_boot_state.sclk_bootup_value) {
1831 			smu_data->smc_state_table.GraphicsBootLevel = level;
1832 			break;
1833 		}
1834 	}
1835 
1836 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
1837 
1838 	for (level = 0; level < count; level++) {
1839 		if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
1840 			>= data->vbios_boot_state.mclk_bootup_value) {
1841 			smu_data->smc_state_table.MemoryBootLevel = level;
1842 			break;
1843 		}
1844 	}
1845 
1846 	return 0;
1847 }
1848 
iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr * hwmgr)1849 static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1850 {
1851 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1852 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1853 	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
1854 	SMU71_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
1855 	struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
1856 	struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
1857 	const uint16_t *def1, *def2;
1858 	int i, j, k;
1859 
1860 
1861 	/*
1862 	 * TDP number of fraction bits are changed from 8 to 7 for Iceland
1863 	 * as requested by SMC team
1864 	 */
1865 
1866 	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
1867 	dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
1868 
1869 
1870 	dpm_table->DTETjOffset = 0;
1871 
1872 	dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
1873 	dpm_table->GpuTjHyst = 8;
1874 
1875 	dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
1876 
1877 	/* The following are for new Iceland Multi-input fan/thermal control */
1878 	if (NULL != ppm) {
1879 		dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
1880 		dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
1881 	} else {
1882 		dpm_table->PPM_PkgPwrLimit = 0;
1883 		dpm_table->PPM_TemperatureLimit = 0;
1884 	}
1885 
1886 	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
1887 	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
1888 
1889 	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
1890 	def1 = defaults->bapmti_r;
1891 	def2 = defaults->bapmti_rc;
1892 
1893 	for (i = 0; i < SMU71_DTE_ITERATIONS; i++) {
1894 		for (j = 0; j < SMU71_DTE_SOURCES; j++) {
1895 			for (k = 0; k < SMU71_DTE_SINKS; k++) {
1896 				dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
1897 				dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
1898 				def1++;
1899 				def2++;
1900 			}
1901 		}
1902 	}
1903 
1904 	return 0;
1905 }
1906 
iceland_populate_smc_svi2_config(struct pp_hwmgr * hwmgr,SMU71_Discrete_DpmTable * tab)1907 static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
1908 					    SMU71_Discrete_DpmTable *tab)
1909 {
1910 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1911 
1912 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
1913 		tab->SVI2Enable |= VDDC_ON_SVI2;
1914 
1915 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1916 		tab->SVI2Enable |= VDDCI_ON_SVI2;
1917 	else
1918 		tab->MergedVddci = 1;
1919 
1920 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
1921 		tab->SVI2Enable |= MVDD_ON_SVI2;
1922 
1923 	PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
1924 		(tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
1925 
1926 	return 0;
1927 }
1928 
iceland_init_smc_table(struct pp_hwmgr * hwmgr)1929 static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1930 {
1931 	int result;
1932 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1933 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1934 	SMU71_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
1935 
1936 
1937 	iceland_initialize_power_tune_defaults(hwmgr);
1938 	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
1939 
1940 	if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) {
1941 		iceland_populate_smc_voltage_tables(hwmgr, table);
1942 	}
1943 
1944 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1945 			PHM_PlatformCaps_AutomaticDCTransition))
1946 		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1947 
1948 
1949 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1950 			PHM_PlatformCaps_StepVddc))
1951 		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1952 
1953 	if (data->is_memory_gddr5)
1954 		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1955 
1956 
1957 	if (data->ulv_supported) {
1958 		result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
1959 		PP_ASSERT_WITH_CODE(0 == result,
1960 			"Failed to initialize ULV state!", return result;);
1961 
1962 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1963 			ixCG_ULV_PARAMETER, 0x40035);
1964 	}
1965 
1966 	result = iceland_populate_smc_link_level(hwmgr, table);
1967 	PP_ASSERT_WITH_CODE(0 == result,
1968 		"Failed to initialize Link Level!", return result;);
1969 
1970 	result = iceland_populate_all_graphic_levels(hwmgr);
1971 	PP_ASSERT_WITH_CODE(0 == result,
1972 		"Failed to initialize Graphics Level!", return result;);
1973 
1974 	result = iceland_populate_all_memory_levels(hwmgr);
1975 	PP_ASSERT_WITH_CODE(0 == result,
1976 		"Failed to initialize Memory Level!", return result;);
1977 
1978 	result = iceland_populate_smc_acpi_level(hwmgr, table);
1979 	PP_ASSERT_WITH_CODE(0 == result,
1980 		"Failed to initialize ACPI Level!", return result;);
1981 
1982 	result = iceland_populate_smc_vce_level(hwmgr, table);
1983 	PP_ASSERT_WITH_CODE(0 == result,
1984 		"Failed to initialize VCE Level!", return result;);
1985 
1986 	result = iceland_populate_smc_acp_level(hwmgr, table);
1987 	PP_ASSERT_WITH_CODE(0 == result,
1988 		"Failed to initialize ACP Level!", return result;);
1989 
1990 	/* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
1991 	/* need to populate the  ARB settings for the initial state. */
1992 	result = iceland_program_memory_timing_parameters(hwmgr);
1993 	PP_ASSERT_WITH_CODE(0 == result,
1994 		"Failed to Write ARB settings for the initial state.", return result;);
1995 
1996 	result = iceland_populate_smc_uvd_level(hwmgr, table);
1997 	PP_ASSERT_WITH_CODE(0 == result,
1998 		"Failed to initialize UVD Level!", return result;);
1999 
2000 	table->GraphicsBootLevel = 0;
2001 	table->MemoryBootLevel = 0;
2002 
2003 	result = iceland_populate_smc_boot_level(hwmgr, table);
2004 	PP_ASSERT_WITH_CODE(0 == result,
2005 		"Failed to initialize Boot Level!", return result;);
2006 
2007 	result = iceland_populate_smc_initial_state(hwmgr);
2008 	PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
2009 
2010 	result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
2011 	PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
2012 
2013 	table->GraphicsVoltageChangeEnable  = 1;
2014 	table->GraphicsThermThrottleEnable  = 1;
2015 	table->GraphicsInterval = 1;
2016 	table->VoltageInterval  = 1;
2017 	table->ThermalInterval  = 1;
2018 
2019 	table->TemperatureLimitHigh =
2020 		(data->thermal_temp_setting.temperature_high *
2021 		 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2022 	table->TemperatureLimitLow =
2023 		(data->thermal_temp_setting.temperature_low *
2024 		SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2025 
2026 	table->MemoryVoltageChangeEnable  = 1;
2027 	table->MemoryInterval  = 1;
2028 	table->VoltageResponseTime  = 0;
2029 	table->PhaseResponseTime  = 0;
2030 	table->MemoryThermThrottleEnable  = 1;
2031 	table->PCIeBootLinkLevel = 0;
2032 	table->PCIeGenInterval = 1;
2033 
2034 	result = iceland_populate_smc_svi2_config(hwmgr, table);
2035 	PP_ASSERT_WITH_CODE(0 == result,
2036 		"Failed to populate SVI2 setting!", return result);
2037 
2038 	table->ThermGpio  = 17;
2039 	table->SclkStepSize = 0x4000;
2040 
2041 	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2042 	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
2043 	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
2044 	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
2045 	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
2046 	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2047 	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2048 	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2049 	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2050 	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2051 
2052 	table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
2053 	table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
2054 	table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2055 
2056 	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2057 	result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
2058 										offsetof(SMU71_Discrete_DpmTable, SystemFlags),
2059 										(uint8_t *)&(table->SystemFlags),
2060 										sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
2061 										SMC_RAM_END);
2062 
2063 	PP_ASSERT_WITH_CODE(0 == result,
2064 		"Failed to upload dpm data to SMC memory!", return result;);
2065 
2066 	/* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
2067 	result = smu7_copy_bytes_to_smc(hwmgr,
2068 			smu_data->smu7_data.ulv_setting_starts,
2069 			(uint8_t *)&(smu_data->ulv_setting),
2070 			sizeof(SMU71_Discrete_Ulv),
2071 			SMC_RAM_END);
2072 
2073 
2074 	result = iceland_populate_initial_mc_reg_table(hwmgr);
2075 	PP_ASSERT_WITH_CODE((0 == result),
2076 		"Failed to populate initialize MC Reg table!", return result);
2077 
2078 	result = iceland_populate_pm_fuses(hwmgr);
2079 	PP_ASSERT_WITH_CODE(0 == result,
2080 			"Failed to  populate PM fuses to SMC memory!", return result);
2081 
2082 	return 0;
2083 }
2084 
iceland_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)2085 static int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2086 {
2087 	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2088 	SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2089 	uint32_t duty100;
2090 	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2091 	uint16_t fdo_min, slope1, slope2;
2092 	uint32_t reference_clock;
2093 	int res;
2094 	uint64_t tmp64;
2095 
2096 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
2097 		return 0;
2098 
2099 	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2100 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2101 			PHM_PlatformCaps_MicrocodeFanControl);
2102 		return 0;
2103 	}
2104 
2105 	if (0 == smu7_data->fan_table_start) {
2106 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2107 		return 0;
2108 	}
2109 
2110 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
2111 
2112 	if (0 == duty100) {
2113 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2114 		return 0;
2115 	}
2116 
2117 	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2118 	do_div(tmp64, 10000);
2119 	fdo_min = (uint16_t)tmp64;
2120 
2121 	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2122 	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2123 
2124 	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2125 	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2126 
2127 	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2128 	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2129 
2130 	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2131 	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2132 	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2133 
2134 	fan_table.Slope1 = cpu_to_be16(slope1);
2135 	fan_table.Slope2 = cpu_to_be16(slope2);
2136 
2137 	fan_table.FdoMin = cpu_to_be16(fdo_min);
2138 
2139 	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2140 
2141 	fan_table.HystUp = cpu_to_be16(1);
2142 
2143 	fan_table.HystSlope = cpu_to_be16(1);
2144 
2145 	fan_table.TempRespLim = cpu_to_be16(5);
2146 
2147 	reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2148 
2149 	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2150 
2151 	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2152 
2153 	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2154 
2155 	/* fan_table.FanControl_GL_Flag = 1; */
2156 
2157 	res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2158 
2159 	return res;
2160 }
2161 
2162 
iceland_program_mem_timing_parameters(struct pp_hwmgr * hwmgr)2163 static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2164 {
2165 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2166 
2167 	if (data->need_update_smu7_dpm_table &
2168 		(DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK))
2169 		return iceland_program_memory_timing_parameters(hwmgr);
2170 
2171 	return 0;
2172 }
2173 
iceland_update_sclk_threshold(struct pp_hwmgr * hwmgr)2174 static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2175 {
2176 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2177 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2178 
2179 	int result = 0;
2180 	uint32_t low_sclk_interrupt_threshold = 0;
2181 
2182 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2183 			PHM_PlatformCaps_SclkThrottleLowNotification)
2184 		&& (data->low_sclk_interrupt_threshold != 0)) {
2185 		low_sclk_interrupt_threshold =
2186 				data->low_sclk_interrupt_threshold;
2187 
2188 		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2189 
2190 		result = smu7_copy_bytes_to_smc(
2191 				hwmgr,
2192 				smu_data->smu7_data.dpm_table_start +
2193 				offsetof(SMU71_Discrete_DpmTable,
2194 					LowSclkInterruptThreshold),
2195 				(uint8_t *)&low_sclk_interrupt_threshold,
2196 				sizeof(uint32_t),
2197 				SMC_RAM_END);
2198 	}
2199 
2200 	result = iceland_update_and_upload_mc_reg_table(hwmgr);
2201 
2202 	PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
2203 
2204 	result = iceland_program_mem_timing_parameters(hwmgr);
2205 	PP_ASSERT_WITH_CODE((result == 0),
2206 			"Failed to program memory timing parameters!",
2207 			);
2208 
2209 	return result;
2210 }
2211 
iceland_get_offsetof(uint32_t type,uint32_t member)2212 static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
2213 {
2214 	switch (type) {
2215 	case SMU_SoftRegisters:
2216 		switch (member) {
2217 		case HandshakeDisables:
2218 			return offsetof(SMU71_SoftRegisters, HandshakeDisables);
2219 		case VoltageChangeTimeout:
2220 			return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout);
2221 		case AverageGraphicsActivity:
2222 			return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
2223 		case AverageMemoryActivity:
2224 			return offsetof(SMU71_SoftRegisters, AverageMemoryActivity);
2225 		case PreVBlankGap:
2226 			return offsetof(SMU71_SoftRegisters, PreVBlankGap);
2227 		case VBlankTimeout:
2228 			return offsetof(SMU71_SoftRegisters, VBlankTimeout);
2229 		case UcodeLoadStatus:
2230 			return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
2231 		case DRAM_LOG_ADDR_H:
2232 			return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
2233 		case DRAM_LOG_ADDR_L:
2234 			return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
2235 		case DRAM_LOG_PHY_ADDR_H:
2236 			return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2237 		case DRAM_LOG_PHY_ADDR_L:
2238 			return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2239 		case DRAM_LOG_BUFF_SIZE:
2240 			return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2241 		}
2242 		break;
2243 	case SMU_Discrete_DpmTable:
2244 		switch (member) {
2245 		case LowSclkInterruptThreshold:
2246 			return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
2247 		}
2248 		break;
2249 	}
2250 	pr_warn("can't get the offset of type %x member %x\n", type, member);
2251 	return 0;
2252 }
2253 
iceland_get_mac_definition(uint32_t value)2254 static uint32_t iceland_get_mac_definition(uint32_t value)
2255 {
2256 	switch (value) {
2257 	case SMU_MAX_LEVELS_GRAPHICS:
2258 		return SMU71_MAX_LEVELS_GRAPHICS;
2259 	case SMU_MAX_LEVELS_MEMORY:
2260 		return SMU71_MAX_LEVELS_MEMORY;
2261 	case SMU_MAX_LEVELS_LINK:
2262 		return SMU71_MAX_LEVELS_LINK;
2263 	case SMU_MAX_ENTRIES_SMIO:
2264 		return SMU71_MAX_ENTRIES_SMIO;
2265 	case SMU_MAX_LEVELS_VDDC:
2266 		return SMU71_MAX_LEVELS_VDDC;
2267 	case SMU_MAX_LEVELS_VDDCI:
2268 		return SMU71_MAX_LEVELS_VDDCI;
2269 	case SMU_MAX_LEVELS_MVDD:
2270 		return SMU71_MAX_LEVELS_MVDD;
2271 	}
2272 
2273 	pr_warn("can't get the mac of %x\n", value);
2274 	return 0;
2275 }
2276 
iceland_process_firmware_header(struct pp_hwmgr * hwmgr)2277 static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2278 {
2279 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2280 	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2281 
2282 	uint32_t tmp;
2283 	int result;
2284 	bool error = false;
2285 
2286 	result = smu7_read_smc_sram_dword(hwmgr,
2287 				SMU71_FIRMWARE_HEADER_LOCATION +
2288 				offsetof(SMU71_Firmware_Header, DpmTable),
2289 				&tmp, SMC_RAM_END);
2290 
2291 	if (0 == result) {
2292 		smu7_data->dpm_table_start = tmp;
2293 	}
2294 
2295 	error |= (0 != result);
2296 
2297 	result = smu7_read_smc_sram_dword(hwmgr,
2298 				SMU71_FIRMWARE_HEADER_LOCATION +
2299 				offsetof(SMU71_Firmware_Header, SoftRegisters),
2300 				&tmp, SMC_RAM_END);
2301 
2302 	if (0 == result) {
2303 		data->soft_regs_start = tmp;
2304 		smu7_data->soft_regs_start = tmp;
2305 	}
2306 
2307 	error |= (0 != result);
2308 
2309 
2310 	result = smu7_read_smc_sram_dword(hwmgr,
2311 				SMU71_FIRMWARE_HEADER_LOCATION +
2312 				offsetof(SMU71_Firmware_Header, mcRegisterTable),
2313 				&tmp, SMC_RAM_END);
2314 
2315 	if (0 == result) {
2316 		smu7_data->mc_reg_table_start = tmp;
2317 	}
2318 
2319 	result = smu7_read_smc_sram_dword(hwmgr,
2320 				SMU71_FIRMWARE_HEADER_LOCATION +
2321 				offsetof(SMU71_Firmware_Header, FanTable),
2322 				&tmp, SMC_RAM_END);
2323 
2324 	if (0 == result) {
2325 		smu7_data->fan_table_start = tmp;
2326 	}
2327 
2328 	error |= (0 != result);
2329 
2330 	result = smu7_read_smc_sram_dword(hwmgr,
2331 				SMU71_FIRMWARE_HEADER_LOCATION +
2332 				offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
2333 				&tmp, SMC_RAM_END);
2334 
2335 	if (0 == result) {
2336 		smu7_data->arb_table_start = tmp;
2337 	}
2338 
2339 	error |= (0 != result);
2340 
2341 
2342 	result = smu7_read_smc_sram_dword(hwmgr,
2343 				SMU71_FIRMWARE_HEADER_LOCATION +
2344 				offsetof(SMU71_Firmware_Header, Version),
2345 				&tmp, SMC_RAM_END);
2346 
2347 	if (0 == result) {
2348 		hwmgr->microcode_version_info.SMC = tmp;
2349 	}
2350 
2351 	error |= (0 != result);
2352 
2353 	result = smu7_read_smc_sram_dword(hwmgr,
2354 				SMU71_FIRMWARE_HEADER_LOCATION +
2355 				offsetof(SMU71_Firmware_Header, UlvSettings),
2356 				&tmp, SMC_RAM_END);
2357 
2358 	if (0 == result) {
2359 		smu7_data->ulv_setting_starts = tmp;
2360 	}
2361 
2362 	error |= (0 != result);
2363 
2364 	return error ? 1 : 0;
2365 }
2366 
2367 /*---------------------------MC----------------------------*/
2368 
iceland_get_memory_modile_index(struct pp_hwmgr * hwmgr)2369 static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2370 {
2371 	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2372 }
2373 
iceland_check_s0_mc_reg_index(uint16_t in_reg,uint16_t * out_reg)2374 static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
2375 {
2376 	bool result = true;
2377 
2378 	switch (in_reg) {
2379 	case  mmMC_SEQ_RAS_TIMING:
2380 		*out_reg = mmMC_SEQ_RAS_TIMING_LP;
2381 		break;
2382 
2383 	case  mmMC_SEQ_DLL_STBY:
2384 		*out_reg = mmMC_SEQ_DLL_STBY_LP;
2385 		break;
2386 
2387 	case  mmMC_SEQ_G5PDX_CMD0:
2388 		*out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
2389 		break;
2390 
2391 	case  mmMC_SEQ_G5PDX_CMD1:
2392 		*out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
2393 		break;
2394 
2395 	case  mmMC_SEQ_G5PDX_CTRL:
2396 		*out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
2397 		break;
2398 
2399 	case mmMC_SEQ_CAS_TIMING:
2400 		*out_reg = mmMC_SEQ_CAS_TIMING_LP;
2401 		break;
2402 
2403 	case mmMC_SEQ_MISC_TIMING:
2404 		*out_reg = mmMC_SEQ_MISC_TIMING_LP;
2405 		break;
2406 
2407 	case mmMC_SEQ_MISC_TIMING2:
2408 		*out_reg = mmMC_SEQ_MISC_TIMING2_LP;
2409 		break;
2410 
2411 	case mmMC_SEQ_PMG_DVS_CMD:
2412 		*out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
2413 		break;
2414 
2415 	case mmMC_SEQ_PMG_DVS_CTL:
2416 		*out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
2417 		break;
2418 
2419 	case mmMC_SEQ_RD_CTL_D0:
2420 		*out_reg = mmMC_SEQ_RD_CTL_D0_LP;
2421 		break;
2422 
2423 	case mmMC_SEQ_RD_CTL_D1:
2424 		*out_reg = mmMC_SEQ_RD_CTL_D1_LP;
2425 		break;
2426 
2427 	case mmMC_SEQ_WR_CTL_D0:
2428 		*out_reg = mmMC_SEQ_WR_CTL_D0_LP;
2429 		break;
2430 
2431 	case mmMC_SEQ_WR_CTL_D1:
2432 		*out_reg = mmMC_SEQ_WR_CTL_D1_LP;
2433 		break;
2434 
2435 	case mmMC_PMG_CMD_EMRS:
2436 		*out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
2437 		break;
2438 
2439 	case mmMC_PMG_CMD_MRS:
2440 		*out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
2441 		break;
2442 
2443 	case mmMC_PMG_CMD_MRS1:
2444 		*out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
2445 		break;
2446 
2447 	case mmMC_SEQ_PMG_TIMING:
2448 		*out_reg = mmMC_SEQ_PMG_TIMING_LP;
2449 		break;
2450 
2451 	case mmMC_PMG_CMD_MRS2:
2452 		*out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
2453 		break;
2454 
2455 	case mmMC_SEQ_WR_CTL_2:
2456 		*out_reg = mmMC_SEQ_WR_CTL_2_LP;
2457 		break;
2458 
2459 	default:
2460 		result = false;
2461 		break;
2462 	}
2463 
2464 	return result;
2465 }
2466 
iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table * table)2467 static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)
2468 {
2469 	uint32_t i;
2470 	uint16_t address;
2471 
2472 	for (i = 0; i < table->last; i++) {
2473 		table->mc_reg_address[i].s0 =
2474 			iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2475 			? address : table->mc_reg_address[i].s1;
2476 	}
2477 	return 0;
2478 }
2479 
iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table * table,struct iceland_mc_reg_table * ni_table)2480 static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2481 					struct iceland_mc_reg_table *ni_table)
2482 {
2483 	uint8_t i, j;
2484 
2485 	PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2486 		"Invalid VramInfo table.", return -EINVAL);
2487 	PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2488 		"Invalid VramInfo table.", return -EINVAL);
2489 
2490 	for (i = 0; i < table->last; i++) {
2491 		ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2492 	}
2493 	ni_table->last = table->last;
2494 
2495 	for (i = 0; i < table->num_entries; i++) {
2496 		ni_table->mc_reg_table_entry[i].mclk_max =
2497 			table->mc_reg_table_entry[i].mclk_max;
2498 		for (j = 0; j < table->last; j++) {
2499 			ni_table->mc_reg_table_entry[i].mc_data[j] =
2500 				table->mc_reg_table_entry[i].mc_data[j];
2501 		}
2502 	}
2503 
2504 	ni_table->num_entries = table->num_entries;
2505 
2506 	return 0;
2507 }
2508 
iceland_set_mc_special_registers(struct pp_hwmgr * hwmgr,struct iceland_mc_reg_table * table)2509 static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2510 					struct iceland_mc_reg_table *table)
2511 {
2512 	uint8_t i, j, k;
2513 	uint32_t temp_reg;
2514 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2515 
2516 	for (i = 0, j = table->last; i < table->last; i++) {
2517 		PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2518 			"Invalid VramInfo table.", return -EINVAL);
2519 
2520 		switch (table->mc_reg_address[i].s1) {
2521 
2522 		case mmMC_SEQ_MISC1:
2523 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
2524 			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2525 			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2526 			for (k = 0; k < table->num_entries; k++) {
2527 				table->mc_reg_table_entry[k].mc_data[j] =
2528 					((temp_reg & 0xffff0000)) |
2529 					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2530 			}
2531 			j++;
2532 
2533 			PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2534 				"Invalid VramInfo table.", return -EINVAL);
2535 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
2536 			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
2537 			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
2538 			for (k = 0; k < table->num_entries; k++) {
2539 				table->mc_reg_table_entry[k].mc_data[j] =
2540 					(temp_reg & 0xffff0000) |
2541 					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2542 
2543 				if (!data->is_memory_gddr5) {
2544 					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2545 				}
2546 			}
2547 			j++;
2548 
2549 			if (!data->is_memory_gddr5) {
2550 				PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2551 					"Invalid VramInfo table.", return -EINVAL);
2552 				table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
2553 				table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
2554 				for (k = 0; k < table->num_entries; k++) {
2555 					table->mc_reg_table_entry[k].mc_data[j] =
2556 						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
2557 				}
2558 				j++;
2559 			}
2560 
2561 			break;
2562 
2563 		case mmMC_SEQ_RESERVE_M:
2564 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
2565 			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
2566 			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
2567 			for (k = 0; k < table->num_entries; k++) {
2568 				table->mc_reg_table_entry[k].mc_data[j] =
2569 					(temp_reg & 0xffff0000) |
2570 					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2571 			}
2572 			j++;
2573 			break;
2574 
2575 		default:
2576 			break;
2577 		}
2578 
2579 	}
2580 
2581 	table->last = j;
2582 
2583 	return 0;
2584 }
2585 
iceland_set_valid_flag(struct iceland_mc_reg_table * table)2586 static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
2587 {
2588 	uint8_t i, j;
2589 	for (i = 0; i < table->last; i++) {
2590 		for (j = 1; j < table->num_entries; j++) {
2591 			if (table->mc_reg_table_entry[j-1].mc_data[i] !=
2592 				table->mc_reg_table_entry[j].mc_data[i]) {
2593 				table->validflag |= (1<<i);
2594 				break;
2595 			}
2596 		}
2597 	}
2598 
2599 	return 0;
2600 }
2601 
iceland_initialize_mc_reg_table(struct pp_hwmgr * hwmgr)2602 static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2603 {
2604 	int result;
2605 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2606 	pp_atomctrl_mc_reg_table *table;
2607 	struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
2608 	uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
2609 
2610 	table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
2611 
2612 	if (NULL == table)
2613 		return -ENOMEM;
2614 
2615 	/* Program additional LP registers that are no longer programmed by VBIOS */
2616 	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2617 	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2618 	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
2619 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
2620 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
2621 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
2622 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
2623 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
2624 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
2625 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
2626 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
2627 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
2628 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
2629 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
2630 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
2631 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
2632 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
2633 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
2634 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
2635 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
2636 
2637 	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
2638 
2639 	if (0 == result)
2640 		result = iceland_copy_vbios_smc_reg_table(table, ni_table);
2641 
2642 	if (0 == result) {
2643 		iceland_set_s0_mc_reg_index(ni_table);
2644 		result = iceland_set_mc_special_registers(hwmgr, ni_table);
2645 	}
2646 
2647 	if (0 == result)
2648 		iceland_set_valid_flag(ni_table);
2649 
2650 	kfree(table);
2651 
2652 	return result;
2653 }
2654 
iceland_is_dpm_running(struct pp_hwmgr * hwmgr)2655 static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
2656 {
2657 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2658 			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2659 			? true : false;
2660 }
2661 
2662 const struct pp_smumgr_func iceland_smu_funcs = {
2663 	.name = "iceland_smu",
2664 	.smu_init = &iceland_smu_init,
2665 	.smu_fini = &smu7_smu_fini,
2666 	.start_smu = &iceland_start_smu,
2667 	.check_fw_load_finish = &smu7_check_fw_load_finish,
2668 	.request_smu_load_fw = &smu7_request_smu_load_fw,
2669 	.request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
2670 	.send_msg_to_smc = &smu7_send_msg_to_smc,
2671 	.send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
2672 	.get_argument = smu7_get_argument,
2673 	.download_pptable_settings = NULL,
2674 	.upload_pptable_settings = NULL,
2675 	.get_offsetof = iceland_get_offsetof,
2676 	.process_firmware_header = iceland_process_firmware_header,
2677 	.init_smc_table = iceland_init_smc_table,
2678 	.update_sclk_threshold = iceland_update_sclk_threshold,
2679 	.thermal_setup_fan_table = iceland_thermal_setup_fan_table,
2680 	.populate_all_graphic_levels = iceland_populate_all_graphic_levels,
2681 	.populate_all_memory_levels = iceland_populate_all_memory_levels,
2682 	.get_mac_definition = iceland_get_mac_definition,
2683 	.initialize_mc_reg_table = iceland_initialize_mc_reg_table,
2684 	.is_dpm_running = iceland_is_dpm_running,
2685 };
2686 
2687