xref: /openbmc/linux/drivers/i2c/busses/i2c-bcm2835.c (revision 59738ab2)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * BCM2835 master mode driver
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/clkdev.h>
8 #include <linux/clk-provider.h>
9 #include <linux/completion.h>
10 #include <linux/err.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 
19 #define BCM2835_I2C_C		0x0
20 #define BCM2835_I2C_S		0x4
21 #define BCM2835_I2C_DLEN	0x8
22 #define BCM2835_I2C_A		0xc
23 #define BCM2835_I2C_FIFO	0x10
24 #define BCM2835_I2C_DIV		0x14
25 #define BCM2835_I2C_DEL		0x18
26 /*
27  * 16-bit field for the number of SCL cycles to wait after rising SCL
28  * before deciding the slave is not responding. 0 disables the
29  * timeout detection.
30  */
31 #define BCM2835_I2C_CLKT	0x1c
32 
33 #define BCM2835_I2C_C_READ	BIT(0)
34 #define BCM2835_I2C_C_CLEAR	BIT(4) /* bits 4 and 5 both clear */
35 #define BCM2835_I2C_C_ST	BIT(7)
36 #define BCM2835_I2C_C_INTD	BIT(8)
37 #define BCM2835_I2C_C_INTT	BIT(9)
38 #define BCM2835_I2C_C_INTR	BIT(10)
39 #define BCM2835_I2C_C_I2CEN	BIT(15)
40 
41 #define BCM2835_I2C_S_TA	BIT(0)
42 #define BCM2835_I2C_S_DONE	BIT(1)
43 #define BCM2835_I2C_S_TXW	BIT(2)
44 #define BCM2835_I2C_S_RXR	BIT(3)
45 #define BCM2835_I2C_S_TXD	BIT(4)
46 #define BCM2835_I2C_S_RXD	BIT(5)
47 #define BCM2835_I2C_S_TXE	BIT(6)
48 #define BCM2835_I2C_S_RXF	BIT(7)
49 #define BCM2835_I2C_S_ERR	BIT(8)
50 #define BCM2835_I2C_S_CLKT	BIT(9)
51 #define BCM2835_I2C_S_LEN	BIT(10) /* Fake bit for SW error reporting */
52 
53 #define BCM2835_I2C_FEDL_SHIFT	16
54 #define BCM2835_I2C_REDL_SHIFT	0
55 
56 #define BCM2835_I2C_CDIV_MIN	0x0002
57 #define BCM2835_I2C_CDIV_MAX	0xFFFE
58 
59 struct bcm2835_i2c_dev {
60 	struct device *dev;
61 	void __iomem *regs;
62 	int irq;
63 	struct i2c_adapter adapter;
64 	struct completion completion;
65 	struct i2c_msg *curr_msg;
66 	struct clk *bus_clk;
67 	int num_msgs;
68 	u32 msg_err;
69 	u8 *msg_buf;
70 	size_t msg_buf_remaining;
71 };
72 
bcm2835_i2c_writel(struct bcm2835_i2c_dev * i2c_dev,u32 reg,u32 val)73 static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
74 				      u32 reg, u32 val)
75 {
76 	writel(val, i2c_dev->regs + reg);
77 }
78 
bcm2835_i2c_readl(struct bcm2835_i2c_dev * i2c_dev,u32 reg)79 static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
80 {
81 	return readl(i2c_dev->regs + reg);
82 }
83 
84 #define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
85 struct clk_bcm2835_i2c {
86 	struct clk_hw hw;
87 	struct bcm2835_i2c_dev *i2c_dev;
88 };
89 
clk_bcm2835_i2c_calc_divider(unsigned long rate,unsigned long parent_rate)90 static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
91 				unsigned long parent_rate)
92 {
93 	u32 divider = DIV_ROUND_UP(parent_rate, rate);
94 
95 	/*
96 	 * Per the datasheet, the register is always interpreted as an even
97 	 * number, by rounding down. In other words, the LSB is ignored. So,
98 	 * if the LSB is set, increment the divider to avoid any issue.
99 	 */
100 	if (divider & 1)
101 		divider++;
102 	if ((divider < BCM2835_I2C_CDIV_MIN) ||
103 	    (divider > BCM2835_I2C_CDIV_MAX))
104 		return -EINVAL;
105 
106 	return divider;
107 }
108 
clk_bcm2835_i2c_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)109 static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
110 				unsigned long parent_rate)
111 {
112 	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
113 	u32 redl, fedl;
114 	u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
115 
116 	if (divider == -EINVAL)
117 		return -EINVAL;
118 
119 	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
120 
121 	/*
122 	 * Number of core clocks to wait after falling edge before
123 	 * outputting the next data bit.  Note that both FEDL and REDL
124 	 * can't be greater than CDIV/2.
125 	 */
126 	fedl = max(divider / 16, 1u);
127 
128 	/*
129 	 * Number of core clocks to wait after rising edge before
130 	 * sampling the next incoming data bit.
131 	 */
132 	redl = max(divider / 4, 1u);
133 
134 	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
135 			   (fedl << BCM2835_I2C_FEDL_SHIFT) |
136 			   (redl << BCM2835_I2C_REDL_SHIFT));
137 	return 0;
138 }
139 
clk_bcm2835_i2c_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)140 static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate,
141 				unsigned long *parent_rate)
142 {
143 	u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate);
144 
145 	return DIV_ROUND_UP(*parent_rate, divider);
146 }
147 
clk_bcm2835_i2c_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)148 static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
149 						unsigned long parent_rate)
150 {
151 	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
152 	u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
153 
154 	return DIV_ROUND_UP(parent_rate, divider);
155 }
156 
157 static const struct clk_ops clk_bcm2835_i2c_ops = {
158 	.set_rate = clk_bcm2835_i2c_set_rate,
159 	.round_rate = clk_bcm2835_i2c_round_rate,
160 	.recalc_rate = clk_bcm2835_i2c_recalc_rate,
161 };
162 
bcm2835_i2c_register_div(struct device * dev,struct clk * mclk,struct bcm2835_i2c_dev * i2c_dev)163 static struct clk *bcm2835_i2c_register_div(struct device *dev,
164 					struct clk *mclk,
165 					struct bcm2835_i2c_dev *i2c_dev)
166 {
167 	struct clk_init_data init;
168 	struct clk_bcm2835_i2c *priv;
169 	char name[32];
170 	const char *mclk_name;
171 
172 	snprintf(name, sizeof(name), "%s_div", dev_name(dev));
173 
174 	mclk_name = __clk_get_name(mclk);
175 
176 	init.ops = &clk_bcm2835_i2c_ops;
177 	init.name = name;
178 	init.parent_names = (const char* []) { mclk_name };
179 	init.num_parents = 1;
180 	init.flags = 0;
181 
182 	priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
183 	if (priv == NULL)
184 		return ERR_PTR(-ENOMEM);
185 
186 	priv->hw.init = &init;
187 	priv->i2c_dev = i2c_dev;
188 
189 	clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
190 	return devm_clk_register(dev, &priv->hw);
191 }
192 
bcm2835_fill_txfifo(struct bcm2835_i2c_dev * i2c_dev)193 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
194 {
195 	u32 val;
196 
197 	while (i2c_dev->msg_buf_remaining) {
198 		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
199 		if (!(val & BCM2835_I2C_S_TXD))
200 			break;
201 		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
202 				   *i2c_dev->msg_buf);
203 		i2c_dev->msg_buf++;
204 		i2c_dev->msg_buf_remaining--;
205 	}
206 }
207 
bcm2835_drain_rxfifo(struct bcm2835_i2c_dev * i2c_dev)208 static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
209 {
210 	u32 val;
211 
212 	while (i2c_dev->msg_buf_remaining) {
213 		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
214 		if (!(val & BCM2835_I2C_S_RXD))
215 			break;
216 		*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
217 						      BCM2835_I2C_FIFO);
218 		i2c_dev->msg_buf++;
219 		i2c_dev->msg_buf_remaining--;
220 	}
221 }
222 
223 /*
224  * Repeated Start Condition (Sr)
225  * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
226  * talks about reading from a slave with 10 bit address. This is achieved by
227  * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
228  * issue a read.
229  * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
230  * firmware actually does it using polling and says that it's a workaround for
231  * a problem in the state machine.
232  * It turns out that it is possible to use the TXW interrupt to know when the
233  * transfer is active, provided the FIFO has not been prefilled.
234  */
235 
bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev * i2c_dev)236 static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
237 {
238 	u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
239 	struct i2c_msg *msg = i2c_dev->curr_msg;
240 	bool last_msg = (i2c_dev->num_msgs == 1);
241 
242 	if (!i2c_dev->num_msgs)
243 		return;
244 
245 	i2c_dev->num_msgs--;
246 	i2c_dev->msg_buf = msg->buf;
247 	i2c_dev->msg_buf_remaining = msg->len;
248 
249 	if (msg->flags & I2C_M_RD)
250 		c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
251 	else
252 		c |= BCM2835_I2C_C_INTT;
253 
254 	if (last_msg)
255 		c |= BCM2835_I2C_C_INTD;
256 
257 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
258 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
259 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
260 }
261 
bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev * i2c_dev)262 static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
263 {
264 	i2c_dev->curr_msg = NULL;
265 	i2c_dev->num_msgs = 0;
266 
267 	i2c_dev->msg_buf = NULL;
268 	i2c_dev->msg_buf_remaining = 0;
269 }
270 
271 /*
272  * Note about I2C_C_CLEAR on error:
273  * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
274  * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
275  * the state machine to send a NACK and a STOP. Since we're setting CLEAR
276  * without I2CEN, that NACK will be hanging around queued up for next time
277  * we start the engine.
278  */
279 
bcm2835_i2c_isr(int this_irq,void * data)280 static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
281 {
282 	struct bcm2835_i2c_dev *i2c_dev = data;
283 	u32 val, err;
284 
285 	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
286 
287 	err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
288 	if (err) {
289 		i2c_dev->msg_err = err;
290 		goto complete;
291 	}
292 
293 	if (val & BCM2835_I2C_S_DONE) {
294 		if (!i2c_dev->curr_msg) {
295 			dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
296 		} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
297 			bcm2835_drain_rxfifo(i2c_dev);
298 			val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
299 		}
300 
301 		if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
302 			i2c_dev->msg_err = BCM2835_I2C_S_LEN;
303 		else
304 			i2c_dev->msg_err = 0;
305 		goto complete;
306 	}
307 
308 	if (val & BCM2835_I2C_S_TXW) {
309 		if (!i2c_dev->msg_buf_remaining) {
310 			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
311 			goto complete;
312 		}
313 
314 		bcm2835_fill_txfifo(i2c_dev);
315 
316 		if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
317 			i2c_dev->curr_msg++;
318 			bcm2835_i2c_start_transfer(i2c_dev);
319 		}
320 
321 		return IRQ_HANDLED;
322 	}
323 
324 	if (val & BCM2835_I2C_S_RXR) {
325 		if (!i2c_dev->msg_buf_remaining) {
326 			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
327 			goto complete;
328 		}
329 
330 		bcm2835_drain_rxfifo(i2c_dev);
331 		return IRQ_HANDLED;
332 	}
333 
334 	return IRQ_NONE;
335 
336 complete:
337 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
338 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
339 			   BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
340 	complete(&i2c_dev->completion);
341 
342 	return IRQ_HANDLED;
343 }
344 
bcm2835_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)345 static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
346 			    int num)
347 {
348 	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
349 	unsigned long time_left;
350 	int i;
351 
352 	for (i = 0; i < (num - 1); i++)
353 		if (msgs[i].flags & I2C_M_RD) {
354 			dev_warn_once(i2c_dev->dev,
355 				      "only one read message supported, has to be last\n");
356 			return -EOPNOTSUPP;
357 		}
358 
359 	i2c_dev->curr_msg = msgs;
360 	i2c_dev->num_msgs = num;
361 	reinit_completion(&i2c_dev->completion);
362 
363 	bcm2835_i2c_start_transfer(i2c_dev);
364 
365 	time_left = wait_for_completion_timeout(&i2c_dev->completion,
366 						adap->timeout);
367 
368 	bcm2835_i2c_finish_transfer(i2c_dev);
369 
370 	if (!time_left) {
371 		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
372 				   BCM2835_I2C_C_CLEAR);
373 		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
374 		return -ETIMEDOUT;
375 	}
376 
377 	if (!i2c_dev->msg_err)
378 		return num;
379 
380 	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
381 
382 	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
383 		return -EREMOTEIO;
384 
385 	return -EIO;
386 }
387 
bcm2835_i2c_func(struct i2c_adapter * adap)388 static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
389 {
390 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
391 }
392 
393 static const struct i2c_algorithm bcm2835_i2c_algo = {
394 	.master_xfer	= bcm2835_i2c_xfer,
395 	.functionality	= bcm2835_i2c_func,
396 };
397 
398 /*
399  * The BCM2835 was reported to have problems with clock stretching:
400  * https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
401  * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
402  */
403 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
404 	.flags = I2C_AQ_NO_CLK_STRETCH,
405 };
406 
bcm2835_i2c_probe(struct platform_device * pdev)407 static int bcm2835_i2c_probe(struct platform_device *pdev)
408 {
409 	struct bcm2835_i2c_dev *i2c_dev;
410 	int ret;
411 	struct i2c_adapter *adap;
412 	struct clk *mclk;
413 	u32 bus_clk_rate;
414 
415 	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
416 	if (!i2c_dev)
417 		return -ENOMEM;
418 	platform_set_drvdata(pdev, i2c_dev);
419 	i2c_dev->dev = &pdev->dev;
420 	init_completion(&i2c_dev->completion);
421 
422 	i2c_dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
423 	if (IS_ERR(i2c_dev->regs))
424 		return PTR_ERR(i2c_dev->regs);
425 
426 	mclk = devm_clk_get(&pdev->dev, NULL);
427 	if (IS_ERR(mclk))
428 		return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
429 				     "Could not get clock\n");
430 
431 	i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
432 
433 	if (IS_ERR(i2c_dev->bus_clk))
434 		return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->bus_clk),
435 				     "Could not register clock\n");
436 
437 	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
438 				   &bus_clk_rate);
439 	if (ret < 0) {
440 		dev_warn(&pdev->dev,
441 			 "Could not read clock-frequency property\n");
442 		bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
443 	}
444 
445 	ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
446 	if (ret < 0)
447 		return dev_err_probe(&pdev->dev, ret,
448 				     "Could not set clock frequency\n");
449 
450 	ret = clk_prepare_enable(i2c_dev->bus_clk);
451 	if (ret) {
452 		dev_err(&pdev->dev, "Couldn't prepare clock");
453 		goto err_put_exclusive_rate;
454 	}
455 
456 	i2c_dev->irq = platform_get_irq(pdev, 0);
457 	if (i2c_dev->irq < 0) {
458 		ret = i2c_dev->irq;
459 		goto err_disable_unprepare_clk;
460 	}
461 
462 	ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
463 			  dev_name(&pdev->dev), i2c_dev);
464 	if (ret) {
465 		dev_err(&pdev->dev, "Could not request IRQ\n");
466 		goto err_disable_unprepare_clk;
467 	}
468 
469 	adap = &i2c_dev->adapter;
470 	i2c_set_adapdata(adap, i2c_dev);
471 	adap->owner = THIS_MODULE;
472 	adap->class = I2C_CLASS_DEPRECATED;
473 	snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
474 		 of_node_full_name(pdev->dev.of_node));
475 	adap->algo = &bcm2835_i2c_algo;
476 	adap->dev.parent = &pdev->dev;
477 	adap->dev.of_node = pdev->dev.of_node;
478 	adap->quirks = of_device_get_match_data(&pdev->dev);
479 
480 	/*
481 	 * Disable the hardware clock stretching timeout. SMBUS
482 	 * specifies a limit for how long the device can stretch the
483 	 * clock, but core I2C doesn't.
484 	 */
485 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_CLKT, 0);
486 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
487 
488 	ret = i2c_add_adapter(adap);
489 	if (ret)
490 		goto err_free_irq;
491 
492 	return 0;
493 
494 err_free_irq:
495 	free_irq(i2c_dev->irq, i2c_dev);
496 err_disable_unprepare_clk:
497 	clk_disable_unprepare(i2c_dev->bus_clk);
498 err_put_exclusive_rate:
499 	clk_rate_exclusive_put(i2c_dev->bus_clk);
500 
501 	return ret;
502 }
503 
bcm2835_i2c_remove(struct platform_device * pdev)504 static void bcm2835_i2c_remove(struct platform_device *pdev)
505 {
506 	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
507 
508 	clk_rate_exclusive_put(i2c_dev->bus_clk);
509 	clk_disable_unprepare(i2c_dev->bus_clk);
510 
511 	free_irq(i2c_dev->irq, i2c_dev);
512 	i2c_del_adapter(&i2c_dev->adapter);
513 }
514 
515 static const struct of_device_id bcm2835_i2c_of_match[] = {
516 	{ .compatible = "brcm,bcm2711-i2c" },
517 	{ .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
518 	{},
519 };
520 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
521 
522 static struct platform_driver bcm2835_i2c_driver = {
523 	.probe		= bcm2835_i2c_probe,
524 	.remove_new	= bcm2835_i2c_remove,
525 	.driver		= {
526 		.name	= "i2c-bcm2835",
527 		.of_match_table = bcm2835_i2c_of_match,
528 	},
529 };
530 module_platform_driver(bcm2835_i2c_driver);
531 
532 MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
533 MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
534 MODULE_LICENSE("GPL v2");
535 MODULE_ALIAS("platform:i2c-bcm2835");
536