1 /*
2 * Sparc32 interrupt helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
22 #include "cpu.h"
23 #include "trace.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "sysemu/runstate.h"
27
28 static const char * const excp_names[0x80] = {
29 [TT_TFAULT] = "Instruction Access Fault",
30 [TT_ILL_INSN] = "Illegal Instruction",
31 [TT_PRIV_INSN] = "Privileged Instruction",
32 [TT_NFPU_INSN] = "FPU Disabled",
33 [TT_WIN_OVF] = "Window Overflow",
34 [TT_WIN_UNF] = "Window Underflow",
35 [TT_UNALIGNED] = "Unaligned Memory Access",
36 [TT_FP_EXCP] = "FPU Exception",
37 [TT_DFAULT] = "Data Access Fault",
38 [TT_TOVF] = "Tag Overflow",
39 [TT_EXTINT | 0x1] = "External Interrupt 1",
40 [TT_EXTINT | 0x2] = "External Interrupt 2",
41 [TT_EXTINT | 0x3] = "External Interrupt 3",
42 [TT_EXTINT | 0x4] = "External Interrupt 4",
43 [TT_EXTINT | 0x5] = "External Interrupt 5",
44 [TT_EXTINT | 0x6] = "External Interrupt 6",
45 [TT_EXTINT | 0x7] = "External Interrupt 7",
46 [TT_EXTINT | 0x8] = "External Interrupt 8",
47 [TT_EXTINT | 0x9] = "External Interrupt 9",
48 [TT_EXTINT | 0xa] = "External Interrupt 10",
49 [TT_EXTINT | 0xb] = "External Interrupt 11",
50 [TT_EXTINT | 0xc] = "External Interrupt 12",
51 [TT_EXTINT | 0xd] = "External Interrupt 13",
52 [TT_EXTINT | 0xe] = "External Interrupt 14",
53 [TT_EXTINT | 0xf] = "External Interrupt 15",
54 [TT_CODE_ACCESS] = "Instruction Access Error",
55 [TT_DATA_ACCESS] = "Data Access Error",
56 [TT_DIV_ZERO] = "Division By Zero",
57 [TT_NCP_INSN] = "Coprocessor Disabled",
58 };
59
excp_name_str(int32_t exception_index)60 static const char *excp_name_str(int32_t exception_index)
61 {
62 if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) {
63 return "Unknown";
64 }
65 return excp_names[exception_index];
66 }
67
cpu_check_irqs(CPUSPARCState * env)68 void cpu_check_irqs(CPUSPARCState *env)
69 {
70 CPUState *cs;
71
72 /* We should be holding the BQL before we mess with IRQs */
73 g_assert(bql_locked());
74
75 if (env->pil_in && (env->interrupt_index == 0 ||
76 (env->interrupt_index & ~15) == TT_EXTINT)) {
77 unsigned int i;
78
79 for (i = 15; i > 0; i--) {
80 if (env->pil_in & (1 << i)) {
81 int old_interrupt = env->interrupt_index;
82
83 env->interrupt_index = TT_EXTINT | i;
84 if (old_interrupt != env->interrupt_index) {
85 cs = env_cpu(env);
86 trace_sun4m_cpu_interrupt(i);
87 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
88 }
89 break;
90 }
91 }
92 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
93 cs = env_cpu(env);
94 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
95 env->interrupt_index = 0;
96 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
97 }
98 }
99
sparc_cpu_do_interrupt(CPUState * cs)100 void sparc_cpu_do_interrupt(CPUState *cs)
101 {
102 CPUSPARCState *env = cpu_env(cs);
103 int cwp, intno = cs->exception_index;
104
105 if (qemu_loglevel_mask(CPU_LOG_INT)) {
106 static int count;
107 const char *name;
108
109 if (intno < 0 || intno >= 0x100) {
110 name = "Unknown";
111 } else if (intno >= 0x80) {
112 name = "Trap Instruction";
113 } else {
114 name = excp_name_str(intno);
115 }
116
117 qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
118 log_cpu_state(cs, 0);
119 count++;
120 }
121 #ifndef CONFIG_USER_ONLY
122 if (env->psret == 0) {
123 if (cs->exception_index == 0x80 &&
124 env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
125 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
126 } else {
127 cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
128 "Error state",
129 cs->exception_index, excp_name_str(cs->exception_index));
130 }
131 return;
132 }
133 if (intno == TT_FP_EXCP) {
134 /*
135 * The sparc32 fpu has three states related to exception handling.
136 * The FPop that signals an exception transitions from fp_execute
137 * to fp_exception_pending. A subsequent FPop transitions from
138 * fp_exception_pending to fp_exception, which forces the trap.
139 *
140 * If the queue is not empty, this trap is due to execution of an
141 * illegal FPop while in fp_exception state. Here we are to
142 * re-enter fp_exception_pending state without queuing the insn.
143 *
144 * We do not model the fp_exception_pending state, but instead
145 * skip directly to fp_exception state. We advance pc/npc to
146 * mimic delayed trap delivery as if by the subsequent insn.
147 */
148 if (!env->fsr_qne) {
149 env->fsr_qne = FSR_QNE;
150 env->fq.s.addr = env->pc;
151 env->fq.s.insn = cpu_ldl_code(env, env->pc);
152 }
153 env->pc = env->npc;
154 env->npc = env->npc + 4;
155 }
156 #endif
157 env->psret = 0;
158 cwp = cpu_cwp_dec(env, env->cwp - 1);
159 cpu_set_cwp(env, cwp);
160 env->regwptr[9] = env->pc;
161 env->regwptr[10] = env->npc;
162 env->psrps = env->psrs;
163 env->psrs = 1;
164 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
165 env->pc = env->tbr;
166 env->npc = env->pc + 4;
167 cs->exception_index = -1;
168
169 #if !defined(CONFIG_USER_ONLY)
170 /* IRQ acknowledgment */
171 if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
172 env->qemu_irq_ack(env, intno);
173 }
174 #endif
175 }
176