1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
23
24 #include <asm/byteorder.h>
25
26 #include "8250.h"
27
28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
35
36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
43
44 #define PCI_VENDOR_ID_CONNECT_TECH 0x12c4
45 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO 0x0340
46 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A 0x0341
47 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B 0x0342
48 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS 0x0350
49 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A 0x0351
50 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B 0x0352
51 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS 0x0353
52 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A 0x0354
53 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B 0x0355
54 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO 0x0360
55 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A 0x0361
56 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B 0x0362
57 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP 0x0370
58 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232 0x0371
59 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485 0x0372
60 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP 0x0373
61 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP 0x0374
62 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP 0x0375
63 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS 0x0376
64 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT 0x0380
65 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT 0x0381
66 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO 0x0382
67 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO 0x0392
68 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP 0x03A0
69 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232 0x03A1
70 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485 0x03A2
71 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS 0x03A3
72 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XEG001 0x0602
73 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_BASE 0x1000
74 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_2 0x1002
75 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_4 0x1004
76 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_8 0x1008
77 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_12 0x100C
78 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_16 0x1010
79 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X 0x110c
80 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X 0x110d
81 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16 0x1110
82
83 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
84 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
85 #define PCI_DEVICE_ID_EXAR_XR17V252 0x0252
86 #define PCI_DEVICE_ID_EXAR_XR17V254 0x0254
87 #define PCI_DEVICE_ID_EXAR_XR17V258 0x0258
88
89 #define PCI_SUBDEVICE_ID_USR_2980 0x0128
90 #define PCI_SUBDEVICE_ID_USR_2981 0x0129
91
92 #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001
93 #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002
94 #define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004
95 #define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008
96 #define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010
97
98 #define UART_EXAR_INT0 0x80
99 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
100 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
101 #define UART_EXAR_DVID 0x8d /* Device identification */
102
103 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
104 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
105 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
106 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
107 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
108 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
109 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
110
111 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
112 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
113
114 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
115 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
116 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
117 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
118 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
119 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
120 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
121 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
122 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
123 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
124 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
125 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
126
127 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
128
129 /*
130 * IOT2040 MPIO wiring semantics:
131 *
132 * MPIO Port Function
133 * ---- ---- --------
134 * 0 2 Mode bit 0
135 * 1 2 Mode bit 1
136 * 2 2 Terminate bus
137 * 3 - <reserved>
138 * 4 3 Mode bit 0
139 * 5 3 Mode bit 1
140 * 6 3 Terminate bus
141 * 7 - <reserved>
142 * 8 2 Enable
143 * 9 3 Enable
144 * 10 - Red LED
145 * 11..15 - <unused>
146 */
147
148 /* IOT2040 MPIOs 0..7 */
149 #define IOT2040_UART_MODE_RS232 0x01
150 #define IOT2040_UART_MODE_RS485 0x02
151 #define IOT2040_UART_MODE_RS422 0x03
152 #define IOT2040_UART_TERMINATE_BUS 0x04
153
154 #define IOT2040_UART1_MASK 0x0f
155 #define IOT2040_UART2_SHIFT 4
156
157 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
158 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
159
160 /* IOT2040 MPIOs 8..15 */
161 #define IOT2040_UARTS_ENABLE 0x03
162 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
163
164 struct exar8250;
165
166 struct exar8250_platform {
167 int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
168 struct serial_rs485 *rs485);
169 const struct serial_rs485 *rs485_supported;
170 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
171 void (*unregister_gpio)(struct uart_8250_port *);
172 };
173
174 /**
175 * struct exar8250_board - board information
176 * @num_ports: number of serial ports
177 * @reg_shift: describes UART register mapping in PCI memory
178 * @setup: quirk run at ->probe() stage
179 * @exit: quirk run at ->remove() stage
180 */
181 struct exar8250_board {
182 unsigned int num_ports;
183 unsigned int reg_shift;
184 int (*setup)(struct exar8250 *, struct pci_dev *,
185 struct uart_8250_port *, int);
186 void (*exit)(struct pci_dev *pcidev);
187 };
188
189 struct exar8250 {
190 unsigned int nr;
191 struct exar8250_board *board;
192 void __iomem *virt;
193 int line[];
194 };
195
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)196 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
197 {
198 /*
199 * Exar UARTs have a SLEEP register that enables or disables each UART
200 * to enter sleep mode separately. On the XR17V35x the register
201 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
202 * the UART channel may only write to the corresponding bit.
203 */
204 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
205 }
206
207 /*
208 * XR17V35x UARTs have an extra fractional divisor register (DLD)
209 * Calculate divisor with extra 4-bit fractional portion
210 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)211 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
212 unsigned int *frac)
213 {
214 unsigned int quot_16;
215
216 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
217 *frac = quot_16 & 0x0f;
218
219 return quot_16 >> 4;
220 }
221
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)222 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
223 unsigned int quot, unsigned int quot_frac)
224 {
225 serial8250_do_set_divisor(p, baud, quot, quot_frac);
226
227 /* Preserve bits not related to baudrate; DLD[7:4]. */
228 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
229 serial_port_out(p, 0x2, quot_frac);
230 }
231
xr17v35x_startup(struct uart_port * port)232 static int xr17v35x_startup(struct uart_port *port)
233 {
234 /*
235 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
236 * MCR [7:5] and MSR [7:0]
237 */
238 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
239
240 /*
241 * Make sure all interrups are masked until initialization is
242 * complete and the FIFOs are cleared
243 *
244 * Synchronize UART_IER access against the console.
245 */
246 spin_lock_irq(&port->lock);
247 serial_port_out(port, UART_IER, 0);
248 spin_unlock_irq(&port->lock);
249
250 return serial8250_do_startup(port);
251 }
252
exar_shutdown(struct uart_port * port)253 static void exar_shutdown(struct uart_port *port)
254 {
255 bool tx_complete = false;
256 struct uart_8250_port *up = up_to_u8250p(port);
257 struct circ_buf *xmit = &port->state->xmit;
258 int i = 0;
259 u16 lsr;
260
261 do {
262 lsr = serial_in(up, UART_LSR);
263 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
264 tx_complete = true;
265 else
266 tx_complete = false;
267 usleep_range(1000, 1100);
268 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
269
270 serial8250_do_shutdown(port);
271 }
272
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)273 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
274 int idx, unsigned int offset,
275 struct uart_8250_port *port)
276 {
277 const struct exar8250_board *board = priv->board;
278 unsigned int bar = 0;
279 unsigned char status;
280
281 port->port.iotype = UPIO_MEM;
282 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
283 port->port.membase = priv->virt + offset;
284 port->port.regshift = board->reg_shift;
285
286 /*
287 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
288 * with when DLAB is set which will cause the device to incorrectly match
289 * and assign port type to PORT_16650. The EFR for this UART is found
290 * at offset 0x09. Instead check the Deice ID (DVID) register
291 * for a 2, 4 or 8 port UART.
292 */
293 status = readb(port->port.membase + UART_EXAR_DVID);
294 if (status == 0x82 || status == 0x84 || status == 0x88) {
295 port->port.type = PORT_XR17V35X;
296
297 port->port.get_divisor = xr17v35x_get_divisor;
298 port->port.set_divisor = xr17v35x_set_divisor;
299
300 port->port.startup = xr17v35x_startup;
301 } else {
302 port->port.type = PORT_XR17D15X;
303 }
304
305 port->port.pm = exar_pm;
306 port->port.shutdown = exar_shutdown;
307
308 return 0;
309 }
310
311 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)312 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
313 struct uart_8250_port *port, int idx)
314 {
315 unsigned int offset = idx * 0x200;
316 unsigned int baud = 1843200;
317 u8 __iomem *p;
318 int err;
319
320 port->port.uartclk = baud * 16;
321
322 err = default_setup(priv, pcidev, idx, offset, port);
323 if (err)
324 return err;
325
326 p = port->port.membase;
327
328 writeb(0x00, p + UART_EXAR_8XMODE);
329 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
330 writeb(32, p + UART_EXAR_TXTRG);
331 writeb(32, p + UART_EXAR_RXTRG);
332
333 /*
334 * Setup Multipurpose Input/Output pins.
335 */
336 if (idx == 0) {
337 switch (pcidev->device) {
338 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
339 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
340 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
341 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
342 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
343 break;
344 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
345 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
346 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
347 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
348 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
349 break;
350 }
351 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
352 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
353 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
354 }
355
356 return 0;
357 }
358
359 static int
pci_connect_tech_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)360 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
361 struct uart_8250_port *port, int idx)
362 {
363 unsigned int offset = idx * 0x200;
364 unsigned int baud = 1843200;
365
366 port->port.uartclk = baud * 16;
367 return default_setup(priv, pcidev, idx, offset, port);
368 }
369
370 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)371 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
372 struct uart_8250_port *port, int idx)
373 {
374 unsigned int offset = idx * 0x200;
375 unsigned int baud = 921600;
376
377 port->port.uartclk = baud * 16;
378 return default_setup(priv, pcidev, idx, offset, port);
379 }
380
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)381 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
382 {
383 /*
384 * The Commtech adapters required the MPIOs to be driven low. The Exar
385 * devices will export them as GPIOs, so we pre-configure them safely
386 * as inputs.
387 */
388
389 u8 dir = 0x00;
390
391 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
392 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
393 // Configure GPIO as inputs for Commtech adapters
394 dir = 0xff;
395 } else {
396 // Configure GPIO as outputs for SeaLevel adapters
397 dir = 0x00;
398 }
399
400 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
401 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
402 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
403 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
404 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
405 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
406 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
407 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
408 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
409 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
410 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
411 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
412 }
413
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct software_node * node)414 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
415 const struct software_node *node)
416 {
417 struct platform_device *pdev;
418
419 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
420 if (!pdev)
421 return NULL;
422
423 pdev->dev.parent = &pcidev->dev;
424 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
425
426 if (device_add_software_node(&pdev->dev, node) < 0 ||
427 platform_device_add(pdev) < 0) {
428 platform_device_put(pdev);
429 return NULL;
430 }
431
432 return pdev;
433 }
434
__xr17v35x_unregister_gpio(struct platform_device * pdev)435 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
436 {
437 device_remove_software_node(&pdev->dev);
438 platform_device_unregister(pdev);
439 }
440
441 static const struct property_entry exar_gpio_properties[] = {
442 PROPERTY_ENTRY_U32("exar,first-pin", 0),
443 PROPERTY_ENTRY_U32("ngpios", 16),
444 { }
445 };
446
447 static const struct software_node exar_gpio_node = {
448 .properties = exar_gpio_properties,
449 };
450
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)451 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
452 {
453 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
454 port->port.private_data =
455 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
456
457 return 0;
458 }
459
xr17v35x_unregister_gpio(struct uart_8250_port * port)460 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
461 {
462 if (!port->port.private_data)
463 return;
464
465 __xr17v35x_unregister_gpio(port->port.private_data);
466 port->port.private_data = NULL;
467 }
468
generic_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)469 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
470 struct serial_rs485 *rs485)
471 {
472 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
473 u8 __iomem *p = port->membase;
474 u8 value;
475
476 value = readb(p + UART_EXAR_FCTR);
477 if (is_rs485)
478 value |= UART_FCTR_EXAR_485;
479 else
480 value &= ~UART_FCTR_EXAR_485;
481
482 writeb(value, p + UART_EXAR_FCTR);
483
484 if (is_rs485)
485 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
486
487 return 0;
488 }
489
490 static const struct serial_rs485 generic_rs485_supported = {
491 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
492 };
493
494 static const struct exar8250_platform exar8250_default_platform = {
495 .register_gpio = xr17v35x_register_gpio,
496 .unregister_gpio = xr17v35x_unregister_gpio,
497 .rs485_config = generic_rs485_config,
498 .rs485_supported = &generic_rs485_supported,
499 };
500
iot2040_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)501 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
502 struct serial_rs485 *rs485)
503 {
504 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
505 u8 __iomem *p = port->membase;
506 u8 mask = IOT2040_UART1_MASK;
507 u8 mode, value;
508
509 if (is_rs485) {
510 if (rs485->flags & SER_RS485_RX_DURING_TX)
511 mode = IOT2040_UART_MODE_RS422;
512 else
513 mode = IOT2040_UART_MODE_RS485;
514
515 if (rs485->flags & SER_RS485_TERMINATE_BUS)
516 mode |= IOT2040_UART_TERMINATE_BUS;
517 } else {
518 mode = IOT2040_UART_MODE_RS232;
519 }
520
521 if (port->line == 3) {
522 mask <<= IOT2040_UART2_SHIFT;
523 mode <<= IOT2040_UART2_SHIFT;
524 }
525
526 value = readb(p + UART_EXAR_MPIOLVL_7_0);
527 value &= ~mask;
528 value |= mode;
529 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
530
531 return generic_rs485_config(port, termios, rs485);
532 }
533
534 static const struct serial_rs485 iot2040_rs485_supported = {
535 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
536 SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
537 };
538
539 static const struct property_entry iot2040_gpio_properties[] = {
540 PROPERTY_ENTRY_U32("exar,first-pin", 10),
541 PROPERTY_ENTRY_U32("ngpios", 1),
542 { }
543 };
544
545 static const struct software_node iot2040_gpio_node = {
546 .properties = iot2040_gpio_properties,
547 };
548
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)549 static int iot2040_register_gpio(struct pci_dev *pcidev,
550 struct uart_8250_port *port)
551 {
552 u8 __iomem *p = port->port.membase;
553
554 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
555 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
556 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
557 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
558
559 port->port.private_data =
560 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
561
562 return 0;
563 }
564
565 static const struct exar8250_platform iot2040_platform = {
566 .rs485_config = iot2040_rs485_config,
567 .rs485_supported = &iot2040_rs485_supported,
568 .register_gpio = iot2040_register_gpio,
569 .unregister_gpio = xr17v35x_unregister_gpio,
570 };
571
572 /*
573 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
574 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
575 * board name after the device was found.
576 */
577 static const struct dmi_system_id exar_platforms[] = {
578 {
579 .matches = {
580 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
581 },
582 .driver_data = (void *)&iot2040_platform,
583 },
584 {}
585 };
586
exar_get_platform(void)587 static const struct exar8250_platform *exar_get_platform(void)
588 {
589 const struct dmi_system_id *dmi_match;
590
591 dmi_match = dmi_first_match(exar_platforms);
592 if (dmi_match)
593 return dmi_match->driver_data;
594
595 return &exar8250_default_platform;
596 }
597
598 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)599 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
600 struct uart_8250_port *port, int idx)
601 {
602 const struct exar8250_platform *platform = exar_get_platform();
603 unsigned int offset = idx * 0x400;
604 unsigned int baud = 7812500;
605 u8 __iomem *p;
606 int ret;
607
608 port->port.uartclk = baud * 16;
609 port->port.rs485_config = platform->rs485_config;
610 port->port.rs485_supported = *(platform->rs485_supported);
611
612 /*
613 * Setup the UART clock for the devices on expansion slot to
614 * half the clock speed of the main chip (which is 125MHz)
615 */
616 if (idx >= 8)
617 port->port.uartclk /= 2;
618
619 ret = default_setup(priv, pcidev, idx, offset, port);
620 if (ret)
621 return ret;
622
623 p = port->port.membase;
624
625 writeb(0x00, p + UART_EXAR_8XMODE);
626 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
627 writeb(128, p + UART_EXAR_TXTRG);
628 writeb(128, p + UART_EXAR_RXTRG);
629
630 if (idx == 0) {
631 /* Setup Multipurpose Input/Output pins. */
632 setup_gpio(pcidev, p);
633
634 ret = platform->register_gpio(pcidev, port);
635 }
636
637 return ret;
638 }
639
pci_xr17v35x_exit(struct pci_dev * pcidev)640 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
641 {
642 const struct exar8250_platform *platform = exar_get_platform();
643 struct exar8250 *priv = pci_get_drvdata(pcidev);
644 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
645
646 platform->unregister_gpio(port);
647 }
648
exar_misc_clear(struct exar8250 * priv)649 static inline void exar_misc_clear(struct exar8250 *priv)
650 {
651 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
652 readb(priv->virt + UART_EXAR_INT0);
653
654 /* Clear INT0 for Expansion Interface slave ports, too */
655 if (priv->board->num_ports > 8)
656 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
657 }
658
659 /*
660 * These Exar UARTs have an extra interrupt indicator that could fire for a
661 * few interrupts that are not presented/cleared through IIR. One of which is
662 * a wakeup interrupt when coming out of sleep. These interrupts are only
663 * cleared by reading global INT0 or INT1 registers as interrupts are
664 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
665 * channel's address space, but for the sake of bus efficiency we register a
666 * dedicated handler at the PCI device level to handle them.
667 */
exar_misc_handler(int irq,void * data)668 static irqreturn_t exar_misc_handler(int irq, void *data)
669 {
670 exar_misc_clear(data);
671
672 return IRQ_HANDLED;
673 }
674
675 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)676 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
677 {
678 unsigned int nr_ports, i, bar = 0, maxnr;
679 struct exar8250_board *board;
680 struct uart_8250_port uart;
681 struct exar8250 *priv;
682 int rc;
683
684 board = (struct exar8250_board *)ent->driver_data;
685 if (!board)
686 return -EINVAL;
687
688 rc = pcim_enable_device(pcidev);
689 if (rc)
690 return rc;
691
692 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
693
694 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
695 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
696 else if (board->num_ports)
697 nr_ports = board->num_ports;
698 else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL)
699 nr_ports = pcidev->device & 0xff;
700 else
701 nr_ports = pcidev->device & 0x0f;
702
703 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
704 if (!priv)
705 return -ENOMEM;
706
707 priv->board = board;
708 priv->virt = pcim_iomap(pcidev, bar, 0);
709 if (!priv->virt)
710 return -ENOMEM;
711
712 pci_set_master(pcidev);
713
714 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
715 if (rc < 0)
716 return rc;
717
718 memset(&uart, 0, sizeof(uart));
719 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
720 uart.port.irq = pci_irq_vector(pcidev, 0);
721 uart.port.dev = &pcidev->dev;
722
723 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
724 IRQF_SHARED, "exar_uart", priv);
725 if (rc)
726 return rc;
727
728 /* Clear interrupts */
729 exar_misc_clear(priv);
730
731 for (i = 0; i < nr_ports && i < maxnr; i++) {
732 rc = board->setup(priv, pcidev, &uart, i);
733 if (rc) {
734 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
735 break;
736 }
737
738 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
739 uart.port.iobase, uart.port.irq, uart.port.iotype);
740
741 priv->line[i] = serial8250_register_8250_port(&uart);
742 if (priv->line[i] < 0) {
743 dev_err(&pcidev->dev,
744 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
745 uart.port.iobase, uart.port.irq,
746 uart.port.iotype, priv->line[i]);
747 break;
748 }
749 }
750 priv->nr = i;
751 pci_set_drvdata(pcidev, priv);
752 return 0;
753 }
754
exar_pci_remove(struct pci_dev * pcidev)755 static void exar_pci_remove(struct pci_dev *pcidev)
756 {
757 struct exar8250 *priv = pci_get_drvdata(pcidev);
758 unsigned int i;
759
760 for (i = 0; i < priv->nr; i++)
761 serial8250_unregister_port(priv->line[i]);
762
763 /* Ensure that every init quirk is properly torn down */
764 if (priv->board->exit)
765 priv->board->exit(pcidev);
766 }
767
exar_suspend(struct device * dev)768 static int __maybe_unused exar_suspend(struct device *dev)
769 {
770 struct pci_dev *pcidev = to_pci_dev(dev);
771 struct exar8250 *priv = pci_get_drvdata(pcidev);
772 unsigned int i;
773
774 for (i = 0; i < priv->nr; i++)
775 if (priv->line[i] >= 0)
776 serial8250_suspend_port(priv->line[i]);
777
778 return 0;
779 }
780
exar_resume(struct device * dev)781 static int __maybe_unused exar_resume(struct device *dev)
782 {
783 struct exar8250 *priv = dev_get_drvdata(dev);
784 unsigned int i;
785
786 exar_misc_clear(priv);
787
788 for (i = 0; i < priv->nr; i++)
789 if (priv->line[i] >= 0)
790 serial8250_resume_port(priv->line[i]);
791
792 return 0;
793 }
794
795 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
796
797 static const struct exar8250_board pbn_fastcom335_2 = {
798 .num_ports = 2,
799 .setup = pci_fastcom335_setup,
800 };
801
802 static const struct exar8250_board pbn_fastcom335_4 = {
803 .num_ports = 4,
804 .setup = pci_fastcom335_setup,
805 };
806
807 static const struct exar8250_board pbn_fastcom335_8 = {
808 .num_ports = 8,
809 .setup = pci_fastcom335_setup,
810 };
811
812 static const struct exar8250_board pbn_connect = {
813 .setup = pci_connect_tech_setup,
814 };
815
816 static const struct exar8250_board pbn_exar_ibm_saturn = {
817 .num_ports = 1,
818 .setup = pci_xr17c154_setup,
819 };
820
821 static const struct exar8250_board pbn_exar_XR17C15x = {
822 .setup = pci_xr17c154_setup,
823 };
824
825 static const struct exar8250_board pbn_exar_XR17V35x = {
826 .setup = pci_xr17v35x_setup,
827 .exit = pci_xr17v35x_exit,
828 };
829
830 static const struct exar8250_board pbn_fastcom35x_2 = {
831 .num_ports = 2,
832 .setup = pci_xr17v35x_setup,
833 .exit = pci_xr17v35x_exit,
834 };
835
836 static const struct exar8250_board pbn_fastcom35x_4 = {
837 .num_ports = 4,
838 .setup = pci_xr17v35x_setup,
839 .exit = pci_xr17v35x_exit,
840 };
841
842 static const struct exar8250_board pbn_fastcom35x_8 = {
843 .num_ports = 8,
844 .setup = pci_xr17v35x_setup,
845 .exit = pci_xr17v35x_exit,
846 };
847
848 static const struct exar8250_board pbn_exar_XR17V4358 = {
849 .num_ports = 12,
850 .setup = pci_xr17v35x_setup,
851 .exit = pci_xr17v35x_exit,
852 };
853
854 static const struct exar8250_board pbn_exar_XR17V8358 = {
855 .num_ports = 16,
856 .setup = pci_xr17v35x_setup,
857 .exit = pci_xr17v35x_exit,
858 };
859
860 #define CONNECT_DEVICE(devid, sdevid, bd) { \
861 PCI_DEVICE_SUB( \
862 PCI_VENDOR_ID_EXAR, \
863 PCI_DEVICE_ID_EXAR_##devid, \
864 PCI_SUBVENDOR_ID_CONNECT_TECH, \
865 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
866 (kernel_ulong_t)&bd \
867 }
868
869 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
870
871 #define IBM_DEVICE(devid, sdevid, bd) { \
872 PCI_DEVICE_SUB( \
873 PCI_VENDOR_ID_EXAR, \
874 PCI_DEVICE_ID_EXAR_##devid, \
875 PCI_VENDOR_ID_IBM, \
876 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
877 (kernel_ulong_t)&bd \
878 }
879
880 #define USR_DEVICE(devid, sdevid, bd) { \
881 PCI_DEVICE_SUB( \
882 PCI_VENDOR_ID_USR, \
883 PCI_DEVICE_ID_EXAR_##devid, \
884 PCI_VENDOR_ID_EXAR, \
885 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
886 (kernel_ulong_t)&bd \
887 }
888
889 static const struct pci_device_id exar_pci_tbl[] = {
890 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
891 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
892 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
893 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
894 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
895 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
896 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
897
898 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
899 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
900 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
901 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
902 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
903 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
904 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
905 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
906 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
907 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
908 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
909 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
910
911 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
912
913 /* USRobotics USR298x-OEM PCI Modems */
914 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
915 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
916
917 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
918 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
919 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
920 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
921
922 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
923 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
924 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
925 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
926 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
927 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
928 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
929 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
930 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
931
932 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
933 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
934 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
935 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
936
937 EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x),
938 EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x),
939 EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x),
940 EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x),
941 EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x),
942 { 0, }
943 };
944 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
945
946 static struct pci_driver exar_pci_driver = {
947 .name = "exar_serial",
948 .probe = exar_pci_probe,
949 .remove = exar_pci_remove,
950 .driver = {
951 .pm = &exar_pci_pm,
952 },
953 .id_table = exar_pci_tbl,
954 };
955 module_pci_driver(exar_pci_driver);
956
957 MODULE_LICENSE("GPL");
958 MODULE_DESCRIPTION("Exar Serial Driver");
959 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
960