xref: /openbmc/u-boot/board/xilinx/zynqmp/zynqmp.c (revision c48b07a9)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
4  * Michal Simek <michal.simek@xilinx.com>
5  */
6 
7 #include <common.h>
8 #include <sata.h>
9 #include <ahci.h>
10 #include <scsi.h>
11 #include <malloc.h>
12 #include <wdt.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/psu_init_gpl.h>
17 #include <asm/io.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
20 #include <usb.h>
21 #include <dwc3-uboot.h>
22 #include <zynqmppl.h>
23 #include <g_dnl.h>
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
28 static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
29 #endif
30 
31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
32     !defined(CONFIG_SPL_BUILD)
33 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
34 
35 static const struct {
36 	u32 id;
37 	u32 ver;
38 	char *name;
39 	bool evexists;
40 } zynqmp_devices[] = {
41 	{
42 		.id = 0x10,
43 		.name = "3eg",
44 	},
45 	{
46 		.id = 0x10,
47 		.ver = 0x2c,
48 		.name = "3cg",
49 	},
50 	{
51 		.id = 0x11,
52 		.name = "2eg",
53 	},
54 	{
55 		.id = 0x11,
56 		.ver = 0x2c,
57 		.name = "2cg",
58 	},
59 	{
60 		.id = 0x20,
61 		.name = "5ev",
62 		.evexists = 1,
63 	},
64 	{
65 		.id = 0x20,
66 		.ver = 0x100,
67 		.name = "5eg",
68 		.evexists = 1,
69 	},
70 	{
71 		.id = 0x20,
72 		.ver = 0x12c,
73 		.name = "5cg",
74 		.evexists = 1,
75 	},
76 	{
77 		.id = 0x21,
78 		.name = "4ev",
79 		.evexists = 1,
80 	},
81 	{
82 		.id = 0x21,
83 		.ver = 0x100,
84 		.name = "4eg",
85 		.evexists = 1,
86 	},
87 	{
88 		.id = 0x21,
89 		.ver = 0x12c,
90 		.name = "4cg",
91 		.evexists = 1,
92 	},
93 	{
94 		.id = 0x30,
95 		.name = "7ev",
96 		.evexists = 1,
97 	},
98 	{
99 		.id = 0x30,
100 		.ver = 0x100,
101 		.name = "7eg",
102 		.evexists = 1,
103 	},
104 	{
105 		.id = 0x30,
106 		.ver = 0x12c,
107 		.name = "7cg",
108 		.evexists = 1,
109 	},
110 	{
111 		.id = 0x38,
112 		.name = "9eg",
113 	},
114 	{
115 		.id = 0x38,
116 		.ver = 0x2c,
117 		.name = "9cg",
118 	},
119 	{
120 		.id = 0x39,
121 		.name = "6eg",
122 	},
123 	{
124 		.id = 0x39,
125 		.ver = 0x2c,
126 		.name = "6cg",
127 	},
128 	{
129 		.id = 0x40,
130 		.name = "11eg",
131 	},
132 	{ /* For testing purpose only */
133 		.id = 0x50,
134 		.ver = 0x2c,
135 		.name = "15cg",
136 	},
137 	{
138 		.id = 0x50,
139 		.name = "15eg",
140 	},
141 	{
142 		.id = 0x58,
143 		.name = "19eg",
144 	},
145 	{
146 		.id = 0x59,
147 		.name = "17eg",
148 	},
149 	{
150 		.id = 0x61,
151 		.name = "21dr",
152 	},
153 	{
154 		.id = 0x63,
155 		.name = "23dr",
156 	},
157 	{
158 		.id = 0x65,
159 		.name = "25dr",
160 	},
161 	{
162 		.id = 0x64,
163 		.name = "27dr",
164 	},
165 	{
166 		.id = 0x60,
167 		.name = "28dr",
168 	},
169 	{
170 		.id = 0x62,
171 		.name = "29dr",
172 	},
173 };
174 #endif
175 
chip_id(unsigned char id)176 int chip_id(unsigned char id)
177 {
178 	struct pt_regs regs;
179 	int val = -EINVAL;
180 
181 	if (current_el() != 3) {
182 		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
183 		regs.regs[1] = 0;
184 		regs.regs[2] = 0;
185 		regs.regs[3] = 0;
186 
187 		smc_call(&regs);
188 
189 		/*
190 		 * SMC returns:
191 		 * regs[0][31:0]  = status of the operation
192 		 * regs[0][63:32] = CSU.IDCODE register
193 		 * regs[1][31:0]  = CSU.version register
194 		 * regs[1][63:32] = CSU.IDCODE2 register
195 		 */
196 		switch (id) {
197 		case IDCODE:
198 			regs.regs[0] = upper_32_bits(regs.regs[0]);
199 			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
200 					ZYNQMP_CSU_IDCODE_SVD_MASK;
201 			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
202 			val = regs.regs[0];
203 			break;
204 		case VERSION:
205 			regs.regs[1] = lower_32_bits(regs.regs[1]);
206 			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
207 			val = regs.regs[1];
208 			break;
209 		case IDCODE2:
210 			regs.regs[1] = lower_32_bits(regs.regs[1]);
211 			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
212 			val = regs.regs[1];
213 			break;
214 		default:
215 			printf("%s, Invalid Req:0x%x\n", __func__, id);
216 		}
217 	} else {
218 		switch (id) {
219 		case IDCODE:
220 			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
221 			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
222 			       ZYNQMP_CSU_IDCODE_SVD_MASK;
223 			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
224 			break;
225 		case VERSION:
226 			val = readl(ZYNQMP_CSU_VER_ADDR);
227 			val &= ZYNQMP_CSU_SILICON_VER_MASK;
228 			break;
229 		default:
230 			printf("%s, Invalid Req:0x%x\n", __func__, id);
231 		}
232 	}
233 
234 	return val;
235 }
236 
237 #define ZYNQMP_VERSION_SIZE		9
238 #define ZYNQMP_PL_STATUS_BIT		9
239 #define ZYNQMP_IPDIS_VCU_BIT		8
240 #define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
241 #define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)
242 #define ZYNQMP_CSU_VCUDIS_VER_MASK	ZYNQMP_CSU_VERSION_MASK & \
243 					~BIT(ZYNQMP_IPDIS_VCU_BIT)
244 #define MAX_VARIANTS_EV			3
245 
246 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
247 	!defined(CONFIG_SPL_BUILD)
zynqmp_get_silicon_idcode_name(void)248 static char *zynqmp_get_silicon_idcode_name(void)
249 {
250 	u32 i, id, ver, j;
251 	char *buf;
252 	static char name[ZYNQMP_VERSION_SIZE];
253 
254 	id = chip_id(IDCODE);
255 	ver = chip_id(IDCODE2);
256 
257 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
258 		if (zynqmp_devices[i].id == id) {
259 			if (zynqmp_devices[i].evexists &&
260 			    !(ver & ZYNQMP_PL_STATUS_MASK))
261 				break;
262 			if (zynqmp_devices[i].ver == (ver &
263 			    ZYNQMP_CSU_VERSION_MASK))
264 				break;
265 		}
266 	}
267 
268 	if (i >= ARRAY_SIZE(zynqmp_devices))
269 		return "unknown";
270 
271 	strncat(name, "zu", 2);
272 	if (!zynqmp_devices[i].evexists ||
273 	    (ver & ZYNQMP_PL_STATUS_MASK)) {
274 		strncat(name, zynqmp_devices[i].name,
275 			ZYNQMP_VERSION_SIZE - 3);
276 		return name;
277 	}
278 
279 	/*
280 	 * Here we are means, PL not powered up and ev variant
281 	 * exists. So, we need to ignore VCU disable bit(8) in
282 	 * version and findout if its CG or EG/EV variant.
283 	 */
284 	for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
285 		if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
286 		    (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
287 			strncat(name, zynqmp_devices[i].name,
288 				ZYNQMP_VERSION_SIZE - 3);
289 			break;
290 		}
291 	}
292 
293 	if (j >= MAX_VARIANTS_EV)
294 		return "unknown";
295 
296 	if (strstr(name, "eg") || strstr(name, "ev")) {
297 		buf = strstr(name, "e");
298 		*buf = '\0';
299 	}
300 
301 	return name;
302 }
303 #endif
304 
board_early_init_f(void)305 int board_early_init_f(void)
306 {
307 	int ret = 0;
308 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
309 	u32 pm_api_version;
310 
311 	pm_api_version = zynqmp_pmufw_version();
312 	printf("PMUFW:\tv%d.%d\n",
313 	       pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
314 	       pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
315 
316 	if (pm_api_version < ZYNQMP_PM_VERSION)
317 		panic("PMUFW version error. Expected: v%d.%d\n",
318 		      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
319 #endif
320 
321 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
322 	ret = psu_init();
323 #endif
324 
325 	return ret;
326 }
327 
board_init(void)328 int board_init(void)
329 {
330 	printf("EL Level:\tEL%d\n", current_el());
331 
332 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
333     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
334     defined(CONFIG_SPL_BUILD))
335 	if (current_el() != 3) {
336 		zynqmppl.name = zynqmp_get_silicon_idcode_name();
337 		printf("Chip ID:\t%s\n", zynqmppl.name);
338 		fpga_init();
339 		fpga_add(fpga_xilinx, &zynqmppl);
340 	}
341 #endif
342 
343 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
344 	if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
345 		debug("Watchdog: Not found by seq!\n");
346 		if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
347 			puts("Watchdog: Not found!\n");
348 			return 0;
349 		}
350 	}
351 
352 	wdt_start(watchdog_dev, 0, 0);
353 	puts("Watchdog: Started\n");
354 #endif
355 
356 	return 0;
357 }
358 
359 #ifdef CONFIG_WATCHDOG
360 /* Called by macro WATCHDOG_RESET */
watchdog_reset(void)361 void watchdog_reset(void)
362 {
363 # if !defined(CONFIG_SPL_BUILD)
364 	static ulong next_reset;
365 	ulong now;
366 
367 	if (!watchdog_dev)
368 		return;
369 
370 	now = timer_get_us();
371 
372 	/* Do not reset the watchdog too often */
373 	if (now > next_reset) {
374 		wdt_reset(watchdog_dev);
375 		next_reset = now + 1000;
376 	}
377 # endif
378 }
379 #endif
380 
board_early_init_r(void)381 int board_early_init_r(void)
382 {
383 	u32 val;
384 
385 	if (current_el() != 3)
386 		return 0;
387 
388 	val = readl(&crlapb_base->timestamp_ref_ctrl);
389 	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
390 
391 	if (!val) {
392 		val = readl(&crlapb_base->timestamp_ref_ctrl);
393 		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
394 		writel(val, &crlapb_base->timestamp_ref_ctrl);
395 
396 		/* Program freq register in System counter */
397 		writel(zynqmp_get_system_timer_freq(),
398 		       &iou_scntr_secure->base_frequency_id_register);
399 		/* And enable system counter */
400 		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
401 		       &iou_scntr_secure->counter_control_register);
402 	}
403 	return 0;
404 }
405 
do_go_exec(ulong (* entry)(int,char * const[]),int argc,char * const argv[])406 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
407 			 char * const argv[])
408 {
409 	int ret = 0;
410 
411 	if (current_el() > 1) {
412 		smp_kick_all_cpus();
413 		dcache_disable();
414 		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
415 				    ES_TO_AARCH64);
416 	} else {
417 		printf("FAIL: current EL is not above EL1\n");
418 		ret = EINVAL;
419 	}
420 	return ret;
421 }
422 
423 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
dram_init_banksize(void)424 int dram_init_banksize(void)
425 {
426 	int ret;
427 
428 	ret = fdtdec_setup_memory_banksize();
429 	if (ret)
430 		return ret;
431 
432 	mem_map_fill();
433 
434 	return 0;
435 }
436 
dram_init(void)437 int dram_init(void)
438 {
439 	if (fdtdec_setup_mem_size_base() != 0)
440 		return -EINVAL;
441 
442 	return 0;
443 }
444 #else
dram_init_banksize(void)445 int dram_init_banksize(void)
446 {
447 #if defined(CONFIG_NR_DRAM_BANKS)
448 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
449 	gd->bd->bi_dram[0].size = get_effective_memsize();
450 #endif
451 
452 	mem_map_fill();
453 
454 	return 0;
455 }
456 
dram_init(void)457 int dram_init(void)
458 {
459 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
460 				    CONFIG_SYS_SDRAM_SIZE);
461 
462 	return 0;
463 }
464 #endif
465 
reset_cpu(ulong addr)466 void reset_cpu(ulong addr)
467 {
468 }
469 
470 #if defined(CONFIG_BOARD_LATE_INIT)
471 static const struct {
472 	u32 bit;
473 	const char *name;
474 } reset_reasons[] = {
475 	{ RESET_REASON_DEBUG_SYS, "DEBUG" },
476 	{ RESET_REASON_SOFT, "SOFT" },
477 	{ RESET_REASON_SRST, "SRST" },
478 	{ RESET_REASON_PSONLY, "PS-ONLY" },
479 	{ RESET_REASON_PMU, "PMU" },
480 	{ RESET_REASON_INTERNAL, "INTERNAL" },
481 	{ RESET_REASON_EXTERNAL, "EXTERNAL" },
482 	{}
483 };
484 
reset_reason(void)485 static u32 reset_reason(void)
486 {
487 	u32 ret;
488 	int i;
489 	const char *reason = NULL;
490 
491 	ret = readl(&crlapb_base->reset_reason);
492 
493 	puts("Reset reason:\t");
494 
495 	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
496 		if (ret & reset_reasons[i].bit) {
497 			reason = reset_reasons[i].name;
498 			printf("%s ", reset_reasons[i].name);
499 			break;
500 		}
501 	}
502 
503 	puts("\n");
504 
505 	env_set("reset_reason", reason);
506 
507 	writel(~0, &crlapb_base->reset_reason);
508 
509 	return ret;
510 }
511 
set_fdtfile(void)512 static int set_fdtfile(void)
513 {
514 	char *compatible, *fdtfile;
515 	const char *suffix = ".dtb";
516 	const char *vendor = "xilinx/";
517 
518 	if (env_get("fdtfile"))
519 		return 0;
520 
521 	compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
522 	if (compatible) {
523 		debug("Compatible: %s\n", compatible);
524 
525 		/* Discard vendor prefix */
526 		strsep(&compatible, ",");
527 
528 		fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
529 				 strlen(suffix) + 1);
530 		if (!fdtfile)
531 			return -ENOMEM;
532 
533 		sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
534 
535 		env_set("fdtfile", fdtfile);
536 		free(fdtfile);
537 	}
538 
539 	return 0;
540 }
541 
board_late_init(void)542 int board_late_init(void)
543 {
544 	u32 reg = 0;
545 	u8 bootmode;
546 	struct udevice *dev;
547 	int bootseq = -1;
548 	int bootseq_len = 0;
549 	int env_targets_len = 0;
550 	const char *mode;
551 	char *new_targets;
552 	char *env_targets;
553 	int ret;
554 
555 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
556 	usb_ether_init();
557 #endif
558 
559 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
560 		debug("Saved variables - Skipping\n");
561 		return 0;
562 	}
563 
564 	ret = set_fdtfile();
565 	if (ret)
566 		return ret;
567 
568 	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
569 	if (ret)
570 		return -EINVAL;
571 
572 	if (reg >> BOOT_MODE_ALT_SHIFT)
573 		reg >>= BOOT_MODE_ALT_SHIFT;
574 
575 	bootmode = reg & BOOT_MODES_MASK;
576 
577 	puts("Bootmode: ");
578 	switch (bootmode) {
579 	case USB_MODE:
580 		puts("USB_MODE\n");
581 		mode = "usb";
582 		env_set("modeboot", "usb_dfu_spl");
583 		break;
584 	case JTAG_MODE:
585 		puts("JTAG_MODE\n");
586 		mode = "pxe dhcp";
587 		env_set("modeboot", "jtagboot");
588 		break;
589 	case QSPI_MODE_24BIT:
590 	case QSPI_MODE_32BIT:
591 		mode = "qspi0";
592 		puts("QSPI_MODE\n");
593 		env_set("modeboot", "qspiboot");
594 		break;
595 	case EMMC_MODE:
596 		puts("EMMC_MODE\n");
597 		mode = "mmc0";
598 		env_set("modeboot", "emmcboot");
599 		break;
600 	case SD_MODE:
601 		puts("SD_MODE\n");
602 		if (uclass_get_device_by_name(UCLASS_MMC,
603 					      "mmc@ff160000", &dev) &&
604 		    uclass_get_device_by_name(UCLASS_MMC,
605 					      "sdhci@ff160000", &dev)) {
606 			puts("Boot from SD0 but without SD0 enabled!\n");
607 			return -1;
608 		}
609 		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
610 
611 		mode = "mmc";
612 		bootseq = dev->seq;
613 		env_set("modeboot", "sdboot");
614 		break;
615 	case SD1_LSHFT_MODE:
616 		puts("LVL_SHFT_");
617 		/* fall through */
618 	case SD_MODE1:
619 		puts("SD_MODE1\n");
620 		if (uclass_get_device_by_name(UCLASS_MMC,
621 					      "mmc@ff170000", &dev) &&
622 		    uclass_get_device_by_name(UCLASS_MMC,
623 					      "sdhci@ff170000", &dev)) {
624 			puts("Boot from SD1 but without SD1 enabled!\n");
625 			return -1;
626 		}
627 		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
628 
629 		mode = "mmc";
630 		bootseq = dev->seq;
631 		env_set("modeboot", "sdboot");
632 		break;
633 	case NAND_MODE:
634 		puts("NAND_MODE\n");
635 		mode = "nand0";
636 		env_set("modeboot", "nandboot");
637 		break;
638 	default:
639 		mode = "";
640 		printf("Invalid Boot Mode:0x%x\n", bootmode);
641 		break;
642 	}
643 
644 	if (bootseq >= 0) {
645 		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
646 		debug("Bootseq len: %x\n", bootseq_len);
647 	}
648 
649 	/*
650 	 * One terminating char + one byte for space between mode
651 	 * and default boot_targets
652 	 */
653 	env_targets = env_get("boot_targets");
654 	if (env_targets)
655 		env_targets_len = strlen(env_targets);
656 
657 	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
658 			     bootseq_len);
659 	if (!new_targets)
660 		return -ENOMEM;
661 
662 	if (bootseq >= 0)
663 		sprintf(new_targets, "%s%x %s", mode, bootseq,
664 			env_targets ? env_targets : "");
665 	else
666 		sprintf(new_targets, "%s %s", mode,
667 			env_targets ? env_targets : "");
668 
669 	env_set("boot_targets", new_targets);
670 
671 	reset_reason();
672 
673 	return 0;
674 }
675 #endif
676 
checkboard(void)677 int checkboard(void)
678 {
679 	puts("Board: Xilinx ZynqMP\n");
680 	return 0;
681 }
682